diff options
| author | Chris Demetriou <cgd@broadcom.com> | 2003-01-08 10:36:47 +0300 |
|---|---|---|
| committer | Chris Demetriou <cgd@broadcom.com> | 2003-01-08 10:36:47 +0300 |
| commit | f981849c93fae29c520e53c9cb1c9252d98da557 (patch) | |
| tree | e3e2d6864b64a0ac9c1b8fd131892fe15586cf9f | |
| parent | 2c98f8247d30c01d5804dcd7febaa847abaa771d (diff) | |
2003-01-07 Chris Demetriou <cgd@broadcom.com>
* mips.h: Fix missing space in comment.
(INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
(INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
by four bits.
| -rw-r--r-- | include/opcode/ChangeLog | 7 | ||||
| -rw-r--r-- | include/opcode/mips.h | 18 |
2 files changed, 16 insertions, 9 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 7386c5edf..e40f05694 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,10 @@ +2003-01-07 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Fix missing space in comment. + (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5) + (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right + by four bits. + 2003-01-02 Chris Demetriou <cgd@broadcom.com> * mips.h: Update copyright years to include 2002 (which had diff --git a/include/opcode/mips.h b/include/opcode/mips.h index bcc0fc680..1f90cfd76 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -373,18 +373,18 @@ struct mips_opcode /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. ISAs, as defined below, are logical - ORs of these bits, indicatingthat they support the instructions + ORs of these bits, indicating that they support the instructions defined at the given level. */ #define INSN_ISA_MASK 0x00000fff -#define INSN_ISA1 0x00000010 -#define INSN_ISA2 0x00000020 -#define INSN_ISA3 0x00000040 -#define INSN_ISA4 0x00000080 -#define INSN_ISA5 0x00000100 -#define INSN_ISA32 0x00000200 -#define INSN_ISA64 0x00000400 -#define INSN_ISA32R2 0x00000800 +#define INSN_ISA1 0x00000001 +#define INSN_ISA2 0x00000002 +#define INSN_ISA3 0x00000004 +#define INSN_ISA4 0x00000008 +#define INSN_ISA5 0x00000010 +#define INSN_ISA32 0x00000020 +#define INSN_ISA64 0x00000040 +#define INSN_ISA32R2 0x00000080 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x0000f000 |