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author | cvs2svn <> | 2000-12-15 01:32:43 +0300 |
---|---|---|
committer | cvs2svn <> | 2000-12-15 01:32:43 +0300 |
commit | 039e8a3c16964d02838b204b72bfdd4b7529107c (patch) | |
tree | c27587fa1efab089a28d5623d6995304fa464f52 /include/opcode/arm.h | |
parent | 9c2b8183424dad2579bebcd818ecd60d6c08832f (diff) |
This commit was manufactured by cvs2svn to create tag 'newlib-1_9_0'.newlib-1_9_0
Sprout from master 2000-12-14 22:32:42 UTC Jeff Johnston <jjohnstn@redhat.com> ''
Cherrypick from cygnus 1999-05-03 07:29:06 UTC Richard Henderson <rth@redhat.com> '19990502 sourceware import':
COPYING
COPYING.LIB
README
config/mh-a68bsd
config/mh-aix386
config/mh-apollo68
config/mh-armpic
config/mh-cxux
config/mh-cygwin
config/mh-decstation
config/mh-delta88
config/mh-dgux
config/mh-dgux386
config/mh-djgpp
config/mh-elfalphapic
config/mh-hp300
config/mh-hpux
config/mh-hpux8
config/mh-interix
config/mh-irix4
config/mh-irix5
config/mh-lynxos
config/mh-lynxrs6k
config/mh-m68kpic
config/mh-mingw32
config/mh-ncr3000
config/mh-ncrsvr43
config/mh-necv4
config/mh-papic
config/mh-ppcpic
config/mh-riscos
config/mh-sco
config/mh-solaris
config/mh-sun3
config/mh-sysv
config/mh-sysv4
config/mh-sysv5
config/mh-vaxult2
config/mh-x86pic
config/mpw-mh-mpw
config/mpw/ChangeLog
config/mpw/MoveIfChange
config/mpw/README
config/mpw/forward-include
config/mpw/g-mpw-make.sed
config/mpw/mpw-touch
config/mpw/mpw-true
config/mpw/null-command
config/mpw/open-brace
config/mpw/tr-7to8-src
config/mpw/true
config/mt-armpic
config/mt-d30v
config/mt-elfalphapic
config/mt-linux
config/mt-m68kpic
config/mt-netware
config/mt-ospace
config/mt-papic
config/mt-ppcpic
config/mt-v810
config/mt-x86pic
etc/ChangeLog
etc/Makefile.in
etc/add-log.el
etc/add-log.vi
etc/configbuild.ein
etc/configbuild.fig
etc/configbuild.jin
etc/configbuild.tin
etc/configdev.ein
etc/configdev.fig
etc/configdev.jin
etc/configdev.tin
etc/configure
etc/configure.in
etc/configure.texi
etc/make-stds.texi
etc/standards.texi
install-sh
makefile.vms
missing
mkinstalldirs
move-if-change
mpw-README
mpw-build.in
mpw-config.in
mpw-configure
mpw-install
setup.com
ylwrap
Delete:
djunpack.bat
include/COPYING
include/ChangeLog
include/MAINTAINERS
include/alloca-conf.h
include/ansidecl.h
include/aout/ChangeLog
include/aout/adobe.h
include/aout/aout64.h
include/aout/ar.h
include/aout/dynix3.h
include/aout/encap.h
include/aout/host.h
include/aout/hp.h
include/aout/hp300hpux.h
include/aout/hppa.h
include/aout/ranlib.h
include/aout/reloc.h
include/aout/stab.def
include/aout/stab_gnu.h
include/aout/sun4.h
include/bfdlink.h
include/bin-bugs.h
include/bout.h
include/callback.h
include/coff/ChangeLog
include/coff/a29k.h
include/coff/alpha.h
include/coff/apollo.h
include/coff/arm.h
include/coff/aux-coff.h
include/coff/ecoff.h
include/coff/go32exe.h
include/coff/h8300.h
include/coff/h8500.h
include/coff/i386.h
include/coff/i860.h
include/coff/i960.h
include/coff/ia64.h
include/coff/internal.h
include/coff/m68k.h
include/coff/m88k.h
include/coff/mcore.h
include/coff/mips.h
include/coff/mipspe.h
include/coff/pe.h
include/coff/powerpc.h
include/coff/rs6000.h
include/coff/rs6k64.h
include/coff/sh.h
include/coff/sparc.h
include/coff/sym.h
include/coff/symconst.h
include/coff/ti.h
include/coff/tic30.h
include/coff/tic54x.h
include/coff/tic80.h
include/coff/w65.h
include/coff/we32k.h
include/coff/z8k.h
include/demangle.h
include/dis-asm.h
include/dyn-string.h
include/elf/ChangeLog
include/elf/alpha.h
include/elf/arc.h
include/elf/arm.h
include/elf/avr.h
include/elf/common.h
include/elf/cris.h
include/elf/d10v.h
include/elf/d30v.h
include/elf/dwarf.h
include/elf/dwarf2.h
include/elf/external.h
include/elf/fr30.h
include/elf/hppa.h
include/elf/i370.h
include/elf/i386.h
include/elf/i860.h
include/elf/i960.h
include/elf/ia64.h
include/elf/internal.h
include/elf/m32r.h
include/elf/m68hc11.h
include/elf/m68k.h
include/elf/mcore.h
include/elf/mips.h
include/elf/mn10200.h
include/elf/mn10300.h
include/elf/pj.h
include/elf/ppc.h
include/elf/reloc-macros.h
include/elf/sh.h
include/elf/sparc.h
include/elf/v850.h
include/elf/x86-64.h
include/filenames.h
include/floatformat.h
include/fnmatch.h
include/fopen-bin.h
include/fopen-same.h
include/fopen-vms.h
include/gdbm.h
include/getopt.h
include/hashtab.h
include/hp-symtab.h
include/ieee.h
include/libiberty.h
include/md5.h
include/mpw/ChangeLog
include/mpw/README
include/mpw/dir.h
include/mpw/dirent.h
include/mpw/fcntl.h
include/mpw/grp.h
include/mpw/mpw.h
include/mpw/pwd.h
include/mpw/spin.h
include/mpw/stat.h
include/mpw/sys/file.h
include/mpw/sys/param.h
include/mpw/sys/resource.h
include/mpw/sys/stat.h
include/mpw/sys/time.h
include/mpw/sys/types.h
include/mpw/utime.h
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include/nlm/ChangeLog
include/nlm/alpha-ext.h
include/nlm/common.h
include/nlm/external.h
include/nlm/i386-ext.h
include/nlm/internal.h
include/nlm/ppc-ext.h
include/nlm/sparc32-ext.h
include/oasys.h
include/objalloc.h
include/obstack.h
include/opcode/ChangeLog
include/opcode/a29k.h
include/opcode/alpha.h
include/opcode/arc.h
include/opcode/arm.h
include/opcode/avr.h
include/opcode/cgen.h
include/opcode/convex.h
include/opcode/cris.h
include/opcode/d10v.h
include/opcode/d30v.h
include/opcode/h8300.h
include/opcode/hppa.h
include/opcode/i370.h
include/opcode/i386.h
include/opcode/i860.h
include/opcode/i960.h
include/opcode/ia64.h
include/opcode/m68hc11.h
include/opcode/m68k.h
include/opcode/m88k.h
include/opcode/mips.h
include/opcode/mn10200.h
include/opcode/mn10300.h
include/opcode/np1.h
include/opcode/ns32k.h
include/opcode/pj.h
include/opcode/pn.h
include/opcode/ppc.h
include/opcode/pyr.h
include/opcode/sparc.h
include/opcode/tahoe.h
include/opcode/tic30.h
include/opcode/tic54x.h
include/opcode/tic80.h
include/opcode/v850.h
include/opcode/vax.h
include/os9k.h
include/partition.h
include/progress.h
include/regs/ChangeLog
include/remote-sim.h
include/safe-ctype.h
include/sim-d10v.h
include/sort.h
include/splay-tree.h
include/symcat.h
winsup/CYGWIN_LICENSE
winsup/ChangeLog
winsup/MAINTAINERS
winsup/Makefile.common
winsup/Makefile.in
winsup/configure
winsup/configure.in
winsup/cygwin/CYGWIN_LICENSE
winsup/cygwin/ChangeLog
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winsup/cygwin/config/i386/profile.h
winsup/cygwin/config/i386/setjmp.c
winsup/cygwin/configure
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winsup/w32api/lib/ws2_32.def
winsup/w32api/lib/wsock32.def
winsup/w32api/lib/wst.def
Diffstat (limited to 'include/opcode/arm.h')
-rw-r--r-- | include/opcode/arm.h | 294 |
1 files changed, 0 insertions, 294 deletions
diff --git a/include/opcode/arm.h b/include/opcode/arm.h deleted file mode 100644 index c7087eb9e..000000000 --- a/include/opcode/arm.h +++ /dev/null @@ -1,294 +0,0 @@ -/* ARM opcode list. - Copyright (C) 1989, Free Software Foundation, Inc. - -This file is part of GDB and GAS. - -GDB and GAS are free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB and GAS are distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB or GAS; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* types of instruction (encoded in bits 26 and 27 of the instruction) */ - -#define TYPE_ARITHMETIC 0 -#define TYPE_LDR_STR 1 -#define TYPE_BLOCK_BRANCH 2 -#define TYPE_SWI 3 - -/* bit 25 decides whether an instruction is a block move or a branch */ -#define SUBTYPE_BLOCK 0 -#define SUBTYPE_BRANCH 1 - -/* codes to distinguish the arithmetic instructions */ - -#define OPCODE_AND 0 -#define OPCODE_EOR 1 -#define OPCODE_SUB 2 -#define OPCODE_RSB 3 -#define OPCODE_ADD 4 -#define OPCODE_ADC 5 -#define OPCODE_SBC 6 -#define OPCODE_RSC 7 -#define OPCODE_TST 8 -#define OPCODE_TEQ 9 -#define OPCODE_CMP 10 -#define OPCODE_CMN 11 -#define OPCODE_ORR 12 -#define OPCODE_MOV 13 -#define OPCODE_BIC 14 -#define OPCODE_MVN 15 - -/* condition codes */ - -#define COND_EQ 0 -#define COND_NE 1 -#define COND_CS 2 -#define COND_CC 3 -#define COND_MI 4 -#define COND_PL 5 -#define COND_VS 6 -#define COND_VC 7 -#define COND_HI 8 -#define COND_LS 9 -#define COND_GE 10 -#define COND_LT 11 -#define COND_GT 12 -#define COND_LE 13 -#define COND_AL 14 -#define COND_NV 15 - -/* Describes the format of an ARM machine instruction */ - -struct generic_fmt { - unsigned rest :25; /* the rest of the instruction */ - unsigned subtype :1; /* used to decide between block and branch */ - unsigned type :2; /* one of TYPE_* */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct arith_fmt { - unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */ - unsigned dest :4; /* place where the answer goes */ - unsigned operand1 :4; /* first operand to instruction */ - unsigned set :1; /* == 1 means set processor flags */ - unsigned opcode :4; /* one of OPCODE_* defined above */ - unsigned immed :1; /* operand2 is an immediate value */ - unsigned type :2; /* == TYPE_ARITHMETIC */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct ldr_str_fmt { - unsigned offset :12; /* #nn or rn or rn shift #m */ - unsigned reg :4; /* destination for LDR, source for STR */ - unsigned base :4; /* base register */ - unsigned is_load :1; /* == 1 for LDR */ - unsigned writeback :1; /* == 1 means write back (base+offset) into base */ - unsigned byte :1; /* == 1 means byte access else word */ - unsigned up :1; /* == 1 means add offset else subtract it */ - unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */ - unsigned immed :1; /* == 0 means immediate offset */ - unsigned type :2; /* == TYPE_LDR_STR */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct block_fmt { - unsigned mask :16; /* register mask */ - unsigned base :4; /* register used as base of move */ - unsigned is_load :1; /* == 1 for LDM */ - unsigned writeback :1; /* == 1 means update base after move */ - unsigned set :1; /* == 1 means set flags in pc if included in mask */ - unsigned increment :1; /* == 1 means increment base register */ - unsigned before :1; /* == 1 means inc/dec before each move */ - unsigned is_block :1; /* == SUBTYPE_BLOCK */ - unsigned type :2; /* == TYPE_BLOCK_BRANCH */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct branch_fmt { - unsigned dest :24; /* destination of the branch */ - unsigned link :1; /* branch with link (function call) */ - unsigned is_branch :1; /* == SUBTYPE_BRANCH */ - unsigned type :2; /* == TYPE_BLOCK_BRANCH */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -#define ROUND_N 0 -#define ROUND_P 1 -#define ROUND_M 2 -#define ROUND_Z 3 - -#define FLOAT2_MVF 0 -#define FLOAT2_MNF 1 -#define FLOAT2_ABS 2 -#define FLOAT2_RND 3 -#define FLOAT2_SQT 4 -#define FLOAT2_LOG 5 -#define FLOAT2_LGN 6 -#define FLOAT2_EXP 7 -#define FLOAT2_SIN 8 -#define FLOAT2_COS 9 -#define FLOAT2_TAN 10 -#define FLOAT2_ASN 11 -#define FLOAT2_ACS 12 -#define FLOAT2_ATN 13 - -#define FLOAT3_ADF 0 -#define FLOAT3_MUF 1 -#define FLOAT3_SUF 2 -#define FLOAT3_RSF 3 -#define FLOAT3_DVF 4 -#define FLOAT3_RDF 5 -#define FLOAT3_POW 6 -#define FLOAT3_RPW 7 -#define FLOAT3_RMF 8 -#define FLOAT3_FML 9 -#define FLOAT3_FDV 10 -#define FLOAT3_FRD 11 -#define FLOAT3_POL 12 - -struct float2_fmt { - unsigned operand2 :3; /* second operand */ - unsigned immed :1; /* == 1 if second operand is a constant */ - unsigned pad1 :1; /* == 0 */ - unsigned rounding :2; /* ROUND_* */ - unsigned is_double :1; /* == 1 if precision is double (only if not extended) */ - unsigned pad2 :4; /* == 1 */ - unsigned dest :3; /* destination */ - unsigned is_2_op :1; /* == 1 if 2 operand ins */ - unsigned operand1 :3; /* first operand (only of is_2_op == 0) */ - unsigned is_extended :1; /* == 1 if precision is extended */ - unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */ - unsigned must_be_2 :2; /* == 2 */ - unsigned type :2; /* == TYPE_SWI */ - unsigned cond :4; /* COND_* */ -}; - -struct swi_fmt { - unsigned argument :24; /* argument to SWI (syscall number) */ - unsigned must_be_3 :2; /* == 3 */ - unsigned type :2; /* == TYPE_SWI */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -union insn_fmt { - struct generic_fmt generic; - struct arith_fmt arith; - struct ldr_str_fmt ldr_str; - struct block_fmt block; - struct branch_fmt branch; - struct swi_fmt swi; - unsigned long ins; -}; - -struct opcode { - unsigned long value, mask; /* recognise instruction if (op&mask)==value */ - char *assembler; /* how to disassemble this instruction */ -}; - -/* format of the assembler string : - - %% % - %<bitfield>d print the bitfield in decimal - %<bitfield>x print the bitfield in hex - %<bitfield>r print as an ARM register - %<bitfield>f print a floating point constant if >7 else an fp register - %c print condition code (always bits 28-31) - %P print floating point precision in arithmetic insn - %Q print floating point precision in ldf/stf insn - %R print floating point rounding mode - %<bitnum>'c print specified char iff bit is one - %<bitnum>`c print specified char iff bit is zero - %<bitnum>?ab print a if bit is one else print b - %p print 'p' iff bits 12-15 are 15 - %o print operand2 (immediate or register + shift) - %a print address for ldr/str instruction - %b print branch destination - %A print address for ldc/stc/ldf/stf instruction - %m print register mask for ldm/stm instruction -*/ - -static struct opcode opcodes[] = { - /* ARM instructions */ - 0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r", - 0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r", - 0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o", - 0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o", - 0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o", - 0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o", - 0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o", - 0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o", - 0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o", - 0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o", - 0x01000000, 0x0de00000, "tst%c%p %16-19r, %o", - 0x01200000, 0x0de00000, "teq%c%p %16-19r, %o", - 0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o", - 0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o", - 0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o", - 0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o", - 0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o", - 0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o", - 0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a", - 0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a", - 0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m", - 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^", - 0x0a000000, 0x0e000000, "b%c%24'l %b", - 0x0f000000, 0x0f000000, "swi%c %0-23x", - /* Floating point coprocessor instructions */ - 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f", - 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f", - 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f", - 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f", - 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f", - 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f", - 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f", - 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f", - 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f", - 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f", - 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f", - 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f", - 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f", - 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f", - 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f", - 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f", - 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f", - 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r", - 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f", - 0x0e200110, 0x0fff0fff, "wfs%c %12-15r", - 0x0e300110, 0x0fff0fff, "rfs%c %12-15r", - 0x0e400110, 0x0fff0fff, "wfc%c %12-15r", - 0x0e500110, 0x0fff0fff, "rfc%c %12-15r", - 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f", - 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f", - 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f", - 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f", - 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A", - 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A", - /* Generic coprocessor instructions */ - 0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A", - 0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A", - /* the rest */ - 0x00000000, 0x00000000, "undefined instruction %0-31x", -}; -#define N_OPCODES (sizeof opcodes / sizeof opcodes[0]) |