This commit was manufactured by cvs2svn to create tag 'cygwin-cygwin-1_7_17-release

1_7_17-release'.

Sprout from cygwin-64bit-branch 2012-08-10 09:37:33 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'cygwin-64bit-'
Cherrypick from cygwin-64bit-branch 2012-10-09 12:05:52 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'cygwin-64bit-':
    newlib/libc/posix/wordexp2.h
Cherrypick from master 2012-10-20 15:31:50 UTC Corinna Vinschen <corinna@vinschen.de> '	* new-features.sgml (ov-new1.7.17): Add section.':
    ChangeLog
    Makefile.def
    Makefile.in
    Makefile.tpl
    compile
    config.guess
    config.sub
    config/ChangeLog
    config/cloog.m4
    config/isl.m4
    config/mt-sde
    configure
    include/ChangeLog
    include/demangle.h
    include/dis-asm.h
    include/dwarf2.def
    include/elf/ChangeLog
    include/elf/aarch64.h
    include/elf/arm.h
    include/elf/common.h
    include/elf/tilegx.h
    include/mach-o/ChangeLog
    include/mach-o/codesign.h
    include/mach-o/external.h
    include/mach-o/loader.h
    include/mach-o/reloc.h
    include/mach-o/x86-64.h
    include/objalloc.h
    include/opcode/ChangeLog
    include/opcode/aarch64.h
    include/opcode/arm.h
    include/opcode/hppa.h
    include/opcode/ia64.h
    include/opcode/mips.h
    include/opcode/moxie.h
    include/opcode/s390.h
    include/opcode/sparc.h
    include/plugin-api.h
    libtool.m4
    ltoptions.m4
    ltversion.m4
    lt~obsolete.m4
    newlib/ChangeLog
    newlib/HOWTO
    newlib/README
    newlib/configure.host
    newlib/doc/makedoc.c
    newlib/libc/include/_ansi.h
    newlib/libc/include/assert.h
    newlib/libc/include/machine/_default_types.h
    newlib/libc/include/machine/ieeefp.h
    newlib/libc/include/machine/setjmp.h
    newlib/libc/include/machine/time.h
    newlib/libc/include/math.h
    newlib/libc/include/stdint.h
    newlib/libc/include/sys/config.h
    newlib/libc/include/sys/features.h
    newlib/libc/include/tgmath.h
    newlib/libc/machine/configure
    newlib/libc/machine/configure.in
    newlib/libc/machine/rl78/Makefile.am
    newlib/libc/machine/rl78/Makefile.in
    newlib/libc/machine/rl78/aclocal.m4
    newlib/libc/machine/rl78/configure
    newlib/libc/machine/rl78/configure.in
    newlib/libc/machine/rl78/setjmp.S
    newlib/libc/posix/engine.c
    newlib/libc/posix/wordexp.c
    newlib/libc/posix/wordfree.c
    newlib/libc/search/hash_buf.c
    newlib/libc/stdio/fgets.c
    newlib/libc/stdio/flags.c
    newlib/libc/stdio/vfprintf.c
    newlib/libc/stdlib/btowc.c
    newlib/libc/stdlib/getopt.c
    newlib/libc/string/strcasestr.c
    newlib/libc/sys/sysnecv850/sbrk.c
    newlib/libc/time/strftime.c
    newlib/libm/machine/configure
    newlib/libm/machine/configure.in
    newlib/testsuite/newlib.stdio/stdio.exp
    newlib/testsuite/newlib.stdio/swprintf.c
    winsup/cygwin/ChangeLog
    winsup/cygwin/DevNotes
    winsup/cygwin/child_info.h
    winsup/cygwin/cygheap.cc
    winsup/cygwin/cygthread.cc
    winsup/cygwin/cygtls.cc
    winsup/cygwin/cygtls.h
    winsup/cygwin/cygwait.cc
    winsup/cygwin/cygwait.h
    winsup/cygwin/dll_init.cc
    winsup/cygwin/errno.cc
    winsup/cygwin/exceptions.cc
    winsup/cygwin/fhandler.cc
    winsup/cygwin/fhandler.h
    winsup/cygwin/fhandler_clipboard.cc
    winsup/cygwin/fhandler_console.cc
    winsup/cygwin/fhandler_floppy.cc
    winsup/cygwin/fhandler_process.cc
    winsup/cygwin/fhandler_raw.cc
    winsup/cygwin/fhandler_socket.cc
    winsup/cygwin/fhandler_tape.cc
    winsup/cygwin/fhandler_termios.cc
    winsup/cygwin/fhandler_tty.cc
    winsup/cygwin/flock.cc
    winsup/cygwin/gendef
    winsup/cygwin/glob.cc
    winsup/cygwin/globals.cc
    winsup/cygwin/gmon.c
    winsup/cygwin/hookapi.cc
    winsup/cygwin/include/cygwin/fs.h
    winsup/cygwin/include/cygwin/in.h
    winsup/cygwin/include/limits.h
    winsup/cygwin/miscfuncs.cc
    winsup/cygwin/mount.cc
    winsup/cygwin/mount.h
    winsup/cygwin/net.cc
    winsup/cygwin/path.cc
    winsup/cygwin/pinfo.cc
    winsup/cygwin/posix_ipc.cc
    winsup/cygwin/pseudo-reloc.cc
    winsup/cygwin/release/1.7.10
    winsup/cygwin/release/1.7.11
    winsup/cygwin/release/1.7.12
    winsup/cygwin/release/1.7.13
    winsup/cygwin/release/1.7.14
    winsup/cygwin/release/1.7.15
    winsup/cygwin/release/1.7.16
    winsup/cygwin/release/1.7.17
    winsup/cygwin/sec_helper.cc
    winsup/cygwin/signal.cc
    winsup/cygwin/sigproc.h
    winsup/cygwin/smallprint.cc
    winsup/cygwin/spawn.cc
    winsup/cygwin/syscalls.cc
    winsup/cygwin/thread.cc
    winsup/cygwin/thread.h
    winsup/cygwin/tty.h
    winsup/cygwin/wait.cc
    winsup/doc/ChangeLog
    winsup/doc/faq-what.xml
    winsup/doc/new-features.sgml
    winsup/utils/ChangeLog
    winsup/utils/Makefile.in
    winsup/utils/cygcheck.cc
    winsup/w32api/ChangeLog
    winsup/w32api/include/winbase.h
    winsup/w32api/lib/kernel32.def

1 files changed, 98 insertions, 37 deletions

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 857fc7173..5691ac535 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -25,6 +25,8 @@
 #ifndef _MIPS_H_
 #define _MIPS_H_
 
+#include "bfd.h"
+
 /* These are bit masks and shift counts to use to access the various
    fields of an instruction.  To retrieve the X field of an
    instruction, use the expression
@@ -353,6 +355,9 @@ struct mips_opcode
   /* A collection of bits describing the instruction sets of which this
      instruction or macro is a member. */
   unsigned long membership;
+  /* A collection of bits describing the instruction sets of which this
+     instruction or macro is not a member.  */
+  unsigned long exclusions;
 };
 
 /* These are the characters which may appear in the args field of an
@@ -829,46 +834,102 @@ static const unsigned int mips_isa_table[] =
 #define CPU_OCTEON2	6502
 #define CPU_XLR     	887682   	/* decimal 'XLR'   */
 
+/* Return true if the given CPU is included in INSN_* mask MASK.  */
+
+static inline bfd_boolean
+cpu_is_member (int cpu, unsigned int mask)
+{
+  switch (cpu)
+    {
+    case CPU_R4650:
+    case CPU_RM7000:
+    case CPU_RM9000:
+      return (mask & INSN_4650) != 0;
+
+    case CPU_R4010:
+      return (mask & INSN_4010) != 0;
+
+    case CPU_VR4100:
+      return (mask & INSN_4100) != 0;
+
+    case CPU_R3900:
+      return (mask & INSN_3900) != 0;
+
+    case CPU_R10000:
+    case CPU_R12000:
+    case CPU_R14000:
+    case CPU_R16000:
+      return (mask & INSN_10000) != 0;
+
+    case CPU_SB1:
+      return (mask & INSN_SB1) != 0;
+
+    case CPU_R4111:
+      return (mask & INSN_4111) != 0;
+
+    case CPU_VR4120:
+      return (mask & INSN_4120) != 0;
+
+    case CPU_VR5400:
+      return (mask & INSN_5400) != 0;
+
+    case CPU_VR5500:
+      return (mask & INSN_5500) != 0;
+
+    case CPU_LOONGSON_2E:
+      return (mask & INSN_LOONGSON_2E) != 0;
+
+    case CPU_LOONGSON_2F:
+      return (mask & INSN_LOONGSON_2F) != 0;
+
+    case CPU_LOONGSON_3A:
+      return (mask & INSN_LOONGSON_3A) != 0;
+
+    case CPU_OCTEON:
+      return (mask & INSN_OCTEON) != 0;
+
+    case CPU_OCTEONP:
+      return (mask & INSN_OCTEONP) != 0;
+
+    case CPU_OCTEON2:
+      return (mask & INSN_OCTEON2) != 0;
+
+    case CPU_XLR:
+      return (mask & INSN_XLR) != 0;
+
+    default:
+      return FALSE;
+    }
+}
+
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
-   test, or zero if no CPU specific ISA test is desired.  */
-
-#define OPCODE_IS_MEMBER(insn, isa, cpu)				\
-    (((isa & INSN_ISA_MASK) != 0                                        \
-      && ((insn)->membership & INSN_ISA_MASK) != 0                      \
-      && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >>                \
-           (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0)       \
-     || ((isa & ~INSN_ISA_MASK)                                         \
-          & ((insn)->membership & ~INSN_ISA_MASK)) != 0                 \
-     || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)	\
-     || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)	\
-     || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)	\
-     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)	\
-     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)	\
-     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)	\
-     || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000	\
-	  || cpu == CPU_R16000)						\
-	 && ((insn)->membership & INSN_10000) != 0)			\
-     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)	\
-     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)	\
-     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)	\
-     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)	\
-     || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)	\
-     || (cpu == CPU_LOONGSON_2E                                         \
-         && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
-     || (cpu == CPU_LOONGSON_2F                                         \
-         && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
-     || (cpu == CPU_LOONGSON_3A                                         \
-         && ((insn)->membership & INSN_LOONGSON_3A) != 0)               \
-     || (cpu == CPU_OCTEON						\
-	 && ((insn)->membership & INSN_OCTEON) != 0)			\
-     || (cpu == CPU_OCTEONP						\
-	 && ((insn)->membership & INSN_OCTEONP) != 0)			\
-     || (cpu == CPU_OCTEON2						\
-	 && ((insn)->membership & INSN_OCTEON2) != 0)			\
-     || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \
-     || 0)	/* Please keep this term for easier source merging.  */
+   test, or zero if no CPU specific ISA test is desired.  Return true
+   if instruction INSN is available to the given ISA and CPU. */
+
+static inline bfd_boolean
+opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
+{
+  if (!cpu_is_member (cpu, insn->exclusions))
+    {
+      /* Test for ISA level compatibility.  */
+      if ((isa & INSN_ISA_MASK) != 0
+	  && (insn->membership & INSN_ISA_MASK) != 0
+	  && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
+	       >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
+	return TRUE;
+
+      /* Test for ASE compatibility.  */
+      if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
+	return TRUE;
+
+      /* Test for processor-specific extensions.  */
+      if (cpu_is_member (cpu, insn->membership))
+	return TRUE;
+    }
+  return FALSE;
+}
 
 /* This is a list of macro expanded instructions.