This commit was manufactured by cvs2svn to create branch 'binutils-binutils-2_12-branchpoint

2_12-branch'.

Sprout from gdb_5_1-2001-07-29-branch 2001-07-26 14:20:06 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch'
Cherrypick from master 2002-02-09 22:54:16 UTC Richard Henderson <rth@redhat.com> '        * alpha.h (R_ALPHA_BRSGP): New.':
    COPYING.NEWLIB
    ChangeLog
    MAINTAINERS
    Makefile.in
    config.guess
    config.sub
    configure
    configure.in
    etc/ChangeLog
    etc/Makefile.in
    gettext.m4
    include/ChangeLog
    include/ansidecl.h
    include/aout/ChangeLog
    include/aout/aout64.h
    include/aout/hp300hpux.h
    include/bfdlink.h
    include/coff/ChangeLog
    include/coff/arm.h
    include/coff/external.h
    include/coff/internal.h
    include/coff/m88k.h
    include/coff/or32.h
    include/coff/ti.h
    include/coff/tic54x.h
    include/coff/xcoff.h
    include/demangle.h
    include/dis-asm.h
    include/dyn-string.h
    include/elf/ChangeLog
    include/elf/alpha.h
    include/elf/arm.h
    include/elf/common.h
    include/elf/dwarf2.h
    include/elf/external.h
    include/elf/h8.h
    include/elf/ia64.h
    include/elf/internal.h
    include/elf/mips.h
    include/elf/mmix.h
    include/elf/or32.h
    include/elf/ppc.h
    include/elf/sh.h
    include/elf/xstormy16.h
    include/fibheap.h
    include/filenames.h
    include/floatformat.h
    include/hashtab.h
    include/libiberty.h
    include/nlm/ChangeLog
    include/nlm/common.h
    include/objalloc.h
    include/opcode/ChangeLog
    include/opcode/alpha.h
    include/opcode/arc.h
    include/opcode/avr.h
    include/opcode/cgen.h
    include/opcode/d10v.h
    include/opcode/d30v.h
    include/opcode/h8300.h
    include/opcode/hppa.h
    include/opcode/i386.h
    include/opcode/mips.h
    include/opcode/mmix.h
    include/opcode/or32.h
    include/opcode/ppc.h
    include/opcode/tic54x.h
    include/opcode/v850.h
    include/partition.h
    include/safe-ctype.h
    include/sort.h
    include/splay-tree.h
    include/xregex.h
    libtool.m4
    ltcf-c.sh
    ltcf-cxx.sh
    ltcf-gcj.sh
    ltconfig
    ltmain.sh
    symlink-tree

1 files changed, 16 insertions, 15 deletions

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 7fd4703e5..1469e1072 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -209,8 +209,8 @@ struct mips_opcode
    Coprocessor instructions:
    "E" 5 bit target register (OP_*_RT)
    "G" 5 bit destination register (OP_*_RD)
+   "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
    "P" 5 bit performance-monitor register (OP_*_PERFREG)
-   "H" 3 bit sel field (OP_*_SEL)
 
    Macro instructions:
    "A" General 32 bit expression
@@ -307,7 +307,7 @@ struct mips_opcode
    ORs of these bits, indicatingthat they support the instructions
    defined at the given level.  */
 
-#define INSN_ISA_MASK		  0x0000ffff
+#define INSN_ISA_MASK		  0x00000fff
 #define INSN_ISA1                 0x00000010
 #define INSN_ISA2                 0x00000020
 #define INSN_ISA3                 0x00000040
@@ -326,8 +326,10 @@ struct mips_opcode
 #define INSN_4100                 0x00040000
 /* Toshiba R3900 instruction.  */
 #define INSN_3900                 0x00080000
-/* 32-bit code running on a ISA3+ CPU.  */
-#define INSN_GP32                 0x00100000
+/* MIPS R10000 instruction.  */
+#define INSN_10000                0x00100000
+/* Broadcom SB-1 instruction.  */
+#define INSN_SB1                  0x00200000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -361,7 +363,6 @@ struct mips_opcode
 #define CPU_R12000	12000
 #define CPU_MIPS16	16
 #define CPU_MIPS32	32
-#define CPU_MIPS32_4K	3204113         /* 32, 04, octal 'K'.  */
 #define CPU_MIPS5       5
 #define CPU_MIPS64      64
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
@@ -369,20 +370,19 @@ struct mips_opcode
 /* Test for membership in an ISA including chip specific ISAs.
    INSN is pointer to an element of the opcode table; ISA is the
    specified ISA to test against; and CPU is the CPU specific ISA
-   to test, or zero if no CPU specific ISA test is desired.
-   The gp32 arg is set when you need to force 32-bit register usage on
-   a machine with 64-bit registers; see the documentation under -mgp32
-   in the MIPS gas docs.  */
-
-#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32)				\
-    ((((insn)->membership & isa) != 0                           	\
-      && ((insn)->membership & INSN_GP32 ? gp32 : 1)			\
-     )									\
+   to test, or zero if no CPU specific ISA test is desired.  */
+
+#define OPCODE_IS_MEMBER(insn, isa, cpu)				\
+    (((insn)->membership & isa) != 0					\
      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)	\
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)	\
      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)			\
 	 && ((insn)->membership & INSN_4100) != 0)			\
-     || (cpu == CPU_R3900  && ((insn)->membership & INSN_3900) != 0))
+     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)	\
+     || ((cpu == CPU_R10000 || cpu == CPU_R12000)			\
+	 && ((insn)->membership & INSN_10000) != 0)			\
+     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)	\
+     || 0)	/* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.
 
@@ -508,6 +508,7 @@ enum
   M_LWR_A,
   M_LWR_AB,
   M_LWU_AB,
+  M_MOVE,
   M_MUL,
   M_MUL_I,
   M_MULO,