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author | cvs2svn <> | 2002-08-24 02:24:58 +0400 |
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committer | cvs2svn <> | 2002-08-24 02:24:58 +0400 |
commit | e3853f659096680f4953e1ec051d10b1f0ff084e (patch) | |
tree | 3d717dad9ee5b9d1d9427ec514dcb8759a12b5ce /include/opcode/ppc.h | |
parent | ce122f0260fafd437209005104cb0d6cf24b6817 (diff) |
This commit was manufactured by cvs2svn to create branch 'readline_4_3readline_4_3-import-branchpointcagney_sysregs-20020825-branchpointreadline_4_3-import-branchcagney_sysregs-20020825-branch
-import-branch'.
Sprout from binutils-2_13-branch 2002-07-11 20:14:42 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'binutils-'
Cherrypick from master 2002-08-23 22:24:57 UTC Andrew Cagney <cagney@gnu.org> '2002-08-23 Andrew Cagney <ac131313@redhat.com>':
ChangeLog
MAINTAINERS
Makefile.in
config.guess
config.sub
configure.in
include/ChangeLog
include/bfdlink.h
include/dis-asm.h
include/elf/ChangeLog
include/elf/common.h
include/elf/i370.h
include/elf/ip2k.h
include/elf/m68hc11.h
include/gdb/ChangeLog
include/gdb/remote-sim.h
include/gdb/sim-h8300.h
include/gdb/sim-sh.h
include/opcode/ChangeLog
include/opcode/m68hc11.h
include/opcode/mips.h
include/opcode/ppc.h
texinfo/texinfo.tex
Delete:
COPYING.LIBGLOSS
Diffstat (limited to 'include/opcode/ppc.h')
-rw-r--r-- | include/opcode/ppc.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index f7db66f63..ffd313acd 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -107,6 +107,30 @@ extern const int powerpc_num_opcodes; /* Opcode isn't supported by Power4 architecture. */ #define PPC_OPCODE_NOPOWER4 (040000) +/* Opcode is only supported by POWERPC Classic architecture. */ +#define PPC_OPCODE_CLASSIC (0100000) + +/* Opcode is only supported by e500x2 Core. */ +#define PPC_OPCODE_SPE (0200000) + +/* Opcode is supported by e500x2 Integer select APU. */ +#define PPC_OPCODE_ISEL (0400000) + +/* Opcode is an e500 SPE floating point instruction. */ +#define PPC_OPCODE_EFS (01000000) + +/* Opcode is supported by branch locking APU. */ +#define PPC_OPCODE_BRLOCK (02000000) + +/* Opcode is supported by performance monitor APU. */ +#define PPC_OPCODE_PMR (04000000) + +/* Opcode is supported by cache locking APU. */ +#define PPC_OPCODE_CACHELCK (010000000) + +/* Opcode is supported by machine check APU. */ +#define PPC_OPCODE_RFMCI (020000000) + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) |