diff options
| author | David S. Miller <davem@davemloft.net> | 2011-09-22 00:49:15 +0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-09-22 00:49:15 +0400 |
| commit | 7661a752ca8b830ec6f518dab08edb16646c03ff (patch) | |
| tree | 9ccc3d9d916599e7d8441fbfc6c82e74b1fe02a9 /include/opcode | |
| parent | 36b6320736dfd69ad4c07ea4ee0e0e5f10a3319d (diff) | |
Annotate sparc objects with cpu hardware capabilities used.
bfd/
* elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New.
* elfxx-sparc.h: Declare it.
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it.
* elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise.
binutils/
* readelf.c (display_sparc_hwcaps): New.
(display_sparc_gnu_attribute): New.
(process_sparc_specific): New.
(process_arch_specific): When EM_SPARC, EM_SPARC32PLUS,
or EM_SPARCV9 invoke process_sparc_specific.
gas/
* config/tc-sparc.c (hwcap_seen): New bitmask, defined when
not TE_SOLARIS.
(sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from
sparc_opcode->flags of instruction into hwcap_seen.
(sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if
hwcap_seen is non-zero and not TE_SOLARIS.
gas/testsuite/
* gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic.
* gas/sparc/hpcvis3.d: Likewise.
include/elf/
* sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute.
(ELF_SPARC_HWCAP_*): New HWCAPS bitmask values.
include/opcode/
* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
(F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
opcodes/
* sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
bits. Fix "fchksm16" mnemonic.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 7 | ||||
| -rw-r--r-- | include/opcode/sparc.h | 37 |
2 files changed, 35 insertions, 9 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index a69f7461d..8f070a10d 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,10 @@ +2011-09-21 David S. Miller <davem@davemloft.net> + + * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. + (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, + F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, + F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. + 2011-08-09 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h index 7203df756..7ae3641cf 100644 --- a/include/opcode/sparc.h +++ b/include/opcode/sparc.h @@ -1,6 +1,6 @@ /* Definitions for opcode table for the sparc. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, - 2003, 2005, 2010 Free Software Foundation, Inc. + 2003, 2005, 2010, 2011 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and the GNU Binutils. @@ -98,18 +98,37 @@ typedef struct sparc_opcode unsigned long lose; /* Bits that must not be set. */ const char *args; /* This was called "delayed" in versions before the flags. */ - char flags; + unsigned int flags; short architecture; /* Bitmask of sparc_opcode_arch_val's. */ } sparc_opcode; -#define F_DELAYED 1 /* Delayed branch. */ -#define F_ALIAS 2 /* Alias for a "real" instruction. */ -#define F_UNBR 4 /* Unconditional branch. */ -#define F_CONDBR 8 /* Conditional branch. */ -#define F_JSR 16 /* Subroutine call. */ -#define F_FLOAT 32 /* Floating point instruction (not a branch). */ -#define F_FBR 64 /* Floating point branch. */ /* FIXME: Add F_ANACHRONISTIC flag for v9. */ +#define F_DELAYED 0x00000001 /* Delayed branch. */ +#define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */ +#define F_UNBR 0x00000004 /* Unconditional branch. */ +#define F_CONDBR 0x00000008 /* Conditional branch. */ +#define F_JSR 0x00000010 /* Subroutine call. */ +#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */ +#define F_FBR 0x00000040 /* Floating point branch. */ +#define F_MUL32 0x00000100 /* umul/umulcc/smul/smulcc insns */ +#define F_DIV32 0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */ +#define F_FSMULD 0x00000400 /* 'fsmuld' insn */ +#define F_V8PLUS 0x00000800 /* v9 insns available to 32bit */ +#define F_POPC 0x00001000 /* 'popc' insn */ +#define F_VIS 0x00002000 /* VIS insns */ +#define F_VIS2 0x00004000 /* VIS2 insns */ +#define F_ASI_BLK_INIT 0x00008000 /* block init ASIs */ +#define F_FMAF 0x00010000 /* fused multiply-add */ +#define F_VIS3 0x00020000 /* VIS3 insns */ +#define F_HPC 0x00040000 /* HPC insns */ +#define F_RANDOM 0x00080000 /* 'random' insn */ +#define F_TRANS 0x00100000 /* transaction insns */ +#define F_FJFMAU 0x00200000 /* unfused multiply-add */ +#define F_IMA 0x00400000 /* integer multiply-add */ +#define F_ASI_CACHE_SPARING \ + 0x00800000 /* cache sparing ASIs */ + +#define F_HWCAP_MASK 0x00ffff00 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a macro), which is 64 bits. It is handled as a special case. |