diff options
| author | Chris Demetriou <cgd@broadcom.com> | 2001-10-18 05:50:26 +0400 |
|---|---|---|
| committer | Chris Demetriou <cgd@broadcom.com> | 2001-10-18 05:50:26 +0400 |
| commit | bd71a776e8811f2c4cb52c1fcb3df91c5f0f6394 (patch) | |
| tree | 058baa3d99d6e16ec9f8420853ccf6fea26f9805 /include/opcode | |
| parent | 90cb41d9e79199deb22d906f25b5dd81b680007b (diff) | |
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h: Sort coprocessor instruction argument characters
in comment, add a few more words of description for "H".
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/mips.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index cb547e3be..8bcb7fc65 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,5 +1,10 @@ 2001-10-17 Chris Demetriou <cgd@broadcom.com> + * mips.h: Sort coprocessor instruction argument characters + in comment, add a few more words of description for "H". + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + * mips.h (INSN_SB1): New cpu-specific instruction bit. (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 if cpu is CPU_SB1. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index b7a0fed88..8c24c85f9 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -209,8 +209,8 @@ struct mips_opcode Coprocessor instructions: "E" 5 bit target register (OP_*_RT) "G" 5 bit destination register (OP_*_RD) + "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) "P" 5 bit performance-monitor register (OP_*_PERFREG) - "H" 3 bit sel field (OP_*_SEL) Macro instructions: "A" General 32 bit expression |