diff options
| author | cvs2svn <> | 2002-02-10 01:54:17 +0300 |
|---|---|---|
| committer | cvs2svn <> | 2002-02-10 01:54:17 +0300 |
| commit | 34124a07180b9c8c7479517436c49292cfd12dcd (patch) | |
| tree | 75b8ab96fbc6007f3c2f5289a74119190b1c246c /include/opcode | |
| parent | 53c570dbbc783190848fb72380c42664c4a5e808 (diff) | |
This commit was manufactured by cvs2svn to create branch 'binutils-binutils-2_12-branchpoint
2_12-branch'.
Sprout from gdb_5_1-2001-07-29-branch 2001-07-26 14:20:06 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch'
Cherrypick from master 2002-02-09 22:54:16 UTC Richard Henderson <rth@redhat.com> ' * alpha.h (R_ALPHA_BRSGP): New.':
COPYING.NEWLIB
ChangeLog
MAINTAINERS
Makefile.in
config.guess
config.sub
configure
configure.in
etc/ChangeLog
etc/Makefile.in
gettext.m4
include/ChangeLog
include/ansidecl.h
include/aout/ChangeLog
include/aout/aout64.h
include/aout/hp300hpux.h
include/bfdlink.h
include/coff/ChangeLog
include/coff/arm.h
include/coff/external.h
include/coff/internal.h
include/coff/m88k.h
include/coff/or32.h
include/coff/ti.h
include/coff/tic54x.h
include/coff/xcoff.h
include/demangle.h
include/dis-asm.h
include/dyn-string.h
include/elf/ChangeLog
include/elf/alpha.h
include/elf/arm.h
include/elf/common.h
include/elf/dwarf2.h
include/elf/external.h
include/elf/h8.h
include/elf/ia64.h
include/elf/internal.h
include/elf/mips.h
include/elf/mmix.h
include/elf/or32.h
include/elf/ppc.h
include/elf/sh.h
include/elf/xstormy16.h
include/fibheap.h
include/filenames.h
include/floatformat.h
include/hashtab.h
include/libiberty.h
include/nlm/ChangeLog
include/nlm/common.h
include/objalloc.h
include/opcode/ChangeLog
include/opcode/alpha.h
include/opcode/arc.h
include/opcode/avr.h
include/opcode/cgen.h
include/opcode/d10v.h
include/opcode/d30v.h
include/opcode/h8300.h
include/opcode/hppa.h
include/opcode/i386.h
include/opcode/mips.h
include/opcode/mmix.h
include/opcode/or32.h
include/opcode/ppc.h
include/opcode/tic54x.h
include/opcode/v850.h
include/partition.h
include/safe-ctype.h
include/sort.h
include/splay-tree.h
include/xregex.h
libtool.m4
ltcf-c.sh
ltcf-cxx.sh
ltcf-gcj.sh
ltconfig
ltmain.sh
symlink-tree
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 220 | ||||
| -rw-r--r-- | include/opcode/alpha.h | 8 | ||||
| -rw-r--r-- | include/opcode/arc.h | 6 | ||||
| -rw-r--r-- | include/opcode/avr.h | 12 | ||||
| -rw-r--r-- | include/opcode/cgen.h | 38 | ||||
| -rw-r--r-- | include/opcode/d10v.h | 12 | ||||
| -rw-r--r-- | include/opcode/d30v.h | 2 | ||||
| -rw-r--r-- | include/opcode/h8300.h | 6 | ||||
| -rw-r--r-- | include/opcode/hppa.h | 192 | ||||
| -rw-r--r-- | include/opcode/i386.h | 9 | ||||
| -rw-r--r-- | include/opcode/mips.h | 31 | ||||
| -rw-r--r-- | include/opcode/mmix.h | 185 | ||||
| -rw-r--r-- | include/opcode/or32.h | 188 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 19 | ||||
| -rw-r--r-- | include/opcode/tic54x.h | 28 | ||||
| -rw-r--r-- | include/opcode/v850.h | 3 |
16 files changed, 768 insertions, 191 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index a027c8df7..3c367d3c8 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,147 @@ +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * or32.h: New file. + +2002-01-22 Graydon Hoare <graydon@redhat.com> + + * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. + (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. + +2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at> + + * h8300.h: Comment typo fix. + +2002-01-03 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. + (PPC_OPCODE_BOOKE64): Likewise. + +Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) + + * hppa.h (call, ret): Move to end of table. + (addb, addib): PA2.0 variants should have been PA2.0W. + (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler + happy. + (fldw, fldd, fstw, fstd, bb): Likewise. + (short loads/stores): Tweak format specifier slightly to keep + disassembler happy. + (indexed loads/stores): Likewise. + (absolute loads/stores): Likewise. + +2001-12-04 Alexandre Oliva <aoliva@redhat.com> + + * d10v.h (OPERAND_NOSP): New macro. + +2001-11-29 Alexandre Oliva <aoliva@redhat.com> + + * d10v.h (OPERAND_SP): New macro. + +2001-11-15 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * tic54x.h: Revise opcode layout; don't really need a separate + structure for parallel opcodes. + +2001-11-13 Zack Weinberg <zack@codesourcery.com> + Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to + accept WordReg. + +2001-11-04 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OPCODE_IS_MEMBER): Remove extra space. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix.h: New file. + +2001-10-18 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end + of the expression, to make source code merging easier. + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Sort coprocessor instruction argument characters + in comment, add a few more words of description for "H". + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h (INSN_SB1): New cpu-specific instruction bit. + (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 + if cpu is CPU_SB1. + +2001-10-17 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. + +2001-10-12 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New + opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 + instructions, respectively. + +2001-09-27 Nick Clifton <nickc@cambridge.redhat.com> + + * v850.h: Remove spurious comment. + +2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> + + * h8300.h: Fix compile time warning messages + +2001-09-04 Richard Henderson <rth@redhat.com> + + * alpha.h (struct alpha_operand): Pack elements into bitfields. + +2001-08-31 Eric Christopher <echristo@redhat.com> + + * mips.h: Remove CPU_MIPS32_4K. + +2001-08-27 Torbjorn Granlund <tege@swox.com> + + * ppc.h (PPC_OPERAND_DS): Define. + +2001-08-25 Andreas Jaeger <aj@suse.de> + + * d30v.h: Fix declaration of reg_name_cnt. + + * d10v.h: Fix declaration of d10v_reg_name_cnt. + + * arc.h: Add prototypes from opcodes/arc-opc.c. + +2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (INSN_10000): Define. + (OPCODE_IS_MEMBER): Check for INSN_10000. + +2001-08-10 Alan Modra <amodra@one.net.au> + + * ppc.h: Revert 2001-08-08. + +2001-08-10 Richard Sandiford <rsandifo@redhat.com> + + * mips.h (INSN_GP32): Remove. + (OPCODE_IS_MEMBER): Remove gp32 parameter. + (M_MOVE): New macro identifier. + +2001-08-08 Alan Modra <amodra@one.net.au> + + 1999-10-25 Torbjorn Granlund <tege@swox.com> + * ppc.h (struct powerpc_operand): New field `reloc'. + +2001-08-01 Aldy Hernandez <aldyh@redhat.com> + + * mips.h (INSN_ISA_MASK): Nuke bits 12-15. + +2001-07-12 Jeff Johnston <jjohnstn@redhat.com> + + * cgen.h (CGEN_INSN): Add regex support. + (build_insn_regex): Declare. + 2001-07-11 Frank Ch. Eigler <fche@redhat.com> * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. @@ -18,7 +162,7 @@ 2001-05-23 John Healy <jhealy@redhat.com> * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48. - + 2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> * mips.h (INSN_ISA_MASK): Define. @@ -155,7 +299,7 @@ * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field. - + 2000-12-12 Nick Clifton <nickc@redhat.com> * mips.h: Fix formatting. @@ -180,7 +324,7 @@ (ISA_UNKNOWN): New constant to indicate unknown ISA. (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, ISA_MIPS32): New constants, defined to be the mask of INSN_* - constants available at that ISA level. + constants available at that ISA level. (CPU_UNKNOWN): New constant to indicate unknown CPU. (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, define it with a unique value. @@ -188,7 +332,7 @@ constant meanings. * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New - definitions. + definitions. * mips.h (CPU_SB1): New constant. @@ -202,21 +346,21 @@ * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. 2000-09-13 Anders Norlander <anorland@acc.umu.se> - + * mips.h: Use defines instead of hard-coded processor numbers. (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, - CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, + CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, CPU_4KC, CPU_4KM, CPU_4KP): Define.. (OPCODE_IS_MEMBER): Use new defines. - (OP_MASK_SEL, OP_SH_SEL): Define. + (OP_MASK_SEL, OP_SH_SEL): Define. (OP_MASK_CODE20, OP_SH_CODE20): Define. - Add 'P' to used characters. - Use 'H' for coprocessor select field. + Add 'P' to used characters. + Use 'H' for coprocessor select field. Use 'm' for 20 bit breakpoint code. - Document new arg characters and add to used characters. - (INSN_MIPS32): New define for MIPS32 extensions. - (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. + Document new arg characters and add to used characters. + (INSN_MIPS32): New define for MIPS32 extensions. + (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. 2000-09-05 Alan Modra <alan@linuxcare.com.au> @@ -396,7 +540,7 @@ Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. (CGEN_CPU_TABLE): flags: new field. Add prototypes for new functions. - + 2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> * i386.h: Add some more UNIXWARE_COMPAT comments. @@ -514,7 +658,7 @@ Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) * hppa.h (pa_opcodes): Use 'fX' for first register operand - in xmpyu. + in xmpyu. * hppa.h (pa_opcodes): Fix mask for probe and probei. @@ -600,7 +744,7 @@ Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. - * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, + * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. 1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> @@ -628,7 +772,7 @@ Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) * hppa.h (pa_opcodes): Move integer arithmetic instructions after - integer logical instructions. + integer logical instructions. 1999-05-28 Linus Nordberg <linus.nordberg@canit.se> @@ -645,7 +789,7 @@ Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) - * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", "addb", and "addib" to be used by the disassembler. 1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> @@ -756,7 +900,7 @@ Sat Feb 13 14:13:44 1999 Richard Henderson <rth@cygnus.com> (CGEN_INSN_ATTR): New type. Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> - + * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. (x_FP, d_FP, dls_FP, sldx_FP): Define. Change *Suf definitions to include x and d suffixes. @@ -797,16 +941,16 @@ Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com> The following is part of a change made by Edith Epstein - <eepstein@sophia.cygnus.com> as part of a project to merge in - changes by HP; HP did not create ChangeLog entries. + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes by HP; HP did not create ChangeLog entries. * hppa.h (completer_chars): list of chars to not put a space - after. + after. Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com> * i386.h (i386_optab): Permit w suffix on processor control and - status word instructions. + status word instructions. 1998-11-30 Doug Evans <devans@casey.cygnus.com> @@ -867,7 +1011,7 @@ Fri Oct 9 13:38:13 1998 Doug Evans <devans@seba.cygnus.com> Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) * hppa.h: Add "fid". - + Sun Oct 4 21:00:00 1998 Alan Modra <alan@spri.levels.unisa.edu.au> From Robert Andrew Dale <rob@nb.net> @@ -921,7 +1065,7 @@ Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) * mn10300.h: Add "machine" field for instructions. (MN103, AM30): Define machine types. - + Fri Jun 19 16:09:09 1998 Alan Modra <alan@spri.levels.unisa.edu.au> * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. @@ -1526,9 +1670,9 @@ Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com) Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu> * alpha.h: Don't include "bfd.h"; private relocation types are now - negative to minimize problems with shared libraries. Organize - instruction subsets by AMASK extensions and PALcode - implementation. + negative to minimize problems with shared libraries. Organize + instruction subsets by AMASK extensions and PALcode + implementation. (struct alpha_operand): Move flags slot for better packing. Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) @@ -1581,9 +1725,9 @@ Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com> * v850.h (v850_operands): Add insert and extract fields, pointers - to functions used to handle unusual operand encoding. + to functions used to handle unusual operand encoding. (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, - V850_OPERAND_SIGNED): Defined. + V850_OPERAND_SIGNED): Defined. Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com> @@ -1597,11 +1741,11 @@ Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com> Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk> * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, - OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, - OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, - OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, - OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): - Defined. + OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, + OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, + OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, + OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): + Defined. Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) @@ -1611,7 +1755,7 @@ Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * d10v.h: Add some additional defines to support the - assembler in determining which operations can be done in parallel. + assembler in determining which operations can be done in parallel. Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com) @@ -1627,7 +1771,7 @@ Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com> Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * d10v.h: Changes for divs, parallel-only instructions, and - signed numbers. + signed numbers. Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com> @@ -1649,7 +1793,7 @@ Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com> - * m68k.h (mcf5200): New macro. + * m68k.h (mcf5200): New macro. Document names of coldfire control registers. Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com) @@ -1799,7 +1943,7 @@ Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com) Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific - instructions. + instructions. Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com> diff --git a/include/opcode/alpha.h b/include/opcode/alpha.h index 6f31e9ae0..487b69605 100644 --- a/include/opcode/alpha.h +++ b/include/opcode/alpha.h @@ -81,16 +81,16 @@ extern const unsigned alpha_num_opcodes; struct alpha_operand { /* The number of bits in the operand. */ - int bits; + unsigned int bits : 5; /* How far the operand is left shifted in the instruction. */ - int shift; + unsigned int shift : 5; /* The default relocation type for this operand. */ - int default_reloc; + signed int default_reloc : 16; /* One bit syntax flags. */ - unsigned flags; + unsigned int flags : 16; /* Insertion function. This is used by the assembler. To insert an operand value into an instruction, check this field. diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 81e5bd847..b13784015 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -313,3 +313,9 @@ const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value)); int arc_opcode_supported PARAMS ((const struct arc_opcode *)); int arc_opval_supported PARAMS ((const struct arc_operand_value *)); +int arc_limm_fixup_adjust PARAMS ((arc_insn)); +int arc_insn_is_j PARAMS ((arc_insn)); +int arc_insn_not_jl PARAMS ((arc_insn)); +int arc_operand_type PARAMS ((int)); +struct arc_operand_value *get_ext_suffix PARAMS ((char *)); +int arc_get_noshortcut_flag PARAMS ((void)); diff --git a/include/opcode/avr.h b/include/opcode/avr.h index 393ca22d6..bcc093d30 100644 --- a/include/opcode/avr.h +++ b/include/opcode/avr.h @@ -25,17 +25,20 @@ supported, no 8K wrap on RJMP and RCALL) */ #define AVR_ISA_MUL 0x0040 /* device has new core (MUL, MOVW, ...) */ #define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ -#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] (none yet) */ +#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ #define AVR_ISA_SPM 0x0200 /* device can program itself */ +#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ #define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) -#define AVR_ISA_M83 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) #define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) #define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) #define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) #define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX) +#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) +#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) #define AVR_ISA_ALL 0xFFFF @@ -86,7 +89,7 @@ Order is important - some binary opcodes have more than one name, the disassembler will only see the first match. - Remaining undefined opcodes (1700 total - some of them might work + Remaining undefined opcodes (1699 total - some of them might work as normal instructions if not all of the bits are decoded): 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) @@ -100,7 +103,7 @@ "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b "10010101001x1000" (2) 0x95[23]8 "1001010101xx1000" (4) 0x95[4-7]8 - "1001010110x11000" (2) 0x95[9b]8 + "1001010110111000" (1) 0x95b8 "1001010111111000" (1) 0x95f8 (`espm' removed in databook update) "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f] */ @@ -139,6 +142,7 @@ AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000) AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508) AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518) AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588) +AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598) AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8) AVR_INSN (spm, "", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8) diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index bcde4729a..09c5cbf03 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -26,7 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc., Perhaps the definition of bfd_vma can be moved outside of bfd.h. Or perhaps one could duplicate its definition in another file. Until such time, this file conditionally compiles definitions that require - bfd_vma using BFD_VERSION. */ + bfd_vma using BFD_VERSION_DATE. */ /* Enums must be defined before they can be used. Allow them to be used in struct definitions, even though the enum must @@ -276,7 +276,7 @@ typedef const char * (cgen_parse_fn) PC is the pc value of the insn. The result is an error message or NULL if success. */ -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE typedef const char * (cgen_insert_fn) PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, @@ -297,7 +297,7 @@ typedef const char * (cgen_insert_fn) (); PC is the pc value of the insn. The result is the length of the insn in bits or zero if not recognized. */ -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE typedef int (cgen_extract_fn) PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, @@ -316,7 +316,7 @@ typedef int (cgen_extract_fn) (); PC is the pc value of the insn. LEN is the length of the insn, in bits. */ -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE typedef void (cgen_print_fn) PARAMS ((CGEN_CPU_DESC, PTR info_, const CGEN_INSN *insn_, CGEN_FIELDS *fields_, bfd_vma pc_, int len_)); @@ -381,7 +381,7 @@ enum cgen_parse_operand_result CGEN_PARSE_OPERAND_RESULT_ERROR }; -#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ +#ifdef BFD_VERSION_DATE /* Don't require bfd.h unnecessarily. */ typedef const char * (cgen_parse_operand_fn) PARAMS ((CGEN_CPU_DESC, enum cgen_parse_operand_type, const char **, int, int, @@ -565,7 +565,7 @@ const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next extern const char *cgen_parse_keyword PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); -#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ +#ifdef BFD_VERSION_DATE /* Don't require bfd.h unnecessarily. */ extern const char *cgen_parse_signed_integer PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); extern const char *cgen_parse_unsigned_integer @@ -609,6 +609,23 @@ enum cgen_operand_type { CGEN_OPERAND_MAX }; /* "nil" indicator for the operand instance table */ #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX +/* A tree of these structs represents the multi-ifield + structure of an operand's hw-index value, if it exists. */ + +struct cgen_ifld; + +typedef struct cgen_maybe_multi_ifield +{ + int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); + n: indexed by array of more cgen_maybe_multi_ifields. */ + union + { + struct cgen_maybe_multi_ifield * multi; + struct cgen_ifld * leaf; + } val; +} +CGEN_MAYBE_MULTI_IFLD; + /* This struct defines each entry in the operand table. */ typedef struct @@ -637,6 +654,11 @@ typedef struct May be unused for a modifier. */ unsigned char length; + /* The (possibly-multi) ifield used as an index for this operand, if it + is indexed by a field at all. This substitutes / extends the start and + length fields above, but unsure at this time whether they are used + anywhere. */ + CGEN_MAYBE_MULTI_IFLD index_fields; #if 0 /* ??? Interesting idea but relocs tend to get too complicated, and ABI dependent, for simple table lookups to work. */ /* Ideally this would be the internal (external?) reloc type. */ @@ -1231,7 +1253,7 @@ typedef struct cgen_cpu_desc const char * (*parse_operand) PARAMS ((CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_)); -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE const char * (*insert_operand) PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR, bfd_vma pc_)); @@ -1264,7 +1286,7 @@ typedef struct cgen_cpu_desc PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); void (*set_int_operand) PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_)); -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE bfd_vma (*get_vma_operand) PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); void (*set_vma_operand) diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h index a1fe770a7..cc27850b0 100644 --- a/include/opcode/d10v.h +++ b/include/opcode/d10v.h @@ -1,5 +1,5 @@ /* d10v.h -- Header file for D10V opcode table - Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -181,6 +181,14 @@ extern const struct d10v_operand d10v_operands[]; /* needed for rac/rachi */ #define RESTRICTED_NUM3 (0x80000) +/* Pre-decrement is only supported for SP. */ +#define OPERAND_SP (0x100000) + +/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and + unlike OPERAND_SP, this flag doesn't prevent the instruction from + matching, it only fails validation later on. */ +#define OPERAND_NOSP (0x200000) + /* Structure to hold information about predefined registers. */ struct pd_reg { @@ -190,7 +198,7 @@ struct pd_reg }; extern const struct pd_reg d10v_predefined_registers[]; -int d10v_reg_name_cnt(); +int d10v_reg_name_cnt PARAMS ((void)); /* an expressionS only has one register type, so we fake it */ /* by setting high bits to indicate type */ diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h index 6cbc2576e..c18874b66 100644 --- a/include/opcode/d30v.h +++ b/include/opcode/d30v.h @@ -32,7 +32,7 @@ struct pd_reg }; extern const struct pd_reg pre_defined_registers[]; -int reg_name_cnt(); +int reg_name_cnt PARAMS ((void)); /* the number of control registers */ #define MAX_CONTROL_REG 64 diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h index 7ea87982c..9cd40a6cb 100644 --- a/include/opcode/h8300.h +++ b/include/opcode/h8300.h @@ -1,5 +1,5 @@ /* Opcode table for the H8/300 - Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000 + Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002 Free Software Foundation, Inc. Written by Steve Chamberlain <sac@cygnus.com>. @@ -21,7 +21,7 @@ 02111-1307, USA. */ /* Instructions are stored as a sequence of nibbles. - If the nibble has value 15 or less then the representation is complete. + If the nibble has value 15 or less than the representation is complete. Otherwise, we record what it contains with several flags. */ typedef int op_type; @@ -594,7 +594,7 @@ struct h8_opcode h8_opcodes[] = NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MACREG,RD32,E}},{{0x0,0x2,MACREG,RD32,E}} EOP, NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP, NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP, - { 0 } + {0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}, 0, 0, 0, 0} }; #else extern struct h8_opcode h8_opcodes[]; diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h index f409ac94b..e90709142 100644 --- a/include/opcode/hppa.h +++ b/include/opcode/hppa.h @@ -170,10 +170,16 @@ Also these: Completer operands all have 'c' as the prefix: cx indexed load completer. + cX indexed load completer. Like cx, but emits a space after + in disassembler. cm short load and store completer. + cM short load and store completer. Like cm, but emits a space + after in disassembler. cq long load and store completer (like cm, but inserted into a different location in the target instruction). cs store bytes short completer. + cA store bytes short completer. Like cs, but emits a space + after in disassembler. ce long load/store completer for LDW/STW with a different encoding than the others cc load cache control hint @@ -285,10 +291,6 @@ static const struct pa_opcode pa_opcodes[] = { "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */ { "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ -{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, -{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, -{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, - { "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, { "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, { "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ @@ -301,12 +303,12 @@ static const struct pa_opcode pa_opcodes[] = /* This entry is for the disassembler only. It will never be used by assembler. */ { "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ -{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20, FLAG_STRICT}, +{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT}, { "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ /* This entry is for the disassembler only. It will never be used by assembler. */ { "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, -{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20, FLAG_STRICT}, +{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT}, { "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ /* This entry is for the disassembler only. It will never be used by assembler. */ @@ -327,10 +329,10 @@ static const struct pa_opcode pa_opcodes[] = { "ldd", 0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, { "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, { "ldw", 0x0c000080, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, { "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT}, { "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, { "ldw", 0x4c000000, 0xfc000000, "ceJ(b),x", pa10, FLAG_STRICT}, @@ -342,19 +344,19 @@ static const struct pa_opcode pa_opcodes[] = { "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10, 0}, { "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, { "ldh", 0x0c000040, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, { "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, { "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, { "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10, 0}, { "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, { "ldb", 0x0c000000, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, -{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, { "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, { "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, { "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10, 0}, @@ -364,10 +366,10 @@ static const struct pa_opcode pa_opcodes[] = { "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, { "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT}, { "std", 0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, { "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT}, { "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT}, { "stw", 0x6c000000, 0xfc000000, "cex,J(b)", pa10, FLAG_STRICT}, @@ -377,17 +379,17 @@ static const struct pa_opcode pa_opcodes[] = { "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, { "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, { "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10, 0}, -{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, { "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, { "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, { "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10, 0}, -{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, { "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, { "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, { "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10, 0}, @@ -395,20 +397,20 @@ static const struct pa_opcode pa_opcodes[] = { "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10, 0}, { "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, { "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10, 0}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, 0}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, 0}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(b),t", pa10, 0}, { "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa10, FLAG_STRICT}, { "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa10, FLAG_STRICT}, { "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa10, FLAG_STRICT}, { "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa10, FLAG_STRICT}, { "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa10, FLAG_STRICT}, { "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa10, FLAG_STRICT}, -{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa10, FLAG_STRICT}, { "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa10, FLAG_STRICT}, { "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, @@ -421,29 +423,29 @@ static const struct pa_opcode pa_opcodes[] = { "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, { "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, 0}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, 0}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, 0}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, 0}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, 0}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, 0}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, 0}, -{ "stws", 0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, -{ "stws", 0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, 0}, -{ "sths", 0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, -{ "sths", 0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, 0}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, 0}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, 0}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, { "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, { "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, 0}, -{ "stbys", 0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(b)", pa10, 0}, /* Immediate instructions. */ { "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0}, @@ -482,10 +484,10 @@ static const struct pa_opcode pa_opcodes[] = { "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, { "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, { "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, -{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, { "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, { "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, +{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, { "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, { "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, { "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, @@ -701,46 +703,46 @@ static const struct pa_opcode pa_opcodes[] = /* Floating Point Coprocessor Instructions. */ -{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, -{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, { "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa10, FLAG_STRICT}, { "fldw", 0x24000000, 0xfc001380, "cxccx(b),fT", pa10, FLAG_STRICT}, { "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa10, FLAG_STRICT}, { "fldw", 0x24001000, 0xfc001380, "cmcc5(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, { "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT}, { "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT}, { "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT}, { "fldw", 0x58000000, 0xfc000000, "cJd(b),fe", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, { "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa10, FLAG_STRICT}, { "fldd", 0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa10, FLAG_STRICT}, { "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa10, FLAG_STRICT}, { "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, { "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT}, { "fldd", 0x50000002, 0xfc000002, "cq#(b),fx", pa20, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT}, { "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa10, FLAG_STRICT}, { "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(b)", pa10, FLAG_STRICT}, { "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa10, FLAG_STRICT}, { "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT}, { "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT}, { "fstw", 0x78000000, 0xfc000000, "cJfe,y(b)", pa20w, FLAG_STRICT}, { "fstw", 0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT}, { "fstw", 0x78000000, 0xfc000000, "cJfe,d(b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT}, { "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa10, FLAG_STRICT}, { "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa10, FLAG_STRICT}, { "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa10, FLAG_STRICT}, { "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT}, { "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT}, { "fstd", 0x70000002, 0xfc000002, "cqfx,#(b)", pa20, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10, 0}, -{ "fldwx", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10, 0}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, 0}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(b),fT", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(b),ft", pa10, 0}, { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0}, { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, @@ -815,38 +817,44 @@ static const struct pa_opcode pa_opcodes[] = { "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, { "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, { "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, 0}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, 0}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, 0}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, 0}, -{ "cldws", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0}, -{ "cldws", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, 0}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa10, 0}, -{ "cstws", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0}, -{ "cstws", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, 0}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, 0}, -{ "cldw", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, 0}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa20, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, + +/* More pseudo instructions which must follow the main table. */ +{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, +{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, + }; #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) diff --git a/include/opcode/i386.h b/include/opcode/i386.h index 38de44aca..571990e1b 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -553,9 +553,12 @@ static const template i386_optab[] = { {"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 7fd4703e5..1469e1072 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -209,8 +209,8 @@ struct mips_opcode Coprocessor instructions: "E" 5 bit target register (OP_*_RT) "G" 5 bit destination register (OP_*_RD) + "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) "P" 5 bit performance-monitor register (OP_*_PERFREG) - "H" 3 bit sel field (OP_*_SEL) Macro instructions: "A" General 32 bit expression @@ -307,7 +307,7 @@ struct mips_opcode ORs of these bits, indicatingthat they support the instructions defined at the given level. */ -#define INSN_ISA_MASK 0x0000ffff +#define INSN_ISA_MASK 0x00000fff #define INSN_ISA1 0x00000010 #define INSN_ISA2 0x00000020 #define INSN_ISA3 0x00000040 @@ -326,8 +326,10 @@ struct mips_opcode #define INSN_4100 0x00040000 /* Toshiba R3900 instruction. */ #define INSN_3900 0x00080000 -/* 32-bit code running on a ISA3+ CPU. */ -#define INSN_GP32 0x00100000 +/* MIPS R10000 instruction. */ +#define INSN_10000 0x00100000 +/* Broadcom SB-1 instruction. */ +#define INSN_SB1 0x00200000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -361,7 +363,6 @@ struct mips_opcode #define CPU_R12000 12000 #define CPU_MIPS16 16 #define CPU_MIPS32 32 -#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K'. */ #define CPU_MIPS5 5 #define CPU_MIPS64 64 #define CPU_SB1 12310201 /* octal 'SB', 01. */ @@ -369,20 +370,19 @@ struct mips_opcode /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. - The gp32 arg is set when you need to force 32-bit register usage on - a machine with 64-bit registers; see the documentation under -mgp32 - in the MIPS gas docs. */ - -#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \ - ((((insn)->membership & isa) != 0 \ - && ((insn)->membership & INSN_GP32 ? gp32 : 1) \ - ) \ + to test, or zero if no CPU specific ISA test is desired. */ + +#define OPCODE_IS_MEMBER(insn, isa, cpu) \ + (((insn)->membership & isa) != 0 \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ && ((insn)->membership & INSN_4100) != 0) \ - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)) + || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ + || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ + && ((insn)->membership & INSN_10000) != 0) \ + || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ + || 0) /* Please keep this term for easier source merging. */ /* This is a list of macro expanded instructions. @@ -508,6 +508,7 @@ enum M_LWR_A, M_LWR_AB, M_LWU_AB, + M_MOVE, M_MUL, M_MUL_I, M_MULO, diff --git a/include/opcode/mmix.h b/include/opcode/mmix.h new file mode 100644 index 000000000..825eb0e24 --- /dev/null +++ b/include/opcode/mmix.h @@ -0,0 +1,185 @@ +/* mmix.h -- Header file for MMIX opcode table + Copyright (C) 2001 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version 2, +or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We could have just a char*[] table indexed by the register number, but + that would not allow for synonyms. The table is terminated with an + entry with a NULL name. */ +struct mmix_spec_reg +{ + const char *name; + unsigned int number; +}; + +/* General indication of the type of instruction. */ +enum mmix_insn_type + { + mmix_type_pseudo, + mmix_type_normal, + mmix_type_branch, + mmix_type_condbranch, + mmix_type_memaccess_octa, + mmix_type_memaccess_tetra, + mmix_type_memaccess_wyde, + mmix_type_memaccess_byte, + mmix_type_memaccess_block, + mmix_type_jsr + }; + +/* Type of operands an instruction takes. Use when parsing assembly code + and disassembling. */ +enum mmix_operands_type + { + mmix_operands_none = 0, + + /* All operands are registers: "$X,$Y,$Z". */ + mmix_operands_regs, + + /* "$X,YZ", like SETH. */ + mmix_operands_reg_yz, + + /* The regular "$X,$Y,$Z|Z". + The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is + assumed. */ + mmix_operands_regs_z_opt, + + /* The regular "$X,$Y,$Z|Z". */ + mmix_operands_regs_z, + + /* "Address"; only JMP. Zero operands allowed unless GNU syntax. */ + mmix_operands_jmp, + + /* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an + integer. */ + mmix_operands_pushgo, + + /* Two registers or a register and a byte, like FLOT, possibly with + rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z". */ + mmix_operands_roundregs_z, + + /* "X,YZ", POP. Unless GNU syntax, zero or one operand is allowed. */ + mmix_operands_pop, + + /* Two registers, possibly with rounding: "$X,$Z" or + "$X,ROUND_MODE,$Z". */ + mmix_operands_roundregs, + + /* "XYZ", like SYNC. */ + mmix_operands_sync, + + /* "X,$Y,$Z|Z", like SYNCD. */ + mmix_operands_x_regs_z, + + /* "$X,Y,$Z|Z", like NEG and NEGU. The Y field is optional, default 0. */ + mmix_operands_neg, + + /* "$X,Address, like GETA or branches. */ + mmix_operands_regaddr, + + /* "$X|X,Address, like PUSHJ. */ + mmix_operands_pushj, + + /* "$X,spec_reg"; GET. */ + mmix_operands_get, + + /* "spec_reg,$Z|Z"; PUT. */ + mmix_operands_put, + + /* Two registers, "$X,$Y". */ + mmix_operands_set, + + /* "$X,0"; SAVE. */ + mmix_operands_save, + + /* "0,$Z"; UNSAVE. */ + mmix_operands_unsave, + + /* "X,Y,Z"; like SWYM or TRAP. Zero (or 1 if GNU syntax) to three + operands, interpreted as 0; XYZ; X, YZ and X, Y, Z. */ + mmix_operands_xyz_opt, + + /* Just "Z", like RESUME. Unless GNU syntax, the operand can be omitted + and will then be assumed zero. */ + mmix_operands_resume, + + /* These are specials to handle that pseudo-directives are specified + like ordinary insns when being mmixal-compatible. They signify the + specific pseudo-directive rather than the operands type. */ + + /* LOC. */ + mmix_operands_loc, + + /* PREFIX. */ + mmix_operands_prefix, + + /* BYTE. */ + mmix_operands_byte, + + /* WYDE. */ + mmix_operands_wyde, + + /* TETRA. */ + mmix_operands_tetra, + + /* OCTA. */ + mmix_operands_octa, + + /* LOCAL. */ + mmix_operands_local, + + /* BSPEC. */ + mmix_operands_bspec, + + /* ESPEC. */ + mmix_operands_espec, + }; + +struct mmix_opcode + { + const char *name; + unsigned long match; + unsigned long lose; + enum mmix_operands_type operands; + + /* This is used by the disassembly function. */ + enum mmix_insn_type type; + }; + +/* Declare the actual tables. */ +extern const struct mmix_opcode mmix_opcodes[]; + +/* This one is terminated with an entry with a NULL name. */ +extern const struct mmix_spec_reg mmix_spec_regs[]; + +/* Some insn values we use when padding and synthesizing address loads. */ +#define IMM_OFFSET_BIT 1 +#define COND_INV_BIT 0x8 +#define PRED_INV_BIT 0x10 + +#define PUSHGO_INSN_BYTE 0xbe +#define GO_INSN_BYTE 0x9e +#define SETL_INSN_BYTE 0xe3 +#define INCML_INSN_BYTE 0xe6 +#define INCMH_INSN_BYTE 0xe5 +#define INCH_INSN_BYTE 0xe4 +#define SWYM_INSN_BYTE 0xfd + +/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable) + global registers. */ +#define MAX_GREGS 223 diff --git a/include/opcode/or32.h b/include/opcode/or32.h new file mode 100644 index 000000000..05c532667 --- /dev/null +++ b/include/opcode/or32.h @@ -0,0 +1,188 @@ +/* Table of opcodes for the OpenRISC 1000 ISA. + Copyright 2002 Free Software Foundation, Inc. + Contributed by Damjan Lampret (lampret@opencores.org). + + This file is part of or1k_gen_isa, or1ksim, GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We treat all letters the same in encode/decode routines so + we need to assign some characteristics to them like signess etc. */ + +#ifndef OR32_H_ISA +#define OR32_H_ISA + +#define NUM_UNSIGNED (0) +#define NUM_SIGNED (1) + +#ifndef PARAMS +#define PARAMS(x) x +#endif + +#ifndef CONST +#define CONST const +#endif + +#define MAX_GPRS 32 +#define PAGE_SIZE 4096 +#undef __HALF_WORD_INSN__ + +#define OPERAND_DELIM (',') + +#define OR32_IF_DELAY (1) +#define OR32_W_FLAG (2) +#define OR32_R_FLAG (4) + +struct or32_letter +{ + char letter; + int sign; + /* int reloc; relocation per letter ?? */ +}; + +/* Main instruction specification array. */ +struct or32_opcode +{ + /* Name of the instruction. */ + char *name; + + /* A string of characters which describe the operands. + Valid characters are: + ,() Itself. Characters appears in the assembly code. + rA Register operand. + rB Register operand. + rD Register operand. + I An immediate operand, range -32768 to 32767. + J An immediate operand, range . (unused) + K An immediate operand, range 0 to 65535. + L An immediate operand, range 0 to 63. + M An immediate operand, range . (unused) + N An immediate operand, range -33554432 to 33554431. + O An immediate operand, range . (unused). */ + char *args; + + /* Opcode and operand encoding. */ + char *encoding; + void (*exec) PARAMS ((void)); + unsigned int flags; +}; + +#define OPTYPE_LAST (0x80000000) +#define OPTYPE_OP (0x40000000) +#define OPTYPE_REG (0x20000000) +#define OPTYPE_SIG (0x10000000) +#define OPTYPE_DIS (0x08000000) +#define OPTYPE_DST (0x04000000) +#define OPTYPE_SBIT (0x00001F00) +#define OPTYPE_SHR (0x0000001F) +#define OPTYPE_SBIT_SHR (8) + +/* MM: Data how to decode operands. */ +extern struct insn_op_struct +{ + unsigned long type; + unsigned long data; +} **op_start; + +#ifdef HAS_EXECUTION +extern void l_invalid PARAMS ((void)); +extern void l_sfne PARAMS ((void)); +extern void l_bf PARAMS ((void)); +extern void l_add PARAMS ((void)); +extern void l_sw PARAMS ((void)); +extern void l_sb PARAMS ((void)); +extern void l_sh PARAMS ((void)); +extern void l_lwz PARAMS ((void)); +extern void l_lbs PARAMS ((void)); +extern void l_lbz PARAMS ((void)); +extern void l_lhs PARAMS ((void)); +extern void l_lhz PARAMS ((void)); +extern void l_movhi PARAMS ((void)); +extern void l_and PARAMS ((void)); +extern void l_or PARAMS ((void)); +extern void l_xor PARAMS ((void)); +extern void l_sub PARAMS ((void)); +extern void l_mul PARAMS ((void)); +extern void l_div PARAMS ((void)); +extern void l_divu PARAMS ((void)); +extern void l_sll PARAMS ((void)); +extern void l_sra PARAMS ((void)); +extern void l_srl PARAMS ((void)); +extern void l_j PARAMS ((void)); +extern void l_jal PARAMS ((void)); +extern void l_jalr PARAMS ((void)); +extern void l_jr PARAMS ((void)); +extern void l_rfe PARAMS ((void)); +extern void l_nop PARAMS ((void)); +extern void l_bnf PARAMS ((void)); +extern void l_sfeq PARAMS ((void)); +extern void l_sfgts PARAMS ((void)); +extern void l_sfges PARAMS ((void)); +extern void l_sflts PARAMS ((void)); +extern void l_sfles PARAMS ((void)); +extern void l_sfgtu PARAMS ((void)); +extern void l_sfgeu PARAMS ((void)); +extern void l_sfltu PARAMS ((void)); +extern void l_sfleu PARAMS ((void)); +extern void l_mtspr PARAMS ((void)); +extern void l_mfspr PARAMS ((void)); +extern void l_sys PARAMS ((void)); +extern void l_trap PARAMS ((void)); /* CZ 21/06/01. */ +extern void l_macrc PARAMS ((void)); +extern void l_mac PARAMS ((void)); +extern void l_msb PARAMS ((void)); +extern void l_invalid PARAMS ((void)); +extern void l_cust1 PARAMS ((void)); +extern void l_cust2 PARAMS ((void)); +extern void l_cust3 PARAMS ((void)); +extern void l_cust4 PARAMS ((void)); +#endif +extern void l_none PARAMS ((void)); + +extern const struct or32_letter or32_letters[]; + +extern const struct or32_opcode or32_opcodes[]; + +extern const unsigned int or32_num_opcodes; + +/* Calculates instruction length in bytes. Always 4 for OR32. */ +extern int insn_len PARAMS ((int)); + +/* Is individual insn's operand signed or unsigned? */ +extern int letter_signed PARAMS ((char)); + +/* Number of letters in the individual lettered operand. */ +extern int letter_range PARAMS ((char)); + +/* MM: Returns index of given instruction name. */ +extern int insn_index PARAMS ((char *)); + +/* MM: Returns instruction name from index. */ +extern const char *insn_name PARAMS ((int)); + +/* MM: Constructs new FSM, based on or32_opcodes. */ +extern void build_automata PARAMS ((void)); + +/* MM: Destructs FSM. */ +extern void destruct_automata PARAMS ((void)); + +/* MM: Decodes instruction using FSM. Call build_automata first. */ +extern int insn_decode PARAMS ((unsigned int)); + +/* Disassemble one instruction from insn to disassemble. + Return the size of the instruction. */ +int disassemble_insn PARAMS ((unsigned long)); + +#endif diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index d23e1c695..dc3983ec0 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -1,5 +1,5 @@ /* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000 Free Software Foundation, Inc. + Copyright 1994, 1995, 1999, 2000, 2001 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -89,7 +89,16 @@ extern const int powerpc_num_opcodes; #define PPC_OPCODE_64_BRIDGE (0400) /* Opcode is supported by Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC (01000) +#define PPC_OPCODE_ALTIVEC (01000) + +/* Opcode is supported by PowerPC 403 processor. */ +#define PPC_OPCODE_403 (02000) + +/* Opcode is supported by PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE (04000) + +/* Opcode is only supported by 64-bit PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE64 (010000) /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -121,6 +130,7 @@ struct powerpc_operand operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ unsigned long (*insert) PARAMS ((unsigned long instruction, long op, + int dialect, const char **errmsg)); /* Extraction function. This is used by the disassembler. To @@ -140,7 +150,8 @@ struct powerpc_operand non-zero if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - long (*extract) PARAMS ((unsigned long instruction, int *invalid)); + long (*extract) PARAMS ((unsigned long instruction, int dialect, + int *invalid)); /* One bit syntax flags. */ unsigned long flags; @@ -229,6 +240,8 @@ extern const struct powerpc_operand powerpc_operands[]; prints these with a leading 'v'. */ #define PPC_OPERAND_VR (010000) +/* This operand is for the DS field in a DS form instruction. */ +#define PPC_OPERAND_DS (020000) /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an diff --git a/include/opcode/tic54x.h b/include/opcode/tic54x.h index 09ee8c903..ae657225d 100644 --- a/include/opcode/tic54x.h +++ b/include/opcode/tic54x.h @@ -19,8 +19,8 @@ along with this file; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#ifndef _TIC54X_H_ -#define _TIC54X_H_ +#ifndef _opcode_tic54x_h_ +#define _opcode_tic54x_h_ typedef struct _symbol { @@ -86,7 +86,6 @@ typedef struct _template { /* The opcode mnemonic */ const char *name; - unsigned int words; /* insn size in words */ int minops, maxops; /* min/max operand count */ /* The significant bits in the opcode. Other bits are zero. @@ -141,27 +140,24 @@ typedef struct _template #define FL_NR 0x100 /* no repeat allowed */ #define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */ - unsigned short opcode2, mask2; /* some insns have an extended opcode */ +#define FL_PAR 0x400 /* Parallel instruction. */ -} template; + unsigned short opcode2, mask2; /* some insns have an extended opcode */ -typedef struct _partemplate { - char *name; - char *parname; - unsigned int words; /* length in words */ - int minops, maxops; /* min/max operand count for 2nd part of insn */ - unsigned short opcode; - unsigned short mask; - enum optype operand_types[MAX_OPERANDS]; + const char* parname; enum optype paroperand_types[MAX_OPERANDS]; -} partemplate; + +} template; extern const template tic54x_unknown_opcode; extern const template tic54x_optab[]; -extern const partemplate tic54x_paroptab[]; +extern const template tic54x_paroptab[]; extern const symbol mmregs[], regs[]; extern const symbol condition_codes[], cc2_codes[], status_bits[]; extern const symbol cc3_codes[]; extern const char *misc_symbols[]; +struct disassemble_info; +extern const template* tic54x_get_insn (struct disassemble_info *, + bfd_vma, unsigned short, int *); -#endif /* TIC54X_H */ +#endif /* _opcode_tic54x_h_ */ diff --git a/include/opcode/v850.h b/include/opcode/v850.h index 737faf88d..2183bc858 100644 --- a/include/opcode/v850.h +++ b/include/opcode/v850.h @@ -1,5 +1,5 @@ /* v850.h -- Header file for NEC V850 opcode table - Copyright 1996, 1997 Free Software Foundation, Inc. + Copyright 1996, 1997, 2001 Free Software Foundation, Inc. Written by J.T. Conklin, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -153,7 +153,6 @@ extern const struct v850_operand v850_operands[]; /* The register specified must not be r0 */ #define V850_NOT_R0 0x80 -/* CYGNUS LOCAL v850e */ /* push/pop type instruction, V850E specific. */ #define V850E_PUSH_POP 0x100 |