diff options
| author | cvs2svn <> | 2000-04-04 18:32:33 +0400 |
|---|---|---|
| committer | cvs2svn <> | 2000-04-04 18:32:33 +0400 |
| commit | 69b6206fef6dd986a554334b6519b0543cab4f5e (patch) | |
| tree | 1092995ccf9aad86f4c3e43be94406c03d02a5cd /include | |
| parent | 929ce68fe67a171b2e3ff506450ca893ed6532b3 (diff) | |
This commit was manufactured by cvs2svn to create branch 'binutils-
2_10-branch'.
Sprout from cygnus 2000-02-22 16:18:13 UTC Ian Lance Taylor <iant@google.com> 'import libiberty from egcs'
Cherrypick from master 2000-03-30 02:19:55 UTC Jason Merrill <jason@redhat.com> ' * configure.in: -linux-gnu*, not -linux-gnu.':
ChangeLog
Makefile.in
config.guess
config.sub
config/ChangeLog
config/mh-i370pic
config/mt-aix43
config/mt-i370pic
config/mt-wince
configure
configure.in
include/ChangeLog
include/ansidecl.h
include/aout/ChangeLog
include/aout/aout64.h
include/bfdlink.h
include/coff/ChangeLog
include/coff/arm.h
include/coff/internal.h
include/coff/mcore.h
include/coff/mipspe.h
include/coff/pe.h
include/coff/sh.h
include/dis-asm.h
include/elf/ChangeLog
include/elf/arm-oabi.h
include/elf/arm.h
include/elf/avr.h
include/elf/common.h
include/elf/dwarf.h
include/elf/dwarf2.h
include/elf/hppa.h
include/elf/i370.h
include/elf/i386.h
include/elf/i960.h
include/elf/m32r.h
include/elf/m68k.h
include/elf/mcore.h
include/elf/mips.h
include/elf/mn10300.h
include/elf/pj.h
include/elf/reloc-macros.h
include/elf/sh.h
include/elf/sparc.h
include/hashtab.h
include/hp-symtab.h
include/opcode/ChangeLog
include/opcode/alpha.h
include/opcode/cgen.h
include/opcode/d10v.h
include/opcode/d30v.h
include/opcode/hppa.h
include/opcode/i370.h
include/opcode/i386.h
include/opcode/m68k.h
include/opcode/mips.h
include/opcode/mn10300.h
include/opcode/pj.h
include/opcode/ppc.h
include/partition.h
include/remote-sim.h
include/sim-d10v.h
ltconfig
ltmain.sh
mkdep
texinfo/texinfo.tex
Cherrypick from master 2000-04-04 14:32:32 UTC Alan Modra <modra@gmail.com> 'Move translated part of bug report string back into .c files so':
include/bin-bugs.h
Delete:
config/mh-aix43
configure.bat
include/wait.h
makeall.bat
Diffstat (limited to 'include')
53 files changed, 3835 insertions, 1028 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 04f9f02a3..cb15edca0 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,8 +1,99 @@ +2000-03-27 Denis Chertykov <denisc@overta.ru> + + * dis-asm.h (print_insn_avr): Declare. + +2000-03-14 Bernd Schmidt <bernds@cygnus.co.uk> + + * hashtab.h (htab_trav): Modify type so that first arg is of type + void **. + (htab_find_with_hash, htab_find_slot_with_hash): Declare new + functions. + +2000-03-09 Alex Samuel <samuel@codesourcery.com> + + * partition.h: New file. + +2000-03-09 Zack Weinberg <zack@wolery.cumb.org> + + * hashtab.h (struct htab): Add del_f. + (htab_del): New type. + (htab_create): Add fourth argument. + +2000-03-08 Zack Weinberg <zack@wolery.cumb.org> + + * hashtab.h (hash_table_t): Rename to htab_t. + (struct hash_table): Rename to struct htab. Shorten element + names. Reorder elements by size. + (htab_hash, htab_eq, htab_trav): New typedefs for the callback + function pointers. + (hash_table_entry_t): Discard; just use void * for element + type. + +2000-03-01 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_callbacks): Add a boolean arg to + the undefined_symbol callback. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * dis-asm.h (print_insn_i370): Declare. + +2000-02-22 Chandra Chavva <cchavva@cygnus.com> + + * opcode/d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation + cannot be combined in parallel with ADD/SUBppp. + +Tue Feb 22 15:19:54 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_trace): Document return values. + (sim_set_trace): Declare. Deprecate. + +2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * dis-asm.h (struct disassemble_info): Change `length' param of + read_memory_func to unsigned. Change type of `buffer_length' and + `octets_per_byte' to unsigned. + (buffer_read_memory): Change `length' param to unsigned. + +2000-02-16 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Add prototypes for ARM register name functions. + +Wed Feb 9 18:45:49 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * wait.h: Delete. No longer used by GDB. + +Tue Feb 8 17:01:13 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_resume): Clarify use of SIGGNAL. + (sim_stop_reason): Clarify meaning of sim_signalled. + +2000-02-03 Timothy Wall <twall@redhat.com> + + * dis-asm.h (struct disassemble_info): Added octets_per_byte + field and initialize it to one (1). + +2000-01-27 Nick Clifton <nickc@redhat.com> + + * dis-asm.h: Add prototype for disassembler_usage(). + Add prototype for arm_disassembler_options(). + Remove prototype for arm_toggle_regnames(). + Add prototype for parse_arm_disassembler_option(). + Sat Jan 1 19:06:52 2000 Hans-Peter Nilsson <hp@bitrange.com> * symcat.h (STRINGX) [!__STDC__ || ALMOST_STDC]: Change "?" to "s" to stringify argument s. +Wed Dec 15 11:22:56 1999 Jeffrey A Law (law@cygnus.com) + + * hp-symtab.h (HP_LANGUAGE_FORTRAN): New enumeration constant. + (HP_LANGUAGE_F77): Define using HP_LANGUAGE_FORTRAN. + +1999-12-15 Doug Evans <dje@transmeta.com> + + * dis-asm.h: Enclose in extern "C" ifdef __cplusplus. + 1999-12-05 Mark Mitchell <mark@codesourcery.com> * splay-tree.h (struct splay_tree_node): Rename to ... @@ -25,16 +116,30 @@ Sat Jan 1 19:06:52 2000 Hans-Peter Nilsson <hp@bitrange.com> (asprintf, vasprintf): Provide declarations. Wed Nov 10 12:43:21 1999 Philippe De Muyter <phdm@macqel.be> - Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * ansidecl.h: Define and test `GCC_VERSION', not `HAVE_GCC_VERSION'. - + +1999-11-04 Jimmy Guo <guo@cup.hp.com> + + * hp-symtab.h (dntt_type_fparam): Add doc_ranges, misc_kind + fields, change location type to CORE_ADDR from int. + (dntt_type_const): Name the 5th field location_type. + +Sun Oct 24 19:11:32 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-d10v.h (SIM_D10V_TS2_DMAP_REGNUM): Define. + 1999-10-23 08:51 -0700 Zack Weinberg <zack@bitmover.com> * hashtab.h: Give hash_table_t a struct tag. Add prototypes for clear_hash_table_slot and traverse_hash_table. Correct prototype of all_hash_table_collisions. +Sat Oct 23 19:00:13 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-d10v.h: New file. + Fri Oct 15 01:47:51 1999 Vladimir Makarov <vmakarov@loony.cygnus.com> * hashtab.h: New file. @@ -43,7 +148,7 @@ Fri Oct 15 01:47:51 1999 Vladimir Makarov <vmakarov@loony.cygnus.com> * ansidecl.h (HAVE_GCC_VERSION): New macro. Use it instead of explicitly testing __GNUC__ and __GNUC_MINOR__. - + (ATTRIBUTE_PRINTF): Use `__format__', not `format'. 1999-09-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> @@ -59,6 +164,10 @@ Tue Sep 14 00:35:02 1999 Marc Espie <espie@cvs.openbsd.org> * libiberty.h (xmemdup): Add prototype for new function. +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * dis-asm.h (print_insn_pj): Declare. + 1999-09-01 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * obstack.h (obstack_grow, obstack_grow0): Move (char*) casts @@ -79,6 +188,37 @@ Tue Sep 14 00:35:02 1999 Marc Espie <espie@cvs.openbsd.org> * ansidecl.h: Copy attribute support macros from egcs. +1999-06-22 Mark Mitchell <mark@codesourcery.com> + + * bfdlink.h (struct bfd_link_hash_entry): Add init_function and + fini_function. + +1999-06-20 Mark Mitchell <mark@codesourcery.com> + + * mips.h (Elf32_Internal_Msym): New structure. + (Elf32_External_Msym): Likewise. + (ELF32_MS_REL_INDEX): New macro. + (ELF32_MS_FLAGS): Likewise. + (ELF32_MS_INFO): Likewise. + +1999-06-14 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h (arm_toggle_regnames): New prototype. + (struct diassemble_info): New field: disassembler_options. + +1999-04-11 Richard Henderson <rth@cygnus.com> + + * bfdlink.h (bfd_elf_version_expr): Rename `match' to `pattern'. + Add `match' callback function. + +1999-04-10 Richard Henderson <rth@cygnus.com> + + * bfdlink.h (bfd_link_info): Add no_undefined. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Add prototype for print_insn_mcore. + 1999-04-02 Mark Mitchell <mark@codesourcery.com> * splay-tree.h (splay_tree_compare_pointers): Declare. @@ -91,25 +231,63 @@ Wed Mar 24 12:46:29 1999 Andrew Cagney <cagney@amy.cygnus.com> * libiberty.h (basename): Cygwin{,32} should have the prototype. +1999-02-22 Jim Lemke <jlemke@cygnus.com> + + * bfdlink.h (bfd_link_info): add field "mpc860c0". + +Mon Feb 1 21:05:46 1999 Catherine Moore <clm@cygnus.com> + + * dis-asm.h (print_insn_i386_att): Declare. + (print_insn_i386_intel): Declare. + +998-12-30 Michael Meissner <meissner@cygnus.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Cast STREAM and + FPRINTF_FUNC to avoid compiler warnings. + +Wed Dec 30 16:07:14 1998 David Taylor <taylor@texas.cygnus.com> + + * dis-asm.h: change void * to PTR (two places). + Mon Dec 14 09:53:31 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * demangle.h: Don't check IN_GCC anymore. * splay-tree.h: Likewise. -Tue Dec 8 00:30:31 1998 Elena Zannoni <ezannoni@kwikemart.cygnus.com> +Tue Dec 8 00:30:31 1998 Elena Zannoni <ezannoni@kwikemart.cygnus.com> + + The following changes were made by Elena Zannoni + <ezannoni@kwikemart.cygnus.com> and Edith Epstein + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes made by HP; HP did not create ChangeLog entries. + + * dis-asm.h (struct disassemble_info): change the type of stream + from FILE* to void*, for use with gdb's new type GDB_FILE. + (fprintf_ftype): change FILE* parameter type to void*. + + * demangle.h: (DMGL_EDG): new macro for Kuck and Associates + (DMGL_STYLE_MASK): modify to include Kuck and Assoc style + (demangling_styles): add new edg_demangling style + (EDG_DEMANGLING_STYLE_STRING): new macro + (EDG_DEMANGLING): new macro - * demangle.h: (DMGL_EDG): new macro for Kuck and Associates - (DMGL_STYLE_MASK): modify to include Kuck and Assoc style - (demangling_styles): add new edg_demangling style - (EDG_DEMANGLING_STYLE_STRING): new macro - (EDG_DEMANGLING): new macro + * demangle.h (DMGL_HP): new macro, for HP/aCC compiler. + (DMGL_STYLE_MASK): modify to include new HP's style. + (demangling_styles): add new hp_demangling value. + (HP_DEMANGLING_STYLE_STRING): new macro. + (ARM_DEMANGLING): coerce to int. + (HP_DEMANGLING): new macro. - * demangle.h (DMGL_HP): new macro, for HP/aCC compiler. - (DMGL_STYLE_MASK): modify to include new HP's style. - (demangling_styles): add new hp_demangling value. - (HP_DEMANGLING_STYLE_STRING): new macro. - (ARM_DEMANGLING): coerce to int. - (HP_DEMANGLING): new macro. + * hp-symtab.h: rewritten, from HP. + (quick_procedure): change type of language field to unsigned int + (quick_module): change type of language field to unsigned int + (struct dntt_type_svar): add field thread_specific. + (hp_language): add languages modcal and dmpascal. + +Mon Nov 30 15:25:58 1998 J"orn Rennecke <amylaar@cygnus.co.uk> + + * elf/sh.h (elf_sh_reloc_type): Add R_SH_FIRST_INVALID_RELOC, + R_SH_LAST_INVALID_RELOC, R_SH_SWITCH8 and R_SH_max. Fri Nov 20 13:14:00 1998 Andrew Cagney <cagney@b1.cygnus.com> @@ -126,11 +304,19 @@ Sun Nov 8 17:42:25 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * demangle.h: Never define PARAMS(). * splay-tree.h: Likewise. +Sat Nov 7 18:30:20 1998 Peter Schauer <peter.schauer@regent.e-technik.tu-muenchen.de> + + * dis-asm.h (print_insn_vax): Declare. + Sat Nov 7 16:04:03 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * demangle.h: Don't include gansidecl.h. * splay-tree.h: Likewise. +1998-10-26 16:03 Ulrich Drepper <drepper@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add new field optimize. + Thu Oct 22 19:58:00 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * splay-tree.h: Wrap function pointer parameter declarations in @@ -157,6 +343,10 @@ Mon Jun 1 13:48:32 1998 Jason Molenda (crash@bugshack.cygnus.com) * obstack.h: Update to latest FSF version. +Tue May 26 20:57:43 1998 Stan Cox <scox@equinox.cygnus.com> + + * elf/sparc.h (EF_SPARC_LEDATA, R_SPARC_32LE): Added. + Tue Feb 24 13:05:02 1998 Doug Evans <devans@canuck.cygnus.com> * dis-asm.h (disassemble_info): Member `symbol' renamed to `symbols' @@ -429,6 +619,10 @@ Thu Feb 6 14:20:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com> bytes_per_chunk and display_endian to control the display of raw instructions. +Fri Dec 27 22:17:37 1996 Fred Fish <fnf@cygnus.com> + + * dis-asm.h (print_insn_tic80): Declare. + Sun Dec 8 17:11:12 1996 Doug Evans <dje@canuck.cygnus.com> * callback.h (host_callback): New member `error'. @@ -806,8 +1000,8 @@ Thu Apr 28 19:06:50 1994 Ken Raeburn (raeburn@cujo.cygnus.com) Fri Apr 1 00:38:17 1994 Jim Wilson (wilson@mole.gnu.ai.mit.edu) - * obstack.h: Delete use of IN_GCC to control whether - stddef.h or gstddef.h is included. + * obstack.h: Delete use of IN_GCC to control whether + stddef.h or gstddef.h is included. Tue Mar 22 13:06:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) diff --git a/include/ansidecl.h b/include/ansidecl.h index 9e8a457c2..10308676f 100644 --- a/include/ansidecl.h +++ b/include/ansidecl.h @@ -160,7 +160,6 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #endif /* ANSI C. */ - /* Using MACRO(x,y) in cpp #if conditionals does not work with some older preprocessors. Thus we can't define something like this: diff --git a/include/aout/ChangeLog b/include/aout/ChangeLog index 854cfd5b5..63f17ec83 100644 --- a/include/aout/ChangeLog +++ b/include/aout/ChangeLog @@ -1,3 +1,8 @@ +1999-07-12 Ian Lance Taylor <ian@zembu.com> + + * aout64.h (N_SHARED_LIB): Define as 0 if TEXT_START_ADDR is + defined as 0. + Sun Jun 28 11:33:48 1998 Peter Schauer <pes@regent.e-technik.tu-muenchen.de> * stab.def: Add N_ALIAS from SunPro F77. diff --git a/include/aout/aout64.h b/include/aout/aout64.h index 76f1140b6..bf743c486 100644 --- a/include/aout/aout64.h +++ b/include/aout/aout64.h @@ -121,8 +121,12 @@ struct external_exec /* Sun shared libraries, not linux. This macro is only relevant for ZMAGIC files. */ #ifndef N_SHARED_LIB +#if defined (TEXT_START_ADDR) && TEXT_START_ADDR == 0 +#define N_SHARED_LIB(x) (0) +#else #define N_SHARED_LIB(x) ((x).a_entry < TEXT_START_ADDR) #endif +#endif /* Returning 0 not TEXT_START_ADDR for OMAGIC and NMAGIC is based on the assumption that we are dealing with a .o file, not an diff --git a/include/bfdlink.h b/include/bfdlink.h index a055fa082..bb827a35f 100644 --- a/include/bfdlink.h +++ b/include/bfdlink.h @@ -237,6 +237,13 @@ struct bfd_link_info MPC860 C0 (or earlier) should be checked for and modified. It gives the number of bytes that should be checked at the end of each text page. */ int mpc860c0; + + /* The function to call when the executable or shared object is + loaded. */ + const char *init_function; + /* The function to call when the executable or shared object is + unloaded. */ + const char *fini_function; }; /* This structures holds a set of callback functions. These are @@ -322,10 +329,13 @@ struct bfd_link_callbacks /* A function which is called when a relocation is attempted against an undefined symbol. NAME is the symbol which is undefined. ABFD, SECTION and ADDRESS identify the location from which the - reference is made. In some cases SECTION may be NULL. */ + reference is made. FATAL indicates whether an undefined symbol is + a fatal error or not. In some cases SECTION may be NULL. */ boolean (*undefined_symbol) PARAMS ((struct bfd_link_info *, const char *name, bfd *abfd, - asection *section, bfd_vma address)); + asection *section, + bfd_vma address, + boolean fatal)); /* A function which is called when a reloc overflow occurs. NAME is the name of the symbol or section the reloc is against, RELOC_NAME is the name of the relocation, and ADDEND is any diff --git a/include/bin-bugs.h b/include/bin-bugs.h new file mode 100644 index 000000000..cb14a66bf --- /dev/null +++ b/include/bin-bugs.h @@ -0,0 +1,3 @@ +#ifndef REPORT_BUGS_TO +#define REPORT_BUGS_TO "bug-gnu-utils@gnu.org" +#endif diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog index 8ad6e0cec..76b52c023 100644 --- a/include/coff/ChangeLog +++ b/include/coff/ChangeLog @@ -1,3 +1,82 @@ +2000-03-15 Kazu Hirata <kazu@hxi.com> + + * internal.h: Fix a typo in the comment for R_MOVL2. + +2000-02-28 Nick Clifton <nickc@cygnus.com> + + * mipspe.h (MIPS_PE_MAGIC): Define. + * sh.h (SH_PE_MAGIC): Define. + +2000-02-22 Nick Clifton <nickc@cygnus.com> DJ Delorie <dj@cygnus.com> + + * sh.h: Add Windows CE definitions. + * arm.h: Add Windows CE definitions. + * mipspe.h: New file: Windows CE definitions for MIPS. + * pe.h: Add constants for ILF support. + +2000-01-05 Nick Clifton <nickc@cygnus.com> + + * pe.h: Fix formatting of comments. + (IMAGE_FILE_AGGRESSIVE_WS_TRIM): Define. + (IMAGE_FILE_LARGE_ADDRESS_AWARE): Define. + (IMAGE_FILE_16BIT_MACHINE): Define. + (IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP): Define. + (IMAGE_FILE_UP_SYSTEM_ONLY): Define. + (IMAGE_FILE_MACHINE_UNKNOWN): Define. + (IMAGE_FILE_MACHINE_ALPHA): Define. + (IMAGE_FILE_MACHINE_ALPHA64): Define. + (IMAGE_FILE_MACHINE_I386): Define. + (IMAGE_FILE_MACHINE_IA64): Define. + (IMAGE_FILE_MACHINE_M68K): Define. + (IMAGE_FILE_MACHINE_MIPS16): Define. + (IMAGE_FILE_MACHINE_MIPSFPU): Define. + (IMAGE_FILE_MACHINE_MIPSFPU16): Define. + (IMAGE_FILE_MACHINE_POWERPC): Define. + (IMAGE_FILE_MACHINE_R3000): Define. + (IMAGE_FILE_MACHINE_R4000): Define. + (IMAGE_FILE_MACHINE_R10000): Define. + (IMAGE_FILE_MACHINE_SH3): Define. + (IMAGE_FILE_MACHINE_SH4): Define. + (IMAGE_FILE_MACHINE_THUMB): Define. + +1999-09-20 Alan Modra <alan@spri.levels.unisa.edu.au> + + * internal.h: Delete bogus R_PCLONG, duplicate R_RELBYTE and + R_RELWORD, and rewrite some R_* as decimal. + +1999-09-06 Donn Terry <donn@interix.com> + + * internal.h (DTYPE): Define. + * pe.h (struct external_PEI_filehdr): Rename from + external_PE_filehdr. Define even if COFF_IMAGE_WITH_PE is not + defined. + +1999-07-17 Nick Clifton <nickc@cygnus.com> + + * arm.h (F_SOFT_FLOAT): Rename from F_SOFTFLOAT. + +1999-06-21 Philip Blundell <pb@nexus.co.uk> + + * arm.h (F_SOFTFLOAT): Define. + +1999-07-05 Nick Clifton <nickc@cygnus.com> + + * arm.h (F_ARM_5): Define. + +Wed Jun 2 18:08:18 1999 Richard Henderson <rth@cygnus.com> + + * internal.h (BEOS_EXE_IMAGE_BASE, BEOS_DLL_IMAGE_BASE): New. + +Mon May 17 13:35:35 1999 Stan Cox <scox@cygnus.com> + + * coff/arm.h (F_PIC, F_ARM_2, F_ARM_2a, F_ARM_3, F_ARM_3M, + F_ARM_4, F_ARM_4T, F_APCS26): Changed values to distinguish + F_ARM_2a, F_ARM_3M, F_ARM_4T. + +1999-05-15 Nick Clifton <nickc@cygnus.com> + + * mcore.h (IMAGE_REL_MCORE_RVA): Define. + 1999-04-21 Nick Clifton <nickc@cygnus.com> * mcore.h (GET_LINENO_LNNO): New macro. @@ -5,7 +84,7 @@ 1999-04-08 Nick Clifton <nickc@cygnus.com> - * mcore.h: New header file. Defines for Motorolla's MCore + * mcore.h: New header file. Defines for Motorola's MCore processor. Sun Dec 6 21:36:37 1998 Mark Elbrecht <snowball3@usa.net> diff --git a/include/coff/arm.h b/include/coff/arm.h index dd578b1a7..7ca93299a 100644 --- a/include/coff/arm.h +++ b/include/coff/arm.h @@ -1,10 +1,28 @@ -/*** coff information for the ARM */ +/* ARM COFF support for BFD. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define COFFARM 1 /********************** FILE HEADER **********************/ -struct external_filehdr { +struct external_filehdr +{ char f_magic[2]; /* magic number */ char f_nscns[2]; /* number of sections */ char f_timdat[4]; /* time & date stamp */ @@ -26,6 +44,7 @@ struct external_filehdr { * F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) * F_APCS_26 file uses 26 bit ARM Procedure Calling Standard * F_APCS_SET the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised + * F_SOFT_FLOAT code does not use floating point instructions */ #define F_RELFLG (0x0001) @@ -40,20 +59,22 @@ struct external_filehdr { #define F_AR32WR (0x0100) #define F_APCS_26 (0x0400) #define F_APCS_SET (0x0800) +#define F_SOFT_FLOAT (0x2000) /* Bits stored in flags field of the internal_f structure */ #define F_INTERWORK (0x0010) -#define F_PIC_INT (0x0020) #define F_APCS_FLOAT (0x0040) -#define F_ARM_ARCHITECTURE_MASK (0x0c00) -#define F_ARM_2 (0x0000) -#define F_ARM_2a (0x0000) -#define F_ARM_3 (0x0400) -#define F_ARM_3M (0x0400) -#define F_ARM_4 (0x0800) -#define F_ARM_4T (0x0c00) -#define F_APCS26 (0x4000) +#define F_PIC (0x0080) +#define F_APCS26 (0x1000) +#define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400) +#define F_ARM_2 (0x0400) +#define F_ARM_2a (0x0800) +#define F_ARM_3 (0x0c00) +#define F_ARM_3M (0x4000) +#define F_ARM_4 (0x4400) +#define F_ARM_4T (0x4800) +#define F_ARM_5 (0x4c00) /* * ARMMAGIC ought to encoded the procesor type, @@ -64,10 +85,16 @@ struct external_filehdr { * XXX - NC 5/6/97 */ -#define ARMMAGIC 0xa00 /* I just made this up */ +#define ARMMAGIC 0xa00 /* I just made this up */ #define ARMBADMAG(x) (((x).f_magic != ARMMAGIC)) +#define ARMPEMAGIC 0x1c0 +#define THUMBPEMAGIC 0x1c2 + +#undef ARMBADMAG +#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC) && ((x).f_magic != ARMPEMAGIC) && ((x).f_magic != THUMBPEMAGIC)) + #define FILHDR struct external_filehdr #define FILHSZ 20 @@ -85,8 +112,6 @@ typedef struct char entry[4]; /* entry pt. */ char text_start[4]; /* base of text used for this file */ char data_start[4]; /* base of data used for this file */ - - } AOUTHDR; @@ -108,9 +133,8 @@ AOUTHDR; #define NT_DEF_COMMIT 0x1000 /********************** SECTION HEADER **********************/ - - -struct external_scnhdr { +struct external_scnhdr +{ char s_name[8]; /* section name */ char s_paddr[4]; /* physical address, aliased s_nlib */ char s_vaddr[4]; /* virtual address */ @@ -145,8 +169,10 @@ struct external_scnhdr { * grouping will have l_lnno = 0 and in place of physical address will be the * symbol table index of the function name. */ -struct external_lineno { - union { +struct external_lineno +{ + union + { char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ char l_paddr[4]; /* (physical) address of line number */ } l_addr; @@ -166,9 +192,11 @@ struct external_lineno { struct external_syment { - union { + union + { char e_name[E_SYMNMLEN]; - struct { + struct + { char e_zeroes[4]; char e_offset[4]; } e; @@ -185,37 +213,47 @@ struct external_syment #define N_BTSHFT (4) #define N_TSHIFT (2) -union external_auxent { - struct { +union external_auxent +{ + struct + { char x_tagndx[4]; /* str, un, or enum tag indx */ - union { - struct { + union + { + struct + { char x_lnno[2]; /* declaration line number */ char x_size[2]; /* str/union/array size */ } x_lnsz; char x_fsize[4]; /* size of function */ } x_misc; - union { - struct { /* if ISFCN, tag, or .bb */ + union + { + struct /* if ISFCN, tag, or .bb */ + { char x_lnnoptr[4]; /* ptr to fcn line # */ char x_endndx[4]; /* entry ndx past block end */ } x_fcn; - struct { /* if ISARY, up to 4 dimen. */ + struct /* if ISARY, up to 4 dimen. */ + { char x_dimen[E_DIMNUM][2]; } x_ary; } x_fcnary; char x_tvndx[2]; /* tv index */ } x_sym; - union { + union + { char x_fname[E_FILNMLEN]; - struct { + struct + { char x_zeroes[4]; char x_offset[4]; } x_n; } x_file; - struct { + struct + { char x_scnlen[4]; /* section length */ char x_nreloc[2]; /* # relocation entries */ char x_nlinno[2]; /* # line numbers */ @@ -224,13 +262,12 @@ union external_auxent { char x_comdat[1]; /* COMDAT selection number */ } x_scn; - struct { + struct + { char x_tvfill[4]; /* tv fill value */ char x_tvlen[2]; /* length of .tv */ char x_tvran[2][2]; /* tv range */ } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ - - }; #define SYMENT struct external_syment @@ -238,21 +275,29 @@ union external_auxent { #define AUXENT union external_auxent #define AUXESZ 18 - -# define _ETEXT "etext" - +#define _ETEXT "etext" /********************** RELOCATION DIRECTIVES **********************/ +#ifdef ARM_WINCE +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; +#define RELOC struct external_reloc +#define RELSZ 10 - -struct external_reloc { +#else +struct external_reloc +{ char r_vaddr[4]; char r_symndx[4]; char r_type[2]; char r_offset[4]; }; - #define RELOC struct external_reloc #define RELSZ 14 +#endif diff --git a/include/coff/internal.h b/include/coff/internal.h index d5ea95103..e89b52875 100644 --- a/include/coff/internal.h +++ b/include/coff/internal.h @@ -89,10 +89,14 @@ typedef struct _IMAGE_DATA_DIRECTORY } IMAGE_DATA_DIRECTORY; #define IMAGE_NUMBEROF_DIRECTORY_ENTRIES 16 -/* default image base for NT */ +/* Default image base for NT. */ #define NT_EXE_IMAGE_BASE 0x400000 #define NT_DLL_IMAGE_BASE 0x10000000 +/* Default image base for BeOS. */ +#define BEOS_EXE_IMAGE_BASE 0x80000000 +#define BEOS_DLL_IMAGE_BASE 0x10000000 + /* Extra stuff in a PE aouthdr */ #define PE_DEF_SECTION_ALIGNMENT 0x1000 @@ -417,6 +421,7 @@ struct internal_syment #define DT_ARY (3) /* array */ #define BTYPE(x) ((x) & N_BTMASK) +#define DTYPE(x) (((x) & N_TMASK) >> N_BTSHFT) #define ISPTR(x) \ (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_PTR << N_BTSHFT)) @@ -585,33 +590,28 @@ struct internal_reloc unsigned long r_offset; /* Used by Alpha ECOFF, SPARC, others */ }; -#define R_RELBYTE 017 -#define R_RELWORD 020 -#define R_PCRBYTE 022 -#define R_PCRWORD 023 -#define R_PCRLONG 024 - -#define R_DIR16 01 -#define R_DIR32 06 -#define R_PCLONG 020 -#define R_RELBYTE 017 -#define R_RELWORD 020 -#define R_IMAGEBASE 07 - - -#define R_PCR16L 128 -#define R_PCR26L 129 -#define R_VRT16 130 -#define R_HVRT16 131 -#define R_LVRT16 132 -#define R_VRT32 133 -#define R_RELLONG (0x11) /* Direct 32-bit relocation */ -#define R_IPRSHORT (0x18) -#define R_IPRLONG (0x1a) -#define R_GETSEG (0x1d) -#define R_GETPA (0x1e) -#define R_TAGWORD (0x1f) -#define R_JUMPTARG 0x20 /* strange 29k 00xx00xx reloc */ +#define R_DIR16 1 +#define R_DIR32 6 +#define R_IMAGEBASE 7 +#define R_RELBYTE 15 +#define R_RELWORD 16 +#define R_RELLONG 17 +#define R_PCRBYTE 18 +#define R_PCRWORD 19 +#define R_PCRLONG 20 +#define R_IPRSHORT 24 +#define R_IPRLONG 26 +#define R_GETSEG 29 +#define R_GETPA 30 +#define R_TAGWORD 31 +#define R_JUMPTARG 32 /* strange 29k 00xx00xx reloc */ + +#define R_PCR16L 128 +#define R_PCR26L 129 +#define R_VRT16 130 +#define R_HVRT16 131 +#define R_LVRT16 132 +#define R_VRT32 133 /* This reloc identifies mov.b instructions with a 16bit absolute @@ -671,7 +671,7 @@ struct internal_reloc #define R_MOVL1 0x4c /* This reloc identifies mov.[wl] insns which formerlly had - a 32/24bit absolute address and how have a 16bit absolute address. */ + a 32/24bit absolute address and now have a 16bit absolute address. */ #define R_MOVL2 0x4d /* This reloc identifies a bCC:8 which will have it's condition diff --git a/include/coff/mcore.h b/include/coff/mcore.h index 974b62e16..0fa319c97 100644 --- a/include/coff/mcore.h +++ b/include/coff/mcore.h @@ -1,4 +1,4 @@ -/* Motorolla MCore support for BFD. +/* Motorola MCore support for BFD. Copyright (C) 1999 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -32,6 +32,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define IMAGE_REL_MCORE_PCREL_IMM4BY2 0x0004 #define IMAGE_REL_MCORE_PCREL_32 0x0005 #define IMAGE_REL_MCORE_PCREL_JSR_IMM11BY2 0x0006 +#define IMAGE_REL_MCORE_RVA 0x0007 #define PEMCORE diff --git a/include/coff/mipspe.h b/include/coff/mipspe.h new file mode 100644 index 000000000..1927d991d --- /dev/null +++ b/include/coff/mipspe.h @@ -0,0 +1,223 @@ +/*** coff information for Windows CE with MIPS VR4111 */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + + + +#define MIPS_ARCH_MAGIC_WINCE 0x0166 /* Windows CE - little endian */ +#define MIPS_PE_MAGIC 0x010b + +#define MIPSBADMAG(x) \ + ((x).f_magic!=MIPS_ARCH_MAGIC_WINCE) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 + + + + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** SECTION HEADER **********************/ + + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *) (ext->l_lnno)); +#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_16(abfd,val, (bfd_byte *) (ext->l_lnno)); + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + char x_checksum[4]; /* section COMDAT checksum */ + char x_associated[2]; /* COMDAT associated section index */ + char x_comdat[1]; /* COMDAT selection number */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + + + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes */ + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + + +#define RELOC struct external_reloc +#define RELSZ 10 + +/* MIPS PE relocation types. */ + +#define MIPS_R_ABSOLUTE 0 /* ignored */ +#define MIPS_R_REFHALF 1 +#define MIPS_R_REFWORD 2 +#define MIPS_R_JMPADDR 3 +#define MIPS_R_REFHI 4 /* PAIR follows */ +#define MIPS_R_REFLO 5 +#define MIPS_R_GPREL 6 +#define MIPS_R_LITERAL 7 /* same as GPREL */ +#define MIPS_R_SECTION 10 +#define MIPS_R_SECREL 11 +#define MIPS_R_SECRELLO 12 +#define MIPS_R_SECRELHI 13 /* PAIR follows */ +#define MIPS_R_RVA 34 /* 0x22 */ +#define MIPS_R_PAIR 37 /* 0x25 - symndx is really a signed 16-bit addend */ diff --git a/include/coff/pe.h b/include/coff/pe.h index 7e676a508..6932ee87b 100644 --- a/include/coff/pe.h +++ b/include/coff/pe.h @@ -3,29 +3,32 @@ #ifndef _PE_H #define _PE_H -/* NT specific file attributes */ +/* NT specific file attributes. */ #define IMAGE_FILE_RELOCS_STRIPPED 0x0001 #define IMAGE_FILE_EXECUTABLE_IMAGE 0x0002 #define IMAGE_FILE_LINE_NUMS_STRIPPED 0x0004 #define IMAGE_FILE_LOCAL_SYMS_STRIPPED 0x0008 +#define IMAGE_FILE_AGGRESSIVE_WS_TRIM 0x0010 +#define IMAGE_FILE_LARGE_ADDRESS_AWARE 0x0020 +#define IMAGE_FILE_16BIT_MACHINE 0x0040 #define IMAGE_FILE_BYTES_REVERSED_LO 0x0080 #define IMAGE_FILE_32BIT_MACHINE 0x0100 #define IMAGE_FILE_DEBUG_STRIPPED 0x0200 +#define IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP 0x0400 #define IMAGE_FILE_SYSTEM 0x1000 #define IMAGE_FILE_DLL 0x2000 +#define IMAGE_FILE_UP_SYSTEM_ONLY 0x4000 #define IMAGE_FILE_BYTES_REVERSED_HI 0x8000 -/* additional flags to be set for section headers to allow the NT loader to +/* Additional flags to be set for section headers to allow the NT loader to read and write to the section data (to replace the addresses of data in - dlls for one thing); also to execute the section in .text's case */ + dlls for one thing); also to execute the section in .text's case. */ #define IMAGE_SCN_MEM_DISCARDABLE 0x02000000 #define IMAGE_SCN_MEM_EXECUTE 0x20000000 #define IMAGE_SCN_MEM_READ 0x40000000 #define IMAGE_SCN_MEM_WRITE 0x80000000 -/* - * Section characteristics added for ppc-nt - */ +/* Section characteristics added for ppc-nt. */ #define IMAGE_SCN_TYPE_NO_PAD 0x00000008 /* Reserved. */ @@ -53,7 +56,6 @@ #define IMAGE_SCN_ALIGN_32BYTES 0x00600000 #define IMAGE_SCN_ALIGN_64BYTES 0x00700000 - #define IMAGE_SCN_LNK_NRELOC_OVFL 0x01000000 /* Section contains extended relocations. */ #define IMAGE_SCN_MEM_NOT_CACHED 0x04000000 /* Section is not cachable. */ #define IMAGE_SCN_MEM_NOT_PAGED 0x08000000 /* Section is not pageable. */ @@ -67,6 +69,26 @@ #define IMAGE_COMDAT_SELECT_EXACT_MATCH (4) /* Warn if different. */ #define IMAGE_COMDAT_SELECT_ASSOCIATIVE (5) /* Base on other section. */ +/* Machine numbers. */ + +#define IMAGE_FILE_MACHINE_UNKNOWN 0x0 +#define IMAGE_FILE_MACHINE_ALPHA 0x184 +#define IMAGE_FILE_MACHINE_ARM 0x1c0 +#define IMAGE_FILE_MACHINE_ALPHA64 0x284 +#define IMAGE_FILE_MACHINE_I386 0x14c +#define IMAGE_FILE_MACHINE_IA64 0x200 +#define IMAGE_FILE_MACHINE_M68K 0x268 +#define IMAGE_FILE_MACHINE_MIPS16 0x266 +#define IMAGE_FILE_MACHINE_MIPSFPU 0x366 +#define IMAGE_FILE_MACHINE_MIPSFPU16 0x466 +#define IMAGE_FILE_MACHINE_POWERPC 0x1f0 +#define IMAGE_FILE_MACHINE_R3000 0x162 +#define IMAGE_FILE_MACHINE_R4000 0x166 +#define IMAGE_FILE_MACHINE_R10000 0x168 +#define IMAGE_FILE_MACHINE_SH3 0x1a2 +#define IMAGE_FILE_MACHINE_SH4 0x1a6 +#define IMAGE_FILE_MACHINE_THUMB 0x1c2 + /* Magic values that are true for all dos/nt implementations */ #define DOSMAGIC 0x5a4d #define NT_SIGNATURE 0x00004550 @@ -76,12 +98,7 @@ #undef FILNMLEN #define FILNMLEN 18 /* # characters in a file name */ - -#ifdef COFF_IMAGE_WITH_PE -/* The filehdr is only weired in images */ - -#undef FILHDR -struct external_PE_filehdr +struct external_PEI_filehdr { /* DOS header fields */ char e_magic[2]; /* Magic number, 0x5a4d */ @@ -108,7 +125,6 @@ struct external_PE_filehdr /* From standard header */ - char f_magic[2]; /* magic number */ char f_nscns[2]; /* number of sections */ char f_timdat[4]; /* time & date stamp */ @@ -119,12 +135,16 @@ struct external_PE_filehdr }; +#ifdef COFF_IMAGE_WITH_PE + +/* The filehdr is only weird in images. */ -#define FILHDR struct external_PE_filehdr -#undef FILHSZ +#undef FILHDR +#define FILHDR struct external_PEI_filehdr +#undef FILHSZ #define FILHSZ 152 -#endif +#endif /* COFF_IMAGE_WITH_PE */ typedef struct { @@ -163,7 +183,16 @@ typedef struct #undef E_FILNMLEN #define E_FILNMLEN 18 /* # characters in a file name */ -#endif +/* Import Tyoes fot ILF format object files.. */ +#define IMPORT_CODE 0 +#define IMPORT_DATA 1 +#define IMPORT_CONST 2 +/* Import Name Tyoes for ILF format object files. */ +#define IMPORT_ORDINAL 0 +#define IMPORT_NAME 1 +#define IMPORT_NAME_NOPREFIX 2 +#define IMPORT_NAME_UNDECORATE 3 +#endif /* _PE_H */ diff --git a/include/coff/sh.h b/include/coff/sh.h index 41957df7f..f7271f210 100644 --- a/include/coff/sh.h +++ b/include/coff/sh.h @@ -16,10 +16,13 @@ struct external_filehdr { #define SH_ARCH_MAGIC_BIG 0x0500 #define SH_ARCH_MAGIC_LITTLE 0x0550 /* Little endian SH */ +#define SH_ARCH_MAGIC_WINCE 0x01a2 /* Windows CE - little endian */ +#define SH_PE_MAGIC 0x010b #define SHBADMAG(x) \ (((x).f_magic!=SH_ARCH_MAGIC_BIG) && \ + ((x).f_magic!=SH_ARCH_MAGIC_WINCE) && \ ((x).f_magic!=SH_ARCH_MAGIC_LITTLE)) #define FILHDR struct external_filehdr @@ -48,6 +51,12 @@ AOUTHDR; +/* Define some NT default values. */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 /********************** SECTION HEADER **********************/ @@ -89,14 +98,26 @@ struct external_lineno { char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ char l_paddr[4]; /* (physical) address of line number */ } l_addr; +#ifdef COFF_WITH_PE + char l_lnno[2]; /* line number */ +#else char l_lnno[4]; /* line number */ +#endif }; #define GET_LINENO_LNNO(abfd, ext) bfd_h_get_32(abfd, (bfd_byte *) (ext->l_lnno)); #define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_32(abfd,val, (bfd_byte *) (ext->l_lnno)); #define LINENO struct external_lineno +#ifdef COFF_WITH_PE +#define LINESZ 6 +#undef GET_LINENO_LNNO +#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *) (ext->l_lnno)); +#undef PUT_LINENO_LNNO +#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_16(abfd,val, (bfd_byte *) (ext->l_lnno)); +#else #define LINESZ 8 +#endif /********************** SYMBOLS **********************/ @@ -163,6 +184,9 @@ union external_auxent { char x_scnlen[4]; /* section length */ char x_nreloc[2]; /* # relocation entries */ char x_nlinno[2]; /* # line numbers */ + char x_checksum[4]; /* section COMDAT checksum */ + char x_associated[2]; /* COMDAT associated section index */ + char x_comdat[1]; /* COMDAT selection number */ } x_scn; struct { @@ -187,6 +211,7 @@ union external_auxent { types on the h8 don't have room in the instruction for the entire offset - eg the strange jump and high page addressing modes */ +#ifndef COFF_WITH_PE struct external_reloc { char r_vaddr[4]; char r_symndx[4]; @@ -194,14 +219,26 @@ struct external_reloc { char r_type[2]; char r_stuff[2]; }; +#else +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; +#endif #define RELOC struct external_reloc +#ifdef COFF_WITH_PE +#define RELSZ 10 +#else #define RELSZ 16 +#endif /* SH relocation types. Not all of these are actually used. */ #define R_SH_UNUSED 0 /* only used internally */ +#define R_SH_IMM32CE 2 /* 32 bit immediate for WinCE */ #define R_SH_PCREL8 3 /* 8 bit pcrel */ #define R_SH_PCREL16 4 /* 16 bit pcrel */ #define R_SH_HIGH8 5 /* high 8 bits of 24 bit address */ @@ -213,6 +250,7 @@ struct external_reloc { #define R_SH_PCDISP 12 /* 12 bit branch */ #define R_SH_IMM32 14 /* 32 bit immediate */ #define R_SH_IMM8 16 /* 8 bit immediate */ +#define R_SH_IMAGEBASE 16 /* Windows CE */ #define R_SH_IMM8BY2 17 /* 8 bit immediate *2 */ #define R_SH_IMM8BY4 18 /* 8 bit immediate *4 */ #define R_SH_IMM4 19 /* 4 bit immediate */ diff --git a/include/dis-asm.h b/include/dis-asm.h index 666ed6901..6e6c04b53 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -9,6 +9,10 @@ #ifndef DIS_ASM_H #define DIS_ASM_H +#ifdef __cplusplus +extern "C" { +#endif + #include <stdio.h> #include "bfd.h" @@ -74,7 +78,7 @@ typedef struct disassemble_info { INFO is a pointer to this struct. Returns an errno value or 0 for success. */ int (*read_memory_func) - PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length, + PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, struct disassemble_info *info)); /* Function which should be called if we get an error that we can't @@ -101,7 +105,7 @@ typedef struct disassemble_info { /* These are for buffer_read_memory. */ bfd_byte *buffer; bfd_vma buffer_vma; - int buffer_length; + unsigned int buffer_length; /* This variable may be set by the instruction decoder. It suggests the number of bytes objdump should display on a single line. If @@ -117,6 +121,11 @@ typedef struct disassemble_info { int bytes_per_chunk; enum bfd_endian display_endian; + /* Number of octets per incremented target address + Normally one, but some DSPs have byte sizes of 16 or 32 bits + */ + unsigned int octets_per_byte; + /* Results from instruction decoders. Not all decoders yet support this information. This info is set each time an instruction is decoded, and is only valid for the last such instruction. @@ -133,6 +142,9 @@ typedef struct disassemble_info { zero if unknown. */ bfd_vma target2; /* Second target address for dref2 */ + /* Command line options specific to the target disassembler. */ + char * disassembler_options; + } disassemble_info; @@ -145,6 +157,7 @@ extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*)); @@ -180,10 +193,21 @@ extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_vax PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic80 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_pj PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_avr PARAMS ((bfd_vma, disassemble_info*)); + +extern void print_arm_disassembler_options PARAMS ((FILE *)); +extern void parse_arm_disassembler_option PARAMS ((char *)); +extern int get_arm_regname_num_options PARAMS ((void)); +extern int set_arm_regname_option PARAMS ((int)); +extern int get_arm_regnames PARAMS ((int, const char **, const char **, const char ***)); /* Fetch the disassembler for a given BFD, if that support is available. */ extern disassembler_ftype disassembler PARAMS ((bfd *)); +/* Document any target specific options available from the disassembler. */ +extern void disassembler_usage PARAMS ((FILE *)); + /* This block of definitions is for particular callers who read instructions into a buffer before calling the instruction decoder. */ @@ -191,7 +215,7 @@ extern disassembler_ftype disassembler PARAMS ((bfd *)); /* Here is a function which callers may wish to use for read_memory_func. It gets bytes from a buffer. */ extern int buffer_read_memory - PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *)); + PARAMS ((bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *)); /* This function goes with buffer_read_memory. It prints a message using info->fprintf_func and info->stream. */ @@ -215,6 +239,7 @@ extern int generic_symbol_at_address (INFO).arch = bfd_arch_unknown, \ (INFO).mach = 0, \ (INFO).endian = BFD_ENDIAN_UNKNOWN, \ + (INFO).octets_per_byte = 1, \ INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) /* Call this macro to initialize only the internal variables for the @@ -240,4 +265,8 @@ extern int generic_symbol_at_address (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \ (INFO).insn_info_valid = 0 +#ifdef __cplusplus +}; +#endif + #endif /* ! defined (DIS_ASM_H) */ diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index deaccd412..e1f68c39b 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,244 @@ +2000-03-27 Denis Chertykov <denisc@overta.ru> + + * avr.h: New file. AVR ELF support for BFD. + * common.h: Add AVR magic number. + +2000-03-10 Geoffrey Keating <geoffk@cygnus.com> + + * mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16, + R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation + numbers. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * i370.h: New file. + +2000-02-22 Nick Clifton <nickc@cygnus.com> + + * common.h (ELF_ST_OTHER): Remove definition. + (ELF32_ST_OTHER): Remove definition. + (ELF64_ST_OTHER): Remove definition. + +2000-02-22 H.J. Lu <hjl@gnu.org> + + * common.h (ELFOSABI_LINUX): Define. + +Thu Feb 17 00:18:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros. + (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. + (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. + +2000-02-03 H.J. Lu <hjl@gnu.org> + + * arm-oabi.h: Duplicate changes made to arm.h on Jan. 27, + 2000 by Thomas de Lellis <tdel@windriver.com>. + +2000-01-27 Thomas de Lellis <tdel@windriver.com> + + * arm.h (STT_ARM_TFUNC): Define in terms of STT_LOPROC. + (STT_ARM_16BIT): New flag. Denotes a label that was defined in + Thumb block but was does not identify a function. + +2000-01-20 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_MCORE): Fix spelling of Motorola. + * mcore.h (EM_MCORE): Fix spelling of Motorola. + +2000-01-13 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_S370): Change comment - this is now the IBM + System/370. + (EM_IA_64): Change comment - this is now the IA-64. + +2000-01-11 Nick Clifton <nickc@cygnus.com> + + * common.h (DT_ENCODING): Fix definition of this value. + (DT_LOOS): Fix definition of this value. + (DT_HIOS): Fix definition of this value. + (OLD_DT_LOOS): Value of DT_LOOS before Oct 4, 1999 draft + of ELF spec changed it. + (OLD_DT_HIOS): Value of DT_HIOS before Oct 4, 1999 draft + of ELF spec changed it. + +2000-01-10 Egor Duda <deo@logos-m.ru> + + * common.h (NT_WIN32PSTATUS): Define. (cygwin elf core dumps). + +1999-12-28 Nick Clifton <nickc@cygnus.com> + + * mips.h (STO_*): Redefine in terms of STV_* values now in + common.h. + +1999-12-27 Nick Clifton <nickc@cygnus.com> + + * common.h: Upgrade to match Oct4, 1999 Draft ELF ABI Spec. + (EM_MIPS_RS3_LE): New machine number. + (EM_RCE): New machine number. + (EM_MMA): New machine number. + (EM_PCP): New machine number. + (EM_NCPU): New machine number. + (EM_NDR1): New machine number. + (EM_STARCORE): New machine number. + (EM_ME16): New machine number. + (EM_ST100): New machine number. + (EM_TINYJ): New machine number. + (EM_FX66): New machine number. + (EM_ST9PLUS): New machine number. + (EM_ST7): New machine number. + (EM_68HC16): New machine number. + (EM_68HC11): New machine number. + (EM_68HC08): New machine number. + (EM_68HC05): New machine number. + (EM_SVX): New machine number. + (EM_VAX): New machine number. + (PF_MASKOS): Change value. + (SHT_INIT_ARRAY): New value for sh_type field. + (SHT_FINI_ARRAY): New value for sh_type field. + (SHT_PREINIT_ARRAY): New value for sh_type field. + (SHT_HIUSER): Change value. + (SHF_MERGE): New valye for sh_flags field. + (SHF_STRINGS): New valye for sh_flags field. + (SHF_INFO_LINK): New valye for sh_flags field. + (SHF_OS_NONCONFORMING): New valye for sh_flags field. + (SHF_MASKOS): Change value. + (ELF_ST_VISIBILITY): New macro. + (ELF_ST_OTHER): New macro. + (STT_COMMON): New symbol type. + (STV_DEFAULT): Value for symbol visibility. + (STV_INTERNAL): Value for symbol visibility. + (STV_HIDDEN): Value for symbol visibility. + (STV_PROTECTED): Value for symbol visibility. + (DT_RUNPATH): New dynamic section tag. + (DT_FLAGS): New dynamic section tag. + (DT_ENCODING): New dynamic section tag. + (DT_PREINIT_ARRAY): New dynamic section tag. + (DT_PREINIT_ARRAYSZ): New dynamic section tag. + (DT_LOPROC): New dynamic section tag index. + (DT_HIPROC): New dynamic section tag index. + (DF_ORIGIN): Value for dynamic section flag. + (DF_SYMBOLIC): Value for dynamic section flag. + (DF_TEXTREL): Value for dynamic section flag. + (DF_BIND_NOW): Value for dynamic section flag. + +1999-12-09 Fred Fish <fnf@cygnus.com> + + * i960.h (reloc-macros.h): Include using relative dir elf/. + * i386.h (reloc-macros.h): Include using relative dir elf/. + * hppa.h (reloc-macros.h): Include using relative dir elf/. + +1999-12-07 Jim Blandy <jimb@cygnus.com> + + * common.h (NT_PRXFPREG): New definition. + +Wed Dec 1 03:02:15 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (E_MN10300_MACH_AM33): Define. + +Mon Oct 11 22:42:37 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (PF_HP_PAGE_SIZE): Define. + (PF_HP_FAR_SHARED, PF_HP_NEAR_SHARED, PF_HP_CODE): Likewise. + (PF_HP_MODIFY, PF_HP_LAZYSWAP, PF_HP_SBP): Likewise. + +Mon Oct 4 17:42:38 1999 Doug Evans <devans@canuck.cygnus.com> + + * m32r.h (E_M32RX_ARCH): Define. + +1999-09-15 Ulrich Drepper <drepper@cygnus.com> + + * hppa.h: Add DT_HP_GST_SIZE, DT_HP_GST_VERSION, and DT_HP_GST_HASHVAL. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * pj.h: New file. + * common.h (EM_PJ): Define. + +1999-09-02 Ulrich Drepper <drepper@cygnus.com> + + * hppa.h: Add HPUX specific symbol type definitions. + + * hppa.h: Add HPUX specific dynamic and program header table + specific definitions. + +1999-08-31 Scott Bambrough <scottb@netwinder.org> + + * common.h (NT_TASKSTRUCT): Define. + +1999-07-16 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (EF_SPARC_SUN_US3): Define in Cheetah extensions + flag (as per SCD2.4.1). + +1999-07-16 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (ELF64_R_TYPE_DATA): Only use ELF64_R_TYPE bits, not + ELF64_R_SYM bits. + +1999-06-21 Philip Blundell <pb@nexus.co.uk> + + * arm.h (EF_SOFT_FLOAT, F_SOFT_FLOAT): Define. + +1999-07-13 Andreas Schwab <schwab@suse.de> + + * m68k.h (EF_CPU32): Move definition inside multiple inclusion + guard. + +1999-07-08 Richard Henderson <rth@cygnus.com> + + * sparc.h (ELF64_R_TYPE_DATA): Sign extend the value. + (ELF64_R_TYPE_INFO): Mask out all but low 24 bits of data. + (DT_SPARC_PLTFMT): Delete. + Based on a patch from Jakub Jelinek. + +Mon Jun 21 16:36:02 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (elf_hppa_reloc_type): Renamed from elf32_hppa_reloc_type. + +1999-06-10 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (R_SPARC_max_std): Define. + +Wed Jun 9 15:16:34 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Update with various changes from newest PA ELF + specifications. + +1999-06-03 Ian Lance Taylor <ian@zembu.com> + + * common.h (EM_PPC64): Define. + +1999-06-02 Stu Grossman <grossman@babylon-5.cygnus.com> + + * dwarf.h: Add LANG_JAVA. + * dwarf2.h: Add DW_LANG_Java. + +1999-05-29 Nick Clifton <nickc@cygnus.com> + + * common.h (ELFOSABI_ARM): Define. + +1999-05-28 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h: Update comment. + +1999-05-28 Ian Lance Taylor <ian@zembu.com> + + * i960.h: New file. + +1999-05-16 Nick Clifton <nickc@cygnus.com> + + * mcore.h (R_MCORE_COPY): Define. + (R_MCORE_GLOB_DAT): Define. + (R_MCORE_JUMP_SLOT): Define. + +1999-05-15 Nick Clifton <nickc@cygnus.com> + + * mcore.h (R_MCORE_RELATIVE): Define. + +999-05-05 Catherine Moore <clm@cygnus.com> + + * m68k.h (EF_CPU32): Define. + 1999-04-21 Nick Clifton <nickc@cygnus.com> * reloc-macros.h (START_RELOC_NUMBERS): Prepend an underscore to @@ -10,22 +251,22 @@ 1999-04-08 Nick Clifton <nickc@cygnus.com> - * mcore.h: New header file. Defines for Motorolla's MCore - processor. + * mcore.h: New header file. Defines for Motorola's MCore + processor. 1999-04-08 Nick Clifton <nickc@cygnus.com> * common.h: Add new constants defined in: "System V Application - Binary Interface - DRAFT - April 29, 1998" found at the web site: + Binary Interface - DRAFT - April 29, 1998" found at the web site: http://www.sco.com/developer/gabi/contents.html (EM_MMA): Removed. Replaced with EM_MCORE as Motorolla own this - value. + value. 1999-03-31 Nick Clifton <nickc@cygnus.com> * reloc-macros.h: Fixed to not generate an enum with a trailing - comma. + comma. 1999-03-16 Gavin Romig-Koch <gavin@cygnus.com> diff --git a/include/elf/arm-oabi.h b/include/elf/arm-oabi.h index 6109842e8..da5e7316e 100644 --- a/include/elf/arm-oabi.h +++ b/include/elf/arm-oabi.h @@ -1,5 +1,5 @@ /* ARM ELF support for BFD. - Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -29,7 +29,7 @@ #define EF_APCS_26 0x08 #define EF_APCS_FLOAT 0x10 #define EF_PIC 0x20 -#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */ +#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ #define EF_NEW_ABI 0x80 #define EF_OLD_ABI 0x100 @@ -39,15 +39,16 @@ #define F_APCS_FLOAT EF_APCS_FLOAT #define F_PIC EF_PIC -/* Additional symbol types for Thumb */ -#define STT_ARM_TFUNC 0xd +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ -/* ARM-specific values for sh_flags */ -#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point */ -#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step */ +/* ARM-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ -/* ARM-specific program header flags */ -#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base */ +/* ARM-specific program header flags. */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ /* Relocation types. */ START_RELOC_NUMBERS (elf_arm_reloc_type) @@ -62,18 +63,18 @@ START_RELOC_NUMBERS (elf_arm_reloc_type) RELOC_NUMBER (R_ARM_THM_PC22, 8) RELOC_NUMBER (R_ARM_SBREL32, 9) RELOC_NUMBER (R_ARM_AMP_VCALL9, 10) - RELOC_NUMBER (R_ARM_THM_PC11, 11) /* cygnus extension to abi: thumb unconditional branch */ - RELOC_NUMBER (R_ARM_THM_PC9, 12) /* cygnus extension to abi: thumb conditional branch */ + RELOC_NUMBER (R_ARM_THM_PC11, 11) /* Cygnus extension to abi: Thumb unconditional branch. */ + RELOC_NUMBER (R_ARM_THM_PC9, 12) /* Cygnus extension to abi: Thumb conditional branch. */ RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13) RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14) - RELOC_NUMBER (R_ARM_COPY, 20) /* copy symbol at runtime */ - RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* create GOT entry */ - RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* create PLT entry */ - RELOC_NUMBER (R_ARM_RELATIVE, 23) /* adjust by program base */ - RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT */ - RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT */ - RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry */ - RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address */ + RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ + RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry. */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address. */ FAKE_RELOC (FIRST_INVALID_RELOC, 28) FAKE_RELOC (LAST_INVALID_RELOC, 249) RELOC_NUMBER (R_ARM_RSBREL32, 250) diff --git a/include/elf/arm.h b/include/elf/arm.h index 2c94b13e2..4d3405dd7 100644 --- a/include/elf/arm.h +++ b/include/elf/arm.h @@ -1,5 +1,5 @@ /* ARM ELF support for BFD. - Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -29,25 +29,28 @@ #define EF_APCS_26 0x08 #define EF_APCS_FLOAT 0x10 #define EF_PIC 0x20 -#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */ +#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ #define EF_NEW_ABI 0x80 #define EF_OLD_ABI 0x100 +#define EF_SOFT_FLOAT 0x200 /* Local aliases for some flags to match names used by COFF port. */ #define F_INTERWORK EF_INTERWORK #define F_APCS26 EF_APCS_26 #define F_APCS_FLOAT EF_APCS_FLOAT #define F_PIC EF_PIC +#define F_SOFT_FLOAT EF_SOFT_FLOAT -/* Additional symbol types for Thumb */ -#define STT_ARM_TFUNC 0xd +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ -/* ARM-specific values for sh_flags */ -#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point */ -#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step */ +/* ARM-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ -/* ARM-specific program header flags */ -#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base */ +/* ARM-specific program header flags. */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ /* Relocation types. */ START_RELOC_NUMBERS (elf_arm_reloc_type) @@ -80,8 +83,8 @@ START_RELOC_NUMBERS (elf_arm_reloc_type) FAKE_RELOC (LAST_INVALID_RELOC1, 99) RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) - RELOC_NUMBER (R_ARM_THM_PC11, 102) /* cygnus extension to abi: thumb unconditional branch */ - RELOC_NUMBER (R_ARM_THM_PC9, 103) /* cygnus extension to abi: thumb conditional branch */ + RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch */ + RELOC_NUMBER (R_ARM_THM_PC9, 103) /* Cygnus extension to abi: Thumb conditional branch */ FAKE_RELOC (FIRST_INVALID_RELOC2, 104) FAKE_RELOC (LAST_INVALID_RELOC2, 248) RELOC_NUMBER (R_ARM_RXPC25, 249) diff --git a/include/elf/avr.h b/include/elf/avr.h new file mode 100644 index 000000000..152745599 --- /dev/null +++ b/include/elf/avr.h @@ -0,0 +1,58 @@ +/* AVR ELF support for BFD. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Contributed by Denis Chertykov <denisc@overta.ru> + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_AVR_H +#define _ELF_AVR_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_AVR_MACH 0xf + +#define E_AVR_MACH_AVR1 1 +#define E_AVR_MACH_AVR2 2 +#define E_AVR_MACH_AVR3 3 +#define E_AVR_MACH_AVR4 4 + +/* Relocations. */ +START_RELOC_NUMBERS (elf_avr_reloc_type) + RELOC_NUMBER (R_AVR_NONE, 0) + RELOC_NUMBER (R_AVR_32, 1) + RELOC_NUMBER (R_AVR_7_PCREL, 2) + RELOC_NUMBER (R_AVR_13_PCREL, 3) + RELOC_NUMBER (R_AVR_16, 4) + RELOC_NUMBER (R_AVR_16_PM, 5) + RELOC_NUMBER (R_AVR_LO8_LDI, 6) + RELOC_NUMBER (R_AVR_HI8_LDI, 7) + RELOC_NUMBER (R_AVR_HH8_LDI, 8) + RELOC_NUMBER (R_AVR_LO8_LDI_NEG, 9) + RELOC_NUMBER (R_AVR_HI8_LDI_NEG, 10) + RELOC_NUMBER (R_AVR_HH8_LDI_NEG, 11) + RELOC_NUMBER (R_AVR_LO8_LDI_PM, 12) + RELOC_NUMBER (R_AVR_HI8_LDI_PM, 13) + RELOC_NUMBER (R_AVR_HH8_LDI_PM, 14) + RELOC_NUMBER (R_AVR_LO8_LDI_PM_NEG, 15) + RELOC_NUMBER (R_AVR_HI8_LDI_PM_NEG, 16) + RELOC_NUMBER (R_AVR_HH8_LDI_PM_NEG, 17) + RELOC_NUMBER (R_AVR_CALL, 18) + EMPTY_RELOC (R_AVR_max) +END_RELOC_NUMBERS + +#endif /* _ELF_AVR_H */ diff --git a/include/elf/common.h b/include/elf/common.h index cda3ba0d9..fe8c2169d 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -1,5 +1,6 @@ /* ELF support for BFD. - Copyright (C) 1991,92,93,94,95,96,97,98,99 Free Software Foundation, Inc. + Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000 + Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support, from information published in "UNIX System V Release 4, Programmers Guide: ANSI C and @@ -59,7 +60,9 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EI_OSABI 7 /* Operating System/ABI indication */ #define ELFOSABI_SYSV 0 /* UNIX System V ABI */ #define ELFOSABI_HPUX 1 /* HP-UX operating system */ +#define ELFOSABI_LINUX 3 /* GNU/Linux */ #define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ +#define ELFOSABI_ARM 97 /* ARM */ #define EI_ABIVERSION 8 /* ABI version */ @@ -89,19 +92,23 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EM_486 6 /* Intel 80486 */ #define EM_860 7 /* Intel 80860 */ #define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */ -#define EM_S370 9 /* Amdahl */ -#define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */ +#define EM_S370 9 /* IBM System/370 */ +#define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */ /* Depreciated */ +#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian (Oct 4 1999 Draft)*/ /* Depreciated */ #define EM_PARISC 15 /* HPPA */ + #define EM_VPP550 17 /* Fujitsu VPP500 */ #define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ #define EM_960 19 /* Intel 80960 */ #define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* 64-bit PowerPC */ #define EM_V800 36 /* NEC V800 series */ #define EM_FR20 37 /* Fujitsu FR20 */ #define EM_RH32 38 /* TRW RH32 */ -#define EM_MCORE 39 /* Motorolla MCore */ /* May also be taken by Fujitsu MMA */ +#define EM_MCORE 39 /* Motorola M*Core */ /* May also be taken by Fujitsu MMA */ +#define EM_RCE 39 /* Old name for MCore */ #define EM_ARM 40 /* ARM */ #define EM_OLD_ALPHA 41 /* Digital Alpha */ #define EM_SH 42 /* Hitachi SH */ @@ -112,10 +119,31 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EM_H8_300H 47 /* Hitachi H8/300H */ #define EM_H8S 48 /* Hitachi H8S */ #define EM_H8_500 49 /* Hitachi H8/500 */ -#define EM_IA_64 50 /* Intel MercedTM Processor */ +#define EM_IA_64 50 /* Intel IA-64 Processor */ #define EM_MIPS_X 51 /* Stanford MIPS-X */ #define EM_COLDFIRE 52 /* Motorola Coldfire */ #define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu Multimedia Accelerator */ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embedded RISC processor */ +#define EM_NDR1 57 /* Denso NDR1 microprocesspr */ +#define EM_STARCORE 58 /* Motorola Star*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronics ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ embedded processor */ + +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 bit microcontroller */ +#define EM_ST7 68 /* STMicroelectronics ST7 8-bit microcontroller */ +#define EM_68HC16 69 /* Motorola MC68HC16 Microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 Microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 Microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 Microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8-bit microcontroller */ +#define EM_VAX 75 /* Digital VAX */ + +#define EM_PJ 99 /* picoJava */ /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision @@ -161,6 +189,10 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* FR30 magic number - no EABI available. */ #define EM_CYGNUS_FR30 0x3330 +/* AVR magic number + Written in the absense of an ABI. */ +#define EM_AVR 0x1057 + /* See the above comment before you add a new EM_* value here. */ /* Values for e_version */ @@ -187,7 +219,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define PF_X (1 << 0) /* Segment is executable */ #define PF_W (1 << 1) /* Segment is writable */ #define PF_R (1 << 2) /* Segment is readable */ -#define PF_MASKOS 0x0F000000 /* OS-specific reserved bits */ +/* #define PF_MASKOS 0x0F000000 *//* OS-specific reserved bits */ +#define PF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ #define PF_MASKPROC 0xF0000000 /* Processor-specific reserved bits */ /* Values for section header, sh_type field */ @@ -205,6 +238,10 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define SHT_SHLIB 10 /* Reserved, unspecified semantics */ #define SHT_DYNSYM 11 /* Dynamic linking symbol table */ +#define SHT_INIT_ARRAY 14 /* Array of pointers to init functions */ +#define SHT_FINI_ARRAY 15 /* Array of pointers to finish functions */ +#define SHT_PREINIT_ARRAY 16 /* Array of pointers to pre-init functions */ + #define SHT_LOOS 0x60000000 /* Operating system specific semantics, lo */ #define SHT_HIOS 0x6fffffff /* Operating system specific semantics, hi */ @@ -222,14 +259,22 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define SHT_LOPROC 0x70000000 /* Processor-specific semantics, lo */ #define SHT_HIPROC 0x7FFFFFFF /* Processor-specific semantics, hi */ #define SHT_LOUSER 0x80000000 /* Application-specific semantics */ -#define SHT_HIUSER 0x8FFFFFFF /* Application-specific semantics */ +/* #define SHT_HIUSER 0x8FFFFFFF *//* Application-specific semantics */ +#define SHT_HIUSER 0xFFFFFFFF /* New value, defined in Oct 4, 1999 Draft */ /* Values for section header, sh_flags field */ #define SHF_WRITE (1 << 0) /* Writable data during execution */ #define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ #define SHF_EXECINSTR (1 << 2) /* Executable machine instructions */ -#define SHF_MASKOS 0x0F000000 /* OS-specific semantics */ +#define SHF_MERGE (1 << 4) /* Data in this section can be merged */ +#define SHF_STRINGS (1 << 5) /* Contains null terminated character strings */ +#define SHF_INFO_LINK (1 << 6) /* sh_info holds section header table index */ +#define SHF_LINK_ORDER (1 << 7) /* Preserve section ordering when linking */ +#define SHF_OS_NONCONFORMING (1 << 8) /* OS specifci processing required */ + +/* #define SHF_MASKOS 0x0F000000 *//* OS-specific semantics */ +#define SHF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ #define SHF_MASKPROC 0xF0000000 /* Processor-specific semantics */ /* Values of note segment descriptor types for core files. */ @@ -237,6 +282,9 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ #define NT_FPREGSET 2 /* Contains copy of fpregset struct */ #define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ +#define NT_TASKSTRUCT 4 /* Contains copy of task struct */ +#define NT_PRXFPREG 0x46e62b7f /* Contains a user_xfpregs_struct; */ + /* note name must be "LINUX". */ /* Note segments for core files on dir-style procfs systems. */ @@ -245,6 +293,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define NT_PSINFO 13 /* Has a struct psinfo */ #define NT_LWPSTATUS 16 /* Has a struct lwpstatus_t */ #define NT_LWPSINFO 17 /* Has a struct lwpsinfo_t */ +#define NT_WIN32PSTATUS 18 /* Has a struct win32_pstatus */ /* Values of note segment descriptor types for object files. */ /* (Only for hppa right now. Should this be moved elsewhere?) */ @@ -259,6 +308,26 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ELF_ST_TYPE(val) ((val) & 0xF) #define ELF_ST_INFO(bind,type) (((bind) << 4) + ((type) & 0xF)) +/* The 64bit and 32bit versions of these macros are identical, but + the ELF spec defines them, so here they are. */ +#define ELF32_ST_BIND ELF_ST_BIND +#define ELF32_ST_TYPE ELF_ST_TYPE +#define ELF32_ST_INFO ELF_ST_INFO +#define ELF64_ST_BIND ELF_ST_BIND +#define ELF64_ST_TYPE ELF_ST_TYPE +#define ELF64_ST_INFO ELF_ST_INFO + +/* This macro disassembles and assembles a symbol's visibility into + the st_other field. The STV_ defines specificy the actual visibility. */ + +#define ELF_ST_VISIBILITY(v) ((v) & 0x3) +/* The remaining bits in the st_other field are not currently used. + They should be set to zero. */ + +#define ELF32_ST_VISIBILITY ELF_ST_VISIBILITY +#define ELF64_ST_VISIBILITY ELF_ST_VISIBILITY + + #define STN_UNDEF 0 /* undefined symbol index */ #define STB_LOCAL 0 /* Symbol not visible outside obj */ @@ -274,6 +343,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define STT_FUNC 2 /* Symbol is a code object */ #define STT_SECTION 3 /* Symbol associated with a section */ #define STT_FILE 4 /* Symbol gives a file name */ +#define STT_COMMON 5 /* An uninitialised common block */ #define STT_LOOS 10 /* OS-specific semantics */ #define STT_HIOS 12 /* OS-specific semantics */ #define STT_LOPROC 13 /* Application-specific semantics */ @@ -292,6 +362,15 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define SHN_COMMON 0xFFF2 /* Associated symbol is in common */ #define SHN_HIRESERVE 0xFFFF /* End range of reserved indices */ +/* The following constants control how a symbol may be accessed once it has + become part of an executable or shared library. */ + +#define STV_DEFAULT 0 /* Visibility is specified by binding type */ +#define STV_INTERNAL 1 /* OS specific version of STV_HIDDEN */ +#define STV_HIDDEN 2 /* Can only be seen inside currect component */ +#define STV_PROTECTED 3 /* Treat as STB_LOCAL inside current component */ + + /* relocation info handling macros */ #define ELF32_R_SYM(i) ((i) >> 8) @@ -333,12 +412,28 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define DT_FINI_ARRAY 26 #define DT_INIT_ARRAYSZ 27 #define DT_FINI_ARRAYSZ 28 +#define DT_RUNPATH 29 +#define DT_FLAGS 30 -#define DT_LOOS 0x60000000 -#define DT_HIOS 0x6fffffff +#define DT_ENCODING 32 +#define DT_PREINIT_ARRAY 32 +#define DT_PREINIT_ARRAYSZ 33 + +/* Note, the Oct 4, 1999 draft of the ELF ABI changed the values + for DT_LOOS and DT_HIOS. Some implementations however, use + values outside of the new range (see below). */ +#define OLD_DT_LOOS 0x60000000 +#define DT_LOOS 0x6000000d +#define DT_HIOS 0x6fff0000 +#define OLD_DT_HIOS 0x6fffffff + +#define DT_LOPROC 0x70000000 +#define DT_HIPROC 0x7fffffff /* The next four dynamic tags are used on Solaris. We support them - everywhere. */ + everywhere. Note these values lie outside of the (new) range for + OS specific values. This is a deliberate special case and we + maintain it for backwards compatability. */ #define DT_VALRNGLO 0x6ffffd00 #define DT_PLTPADSZ 0x6ffffdf9 #define DT_MOVEENT 0x6ffffdfa @@ -394,6 +489,12 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define DF_1_TRANS 0x00000200 #define DF_1_INTERPOSE 0x00000400 +/* Flag values for the DT_FLAGS entry. */ +#define DF_ORIGIN (1 << 0) +#define DF_SYMBOLIC (1 << 1) +#define DF_TEXTREL (1 << 2) +#define DF_BIND_NOW (1 << 3) + /* These constants are used for the version number of a Elf32_Verdef structure. */ diff --git a/include/elf/dwarf.h b/include/elf/dwarf.h index 4333d5eda..1e72cd70d 100644 --- a/include/elf/dwarf.h +++ b/include/elf/dwarf.h @@ -3,7 +3,7 @@ Written by Ron Guilmette (rfg@ncd.com) -Copyright (C) 1992 Free Software Foundation, Inc. +Copyright (C) 1992, 1999 Free Software Foundation, Inc. This file is part of GNU CC. @@ -301,7 +301,8 @@ enum dwarf_source_language { /* GNU extensions */ - LANG_CHILL = 0x00009af3 /* random value for GNU Chill */ + LANG_CHILL = 0x00009af3, /* random value for GNU Chill */ + LANG_JAVA = 0x00009af4 /* random value + 1 for GNU Java */ }; #define LANG_lo_user 0x00008000 /* implementation-defined range start */ diff --git a/include/elf/dwarf2.h b/include/elf/dwarf2.h index b2cbb24d9..1bd4fa6ca 100644 --- a/include/elf/dwarf2.h +++ b/include/elf/dwarf2.h @@ -616,6 +616,7 @@ enum dwarf_source_language DW_LANG_Fortran90 = 0x0008, DW_LANG_Pascal83 = 0x0009, DW_LANG_Modula2 = 0x000a, + DW_LANG_Java = 0x9af4, DW_LANG_Mips_Assembler = 0x8001 }; diff --git a/include/elf/hppa.h b/include/elf/hppa.h index 2952e2398..0e45d7451 100644 --- a/include/elf/hppa.h +++ b/include/elf/hppa.h @@ -1,5 +1,5 @@ /* HPPA ELF support for BFD. - Copyright (C) 1993, 1994 Free Software Foundation, Inc. + Copyright (C) 1993, 1994, 1999 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -25,87 +25,92 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* Processor specific flags for the ELF header e_flags field. */ -/* Target processor IDs to be placed in the low 16 bits of the flags - field. Note these names are shared with SOM, and therefore do not - follow ELF naming conventions. */ +/* Trap null address dereferences. */ +#define EF_PARISC_TRAPNIL 0x00010000 -/* PA 1.0 big endian. */ -#ifndef CPU_PA_RISC1_0 -#define CPU_PA_RISC1_0 0x0000020b -#endif +/* .PARISC.archext section is present. */ +#define EF_PARISC_EXT 0x00020000 -/* PA 1.1 big endian. */ -#ifndef CPU_PA_RISC1_1 -#define CPU_PA_RISC1_1 0x00000210 -#endif +/* Program expects little-endian mode. */ +#define EF_PARISC_LSB 0x00040000 -/* PA 1.0 little endian (unsupported) is 0x0000028b. */ -/* PA 1.1 little endian (unsupported) is 0x00000290. */ +/* Program expects wide mode. */ +#define EF_PARISC_WIDE 0x00080000 -/* Trap null address dereferences. */ -#define ELF_PARISC_TRAPNIL 0x00010000 +/* Do not allow kernel-assisted branch prediction. */ +#define EF_PARISC_NO_KABP 0x00100000 -/* .PARISC.archext section is present. */ -#define EF_PARISC_EXT 0x00020000 +/* Allow lazy swap for dynamically allocated program segments. */ +#define EF_PARISC_LAZYSWAP 0x00400000 -/* Processor specific section types. */ +/* Architecture version */ +#define EF_PARISC_ARCH 0x0000ffff -/* Holds the global offset table, a table of pointers to external - data. */ -#define SHT_PARISC_GOT SHT_LOPROC+0 +#define EFA_PARISC_1_0 0x020b +#define EFA_PARISC_1_1 0x0210 +#define EFA_PARISC_2_0 0x0214 -/* Nonloadable section containing information in architecture - extensions used by the code. */ -#define SHT_PARISC_ARCH SHT_LOPROC+1 +/* Special section indices. */ +/* A symbol that has been declared as a tentative definition in an ANSI C + compilation. */ +#define SHN_PARISC_ANSI_COMMON 0xff00 -/* Section in which $global$ is defined. */ -#define SHT_PARISC_GLOBAL SHT_LOPROC+2 +/* A symbol that has been declared as a common block using the + huge memory model. */ +#define SHN_PARISC_HUGE_COMMON 0xff01 -/* Section holding millicode routines (mul, div, rem, dyncall, etc. */ -#define SHT_PARISC_MILLI SHT_LOPROC+3 +/* Processor specific section types. */ + +/* Section contains product specific extension bits. */ +#define SHT_PARISC_EXT 0x70000000 -/* Section holding unwind information for use by debuggers. */ -#define SHT_PARISC_UNWIND SHT_LOPROC+4 +/* Section contains unwind table entries. */ +#define SHT_PARISC_UNWIND 0x70000001 -/* Section holding the procedure linkage table. */ -#define SHT_PARISC_PLT SHT_LOPROC+5 +/* Section contains debug information for optimized code. */ +#define SHT_PARISC_DOC 0x70000002 -/* Short initialized and uninitialized data. */ -#define SHT_PARISC_SDATA SHT_LOPROC+6 -#define SHT_PARISC_SBSS SHT_LOPROC+7 +/* Section contains code annotations. */ +#define SHT_PARISC_ANNOT 0x70000003 +/* These are strictly for compatibility with the older elf32-hppa + implementation. Hopefully we can eliminate them in the future. */ /* Optional section holding argument location/relocation info. */ -#define SHT_PARISC_SYMEXTN SHT_LOPROC+8 +#define SHT_PARISC_SYMEXTN SHT_LOPROC+8 /* Option section for linker stubs. */ -#define SHT_PARISC_STUBS SHT_LOPROC+9 +#define SHT_PARISC_STUBS SHT_LOPROC+9 /* Processor specific section flags. */ -/* This section is near the global data pointer and thus allows short - addressing modes to be used. */ -#define SHF_PARISC_SHORT 0x20000000 +/* Section contains code compiled for static branch prediction. */ +#define SHF_PARISC_SBP 0x80000000 + +/* Section should be allocated from from GP. */ +#define SHF_PARISC_HUGE 0x40000000 -/* Processor specific symbol types. */ +/* Section should go near GP. */ +#define SHF_PARISC_SHORT 0x20000000 -/* Millicode function entry point. */ -#define STT_PARISC_MILLICODE STT_LOPROC+0 +/* Identifies the entry point of a millicode routine. */ +#define STT_PARISC_MILLI 13 /* ELF/HPPA relocation types */ -#include "reloc-macros.h" +/* Note: PA-ELF is defined to use only RELA relocations. */ +#include "elf/reloc-macros.h" -START_RELOC_NUMBERS (elf32_hppa_reloc_type) +START_RELOC_NUMBERS (elf_hppa_reloc_type) RELOC_NUMBER (R_PARISC_NONE, 0) /* No reloc */ - + /* These relocation types do simple base + offset relocations. */ - RELOC_NUMBER (R_PARISC_DIR32, 0x01) - RELOC_NUMBER (R_PARISC_DIR21L, 0x02) - RELOC_NUMBER (R_PARISC_DIR17R, 0x03) - RELOC_NUMBER (R_PARISC_DIR17F, 0x04) - RELOC_NUMBER (R_PARISC_DIR14R, 0x06) + RELOC_NUMBER (R_PARISC_DIR32, 1) + RELOC_NUMBER (R_PARISC_DIR21L, 2) + RELOC_NUMBER (R_PARISC_DIR17R, 3) + RELOC_NUMBER (R_PARISC_DIR17F, 4) + RELOC_NUMBER (R_PARISC_DIR14R, 6) /* PC-relative relocation types Typically used for calls. @@ -113,25 +118,28 @@ START_RELOC_NUMBERS (elf32_hppa_reloc_type) PCREL17C never reports a relocation error. When supporting argument relocations, function calls must be - accompanied by parameter relocation information. This information is + accompanied by parameter relocation information. This information is carried in the ten high-order bits of the addend field. The remaining 22 bits of of the addend field are sign-extended to form the Addend. - Note the code to build argument relocations depends on the + Note the code to build argument relocations depends on the addend being zero. A consequence of this limitation is GAS can not perform relocation reductions for function symbols. */ - - RELOC_NUMBER (R_PARISC_PCREL21L, 0x0a) - RELOC_NUMBER (R_PARISC_PCREL17R, 0x0b) - RELOC_NUMBER (R_PARISC_PCREL17F, 0x0c) - RELOC_NUMBER (R_PARISC_PCREL17C, 0x0d) - RELOC_NUMBER (R_PARISC_PCREL14R, 0x0e) - RELOC_NUMBER (R_PARISC_PCREL14F, 0x0f) + + RELOC_NUMBER (R_PARISC_PCREL32, 9) + RELOC_NUMBER (R_PARISC_PCREL21L, 10) + RELOC_NUMBER (R_PARISC_PCREL17R, 11) + RELOC_NUMBER (R_PARISC_PCREL17F, 12) + RELOC_NUMBER (R_PARISC_PCREL17C, 13) + RELOC_NUMBER (R_PARISC_PCREL14R, 14) + RELOC_NUMBER (R_PARISC_PCREL14F, 15) /* DP-relative relocation types. */ - RELOC_NUMBER (R_PARISC_DPREL21L, 0x12) - RELOC_NUMBER (R_PARISC_DPREL14R, 0x16) - RELOC_NUMBER (R_PARISC_DPREL14F, 0x17) + RELOC_NUMBER (R_PARISC_DPREL21L, 18) + RELOC_NUMBER (R_PARISC_DPREL14WR, 19) + RELOC_NUMBER (R_PARISC_DPREL14DR, 20) + RELOC_NUMBER (R_PARISC_DPREL14R, 22) + RELOC_NUMBER (R_PARISC_DPREL14F, 23) /* Data linkage table (DLT) relocation types @@ -139,49 +147,190 @@ START_RELOC_NUMBERS (elf32_hppa_reloc_type) from position-independent code within shared libraries. They are similar to the GOT relocation types in some SVR4 implementations. */ - RELOC_NUMBER (R_PARISC_DLTREL21L, 0x1a) - RELOC_NUMBER (R_PARISC_DLTREL14R, 0x1e) - RELOC_NUMBER (R_PARISC_DLTREL14F, 0x1f) + RELOC_NUMBER (R_PARISC_DLTREL21L, 26) + RELOC_NUMBER (R_PARISC_DLTREL14R, 30) + RELOC_NUMBER (R_PARISC_DLTREL14F, 31) /* DLT indirect relocation types */ - RELOC_NUMBER (R_PARISC_DLTIND21L, 0x22) - RELOC_NUMBER (R_PARISC_DLTIND14R, 0x26) - RELOC_NUMBER (R_PARISC_DLTIND14F, 0x27) + RELOC_NUMBER (R_PARISC_DLTIND21L, 34) + RELOC_NUMBER (R_PARISC_DLTIND14R, 38) + RELOC_NUMBER (R_PARISC_DLTIND14F, 39) /* Base relative relocation types. Ugh. These imply lots of state */ - RELOC_NUMBER (R_PARISC_SETBASE, 0x28) - RELOC_NUMBER (R_PARISC_BASEREL32, 0x29) - RELOC_NUMBER (R_PARISC_BASEREL21L, 0x2a) - RELOC_NUMBER (R_PARISC_BASEREL17R, 0x2b) - RELOC_NUMBER (R_PARISC_BASEREL17F, 0x2c) - RELOC_NUMBER (R_PARISC_BASEREL14R, 0x2e) - RELOC_NUMBER (R_PARISC_BASEREL14F, 0x2f) + RELOC_NUMBER (R_PARISC_SETBASE, 40) + RELOC_NUMBER (R_PARISC_SECREL32, 41) + RELOC_NUMBER (R_PARISC_BASEREL21L, 42) + RELOC_NUMBER (R_PARISC_BASEREL17R, 43) + RELOC_NUMBER (R_PARISC_BASEREL17F, 44) + RELOC_NUMBER (R_PARISC_BASEREL14R, 46) + RELOC_NUMBER (R_PARISC_BASEREL14F, 47) /* Segment relative relocation types. */ - RELOC_NUMBER (R_PARISC_TEXTREL32, 0x31) - RELOC_NUMBER (R_PARISC_DATAREL32, 0x39) + RELOC_NUMBER (R_PARISC_SEGBASE, 48) + RELOC_NUMBER (R_PARISC_SEGREL32, 49) + + /* Offsets from the PLT. */ + RELOC_NUMBER (R_PARISC_PLTOFF21L, 50) + RELOC_NUMBER (R_PARISC_PLTOFF14R, 54) + RELOC_NUMBER (R_PARISC_PLTOFF14F, 55) + + RELOC_NUMBER (R_PARISC_LTOFF_FPTR32, 57) + RELOC_NUMBER (R_PARISC_LTOFF_FPTR21L, 58) + RELOC_NUMBER (R_PARISC_LTOFF_FPTR14R, 62) + + RELOC_NUMBER (R_PARISC_FPTR64, 64) /* Plabel relocation types. */ - RELOC_NUMBER (R_PARISC_PLABEL32, 0x41) - RELOC_NUMBER (R_PARISC_PLABEL21L, 0x42) - RELOC_NUMBER (R_PARISC_PLABEL14R, 0x46) - - /* PLT relocations. */ - RELOC_NUMBER (R_PARISC_PLTIND21L, 0x82) - RELOC_NUMBER (R_PARISC_PLTIND14R, 0x86) - RELOC_NUMBER (R_PARISC_PLTIND14F, 0x87) - - /* Misc relocation types. */ - RELOC_NUMBER (R_PARISC_COPY, 0x88) - RELOC_NUMBER (R_PARISC_GLOB_DAT, 0x89) - RELOC_NUMBER (R_PARISC_JMP_SLOT, 0x8a) - RELOC_NUMBER (R_PARISC_RELATIVE, 0x8b) - - EMPTY_RELOC (R_PARISC_UNIMPLEMENTED) + RELOC_NUMBER (R_PARISC_PLABEL32, 65) + RELOC_NUMBER (R_PARISC_PLABEL21L, 66) + RELOC_NUMBER (R_PARISC_PLABEL14R, 70) + + /* PCREL relocations. */ + RELOC_NUMBER (R_PARISC_PCREL64, 72) + RELOC_NUMBER (R_PARISC_PCREL22C, 73) + RELOC_NUMBER (R_PARISC_PCREL22F, 74) + RELOC_NUMBER (R_PARISC_PCREL14WR, 75) + RELOC_NUMBER (R_PARISC_PCREL14DR, 76) + RELOC_NUMBER (R_PARISC_PCREL16F, 77) + RELOC_NUMBER (R_PARISC_PCREL16WF, 78) + RELOC_NUMBER (R_PARISC_PCREL16DF, 79) + + + RELOC_NUMBER (R_PARISC_DIR64, 80) + RELOC_NUMBER (R_PARISC_DIR64WR, 81) + RELOC_NUMBER (R_PARISC_DIR64DR, 82) + RELOC_NUMBER (R_PARISC_DIR14WR, 83) + RELOC_NUMBER (R_PARISC_DIR14DR, 84) + RELOC_NUMBER (R_PARISC_DIR16F, 85) + RELOC_NUMBER (R_PARISC_DIR16WF, 86) + RELOC_NUMBER (R_PARISC_DIR16DF, 87) + + RELOC_NUMBER (R_PARISC_GPREL64, 88) + + RELOC_NUMBER (R_PARISC_DLTREL14WR, 91) + RELOC_NUMBER (R_PARISC_DLTREL14DR, 92) + RELOC_NUMBER (R_PARISC_GPREL16F, 93) + RELOC_NUMBER (R_PARISC_GPREL16WF, 94) + RELOC_NUMBER (R_PARISC_GPREL16DF, 95) + + + RELOC_NUMBER (R_PARISC_LTOFF64, 96) + RELOC_NUMBER (R_PARISC_DLTIND14WR, 99) + RELOC_NUMBER (R_PARISC_DLTIND14DR, 100) + RELOC_NUMBER (R_PARISC_LTOFF16F, 101) + RELOC_NUMBER (R_PARISC_LTOFF16WF, 102) + RELOC_NUMBER (R_PARISC_LTOFF16DF, 103) + + RELOC_NUMBER (R_PARISC_SECREL64, 104) + + RELOC_NUMBER (R_PARISC_BASEREL14WR, 107) + RELOC_NUMBER (R_PARISC_BASEREL14DR, 108) + + RELOC_NUMBER (R_PARISC_SEGREL64, 112) + + RELOC_NUMBER (R_PARISC_PLTOFF14WR, 115) + RELOC_NUMBER (R_PARISC_PLTOFF14DR, 116) + RELOC_NUMBER (R_PARISC_PLTOFF16F, 117) + RELOC_NUMBER (R_PARISC_PLTOFF16WF, 118) + RELOC_NUMBER (R_PARISC_PLTOFF16DF, 119) + + RELOC_NUMBER (R_PARISC_LTOFF_FPTR64, 120) + RELOC_NUMBER (R_PARISC_LTOFF_FPTR14WR, 123) + RELOC_NUMBER (R_PARISC_LTOFF_FPTR14DR, 124) + RELOC_NUMBER (R_PARISC_LTOFF_FPTR16F, 125) + RELOC_NUMBER (R_PARISC_LTOFF_FPTR16WF, 126) + RELOC_NUMBER (R_PARISC_LTOFF_FPTR16DF, 127) + + + RELOC_NUMBER (R_PARISC_COPY, 128) + RELOC_NUMBER (R_PARISC_IPLT, 129) + RELOC_NUMBER (R_PARISC_EPLT, 130) + + RELOC_NUMBER (R_PARISC_TPREL32, 153) + RELOC_NUMBER (R_PARISC_TPREL21L, 154) + RELOC_NUMBER (R_PARISC_TPREL14R, 158) + + RELOC_NUMBER (R_PARISC_LTOFF_TP21L, 162) + RELOC_NUMBER (R_PARISC_LTOFF_TP14R, 166) + RELOC_NUMBER (R_PARISC_LTOFF_TP14F, 167) + + RELOC_NUMBER (R_PARISC_TPREL64, 216) + RELOC_NUMBER (R_PARISC_TPREL14WR, 219) + RELOC_NUMBER (R_PARISC_TPREL14DR, 220) + RELOC_NUMBER (R_PARISC_TPREL16F, 221) + RELOC_NUMBER (R_PARISC_TPREL16WF, 222) + RELOC_NUMBER (R_PARISC_TPREL16DF, 223) + + RELOC_NUMBER (R_PARISC_LTOFF_TP64, 224) + RELOC_NUMBER (R_PARISC_LTOFF_TP14WR, 227) + RELOC_NUMBER (R_PARISC_LTOFF_TP14DR, 228) + RELOC_NUMBER (R_PARISC_LTOFF_TP16F, 229) + RELOC_NUMBER (R_PARISC_LTOFF_TP16WF, 230) + RELOC_NUMBER (R_PARISC_LTOFF_TP16DF, 231) + EMPTY_RELOC (R_PARISC_UNIMPLEMENTED) END_RELOC_NUMBERS #ifndef RELOC_MACROS_GEN_FUNC -typedef enum elf32_hppa_reloc_type elf32_hppa_reloc_type; +typedef enum elf_hppa_reloc_type elf_hppa_reloc_type; #endif +#define PT_PARISC_ARCHEXT 0x70000000 +#define PT_PARISC_UNWIND 0x70000001 +#define PF_PARISC_SBP 0x08000000 +#define PF_HP_PAGE_SIZE 0x00100000 +#define PF_HP_FAR_SHARED 0x00200000 +#define PF_HP_NEAR_SHARED 0x00400000 +#define PF_HP_CODE 0x01000000 +#define PF_HP_MODIFY 0x02000000 +#define PF_HP_LAZYSWAP 0x04000000 +#define PF_HP_SBP 0x08000000 + + +/* Processor specific dynamic array tags. */ + +#define DT_HP_LOAD_MAP (DT_LOOS + 0x0) +#define DT_HP_DLD_FLAGS (DT_LOOS + 0x1) +#define DT_HP_DLD_HOOK (DT_LOOS + 0x2) +#define DT_HP_UX10_INIT (DT_LOOS + 0x3) +#define DT_HP_UX10_INITSZ (DT_LOOS + 0x4) +#define DT_HP_PREINIT (DT_LOOS + 0x5) +#define DT_HP_PREINITSZ (DT_LOOS + 0x6) +#define DT_HP_NEEDED (DT_LOOS + 0x7) +#define DT_HP_TIME_STAMP (DT_LOOS + 0x8) +#define DT_HP_CHECKSUM (DT_LOOS + 0x9) +#define DT_HP_GST_SIZE (DT_LOOS + 0xa) +#define DT_HP_GST_VERSION (DT_LOOS + 0xb) +#define DT_HP_GST_HASHVAL (DT_LOOS + 0xc) + +/* Values for DT_HP_DLD_FLAGS. */ +#define DT_HP_DEBUG_PRIVATE 0x0001 /* Map text private */ +#define DT_HP_DEBUG_CALLBACK 0x0002 /* Callback */ +#define DT_HP_DEBUG_CALLBACK_BOR 0x0004 /* BOR callback */ +#define DT_HP_NO_ENVVAR 0x0008 /* No env var */ +#define DT_HP_BIND_NOW 0x0010 /* Bind now */ +#define DT_HP_BIND_NONFATAL 0x0020 /* Bind non-fatal */ +#define DT_HP_BIND_VERBOSE 0x0040 /* Bind verbose */ +#define DT_HP_BIND_RESTRICTED 0x0080 /* Bind restricted */ +#define DT_HP_BIND_SYMBOLIC 0x0100 /* Bind symbolic */ +#define DT_HP_RPATH_FIRST 0x0200 /* RPATH first */ +#define DT_HP_BIND_DEPTH_FIRST 0x0400 /* Bind depth-first */ + +/* Program header extensions. */ +#define PT_HP_TLS (PT_LOOS + 0x0) +#define PT_HP_CORE_NONE (PT_LOOS + 0x1) +#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) +#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) +#define PT_HP_CORE_COMM (PT_LOOS + 0x4) +#define PT_HP_CORE_PROC (PT_LOOS + 0x5) +#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) +#define PT_HP_CORE_STACK (PT_LOOS + 0x7) +#define PT_HP_CORE_SHM (PT_LOOS + 0x8) +#define PT_HP_CORE_MMF (PT_LOOS + 0x9) +#define PT_HP_PARALLEL (PT_LOOS + 0x10) +#define PT_HP_FASTBIND (PT_LOOS + 0x11) + +/* Additional symbol types. */ +#define STT_HP_OPAQUE (STT_LOOS + 0x1) +#define STT_HP_STUB (STT_LOOS + 0x2) + #endif /* _ELF_HPPA_H */ diff --git a/include/elf/i370.h b/include/elf/i370.h new file mode 100644 index 000000000..9c021f00e --- /dev/null +++ b/include/elf/i370.h @@ -0,0 +1,46 @@ +/* i370 ELF support for BFD. + Copyright (C) 1995, 2000 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the i370 ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_I370_H +#define _ELF_I370_H + +/* Processor specific section headers, sh_type field */ + +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +#define EF_I370_RELOCATABLE 0x00010000 /* i370 -mrelocatable flag */ +#define EF_I370_RELOCATABLE_LIB 0x00008000 /* i370 -mrelocatable-lib flag */ +/* Processor specific section flags, sh_flags field */ + +#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \ + this section from executable \ + and shared objects that it \ + builds when those objects \ + are not to be furhter \ + relocated. */ +#endif /* _ELF_I370_H */ + + diff --git a/include/elf/i386.h b/include/elf/i386.h index 219f10511..058666172 100644 --- a/include/elf/i386.h +++ b/include/elf/i386.h @@ -20,7 +20,7 @@ #ifndef _ELF_I386_H #define _ELF_I386_H -#include "reloc-macros.h" +#include "elf/reloc-macros.h" START_RELOC_NUMBERS (elf_i386_reloc_type) RELOC_NUMBER (R_386_NONE, 0) /* No reloc */ diff --git a/include/elf/i960.h b/include/elf/i960.h new file mode 100644 index 000000000..3e60289ea --- /dev/null +++ b/include/elf/i960.h @@ -0,0 +1,38 @@ +/* Intel 960 ELF support for BFD. + Copyright (C) 1999 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_I960_H +#define _ELF_I960_H + +#include "elf/reloc-macros.h" + + +START_RELOC_NUMBERS (elf_i960_reloc_type) + RELOC_NUMBER (R_960_NONE, 0) + RELOC_NUMBER (R_960_12, 1) + RELOC_NUMBER (R_960_32, 2) + RELOC_NUMBER (R_960_IP24, 3) + RELOC_NUMBER (R_960_SUB, 4) + RELOC_NUMBER (R_960_OPTCALL, 5) + RELOC_NUMBER (R_960_OPTCALLX, 6) + RELOC_NUMBER (R_960_OPTCALLXA, 7) + EMPTY_RELOC (R_960_max) +END_RELOC_NUMBERS + +#endif /* _ELF_I960_H */ diff --git a/include/elf/m32r.h b/include/elf/m32r.h index 0537d1369..a12ae16ae 100644 --- a/include/elf/m32r.h +++ b/include/elf/m32r.h @@ -62,5 +62,7 @@ END_RELOC_NUMBERS /* m32r code. */ #define E_M32R_ARCH 0x00000000 +/* m32rx code. */ +#define E_M32RX_ARCH 0x10000000 #endif diff --git a/include/elf/m68k.h b/include/elf/m68k.h index db31cdcda..e2d51ef4a 100644 --- a/include/elf/m68k.h +++ b/include/elf/m68k.h @@ -53,4 +53,6 @@ START_RELOC_NUMBERS (elf_m68k_reloc_type) EMPTY_RELOC (R_68K_max) END_RELOC_NUMBERS +#define EF_CPU32 0x00810000 + #endif diff --git a/include/elf/mcore.h b/include/elf/mcore.h index a7c4dad11..62a88c909 100644 --- a/include/elf/mcore.h +++ b/include/elf/mcore.h @@ -1,4 +1,4 @@ -/* Motorolla MCore support for BFD. +/* Motorola MCore support for BFD. Copyright (C) 1995, 1999 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -34,6 +34,10 @@ START_RELOC_NUMBERS (elf_mcore_reloc_type) RELOC_NUMBER (R_MCORE_PCRELJSR_IMM11BY2, 6) RELOC_NUMBER (R_MCORE_GNU_VTINHERIT, 7) RELOC_NUMBER (R_MCORE_GNU_VTENTRY, 8) + RELOC_NUMBER (R_MCORE_RELATIVE, 9) + RELOC_NUMBER (R_MCORE_COPY, 10) + RELOC_NUMBER (R_MCORE_GLOB_DAT, 11) + RELOC_NUMBER (R_MCORE_JUMP_SLOT, 12) EMPTY_RELOC (R_MCORE_max) END_RELOC_NUMBERS diff --git a/include/elf/mips.h b/include/elf/mips.h index c967248da..1e2a9f99a 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -75,6 +75,12 @@ START_RELOC_NUMBERS (elf_mips_reloc_type) /* These relocs are used for the mips16. */ RELOC_NUMBER (R_MIPS16_26, 100) RELOC_NUMBER (R_MIPS16_GPREL, 101) + /* These are GNU extensions to handle embedded-pic. */ + RELOC_NUMBER (R_MIPS_PC32, 248) + RELOC_NUMBER (R_MIPS_PC64, 249) + RELOC_NUMBER (R_MIPS_GNU_REL16_S2, 250) + RELOC_NUMBER (R_MIPS_GNU_REL_LO16, 251) + RELOC_NUMBER (R_MIPS_GNU_REL_HI16, 252) /* These are GNU extensions to enable C++ vtable garbage collection. */ RELOC_NUMBER (R_MIPS_GNU_VTINHERIT, 253) RELOC_NUMBER (R_MIPS_GNU_VTENTRY, 254) @@ -617,10 +623,10 @@ extern void bfd_mips_elf32_swap_reginfo_out /* Special values for the st_other field in the symbol table. These are used in an Irix 5 dynamic symbol table. */ -#define STO_DEFAULT 0x00 -#define STO_INTERNAL 0x01 -#define STO_HIDDEN 0x02 -#define STO_PROTECTED 0x03 +#define STO_DEFAULT STV_DEFAULT +#define STO_INTERNAL STV_INTERNAL +#define STO_HIDDEN STV_HIDDEN +#define STO_PROTECTED STV_PROTECTED /* This value is used for a mips16 .text symbol. */ #define STO_MIPS16 0xf0 @@ -816,6 +822,40 @@ typedef struct bfd_vma ri_gp_value; } Elf64_Internal_RegInfo; +typedef struct +{ + /* The hash value computed from the name of the corresponding + dynamic symbol. */ + unsigned char ms_hash_value[4]; + /* Contains both the dynamic relocation index and the symbol flags + field. The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used + to access the individual values. The dynamic relocation index + identifies the first entry in the .rel.dyn section that + references the dynamic symbol corresponding to this msym entry. + If the index is 0, no dynamic relocations are associated with the + symbol. The symbol flags field is reserved for future use. */ + unsigned char ms_info[4]; +} Elf32_External_Msym; + +typedef struct +{ + /* The hash value computed from the name of the corresponding + dynamic symbol. */ + unsigned long ms_hash_value; + /* Contains both the dynamic relocation index and the symbol flags + field. The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used + to access the individual values. The dynamic relocation index + identifies the first entry in the .rel.dyn section that + references the dynamic symbol corresponding to this msym entry. + If the index is 0, no dynamic relocations are associated with the + symbol. The symbol flags field is reserved for future use. */ + unsigned long ms_info; +} Elf32_Internal_Msym; + +#define ELF32_MS_REL_INDEX(i) ((i) >> 8) +#define ELF32_MS_FLAGS(i) (i) & 0xff) +#define ELF32_MS_INFO(r, f) (((r) << 8) + ((f) & 0xff)) + /* MIPS ELF reginfo swapping routines. */ extern void bfd_mips_elf64_swap_reginfo_in PARAMS ((bfd *, const Elf64_External_RegInfo *, Elf64_Internal_RegInfo *)); diff --git a/include/elf/mn10300.h b/include/elf/mn10300.h index 64a075045..1b90a1379 100644 --- a/include/elf/mn10300.h +++ b/include/elf/mn10300.h @@ -50,4 +50,5 @@ END_RELOC_NUMBERS the rest are open. */ #define E_MN10300_MACH_MN10300 0x00810000 +#define E_MN10300_MACH_AM33 0x00820000 #endif /* _ELF_MN10300_H */ diff --git a/include/elf/pj.h b/include/elf/pj.h new file mode 100644 index 000000000..6bb830652 --- /dev/null +++ b/include/elf/pj.h @@ -0,0 +1,45 @@ +/* picoJava ELF support for BFD. + Copyright (C) 1999 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_PJ_H +#define _ELF_PJ_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ + +START_RELOC_NUMBERS (elf_pj_reloc_type) + RELOC_NUMBER (R_PJ_NONE, 0) + RELOC_NUMBER (R_PJ_DATA_DIR32, 1) + RELOC_NUMBER (R_PJ_CODE_REL32, 2) + RELOC_NUMBER (R_PJ_CODE_REL16, 3) + RELOC_NUMBER (R_PJ_CODE_DIR32, 6) + RELOC_NUMBER (R_PJ_CODE_DIR16, 7) + RELOC_NUMBER (R_PJ_CODE_LO16, 13) + RELOC_NUMBER (R_PJ_CODE_HI16, 14) + RELOC_NUMBER (R_PJ_GNU_VTINHERIT, 15) + RELOC_NUMBER (R_PJ_GNU_VTENTRY, 16) + EMPTY_RELOC (R_PJ_max) +END_RELOC_NUMBERS + +#define EF_PICOJAVA_ARCH 0x0000000f +#define EF_PICOJAVA_NEWCALLS 0x00000010 +#define EF_PICOJAVA_GNUCALLS 0x00000020 /* The (currently) non standard GNU calling convention */ + +#endif diff --git a/include/elf/reloc-macros.h b/include/elf/reloc-macros.h index 976229129..42174caee 100644 --- a/include/elf/reloc-macros.h +++ b/include/elf/reloc-macros.h @@ -46,8 +46,8 @@ If RELOC_MACROS_GEN_FUNC *is* defined, then instead the following function will be generated: - static char * foo PARAMS ((unsigned long rtype)); - static char * + static const char * foo PARAMS ((unsigned long rtype)); + static const char * foo (rtype) unsigned long rtype; { diff --git a/include/elf/sh.h b/include/elf/sh.h index 4a476679a..faee50994 100644 --- a/include/elf/sh.h +++ b/include/elf/sh.h @@ -20,6 +20,33 @@ #ifndef _ELF_SH_H #define _ELF_SH_H +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_SH_MACH_MASK 0x1f +#define EF_SH_UNKNOWN 0 /* For backwards compatibility. */ +#define EF_SH1 1 +#define EF_SH2 2 +#define EF_SH3 3 +#define EF_SH_HAS_DSP(flags) ((flags) & 4) +#define EF_SH_DSP 4 +#define EF_SH3_DSP 5 +#define EF_SH_HAS_FP(flags) ((flags) & 8) +#define EF_SH3E 8 +#define EF_SH4 9 + +#define EF_SH_MERGE_MACH(mach1, mach2) \ + (((((mach1) == EF_SH3 || (mach1) == EF_SH_UNKNOWN) && (mach2) == EF_SH_DSP) \ + || ((mach1) == EF_SH_DSP \ + && ((mach2) == EF_SH3 || (mach2) == EF_SH_UNKNOWN))) \ + ? EF_SH3_DSP \ + : (((mach1) < EF_SH3 && (mach2) == EF_SH_UNKNOWN) \ + || ((mach2) < EF_SH3 && (mach1) == EF_SH_UNKNOWN)) \ + ? EF_SH3 \ + : (((mach1) == EF_SH3E && (mach2) == EF_SH_UNKNOWN) \ + || ((mach2) == EF_SH3E && (mach1) == EF_SH_UNKNOWN)) \ + ? EF_SH4 \ + : ((mach1) > (mach2) ? (mach1) : (mach2))) + #include "elf/reloc-macros.h" /* Relocations. */ diff --git a/include/elf/sparc.h b/include/elf/sparc.h index c9e4cdd40..390e4a844 100644 --- a/include/elf/sparc.h +++ b/include/elf/sparc.h @@ -29,6 +29,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ #define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ #define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ +#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ #define EF_SPARC_LEDATA 0x800000 /* little endian data */ @@ -128,6 +129,8 @@ START_RELOC_NUMBERS (elf_sparc_reloc_type) /* little endian data relocs */ RELOC_NUMBER (R_SPARC_REV32, 56) + EMPTY_RELOC (R_SPARC_max_std) + RELOC_NUMBER (R_SPARC_GNU_VTINHERIT, 250) RELOC_NUMBER (R_SPARC_GNU_VTENTRY, 251) @@ -136,21 +139,15 @@ END_RELOC_NUMBERS /* Relocation macros. */ -#define ELF64_R_TYPE_DATA(info) (((bfd_vma) (info) << 32) >> 40) -#define ELF64_R_TYPE_ID(info) (((bfd_vma) (info) << 56) >> 56) -#define ELF64_R_TYPE_INFO(data, type) (((bfd_vma) (data) << 8) \ - + (bfd_vma) (type)) - -#define DT_SPARC_REGISTER 0x70000001 +#define ELF64_R_TYPE_DATA(info) \ + (((bfd_signed_vma)(ELF64_R_TYPE(info) >> 8) ^ 0x800000) - 0x800000) +#define ELF64_R_TYPE_ID(info) \ + ((info) & 0xff) +#define ELF64_R_TYPE_INFO(data, type) \ + (((bfd_vma) ((data) & 0xffffff) << 8) | (bfd_vma) (type)) -/* - * FIXME: NOT ABI -- GET RID OF THIS - * Defines the format used by the .plt. Currently defined values are - * 0 -- reserved to SI - * 1 -- absolute address in .got.plt - * 2 -- got-relative address in .got.plt - */ +/* Values for Elf64_Dyn.d_tag. */ -#define DT_SPARC_PLTFMT 0x70000001 +#define DT_SPARC_REGISTER 0x70000001 #endif /* _ELF_SPARC_H */ diff --git a/include/hashtab.h b/include/hashtab.h index 3990c14cb..5fe239391 100644 --- a/include/hashtab.h +++ b/include/hashtab.h @@ -38,69 +38,88 @@ extern "C" { #include <ansidecl.h> -/* The hash table element is represented by the following type. */ - -typedef const void *hash_table_entry_t; +/* Callback function pointer types. */ + +/* Calculate hash of a table entry. */ +typedef unsigned int (*htab_hash) PARAMS ((const void *)); + +/* Compare a table entry with a possible entry. The entry already in + the table always comes first, so the second element can be of a + different type (but in this case htab_find and htab_find_slot + cannot be used; instead the variants that accept a hash value + must be used). */ +typedef int (*htab_eq) PARAMS ((const void *, const void *)); + +/* Cleanup function called whenever a live element is removed from + the hash table. */ +typedef void (*htab_del) PARAMS ((void *)); + +/* Function called by htab_traverse for each live element. The first + arg is the slot of the element (which can be passed to htab_clear_slot + if desired), the second arg is the auxiliary pointer handed to + htab_traverse. Return 1 to continue scan, 0 to stop. */ +typedef int (*htab_trav) PARAMS ((void **, void *)); /* Hash tables are of the following type. The structure (implementation) of this type is not needed for using the hash tables. All work with hash table should be executed only through functions mentioned below. */ -typedef struct hash_table +struct htab { - /* Current size (in entries) of the hash table */ - size_t size; - /* Current number of elements including also deleted elements */ - size_t number_of_elements; - /* Current number of deleted elements in the table */ - size_t number_of_deleted_elements; - /* The following member is used for debugging. Its value is number - of all calls of `find_hash_table_entry' for the hash table. */ - int searches; - /* The following member is used for debugging. Its value is number - of collisions fixed for time of work with the hash table. */ - int collisions; - /* Pointer to function for evaluation of hash value (any unsigned value). - This function has one parameter of type hash_table_entry_t. */ - unsigned (*hash_function) PARAMS ((hash_table_entry_t)); - /* Pointer to function for test on equality of hash table elements (two - parameter of type hash_table_entry_t. */ - int (*eq_function) PARAMS ((hash_table_entry_t, hash_table_entry_t)); - /* Table itself */ - hash_table_entry_t *entries; -} *hash_table_t; - + /* Pointer to hash function. */ + htab_hash hash_f; -/* The prototypes of the package functions. */ + /* Pointer to comparison function. */ + htab_eq eq_f; -extern hash_table_t create_hash_table - PARAMS ((size_t, unsigned (*) (hash_table_entry_t), - int (*) (hash_table_entry_t, hash_table_entry_t))); + /* Pointer to cleanup function. */ + htab_del del_f; -extern void delete_hash_table PARAMS ((hash_table_t)); + /* Table itself. */ + void **entries; -extern void empty_hash_table PARAMS ((hash_table_t)); + /* Current size (in entries) of the hash table */ + size_t size; -extern hash_table_entry_t *find_hash_table_entry - PARAMS ((hash_table_t, hash_table_entry_t, int)); + /* Current number of elements including also deleted elements */ + size_t n_elements; -extern void remove_element_from_hash_table_entry PARAMS ((hash_table_t, - hash_table_entry_t)); + /* Current number of deleted elements in the table */ + size_t n_deleted; -extern void clear_hash_table_slot PARAMS ((hash_table_t, hash_table_entry_t *)); + /* The following member is used for debugging. Its value is number + of all calls of `htab_find_slot' for the hash table. */ + unsigned int searches; -extern void traverse_hash_table PARAMS ((hash_table_t, - int (*) (hash_table_entry_t, void *), - void *)); - -extern size_t hash_table_size PARAMS ((hash_table_t)); + /* The following member is used for debugging. Its value is number + of collisions fixed for time of work with the hash table. */ + unsigned int collisions; +}; -extern size_t hash_table_elements_number PARAMS ((hash_table_t)); +typedef struct htab *htab_t; -extern int hash_table_collisions PARAMS ((hash_table_t)); +/* The prototypes of the package functions. */ -extern int all_hash_table_collisions PARAMS ((void)); +extern htab_t htab_create PARAMS ((size_t, htab_hash, + htab_eq, htab_del)); +extern void htab_delete PARAMS ((htab_t)); +extern void htab_empty PARAMS ((htab_t)); + +extern void *htab_find PARAMS ((htab_t, const void *)); +extern void **htab_find_slot PARAMS ((htab_t, const void *, int)); +extern void *htab_find_with_hash PARAMS ((htab_t, const void *, + unsigned int)); +extern void **htab_find_slot_with_hash PARAMS ((htab_t, const void *, + unsigned int, int)); +extern void htab_clear_slot PARAMS ((htab_t, void **)); +extern void htab_remove_elt PARAMS ((htab_t, void *)); + +extern void htab_traverse PARAMS ((htab_t, htab_trav, void *)); + +extern size_t htab_size PARAMS ((htab_t)); +extern size_t htab_elements PARAMS ((htab_t)); +extern double htab_collisions PARAMS ((htab_t)); #ifdef __cplusplus } diff --git a/include/hp-symtab.h b/include/hp-symtab.h index fff56688e..cf626c073 100644 --- a/include/hp-symtab.h +++ b/include/hp-symtab.h @@ -88,7 +88,8 @@ enum hp_language { HP_LANGUAGE_UNKNOWN, HP_LANGUAGE_C, - HP_LANGUAGE_F77, + HP_LANGUAGE_FORTRAN, + HP_LANGUAGE_F77 = HP_LANGUAGE_FORTRAN, HP_LANGUAGE_PASCAL, HP_LANGUAGE_MODCAL, HP_LANGUAGE_COBOL, @@ -485,9 +486,11 @@ struct dntt_type_fparam unsigned int longaddr: 1; unsigned int copyparam: 1; unsigned int dflt: 1; - unsigned int unused: 16; + unsigned int doc_ranges: 1; + unsigned int misc_kind: 1; + unsigned int unused: 14; vtpointer name; - int location; + CORE_ADDR location; dnttpointer type; dnttpointer nextparam; int misc; @@ -595,7 +598,7 @@ struct dntt_type_const unsigned int kind: 10; unsigned int global: 1; unsigned int indirect: 1; - unsigned int: 3; + unsigned int location_type: 3; unsigned int classmem: 1; unsigned int unused: 15; vtpointer name; diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 79bc3cc7c..7452c2bea 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,307 @@ +2000-03-27 Nick Clifton <nickc@cygnus.com> + + * d30v.h (SHORT_A1): Fix value. + (SHORT_AR): Renumber so that it is at the end of the list of short + instructions, not the end of the list of long instructions. + +2000-03-26 Alan Modra <alan@linuxcare.com> + + * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the + problem isn't really specific to Unixware. + (OLDGCC_COMPAT): Define. + (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with + destination %st(0). + Fix lots of comments. + +2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk> + + * d30v.h: + (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated. + (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated. + (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated. + (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated. + (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated. + (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated. + (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated. + +2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (fild, fistp): Change intel d_Suf form to fildd and + fistpd without suffix. + +2000-02-24 Nick Clifton <nickc@cygnus.com> + + * cgen.h (cgen_cpu_desc): Rename field 'flags' to + 'signed_overflow_ok_p'. + Delete prototypes for cgen_set_flags() and cgen_get_flags(). + +2000-02-24 Andrew Haley <aph@cygnus.com> + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + (CGEN_CPU_TABLE): flags: new field. + Add prototypes for new functions. + +2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add some more UNIXWARE_COMPAT comments. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * i370.h: New file. + +2000-02-22 Andrew Haley <aph@cygnus.com> + + * mips.h: (OPCODE_IS_MEMBER): Add comment. + +1999-12-30 Andrew Haley <aph@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines + whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit + insns. + +2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Qualify intel mode far call and jmp with x_Suf. + +1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add JumpAbsolute qualifier to all non-intel mode + indirect jumps and calls. Add FF/3 call for intel mode. + +Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add new operand types. Add new instruction formats. + +Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" + instruction. + +1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (INSN_ISA5): New. + +1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): New. + +1999-10-29 Nick Clifton <nickc@cygnus.com> + + * d30v.h (SHORT_AR): Define. + +1999-10-18 Michael Meissner <meissner@cygnus.com> + + * alpha.h (alpha_num_opcodes): Convert to unsigned. + (alpha_num_operands): Ditto. + +Sun Oct 10 01:46:56 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> + + * hppa.h (pa_opcodes): Add load and store cache control to + instructions. Add ordered access load and store. + + * hppa.h (pa_opcode): Add new entries for addb and addib. + + * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. + + * hppa.h (pa_opcodes): Add entries for cmpb and cmpib. + +Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com> + + * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands. + +Thu Sep 23 07:08:38 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" + and "be" using completer prefixes. + + * hppa.h (pa_opcodes): Add initializers to silence compiler. + + * hppa.h: Update comments about character usage. + +Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning + up the new fstw & bve instructions. + +Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store + instructions. + + * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. + + * hppa.h (pa_opcodes): Add long offset double word load/store + instructions. + + * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and + stores. + + * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. + + * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. + + * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. + + * hppa.h (pa_opcodes): Add new syntax "be" instructions. + + * hppa.h (pa_opcodes): Note use of 'M' and 'L'. + + * hppa.h (pa_opcodes): Add support for "b,l". + + * hppa.h (pa_opcodes): Add support for "b,gate". + +Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Use 'fX' for first register operand + in xmpyu. + + * hppa.h (pa_opcodes): Fix mask for probe and probei. + + * hppa.h (pa_opcodes): Fix mask for depwi. + +Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as + an explicit output argument. + +Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. + Add a few PA2.0 loads and store variants. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * pj.h: New file. + +1999-08-29 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_regtab): Move %st to top of table, and split off + other fp reg entries. + (i386_float_regtab): To here. + +Sat Aug 28 00:25:25 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args + by 'f'. + + * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. + Add supporting args. + + * hppa.h: Document new completers and args. + * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor, + uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0 + extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions + pmenb and pmdis. + + * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, + hshr, hsub, mixh, mixw, permh. + + * hppa.h (pa_opcodes): Change completers in instructions to + use 'c' prefix. + + * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, + hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments. + + * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, + fnegabs to use 'I' instead of 'F'. + +1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd. + Document pf2iw and pi2fw as athlon insns. Remove pswapw. + Alphabetically sort PIII insns. + +Wed Aug 18 18:14:40 1999 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + +Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, + and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr. + + * hppa.h: Document 64 bit condition completers. + +Thu Aug 5 16:56:07 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Change condition args to use '?' prefix. + +1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Add DefaultSize modifier to all insns + that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf, + sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table. + +Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". + + * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. + + * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, + and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. + +1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. + +Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (struct pa_opcode): Add new field "flags". + (FLAGS_STRICT): Define. + +Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. + + * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. + +1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, + lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP + flag to fcomi and friends. + +Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Move integer arithmetic instructions after + integer logical instructions. + +1999-05-28 Linus Nordberg <linus.nordberg@canit.se> + + * m68k.h: Document new formats `E', `G', `H' and new places `N', + `n', `o'. + + * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' + and new places `m', `M', `h'. + +Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com + + * hppa.h (pa_opcodes): Add several processor specific system + instructions. + +Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + "addb", and "addib" to be used by the disassembler. + +1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> + + * i386.h (ReverseModrm): Remove all occurences. + (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, + movmskps, pextrw, pmovmskb, maskmovq. + Change NoSuf to FP on all MMX, XMM and AMD insns as these all + ignore the data size prefix. + + * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. + Mostly stolen from Doug Ledford <dledford@redhat.com> + +Sat May 8 23:27:35 1999 Richard Henderson <rth@cygnus.com> + + * ppc.h (PPC_OPCODE_64_BRIDGE): New. + 1999-04-14 Doug Evans <devans@casey.cygnus.com> * cgen.h (CGEN_ATTR): Delete member num_nonbools. diff --git a/include/opcode/alpha.h b/include/opcode/alpha.h index d18eb0445..6f31e9ae0 100644 --- a/include/opcode/alpha.h +++ b/include/opcode/alpha.h @@ -54,7 +54,7 @@ struct alpha_opcode in the order in which the disassembler should consider instructions. */ extern const struct alpha_opcode alpha_opcodes[]; -extern const int alpha_num_opcodes; +extern const unsigned alpha_num_opcodes; /* Values defined for the flags field of a struct alpha_opcode. */ @@ -135,7 +135,7 @@ struct alpha_operand the operands field of the alpha_opcodes table. */ extern const struct alpha_operand alpha_operands[]; -extern const int alpha_num_operands; +extern const unsigned alpha_num_operands; /* Values defined for the flags field of a struct alpha_operand. */ diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 84542a37c..0cff7c826 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -1037,6 +1037,12 @@ extern int cgen_macro_insn_count PARAMS ((CGEN_CPU_DESC)); /* Return value of base part of INSN. */ #define CGEN_INSN_BASE_VALUE(insn) \ CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) + +/* Standard way to test whether INSN is supported by MACH. + MACH is one of enum mach_attr. + The "|1" is because the base mach is always selected. */ +#define CGEN_INSN_MACH_HAS_P(insn, mach) \ +((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) /* Macro instructions. Macro insns aren't real insns, they map to one or more real insns. @@ -1275,6 +1281,10 @@ typedef struct cgen_cpu_desc /* Disassembler instruction hash table. */ CGEN_INSN_LIST **dis_hash_table; CGEN_INSN_LIST *dis_hash_table_entries; + + /* This field could be turned into a bitfield if room for other flags is needed. */ + unsigned int signed_overflow_ok_p; + } CGEN_CPU_TABLE; /* wip */ @@ -1377,4 +1387,13 @@ extern void cgen_put_insn_value extern const char * cgen_read_cpu_file PARAMS ((CGEN_CPU_DESC, const char * filename_)); +/* Allow signed overflow of instruction fields. */ +extern void cgen_set_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); + +/* Generate an error message if a signed field in an instruction overflows. */ +extern void cgen_clear_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); + +/* Will an error message be generated if a signed field in an instruction overflows ? */ +extern unsigned int cgen_signed_overflow_ok_p PARAMS ((CGEN_CPU_DESC)); + #endif /* CGEN_H */ diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h index 4b74c9862..7c6d32ddf 100644 --- a/include/opcode/d10v.h +++ b/include/opcode/d10v.h @@ -176,6 +176,10 @@ extern const struct d10v_operand d10v_operands[]; /* general purpose register */ #define OPERAND_GPR (0x40000) +/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ +/* needed for rac/rachi */ +#define RESTRICTED_NUM3 (0x80000) + /* Structure to hold information about predefined registers. */ struct pd_reg { diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h index b828dab32..f90b7a420 100644 --- a/include/opcode/d30v.h +++ b/include/opcode/d30v.h @@ -1,5 +1,5 @@ /* d30v.h -- Header file for D30V opcode table - Copyright 1997 Free Software Foundation, Inc. + Copyright (C) 1997, 2000 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions This file is part of GDB, GAS, and the GNU binutils. @@ -85,39 +85,46 @@ struct d30v_opcode #define SHORT_A 9 #define SHORT_B1 11 #define SHORT_B2 12 -#define SHORT_B3 13 -#define SHORT_B3b 15 -#define SHORT_D1 17 -#define SHORT_D2 19 -#define SHORT_D2B 21 -#define SHORT_U 23 /* unary SHORT_A. ABS for example */ -#define SHORT_F 25 /* SHORT_A with flag registers */ -#define SHORT_AF 27 /* SHORT_A with only the first register a flag register */ -#define SHORT_T 29 /* for trap instruction */ -#define SHORT_A5 30 /* SHORT_A with a 5-bit immediate instead of 6 */ -#define SHORT_CMP 32 /* special form for CMPcc */ -#define SHORT_CMPU 34 /* special form for CMPUcc */ -#define SHORT_A1 36 /* special form of SHORT_A for MACa opcodes where a=1 */ -#define SHORT_AA 38 /* SHORT_A with the first register an accumulator */ -#define SHORT_RA 40 /* SHORT_A with the second register an accumulator */ -#define SHORT_MODINC 42 -#define SHORT_MODDEC 43 -#define SHORT_C1 44 -#define SHORT_C2 45 -#define SHORT_UF 46 -#define SHORT_A2 47 -#define SHORT_A5S 49 -#define SHORT_NONE 51 /* no operands */ -#define LONG 52 -#define LONG_U 53 /* unary LONG */ -#define LONG_AF 54 /* LONG with the first register a flag register */ -#define LONG_CMP 55 /* special form for CMPcc and CMPUcc */ -#define LONG_M 56 /* Memory long for ldb, stb */ -#define LONG_M2 57 /* Memory long for ld2w, st2w */ -#define LONG_2 58 /* LONG with 2 operands; bratnz */ -#define LONG_2b 59 /* LONG_2 with modifier of 3 */ -#define LONG_D 60 /* for DBRAI*/ -#define LONG_Db 61 /* for repeati*/ +#define SHORT_B2r 13 +#define SHORT_B3 14 +#define SHORT_B3r 16 +#define SHORT_B3b 18 +#define SHORT_B3br 20 +#define SHORT_D1r 22 +#define SHORT_D2 24 +#define SHORT_D2r 26 +#define SHORT_D2Br 28 +#define SHORT_U 30 /* unary SHORT_A. ABS for example */ +#define SHORT_F 31 /* SHORT_A with flag registers */ +#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ +#define SHORT_T 35 /* for trap instruction */ +#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ +#define SHORT_CMP 38 /* special form for CMPcc */ +#define SHORT_CMPU 40 /* special form for CMPUcc */ +#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ +#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ +#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ +#define SHORT_MODINC 48 +#define SHORT_MODDEC 49 +#define SHORT_C1 50 +#define SHORT_C2 51 +#define SHORT_UF 52 +#define SHORT_A2 53 +#define SHORT_NONE 55 /* no operands */ +#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ +#define LONG 57 +#define LONG_U 58 /* unary LONG */ +#define LONG_Ur 59 /* LONG pc-relative */ +#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ +#define LONG_M 61 /* Memory long for ldb, stb */ +#define LONG_M2 62 /* Memory long for ld2w, st2w */ +#define LONG_2 63 /* LONG with 2 operands; jmptnz */ +#define LONG_2r 64 /* LONG with 2 operands; bratnz */ +#define LONG_2b 65 /* LONG_2 with modifier of 3 */ +#define LONG_2br 66 /* LONG_2r with modifier of 3 */ +#define LONG_D 67 /* for DJMPI */ +#define LONG_Dr 68 /* for DBRAI */ +#define LONG_Dbr 69 /* for repeati */ /* the execution unit(s) used */ int unit; @@ -146,7 +153,9 @@ struct d30v_opcode #define FLAG_JMP (1L<<13) /* instruction is a branch */ #define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ #define FLAG_MEM (1L<<15) /* reads/writes memory */ -#define FLAG_2WORD (1L<<16) /* 2 word/4 byte operation */ +#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation + New meaning: operation cannot be + combined in parallel with ADD/SUBppp. */ #define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ #define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ #define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ @@ -246,6 +255,10 @@ extern const struct d30v_operand d30v_operand_table[]; /* let the optimizer know that two registers are affected */ #define OPERAND_2REG (0x10000) +/* This operand is pc-relative. Note that repeati can have two immediate + operands, one of which is pcrel, the other (the IMM6U one) is not. */ +#define OPERAND_PCREL (0x20000) + /* The format table is an array of struct d30v_format. */ struct d30v_format { diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h index 30ccb6ccf..1c41ff07c 100644 --- a/include/opcode/hppa.h +++ b/include/opcode/hppa.h @@ -43,8 +43,12 @@ struct pa_opcode unsigned long int mask; /* ... in these bits. */ char *args; enum pa_arch arch; + char flags; }; +/* Enable/disable strict syntax checking. Not currently used, but will + be necessary for PA2.0 support in the future. */ +#define FLAG_STRICT 0x1 /* All hppa opcodes are 32 bits. @@ -53,8 +57,9 @@ struct pa_opcode particular opcode in order for an instruction to be an instance of that opcode. - The args component is a string containing one character - for each operand of the instruction. + The args component is a string containing one character for each operand of + the instruction. Characters used as a prefix allow any second character to + be used without conflicting with the main operand characters. Bit positions in this description follow HP usage of lsb = 31, "at" is lsb of field. @@ -65,9 +70,9 @@ struct pa_opcode In the args field, the following characters are unused: - ' "#$% *+- ./ :; ' - ' [\] ' - ' { } ' + ' " & - / 34 6789:;< > @' + ' C M [\] ' + ' e g l y } ' Here are all the characters: @@ -79,20 +84,10 @@ Kinds of operands: x integer register field at 15. b integer register field at 10. t integer register field at 31. - y floating point register field at 31 + a integer register field at 10 and 15 (for PERMH) 5 5 bit immediate at 15. s 2 bit space specifier at 17. S 3 bit space specifier at 18. - c indexed load completer. - C short load and store completer. - Y Store Bytes Short completer - < non-negated compare/subtract conditions. - a compare/subtract conditions - d non-negated add conditions - & logical instruction conditions - U unit instruction conditions - > shift/extract/deposit conditions. - ~ bvb,bb conditions V 5 bit immediate value at 31 i 11 bit immediate value at 31 j 14 bit immediate value at 31 @@ -101,20 +96,28 @@ Kinds of operands: N nullification for spop and copr instructions w 12 bit branch displacement W 17 bit branch displacement (PC relative) + X 22 bit branch displacement (PC relative) z 17 bit branch displacement (just a number, not an address) Also these: + . 2 bit shift amount at 25 + * 4 bit shift amount at 25 p 5 bit shift count at 26 (to support the SHD instruction) encoded as 31-p + ~ 6 bit shift count at 20,22:26 encoded as 63-~. P 5 bit bit position at 26 + q 6 bit bit position at 20,22:26 T 5 bit field length at 31 (encoded as 32-T) + % 6 bit field length at 23,27:31 (variable extract/deposit) + | 6 bit field length at 19,27:31 (fixed extract/deposit) A 13 bit immediate at 18 (to support the BREAK instruction) ^ like b, but describes a control register - Z System Control Completer (to support LPA, LHA, etc.) + ! sar (cr11) register D 26 bit immediate at 31 (to support the DIAG instruction) + $ 9 bit immediate at 28 (to support POPBTS) - f 3 bit Special Function Unit identifier at 25 + v 3 bit Special Function Unit identifier at 25 O 20 bit Special Function Unit operation split between 15 bits at 20 and 5 bits at 31 o 15 bit Special Function Unit operation at 20 @@ -129,37 +132,126 @@ Also these: I Source Floating Point Operand Format Completer encoded 1 bits at 20 (for 0xe format FP instructions) G Destination Floating Point Operand Format Completer encoded 2 bits at 18 - M Floating-Point Compare Conditions (encoded as 5 bits at 31) - ? non-negated/negated compare/subtract conditions. - @ non-negated/negated add conditions. - ! non-negated add conditions. + H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' + (very similar to 'F') - s 2 bit space specifier at 17. - b register field at 10. r 5 bit immediate value at 31 (for the break instruction) (very similar to V above, except the value is unsigned instead of low_sign_ext) R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions) (same as r above, except the value is in a different location) + U 10 bit immediate value at 15 (for SSM, RSM on pa2.0) Q 5 bit immediate value at 10 (a bit position specified in the bb instruction. It's the same as r above, except the value is in a different location) - | shift/extract/deposit conditions when used in a conditional branch - -And these (PJH) for PA-89 F.P. registers and instructions: - - v a 't' operand type extended to handle L/R register halves. - E a 'b' operand type extended to handle L/R register halves. - X an 'x' operand type extended to handle L/R register halves. - J a 'b' operand type further extended to handle extra 1.1 registers - K a 'x' operand type further extended to handle extra 1.1 registers - 4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub' - 6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub' - 7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub' - 8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub') - 9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub') - H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' - (very similar to 'F') + B 5 bit immediate value at 10 (a bit position specified in + the bb instruction. Similar to Q, but 64bit handling is + different. + Z %r1 -- implicit target of addil instruction. + L ,%r2 completer for new syntax branch + { Source format completer for fcnv + _ Destination format completer for fcnv + h cbit for fcmp + = gfx tests for ftest + d 14bit offset for single precision FP long load/store. + # 14bit offset for double precision FP load long/store. + J Yet another 14bit offset with an unusual encoding. + K Yet another 14bit offset with an unusual encoding. + Y %sr0,%r31 -- implicit target of be,l instruction. + @ implicit immediate value of 0 + +Completer operands all have 'c' as the prefix: + + cx indexed load completer. + cm short load and store completer. + cq long load and store completer (like cm, but inserted into a + different location in the target instruction). + cs store bytes short completer. + ce long load/store completer for LDW/STW with a different encoding than the + others + cc load cache control hint + cd load and clear cache control hint + cC store cache control hint + co ordered access + + cp branch link and push completer + cP branch pop completer + cl branch link completer + cg branch gate completer + + cw read/write completer for PROBE + cW wide completer for MFCTL + cL local processor completer for cache control + cZ System Control Completer (to support LPA, LHA, etc.) + + ci correction completer for DCOR + ca add completer + cy 32 bit add carry completer + cY 64 bit add carry completer + cv signed overflow trap completer + ct trap on condition completer for ADDI, SUB + cT trap on condition completer for UADDCM + cb 32 bit borrow completer for SUB + cB 64 bit borrow completer for SUB + + ch left/right half completer + cH signed/unsigned saturation completer + cS signed/unsigned completer at 21 + c* permutation completer + +Condition operands all have '?' as the prefix: + + ?f Floating point compare conditions (encoded as 5 bits at 31) + + ?a add conditions + ?A 64 bit add conditions + ?@ add branch conditions followed by nullify + ?d non-negated add branch conditions + ?D negated add branch conditions + ?w wide mode non-negated add branch conditions + ?W wide mode negated add branch conditions + + ?s compare/subtract conditions + ?S 64 bit compare/subtract conditions + ?t non-negated compare and branch conditions + ?n 32 bit compare and branch conditions followed by nullify + ?N 64 bit compare and branch conditions followed by nullify + ?Q 64 bit compare and branch conditions for CMPIB instruction + + ?l logical conditions + ?L 64 bit logical conditions + + ?b branch on bit conditions + ?B 64 bit branch on bit conditions + + ?x shift/extract/deposit conditions + ?X 64 bit shift/extract/deposit conditions + ?y shift/extract/deposit conditions followed by nullify for conditional + branches + + ?u unit conditions + ?U 64 bit unit conditions + +Floating point registers all have 'f' as a prefix: + + ft target register at 31 + fT target register with L/R halves at 31 + fa operand 1 register at 10 + fA operand 1 register with L/R halves at 10 + fX Same as fA, except prints a space before register during disasm + fb operand 2 register at 15 + fB operand 2 register with L/R halves at 15 + fC operand 3 register with L/R halves at 16:18,21:23 + fe Like fT, but encoding is different. + +Float registers for fmpyadd and fmpysub: + + fi mult operand 1 register at 10 + fj mult operand 2 register at 15 + fk mult target register at 20 + fl add/sub operand register at 25 + fm add/sub target register at 31 + */ @@ -178,299 +270,562 @@ static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e static const struct pa_opcode pa_opcodes[] = { - /* pseudo-instructions */ -{ "b", 0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */ -{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10}, /* ldo val(r0),r */ -{ "comib", 0x84000000, 0xfc000000, "?n5,b,w", pa10}, /* comib{tf}*/ -{ "comb", 0x80000000, 0xfc000000, "?nx,b,w", pa10}, /* comb{tf} */ -{ "addb", 0xa0000000, 0xfc000000, "@nx,b,w", pa10}, /* addb{tf} */ -{ "addib", 0xa4000000, 0xfc000000, "@n5,b,w", pa10}, /* addib{tf}*/ -{ "nop", 0x08000240, 0xffffffff, "", pa10}, /* or 0,0,0 */ -{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10}, /* or r,0,t */ -{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */ +{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ + +{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, +{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, + +{ "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, +{ "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, +{ "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +{ "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT}, +{ "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT}, +{ "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20, FLAG_STRICT}, +{ "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, +{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20, FLAG_STRICT}, +{ "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +{ "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */ +{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */ +{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */ /* Loads and Stores for integer registers. */ -{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10}, -{ "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10}, -{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10}, -{ "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10}, -{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10}, -{ "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10}, -{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10}, -{ "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10}, -{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10}, -{ "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10}, -{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10}, -{ "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10}, -{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10}, -{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10}, -{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10}, -{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(s,b),t", pa10}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(b),t", pa10}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(s,b),t", pa10}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(b),t", pa10}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(s,b),t", pa10}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(b),t", pa10}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cx(b),t", pa10}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(s,b),t", pa10}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(b),t", pa10}, -{ "ldws", 0x0c001080, 0xfc001fc0, "C5(s,b),t", pa10}, -{ "ldws", 0x0c001080, 0xfc001fc0, "C5(b),t", pa10}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(s,b),t", pa10}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(b),t", pa10}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(s,b),t", pa10}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(b),t", pa10}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "C5(b),t", pa10}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(s,b),t", pa10}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(b),t", pa10}, -{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(s,b)", pa10}, -{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(b)", pa10}, -{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(s,b)", pa10}, -{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(b)", pa10}, -{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(s,b)", pa10}, -{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(b)", pa10}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "Cx,V(b)", pa10}, -{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(s,b)", pa10}, -{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(b)", pa10}, + +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(b)", pa10, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(b)", pa20, FLAG_STRICT}, +{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa10, FLAG_STRICT}, +{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa10, FLAG_STRICT}, +{ "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(b),t", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, 0}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, 0}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, 0}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, 0}, /* Immediate instructions. */ -{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10}, -{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10}, -{ "addil", 0x28000000, 0xfc000000, "k,b", pa10}, +{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0}, /* Branching instructions. */ -{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10}, -{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10}, -{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10}, -{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10}, -{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10}, -{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10}, -{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10}, -{ "movb", 0xc8000000, 0xfc000000, "|nx,b,w", pa10}, -{ "movib", 0xcc000000, 0xfc000000, "|n5,b,w", pa10}, -{ "combt", 0x80000000, 0xfc000000, "<nx,b,w", pa10}, -{ "combf", 0x88000000, 0xfc000000, "<nx,b,w", pa10}, -{ "comibt", 0x84000000, 0xfc000000, "<n5,b,w", pa10}, -{ "comibf", 0x8c000000, 0xfc000000, "<n5,b,w", pa10}, -{ "addbt", 0xa0000000, 0xfc000000, "!nx,b,w", pa10}, -{ "addbf", 0xa8000000, 0xfc000000, "!nx,b,w", pa10}, -{ "addibt", 0xa4000000, 0xfc000000, "!n5,b,w", pa10}, -{ "addibf", 0xac000000, 0xfc000000, "!n5,b,w", pa10}, -{ "bb", 0xc4004000, 0xfc004000, "~nx,Q,w", pa10}, -{ "bvb", 0xc0004000, 0xffe04000, "~nx,w", pa10}, +{ "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT}, +{ "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT}, +{ "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */ +{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0}, +{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0}, +{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0}, +{ "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT}, +{ "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0}, +{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0}, +{ "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0}, +{ "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, +{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, +{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, +{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, +{ "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT}, /* Computation Instructions */ -{ "add", 0x08000600, 0xfc000fe0, "dx,b,t", pa10}, -{ "addl", 0x08000a00, 0xfc000fe0, "dx,b,t", pa10}, -{ "addo", 0x08000e00, 0xfc000fe0, "dx,b,t", pa10}, -{ "addc", 0x08000700, 0xfc000fe0, "dx,b,t", pa10}, -{ "addco", 0x08000f00, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1add", 0x08000640, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1addl", 0x08000a40, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1addo", 0x08000e40, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2add", 0x08000680, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2addl", 0x08000a80, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2addo", 0x08000e80, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3add", 0x080006c0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3addl", 0x08000ac0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3addo", 0x08000ec0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sub", 0x08000400, 0xfc000fe0, "ax,b,t", pa10}, -{ "subo", 0x08000c00, 0xfc000fe0, "ax,b,t", pa10}, -{ "subb", 0x08000500, 0xfc000fe0, "ax,b,t", pa10}, -{ "subbo", 0x08000d00, 0xfc000fe0, "ax,b,t", pa10}, -{ "subt", 0x080004c0, 0xfc000fe0, "ax,b,t", pa10}, -{ "subto", 0x08000cc0, 0xfc000fe0, "ax,b,t", pa10}, -{ "ds", 0x08000440, 0xfc000fe0, "ax,b,t", pa10}, -{ "comclr", 0x08000880, 0xfc000fe0, "ax,b,t", pa10}, -{ "or", 0x08000240, 0xfc000fe0, "&x,b,t", pa10}, -{ "xor", 0x08000280, 0xfc000fe0, "&x,b,t", pa10}, -{ "and", 0x08000200, 0xfc000fe0, "&x,b,t", pa10}, -{ "andcm", 0x08000000, 0xfc000fe0, "&x,b,t", pa10}, -{ "uxor", 0x08000380, 0xfc000fe0, "Ux,b,t", pa10}, -{ "uaddcm", 0x08000980, 0xfc000fe0, "Ux,b,t", pa10}, -{ "uaddcmt", 0x080009c0, 0xfc000fe0, "Ux,b,t", pa10}, -{ "dcor", 0x08000b80, 0xfc1f0fe0, "Ub,t", pa10}, -{ "idcor", 0x08000bc0, 0xfc1f0fe0, "Ub,t", pa10}, -{ "addi", 0xb4000000, 0xfc000800, "di,b,x", pa10}, -{ "addio", 0xb4000800, 0xfc000800, "di,b,x", pa10}, -{ "addit", 0xb0000000, 0xfc000800, "di,b,x", pa10}, -{ "addito", 0xb0000800, 0xfc000800, "di,b,x", pa10}, -{ "subi", 0x94000000, 0xfc000800, "ai,b,x", pa10}, -{ "subio", 0x94000800, 0xfc000800, "ai,b,x", pa10}, -{ "comiclr", 0x90000000, 0xfc000800, "ai,b,x", pa10}, +{ "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT}, +{ "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT}, +{ "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT}, +{ "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT}, +{ "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0}, +{ "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT}, +{ "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT}, +{ "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT}, +{ "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT}, +{ "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0}, + +/* Subword Operation Instructions */ + +{ "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT}, +{ "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT}, +{ "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT}, +{ "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT}, + /* Extract and Deposit Instructions */ -{ "vshd", 0xd0000000, 0xfc001fe0, ">x,b,t", pa10}, -{ "shd", 0xd0000800, 0xfc001c00, ">x,b,p,t", pa10}, -{ "vextru", 0xd0001000, 0xfc001fe0, ">b,T,x", pa10}, -{ "vextrs", 0xd0001400, 0xfc001fe0, ">b,T,x", pa10}, -{ "extru", 0xd0001800, 0xfc001c00, ">b,P,T,x", pa10}, -{ "extrs", 0xd0001c00, 0xfc001c00, ">b,P,T,x", pa10}, -{ "zvdep", 0xd4000000, 0xfc001fe0, ">x,T,b", pa10}, -{ "vdep", 0xd4000400, 0xfc001fe0, ">x,T,b", pa10}, -{ "zdep", 0xd4000800, 0xfc001c00, ">x,p,T,b", pa10}, -{ "dep", 0xd4000c00, 0xfc001c00, ">x,p,T,b", pa10}, -{ "zvdepi", 0xd4001000, 0xfc001fe0, ">5,T,b", pa10}, -{ "vdepi", 0xd4001400, 0xfc001fe0, ">5,T,b", pa10}, -{ "zdepi", 0xd4001800, 0xfc001c00, ">5,p,T,b", pa10}, -{ "depi", 0xd4001c00, 0xfc001c00, ">5,p,T,b", pa10}, +{ "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT}, +{ "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT}, +{ "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT}, +{ "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT}, +{ "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0}, +{ "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0}, +{ "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT}, +{ "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT}, +{ "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT}, +{ "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT}, +{ "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT}, +{ "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT}, +{ "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT}, +{ "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT}, +{ "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT}, +{ "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT}, +{ "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0}, +{ "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0}, /* System Control Instructions */ -{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10}, -{ "rfi", 0x00000c00, 0xffffffff, "", pa10}, -{ "rfir", 0x00000ca0, 0xffffffff, "", pa11}, -{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10}, -{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10}, -{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10}, -{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10}, -{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10}, -{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10}, -{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10}, -{ "sync", 0x00000400, 0xffffffff, "", pa10}, -{ "syncdma", 0x00100400, 0xffffffff, "", pa10}, -{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10}, -{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10}, -{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10}, -{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10}, -{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10}, -{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10}, -{ "lpa", 0x04001340, 0xfc003fc0, "Zx(s,b),t", pa10}, -{ "lpa", 0x04001340, 0xfc003fc0, "Zx(b),t", pa10}, -{ "lha", 0x04001300, 0xfc003fc0, "Zx(s,b),t", pa10}, -{ "lha", 0x04001300, 0xfc003fc0, "Zx(b),t", pa10}, -{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10}, -{ "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(b)", pa10}, -{ "pitlb", 0x04000200, 0xfc001fdf, "Zx(S,b)", pa10}, -{ "pitlb", 0x04000200, 0xfc001fdf, "Zx(b)", pa10}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(b)", pa10}, -{ "pitlbe", 0x04000240, 0xfc001fdf, "Zx(S,b)", pa10}, -{ "pitlbe", 0x04000240, 0xfc001fdf, "Zx(b)", pa10}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10}, -{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10}, -{ "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10}, -{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10}, -{ "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10}, -{ "pdc", 0x04001380, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "pdc", 0x04001380, 0xfc003fdf, "Zx(b)", pa10}, -{ "fdc", 0x04001280, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "fdc", 0x04001280, 0xfc003fdf, "Zx(b)", pa10}, -{ "fic", 0x04000280, 0xfc001fdf, "Zx(S,b)", pa10}, -{ "fic", 0x04000280, 0xfc001fdf, "Zx(b)", pa10}, -{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(b)", pa10}, -{ "fice", 0x040002c0, 0xfc001fdf, "Zx(S,b)", pa10}, -{ "fice", 0x040002c0, 0xfc001fdf, "Zx(b)", pa10}, -{ "diag", 0x14000000, 0xfc000000, "D", pa10}, +{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0}, +{ "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT}, +{ "rfi", 0x00000c00, 0xffffffff, "", pa10, 0}, +{ "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0}, +{ "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10, 0}, +{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0}, +{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0}, +{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, +{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT}, +{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0}, +{ "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT}, +{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0}, +{ "sync", 0x00000400, 0xffffffff, "", pa10, 0}, +{ "syncdma", 0x00100400, 0xffffffff, "", pa10, 0}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT}, +{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10, 0}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, +{ "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, +{ "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, + +/* These may be specific to certain versions of the PA. Joel claimed + they were 72000 (7200?) specific. However, I'm almost certain the + mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, +{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, +{ "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, +{ "tocdis", 0x14401620, 0xffffffff, "", pa10, 0}, +{ "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, +{ "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either the Timex FPU or the Mustang ERS (not sure which) manual. */ -{ "gfw", 0x04001680, 0xfc003fdf, "Zx(s,b)", pa11}, -{ "gfw", 0x04001680, 0xfc003fdf, "Zx(b)", pa11}, -{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(s,b)", pa11}, -{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(b)", pa11}, +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(b)", pa11, 0}, /* Floating Point Coprocessor Instructions */ - -{ "fldwx", 0x24000000, 0xfc001f80, "cx(s,b),v", pa10}, -{ "fldwx", 0x24000000, 0xfc001f80, "cx(b),v", pa10}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cx(s,b),y", pa10}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cx(b),y", pa10}, -{ "fstwx", 0x24000200, 0xfc001f80, "cv,x(s,b)", pa10}, -{ "fstwx", 0x24000200, 0xfc001f80, "cv,x(b)", pa10}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(s,b)", pa10}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(b)", pa10}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(s,b)", pa10}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(b)", pa10}, -{ "fldws", 0x24001000, 0xfc001f80, "C5(s,b),v", pa10}, -{ "fldws", 0x24001000, 0xfc001f80, "C5(b),v", pa10}, -{ "fldds", 0x2c001000, 0xfc001fc0, "C5(s,b),y", pa10}, -{ "fldds", 0x2c001000, 0xfc001fc0, "C5(b),y", pa10}, -{ "fstws", 0x24001200, 0xfc001f80, "Cv,5(s,b)", pa10}, -{ "fstws", 0x24001200, 0xfc001f80, "Cv,5(b)", pa10}, -{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(s,b)", pa10}, -{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(b)", pa10}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(s,b)", pa10}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(b)", pa10}, -{ "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "fadd", 0x38000600, 0xfc00e720, "IJ,K,v", pa10}, -{ "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "fsub", 0x38002600, 0xfc00e720, "IJ,K,v", pa10}, -{ "fmpy", 0x30004600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "fmpy", 0x38004600, 0xfc00e720, "IJ,K,v", pa10}, -{ "fdiv", 0x30006600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "fdiv", 0x38006600, 0xfc00e720, "IJ,K,v", pa10}, -{ "fsqrt", 0x30008000, 0xfc1fe7e0, "FE,v", pa10}, -{ "fsqrt", 0x38008000, 0xfc1fe720, "FJ,v", pa10}, -{ "fabs", 0x30006000, 0xfc1fe7e0, "FE,v", pa10}, -{ "fabs", 0x38006000, 0xfc1fe720, "FJ,v", pa10}, -{ "frem", 0x30008600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "frem", 0x38008600, 0xfc00e720, "FJ,K,v", pa10}, -{ "frnd", 0x3000a000, 0xfc1fe7e0, "FE,v", pa10}, -{ "frnd", 0x3800a000, 0xfc1fe720, "FJ,v", pa10}, -{ "fcpy", 0x30004000, 0xfc1fe7e0, "FE,v", pa10}, -{ "fcpy", 0x38004000, 0xfc1fe720, "FJ,v", pa10}, -{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGE,v", pa10}, -{ "fcnvff", 0x38000200, 0xfc1f8720, "FGJ,v", pa10}, -{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGE,v", pa10}, -{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGJ,v", pa10}, -{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGE,v", pa10}, -{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGJ,v", pa10}, -{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGE,v", pa10}, -{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGJ,v", pa10}, -{ "fmpyfadd", 0xb8000000, 0xfc000020, "FE,X,3,v", pa20}, -{ "fmpynfadd", 0xb8000020, 0xfc000020, "FE,X,3,v", pa20}, -{ "fneg", 0x3000c000, 0xfc1fe7e0, "FE,v", pa20}, -{ "fneg", 0x3800c000, 0xfc1fe720, "FJ,v", pa20}, -{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "FE,v", pa20}, -{ "fnegabs", 0x3800e000, 0xfc1fe720, "FJ,v", pa20}, -{ "fcmp", 0x30000400, 0xfc00e7e0, "FME,X", pa10}, -{ "fcmp", 0x38000400, 0xfc00e720, "IMJ,K", pa10}, -{ "xmpyu", 0x38004700, 0xfc00e720, "E,X,v", pa11}, -{ "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8", pa11}, -{ "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8", pa11}, -{ "ftest", 0x30002420, 0xffffffff, "", pa10}, -{ "fid", 0x30000000, 0xffffffff, "", pa11}, - + +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc001380, "cxccx(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000004, "cJd(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000004, "cJd(b),fe", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fe,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000004, "cJfe,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000004, "cJfe,d(b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, +{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0}, +{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0}, +{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0}, +{ "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0}, +{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT}, +{ "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT}, +{ "ftest", 0x30002420, 0xffffffff, "", pa10, 0}, +{ "fid", 0x30000000, 0xffffffff, "", pa11, 0}, + +/* Performance Monitor Instructions */ + +{ "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT}, +{ "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT}, /* Assist Instructions */ -{ "spop0", 0x10000000, 0xfc000600, "f,ON", pa10}, -{ "spop1", 0x10000200, 0xfc000600, "f,oNt", pa10}, -{ "spop2", 0x10000400, 0xfc000600, "f,1Nb", pa10}, -{ "spop3", 0x10000600, 0xfc000600, "f,0Nx,b", pa10}, -{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucx(s,b),t", pa10}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucx(b),t", pa10}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucx(s,b),t", pa10}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucx(b),t", pa10}, -{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(s,b)", pa10}, -{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(b)", pa10}, -{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(s,b)", pa10}, -{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(b)", pa10}, -{ "cldws", 0x24001000, 0xfc001e00, "uC5(s,b),t", pa10}, -{ "cldws", 0x24001000, 0xfc001e00, "uC5(b),t", pa10}, -{ "cldds", 0x2c001000, 0xfc001e00, "uC5(s,b),t", pa10}, -{ "cldds", 0x2c001000, 0xfc001e00, "uC5(b),t", pa10}, -{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(s,b)", pa10}, -{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(b)", pa10}, -{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(s,b)", pa10}, -{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(b)", pa10}, +{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0}, +{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0}, +{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, +{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, +{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, 0}, +{ "cldw", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, }; #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) diff --git a/include/opcode/i370.h b/include/opcode/i370.h new file mode 100644 index 000000000..f2049e741 --- /dev/null +++ b/include/opcode/i370.h @@ -0,0 +1,265 @@ +/* i370.h -- Header file for S/390 opcode table + Copyright 1994, 95, 98, 99, 2000 Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef I370_H +#define I370_H + +/* The opcode table is an array of struct i370_opcode. */ +typedef union +{ + unsigned int i[2]; + unsigned short s[4]; + unsigned char b[8]; +} i370_insn_t; + +struct i370_opcode +{ + /* The opcode name. */ + const char *name; + + /* the length of the instruction */ + char len; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + i370_insn_t opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + i370_insn_t mask; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The defined values + are listed below. */ + unsigned long flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct i370_opcode i370_opcodes[]; +extern const int i370_num_opcodes; + +/* Values defined for the flags field of a struct i370_opcode. */ + +/* Opcode is defined for the original 360 architecture. */ +#define I370_OPCODE_360 (0x01) + +/* Opcode is defined for the 370 architecture. */ +#define I370_OPCODE_370 (0x02) + +/* Opcode is defined for the 370-XA architecture. */ +#define I370_OPCODE_370_XA (0x04) + +/* Opcode is defined for the ESA/370 architecture. */ +#define I370_OPCODE_ESA370 (0x08) + +/* Opcode is defined for the ESA/390 architecture. */ +#define I370_OPCODE_ESA390 (0x10) + +/* Opcode is defined for the ESA/390 w/ BFP facility. */ +#define I370_OPCODE_ESA390_BF (0x20) + +/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ +#define I370_OPCODE_ESA390_BS (0x40) + +/* Opcode is defined for the ESA/390 w/ checksum facility. */ +#define I370_OPCODE_ESA390_CK (0x80) + +/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ +#define I370_OPCODE_ESA390_CM (0x100) + +/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ +#define I370_OPCODE_ESA390_FX (0x200) + +/* Opcode is defined for the ESA/390 w/ HFP facility. */ +#define I370_OPCODE_ESA390_HX (0x400) + +/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ +#define I370_OPCODE_ESA390_IR (0x800) + +/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ +#define I370_OPCODE_ESA390_MI (0x1000) + +/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ +#define I370_OPCODE_ESA390_PC (0x2000) + +/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ +#define I370_OPCODE_ESA390_PL (0x4000) + +/* Opcode is defined for the ESA/390 w/ square-root facility. */ +#define I370_OPCODE_ESA390_QR (0x8000) + +/* Opcode is defined for the ESA/390 w/ resume-program facility. */ +#define I370_OPCODE_ESA390_RP (0x10000) + +/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ +#define I370_OPCODE_ESA390_SA (0x20000) + +/* Opcode is defined for the ESA/390 w/ subspace group facility. */ +#define I370_OPCODE_ESA390_SG (0x40000) + +/* Opcode is defined for the ESA/390 w/ string facility. */ +#define I370_OPCODE_ESA390_SR (0x80000) + +/* Opcode is defined for the ESA/390 w/ trap facility. */ +#define I370_OPCODE_ESA390_TR (0x100000) + +#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) + + +/* The operands table is an array of struct i370_operand. */ + +struct i370_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + i370_insn_t (*insert) PARAMS ((i370_insn_t instruction, long op, + const char **errmsg)); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & I370_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) PARAMS ((i370_insn_t instruction, int *invalid)); + + /* One bit syntax flags. */ + unsigned long flags; + + /* name -- handy for debugging, otherwise pointless */ + char * name; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the i370_opcodes table. */ + +extern const struct i370_operand i370_operands[]; + +/* Values defined for the flags field of a struct i370_operand. */ + +/* This operand should be wrapped in parentheses rather than + separated from the previous by a comma. This is used for S, RS and + SS form instructions which want their operands to look like + reg,displacement(basereg) */ +#define I370_OPERAND_SBASE (0x01) + +/* This operand is a base register. It may or may not appear next + to an index register, i.e. either of the two forms + reg,displacement(basereg) + reg,displacement(index,basereg) */ +#define I370_OPERAND_BASE (0x02) + +/* This pair of operands should be wrapped in parentheses rather than + separated from the last by a comma. This is used for the RX form + instructions which want their operands to look like + reg,displacement(index,basereg) */ +#define I370_OPERAND_INDEX (0x04) + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define I370_OPERAND_GPR (0x08) + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define I370_OPERAND_FPR (0x10) + +/* This operand is a displacement. */ +#define I370_OPERAND_RELATIVE (0x20) + +/* This operand is a length, such as that in SS form instructions. */ +#define I370_OPERAND_LENGTH (0x40) + +/* This operand is optional, and is zero if omitted. This is used for + the optional B2 field in the shift-left, shift-right instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ +#define I370_OPERAND_OPTIONAL (0x80) + + +/* Define some misc macros. We keep them with the operands table + for simplicity. The macro table is an array of struct i370_macro. */ + +struct i370_macro +{ + /* The macro name. */ + const char *name; + + /* The number of operands the macro takes. */ + unsigned int operands; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct i370_opcode flags field. */ + unsigned long flags; + + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char *format; +}; + +extern const struct i370_macro i370_macros[]; +extern const int i370_num_macros; + + +#endif /* I370_H */ diff --git a/include/opcode/i386.h b/include/opcode/i386.h index ef8fece15..d399f4eb2 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -17,32 +17,38 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* The UnixWare assembler, and probably other AT&T derived ix86 Unix - assemblers, generate floating point instructions with reversed - source and destination registers in certain cases. Unfortunately, - gcc and possibly many other programs use this reversed syntax, so - we're stuck with it. +/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived + ix86 Unix assemblers, generate floating point instructions with + reversed source and destination registers in certain cases. + Unfortunately, gcc and possibly many other programs use this + reversed syntax, so we're stuck with it. - eg. `fsub %st(3),%st' results in st <- st - st(3) as expected, but - `fsub %st,%st(3)' results in st(3) <- st - st(3), rather than - the expected st(3) <- st(3) - st ! + eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but + `fsub %st,%st(3)' results in st(3) = st - st(3), rather than + the expected st(3) = st(3) - st This happens with all the non-commutative arithmetic floating point operations with two register operands, where the source register is - %st, and destination register is %st(i). Look for FloatDR below. */ + %st, and destination register is %st(i). See FloatDR below. -#ifndef UNIXWARE_COMPAT + The affected opcode map is dceX, dcfX, deeX, defX. */ + +#ifndef SYSV386_COMPAT /* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes at your peril. gcc generates UnixWare + non-broken opcodes at your peril. gcc generates SystemV/386 compatible instructions. */ -#define UNIXWARE_COMPAT 1 +#define SYSV386_COMPAT 1 +#endif +#ifndef OLDGCC_COMPAT +/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could + generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands + reversed. */ +#define OLDGCC_COMPAT SYSV386_COMPAT #endif - static const template i386_optab[] = { #define X None -#define ReverseModrm (ReverseRegRegmem|Modrm) #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) @@ -64,13 +70,16 @@ static const template i386_optab[] = { #define sl_FP (sl_Suf|IgnoreSize) #define sld_FP (sld_Suf|IgnoreSize) #define sldx_FP (sldx_Suf|IgnoreSize) -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT +/* Someone forgot that the FloatR bit reverses the operation when not + equal to the FloatD bit. ie. Changing only FloatD results in the + destination being swapped *and* the direction being reversed. */ #define FloatDR FloatD #else #define FloatDR (FloatD|FloatR) #endif -/* move instructions */ +/* Move instructions. */ #define MOV_AX_DISP32 0xa0 { "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, { "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } }, @@ -83,55 +92,53 @@ static const template i386_optab[] = { the implementation defined value is zero). */ { "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, { "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } }, -/* move to/from control debug registers */ -{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32, 0} }, -{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32, 0} }, -{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32, 0} }, +/* Move to/from control debug registers. */ +{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, -/* move with sign extend */ +/* Move with sign extend. */ /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid conflict with the "movs" string move instruction. */ -{"movsbl", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg32, 0} }, -{"movsbw", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg16, 0} }, -{"movswl", 2, 0x0fbf, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} }, +{"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, +{"movsbw", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, +{"movswl", 2, 0x0fbf, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, /* Intel Syntax */ -{"movsx", 2, 0x0fbf, X, w_Suf|ReverseModrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, -{"movsx", 2, 0x0fbe, X, b_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, +{"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -/* move with zero extend */ -{"movzb", 2, 0x0fb6, X, wl_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzwl", 2, 0x0fb7, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} }, +/* Move with zero extend. */ +{"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, /* Intel Syntax */ -{"movzx", 2, 0x0fb7, X, w_Suf|ReverseModrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, -{"movzx", 2, 0x0fb6, X, b_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, - -/* push instructions */ -{"push", 1, 0x50, X, wl_Suf|ShortForm, { WordReg,0,0 } }, -{"push", 1, 0xff, 6, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, wl_Suf, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, wl_Suf, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } }, -{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } }, -/* push all */ -{"pusha", 0, 0x60, X, wl_Suf, { 0, 0, 0 } }, - -/* pop instructions */ -{"pop", 1, 0x58, X, wl_Suf|ShortForm, { WordReg,0,0 } }, -{"pop", 1, 0x8f, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } }, +{"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, + +/* Push instructions. */ +{"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, +{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +{"pusha", 0, 0x60, X, wl_Suf|DefaultSize, { 0, 0, 0 } }, + +/* Pop instructions. */ +{"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, #define POP_SEG_SHORT 0x07 -{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } }, -{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } }, -/* pop all */ -{"popa", 0, 0x61, X, wl_Suf, { 0, 0, 0 } }, +{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +{"popa", 0, 0x61, X, wl_Suf|DefaultSize, { 0, 0, 0 } }, -/* xchg exchange instructions - xchg commutes: we allow both operand orders */ +/* Exchange instructions. + xchg commutes: we allow both operand orders. */ {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, -/* in/out from ports */ +/* In/out from ports. */ {"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } }, {"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, {"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } }, @@ -141,17 +148,17 @@ static const template i386_optab[] = { {"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } }, {"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } }, -/* load effective address */ +/* Load effective address. */ {"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } }, -/* load segment registers from memory */ +/* Load segment registers from memory. */ {"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, {"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, {"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, {"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, {"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -/* flags register instructions */ +/* Flags register instructions. */ {"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} }, {"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} }, {"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} }, @@ -159,13 +166,13 @@ static const template i386_optab[] = { {"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} }, {"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} }, {"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, wl_Suf, { 0, 0, 0} }, -{"popf", 0, 0x9d, X, wl_Suf, { 0, 0, 0} }, +{"pushf", 0, 0x9c, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"popf", 0, 0x9d, X, wl_Suf|DefaultSize, { 0, 0, 0} }, {"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} }, {"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} }, {"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} }, -/* arithmetic */ +/* Arithmetic. */ {"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} }, @@ -212,7 +219,7 @@ static const template i386_optab[] = { {"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} }, {"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, -/* iclr with 1 operand is really xor with 2 operands. */ +/* iclr with 1 operand is really xor with 2 operands. */ {"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, {"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, @@ -232,13 +239,13 @@ static const template i386_optab[] = { {"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} }, {"aam", 1, 0xd4, X, NoSuf, { Imm8S, 0, 0} }, -/* conversion insns */ -/* conversion: intel naming */ +/* Conversion insns. */ +/* Intel naming */ {"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, {"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, {"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, {"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} }, -/* att naming */ +/* AT&T naming */ {"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, {"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, {"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, @@ -250,9 +257,9 @@ static const template i386_optab[] = { These multiplies can only be selected with single operand forms. */ {"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, {"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 2, 0x0faf, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"imul", 3, 0x6b, X, wl_Suf|ReverseModrm, { Imm8S, WordReg|WordMem, WordReg} }, -{"imul", 3, 0x69, X, wl_Suf|ReverseModrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, +{"imul", 2, 0x0faf, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"imul", 3, 0x6b, X, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, +{"imul", 3, 0x69, X, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, /* imul with 2 operands mimics imul with 3 by putting the register in both i.rm.reg & i.rm.regmem fields. regKludge enables this transformation. */ @@ -311,31 +318,34 @@ static const template i386_optab[] = { {"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, {"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -/* control transfer instructions */ -{"call", 1, 0xe8, X, wl_Suf|JumpDword, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xff, 2, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +/* Control transfer instructions. */ +{"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, +{"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"lcall", 1, 0xff, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +/* Intel Syntax */ +{"call", 1, 0xff, 3, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, +{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +{"lcall", 1, 0xff, 3, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, #define JUMP_PC_RELATIVE 0xeb {"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} }, {"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"jmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +/* Intel Syntax */ +{"jmp", 1, 0xff, 5, x_Suf|Modrm, { WordMem, 0, 0} }, {"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, -{"ret", 0, 0xc3, X, wl_Suf, { 0, 0, 0} }, -{"ret", 1, 0xc2, X, wl_Suf, { Imm16, 0, 0} }, -{"lret", 0, 0xcb, X, wl_Suf, { 0, 0, 0} }, -{"lret", 1, 0xca, X, wl_Suf, { Imm16, 0, 0} }, -{"enter", 2, 0xc8, X, wl_Suf, { Imm16, Imm8, 0} }, -{"leave", 0, 0xc9, X, wl_Suf, { 0, 0, 0} }, +{"ret", 0, 0xc3, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"ret", 1, 0xc2, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, +{"lret", 0, 0xcb, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"lret", 1, 0xca, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, +{"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, +{"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} }, -/* conditional jumps */ +/* Conditional jumps. */ {"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} }, {"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} }, {"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, @@ -381,7 +391,7 @@ static const template i386_optab[] = { {"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, {"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, -/* set byte on flag instructions */ +/* Set byte on flag instructions. */ {"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, {"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, {"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, @@ -413,7 +423,7 @@ static const template i386_optab[] = { {"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, {"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -/* string manipulation */ +/* String manipulation. */ {"cmps", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, {"cmps", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, {"scmp", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, @@ -447,9 +457,9 @@ static const template i386_optab[] = { {"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} }, {"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} }, -/* bit manipulation */ -{"bsf", 2, 0x0fbc, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"bsr", 2, 0x0fbd, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, +/* Bit manipulation. */ +{"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, {"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, {"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, @@ -459,44 +469,44 @@ static const template i386_optab[] = { {"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, {"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -/* interrupts & op. sys insns */ +/* Interrupts & op. sys insns. */ /* See gas/config/tc-i386.c for conversion of 'int $3' into the special - int 3 insn. */ + int 3 insn. */ #define INT_OPCODE 0xcd #define INT3_OPCODE 0xcc {"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} }, {"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} }, {"into", 0, 0xce, X, NoSuf, { 0, 0, 0} }, {"iret", 0, 0xcf, X, wl_Suf, { 0, 0, 0} }, -/* i386sl, i486sl, later 486, and Pentium */ +/* i386sl, i486sl, later 486, and Pentium. */ {"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} }, {"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} }, {"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} }, -/* nop is actually 'xchgl %eax, %eax' */ +/* nop is actually 'xchgl %eax, %eax'. */ {"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} }, -/* protection control */ -{"arpl", 2, 0x63, X, NoSuf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, -{"lar", 2, 0x0f02, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, +/* Protection control. */ +{"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, +{"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} }, {"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lldt", 1, 0x0f00, 2, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lmsw", 1, 0x0f01, 6, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lsl", 2, 0x0f03, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"ltr", 1, 0x0f00, 3, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} }, {"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, {"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"str", 1, 0x0f00, 1, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verr", 1, 0x0f00, 4, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verw", 1, 0x0f00, 5, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -/* floating point instructions */ +/* Floating point instructions. */ /* load */ {"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */ @@ -506,7 +516,7 @@ static const template i386_optab[] = { {"fld", 1, 0xdb, 5, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */ {"fild", 1, 0xdf, 0, sl_Suf|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */ /* Intel Syntax */ -{"fild", 1, 0xdf, 5, d_Suf|IgnoreSize|Modrm,{ LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ +{"fildd", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ {"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ {"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ {"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */ @@ -526,7 +536,7 @@ static const template i386_optab[] = { {"fstp", 1, 0xdb, 7, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */ {"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */ /* Intel Syntax */ -{"fistp", 1, 0xdf, 7, d_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ +{"fistpd", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ {"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ {"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ {"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */ @@ -575,7 +585,7 @@ static const template i386_optab[] = { /* add */ {"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, {"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fadd %st(i), %st */ -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, /* alias for faddp */ #endif {"fadd", 1, 0xd8, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, @@ -589,17 +599,19 @@ static const template i386_optab[] = { /* subtract */ {"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, {"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubp */ #endif {"fsub", 1, 0xd8, 4, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, {"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, {"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT {"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +#endif #else {"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, @@ -609,17 +621,19 @@ static const template i386_optab[] = { /* subtract reverse */ {"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, {"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubrp */ #endif {"fsubr", 1, 0xd8, 5, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, {"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, {"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT {"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +#endif #else {"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, @@ -629,7 +643,7 @@ static const template i386_optab[] = { /* multiply */ {"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, {"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fmulp */ #endif {"fmul", 1, 0xd8, 1, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, @@ -643,17 +657,19 @@ static const template i386_optab[] = { /* divide */ {"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, {"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivp */ #endif {"fdiv", 1, 0xd8, 6, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, {"fidiv", 1, 0xde, 6, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, {"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT {"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +#endif #else {"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, @@ -663,17 +679,19 @@ static const template i386_optab[] = { /* divide reverse */ {"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, {"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivrp */ #endif {"fdivr", 1, 0xd8, 7, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, {"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -#if UNIXWARE_COMPAT +#if SYSV386_COMPAT {"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, {"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT {"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +#endif #else {"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, @@ -713,8 +731,7 @@ static const template i386_optab[] = { {"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} }, {"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} }, {"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} }, -/* Short forms of fldenv, fstenv use data size prefix. - FIXME: Are these the right suffixes? */ +/* Short forms of fldenv, fstenv use data size prefix. */ {"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} }, {"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, {"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} }, @@ -729,9 +746,8 @@ static const template i386_optab[] = { #define FWAIT_OPCODE 0x9b {"fwait", 0, 0x9b, X, FP, { 0, 0, 0} }, -/* - opcode prefixes; we allow them as seperate insns too -*/ +/* Opcode prefixes; we allow them as separate insns too. */ + #define ADDR_PREFIX_OPCODE 0x67 {"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, {"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, @@ -765,202 +781,305 @@ static const template i386_optab[] = { {"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, {"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, -/* 486 extensions */ +/* 486 extensions. */ -{"bswap", 1, 0x0fc8, X, NoSuf|ShortForm, { Reg32,0,0 } }, +{"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } }, {"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} }, {"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} }, {"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} }, -/* 586 and late 486 extensions */ +/* 586 and late 486 extensions. */ {"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} }, -/* Pentium extensions */ +/* Pentium extensions. */ {"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} }, {"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} }, {"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} }, {"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} }, -{"sysenter", 0, 0x0f34, X, NoSuf, { 0, 0, 0} }, -{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, +{"sysenter",0, 0x0f34, X, NoSuf, { 0, 0, 0} }, +{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, +{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, -/* Pentium Pro extensions */ +/* Pentium Pro extensions. */ {"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} }, {"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* official undefined instr. */ {"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* alias for ud2 */ {"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, /* 2nd. official undefined instr. */ -{"cmovo", 2, 0x0f40, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovno", 2, 0x0f41, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovb", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovc", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnae", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovae", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnc", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnb", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmove", 2, 0x0f44, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovz", 2, 0x0f44, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovne", 2, 0x0f45, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnz", 2, 0x0f45, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovbe", 2, 0x0f46, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovna", 2, 0x0f46, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmova", 2, 0x0f47, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnbe", 2, 0x0f47, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovs", 2, 0x0f48, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovns", 2, 0x0f49, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovp", 2, 0x0f4a, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnp", 2, 0x0f4b, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovl", 2, 0x0f4c, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnge", 2, 0x0f4c, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovge", 2, 0x0f4d, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnl", 2, 0x0f4d, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovle", 2, 0x0f4e, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovng", 2, 0x0f4e, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovg", 2, 0x0f4f, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnle", 2, 0x0f4f, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, - -{"fcmovb", 2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnae",2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmove", 2, 0xdac8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovbe", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovna", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovu", 2, 0xdad8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovae", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnb", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovne", 2, 0xdbc8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmova", 2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnbe",2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnu", 2, 0xdbd8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, - -{"fcomi", 2, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcomi", 0, 0xdbf1, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fcomi", 1, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fucomi", 2, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomi", 0, 0xdbe9, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fucomi", 1, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fcomip", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 0, 0xdff1, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fcompi", 1, 0xdff0, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fucomip", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 0, 0xdfe9, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fucompi", 1, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, +{"cmovo", 2, 0x0f40, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovno", 2, 0x0f41, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovb", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovc", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovae", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnc", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnb", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmove", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovz", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovne", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnz", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovbe", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovna", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmova", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovs", 2, 0x0f48, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovns", 2, 0x0f49, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovp", 2, 0x0f4a, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnp", 2, 0x0f4b, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovl", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovge", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnl", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovle", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovng", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, + +{"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, + +{"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} }, +{"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} }, +{"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} }, +{"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} }, +{"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} }, /* MMX instructions. */ -{"emms", 0, 0x0f77, X, NoSuf, { 0, 0, 0 } }, -{"movd", 2, 0x0f6e, X, NoSuf|Modrm, { Reg32|LongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, NoSuf|Modrm, { RegMMX, Reg32|LongMem, 0 } }, -{"movq", 2, 0x0f6f, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, NoSuf|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, -{"packssdw", 2, 0x0f6b, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packsswb", 2, 0x0f63, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packuswb", 2, 0x0f67, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddb", 2, 0x0ffc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddw", 2, 0x0ffd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddd", 2, 0x0ffe, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsb", 2, 0x0fec, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsw", 2, 0x0fed, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusb", 2, 0x0fdc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusw", 2, 0x0fdd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pand", 2, 0x0fdb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pandn", 2, 0x0fdf, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x0f74, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x0f75, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x0f76, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x0f64, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x0f65, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x0f66, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x0ff5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x0fe5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmullw", 2, 0x0fd5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"por", 2, 0x0feb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x0ff1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x0f71, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x0ff2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pslld", 2, 0x0f72, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x0ff3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllq", 2, 0x0f73, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x0fe1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psraw", 2, 0x0f71, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x0fe2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrad", 2, 0x0f72, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x0fd1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlw", 2, 0x0f71, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x0fd2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrld", 2, 0x0f72, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x0fd3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlq", 2, 0x0f73, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psubb", 2, 0x0ff8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubw", 2, 0x0ff9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubd", 2, 0x0ffa, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsb", 2, 0x0fe8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsw", 2, 0x0fe9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusb", 2, 0x0fd8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusw", 2, 0x0fd9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhbw",2, 0x0f68, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhwd",2, 0x0f69, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhdq",2, 0x0f6a, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklbw",2, 0x0f60, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklwd",2, 0x0f61, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckldq",2, 0x0f62, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pxor", 2, 0x0fef, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, - - -/* AMD 3DNow! instructions */ -#define AMD_3DNOW_OPCODE 0x0f0f - -{"prefetch", 1, 0x0f0d, 0, NoSuf|Modrm, { ByteMem, 0, 0 } }, -{"prefetchw",1, 0x0f0d, 1, NoSuf|Modrm, { ByteMem, 0, 0 } }, -{"femms", 0, 0x0f0e, X, NoSuf, { 0, 0, 0 } }, -{"pavgusb", 2, 0x0f0f, 0xbf, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2id", 2, 0x0f0f, 0x1d, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfacc", 2, 0x0f0f, 0xae, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfadd", 2, 0x0f0f, 0x9e, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpeq", 2, 0x0f0f, 0xb0, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpge", 2, 0x0f0f, 0x90, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpgt", 2, 0x0f0f, 0xa0, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmax", 2, 0x0f0f, 0xa4, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmin", 2, 0x0f0f, 0x94, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmul", 2, 0x0f0f, 0xb4, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcp", 2, 0x0f0f, 0x96, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit1", 2, 0x0f0f, 0xa6, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit2", 2, 0x0f0f, 0xb6, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqit1", 2, 0x0f0f, 0xa7, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqrt", 2, 0x0f0f, 0x97, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsub", 2, 0x0f0f, 0x9a, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsubr", 2, 0x0f0f, 0xaa, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fd", 2, 0x0f0f, 0x0d, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhrw", 2, 0x0f0f, 0xb7, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"emms", 0, 0x0f77, X, FP, { 0, 0, 0 } }, +{"movd", 2, 0x0f6e, X, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, +{"movq", 2, 0x0f6f, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7f, X, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, +{"packssdw", 2, 0x0f6b, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packsswb", 2, 0x0f63, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packuswb", 2, 0x0f67, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddb", 2, 0x0ffc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddw", 2, 0x0ffd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddd", 2, 0x0ffe, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsb", 2, 0x0fec, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsw", 2, 0x0fed, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusb", 2, 0x0fdc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusw", 2, 0x0fdd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pand", 2, 0x0fdb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pandn", 2, 0x0fdf, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqb", 2, 0x0f74, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqw", 2, 0x0f75, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqd", 2, 0x0f76, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtb", 2, 0x0f64, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtw", 2, 0x0f65, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtd", 2, 0x0f66, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmaddwd", 2, 0x0ff5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhw", 2, 0x0fe5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmullw", 2, 0x0fd5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"por", 2, 0x0feb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x0ff1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x0f71, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"pslld", 2, 0x0ff2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pslld", 2, 0x0f72, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psllq", 2, 0x0ff3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllq", 2, 0x0f73, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psraw", 2, 0x0fe1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psraw", 2, 0x0f71, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrad", 2, 0x0fe2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrad", 2, 0x0f72, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlw", 2, 0x0fd1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlw", 2, 0x0f71, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrld", 2, 0x0fd2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrld", 2, 0x0f72, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlq", 2, 0x0fd3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlq", 2, 0x0f73, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psubb", 2, 0x0ff8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubw", 2, 0x0ff9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubd", 2, 0x0ffa, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsb", 2, 0x0fe8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsw", 2, 0x0fe9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusb", 2, 0x0fd8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusw", 2, 0x0fd9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhbw",2, 0x0f68, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhwd",2, 0x0f69, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhdq",2, 0x0f6a, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklbw",2, 0x0f60, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklwd",2, 0x0f61, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckldq",2, 0x0f62, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, + + +/* PIII Katmai New Instructions / SIMD instructions. */ + +{"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"andnps", 2, 0x0f55, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andps", 2, 0x0f54, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqps", 2, 0x0fc2, 0, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqss", 2, 0xf30fc2, 0, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpleps", 2, 0x0fc2, 2, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpless", 2, 0xf30fc2, 2, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpltps", 2, 0x0fc2, 1, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltss", 2, 0xf30fc2, 1, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpneqps", 2, 0x0fc2, 4, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqss", 2, 0xf30fc2, 4, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnleps", 2, 0x0fc2, 6, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnless", 2, 0xf30fc2, 6, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnltps", 2, 0x0fc2, 5, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltss", 2, 0xf30fc2, 5, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpordps", 2, 0x0fc2, 7, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordss", 2, 0xf30fc2, 7, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpunordps",2, 0x0fc2, 3, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordss",2, 0xf30fc2, 3, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpps", 3, 0x0fc2, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"cmpss", 3, 0xf30fc2, X, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, +{"comiss", 2, 0x0f2f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cvtpi2ps", 2, 0x0f2a, X, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtps2pi", 2, 0x0f2d, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtsi2ss", 2, 0xf30f2a, X, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } }, +{"cvtss2si", 2, 0xf30f2d, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"cvttps2pi", 2, 0x0f2c, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttss2si", 2, 0xf30f2c, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"divps", 2, 0x0f5e, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divss", 2, 0xf30f5e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ldmxcsr", 1, 0x0fae, 2, FP|Modrm, { WordMem, 0, 0 } }, +{"maskmovq", 2, 0x0ff7, X, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, +{"maxps", 2, 0x0f5f, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxss", 2, 0xf30f5f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"minps", 2, 0x0f5d, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minss", 2, 0xf30f5d, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f28, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f29, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhlps", 2, 0x0f12, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f16, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f17, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlhps", 2, 0x0f16, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f12, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f13, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movmskps", 2, 0x0f50, X, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"movntps", 2, 0x0f2b, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movntq", 2, 0x0fe7, X, FP|Modrm, { RegMMX, LLongMem, 0 } }, +{"movss", 2, 0xf30f10, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movss", 2, 0xf30f11, X, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, +{"movups", 2, 0x0f10, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movups", 2, 0x0f11, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulps", 2, 0x0f59, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulss", 2, 0xf30f59, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"orps", 2, 0x0f56, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgb", 2, 0x0fe0, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgw", 2, 0x0fe3, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pextrw", 3, 0x0fc5, X, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, +{"pinsrw", 3, 0x0fc4, X, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, +{"pmaxsw", 2, 0x0fee, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxub", 2, 0x0fde, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminsw", 2, 0x0fea, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminub", 2, 0x0fda, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmovmskb", 2, 0x0fd7, X, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, +{"pmulhuw", 2, 0x0fe4, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"prefetchnta", 1, 0x0f18, 0, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht0", 1, 0x0f18, 1, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht1", 1, 0x0f18, 2, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht2", 1, 0x0f18, 3, FP|Modrm, { LLongMem, 0, 0 } }, +{"psadbw", 2, 0x0ff6, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pshufw", 3, 0x0f70, X, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, +{"rcpps", 2, 0x0f53, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rcpss", 2, 0xf30f53, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"rsqrtps", 2, 0x0f52, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rsqrtss", 2, 0xf30f52, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"sfence", 0, 0x0faef8, X, FP, { 0, 0, 0 } }, +{"shufps", 3, 0x0fc6, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtps", 2, 0x0f51, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtss", 2, 0xf30f51, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"stmxcsr", 1, 0x0fae, 3, FP|Modrm, { WordMem, 0, 0 } }, +{"subps", 2, 0x0f5c, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subss", 2, 0xf30f5c, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ucomiss", 2, 0x0f2e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"unpckhps", 2, 0x0f15, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, + +/* AMD 3DNow! instructions. */ + +{"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } }, +{"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } }, +{"femms", 0, 0x0f0e, X, FP, { 0, 0, 0 } }, +{"pavgusb", 2, 0x0f0f, 0xbf, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2id", 2, 0x0f0f, 0x1d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2iw", 2, 0x0f0f, 0x1c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfacc", 2, 0x0f0f, 0xae, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfadd", 2, 0x0f0f, 0x9e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpeq", 2, 0x0f0f, 0xb0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpge", 2, 0x0f0f, 0x90, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpgt", 2, 0x0f0f, 0xa0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmax", 2, 0x0f0f, 0xa4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmin", 2, 0x0f0f, 0x94, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmul", 2, 0x0f0f, 0xb4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfnacc", 2, 0x0f0f, 0x8a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfpnacc", 2, 0x0f0f, 0x8e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfrcp", 2, 0x0f0f, 0x96, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqrt", 2, 0x0f0f, 0x97, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsub", 2, 0x0f0f, 0x9a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsubr", 2, 0x0f0f, 0xaa, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fd", 2, 0x0f0f, 0x0d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fw", 2, 0x0f0f, 0x0c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pmulhrw", 2, 0x0f0f, 0xb7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pswapd", 2, 0x0f0f, 0xbb, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ {NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ }; #undef X -#undef ReverseModrm #undef NoSuf #undef b_Suf #undef w_Suf #undef l_Suf +#undef d_Suf +#undef x_Suf #undef bw_Suf #undef bl_Suf #undef wl_Suf #undef sl_Suf +#undef sld_Suf +#undef sldx_Suf #undef bwl_Suf +#undef bwld_Suf #undef FP #undef l_FP +#undef d_FP +#undef x_FP #undef sl_FP +#undef sld_FP +#undef sldx_FP #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ -/* 386 register table */ +/* 386 register table. */ static const reg_entry i386_regtab[] = { + /* make %st first as we test for it */ + {"st", FloatReg|FloatAcc, 0}, /* 8 bit regs */ {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, @@ -1030,16 +1149,7 @@ static const reg_entry i386_regtab[] = { {"tr5", Test, 5}, {"tr6", Test, 6}, {"tr7", Test, 7}, - /* float registers */ - {"st(0)", FloatReg|FloatAcc, 0}, - {"st", FloatReg|FloatAcc, 0}, - {"st(1)", FloatReg, 1}, - {"st(2)", FloatReg, 2}, - {"st(3)", FloatReg, 3}, - {"st(4)", FloatReg, 4}, - {"st(5)", FloatReg, 5}, - {"st(6)", FloatReg, 6}, - {"st(7)", FloatReg, 7}, + /* mmx and simd registers */ {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2}, @@ -1047,7 +1157,26 @@ static const reg_entry i386_regtab[] = { {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, {"mm6", RegMMX, 6}, - {"mm7", RegMMX, 7} + {"mm7", RegMMX, 7}, + {"xmm0", RegXMM, 0}, + {"xmm1", RegXMM, 1}, + {"xmm2", RegXMM, 2}, + {"xmm3", RegXMM, 3}, + {"xmm4", RegXMM, 4}, + {"xmm5", RegXMM, 5}, + {"xmm6", RegXMM, 6}, + {"xmm7", RegXMM, 7} +}; + +static const reg_entry i386_float_regtab[] = { + {"st(0)", FloatReg|FloatAcc, 0}, + {"st(1)", FloatReg, 1}, + {"st(2)", FloatReg, 2}, + {"st(3)", FloatReg, 3}, + {"st(4)", FloatReg, 4}, + {"st(5)", FloatReg, 5}, + {"st(6)", FloatReg, 6}, + {"st(7)", FloatReg, 7} }; #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h index ecb3f95dd..3208b77f4 100644 --- a/include/opcode/m68k.h +++ b/include/opcode/m68k.h @@ -1,5 +1,5 @@ /* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. + Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1999 Free Software Foundation. This file is part of GDB, GAS, and the GNU binutils. @@ -36,6 +36,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define m68851 0x080 #define cpu32 0x100 /* e.g., 68332 */ #define mcf5200 0x200 +#define mcf5206e 0x400 +#define mcf5307 0x800 /* handy aliases */ #define m68040up (m68040 | m68060) @@ -43,6 +45,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define m68020up (m68020 | m68030up) #define m68010up (m68010 | cpu32 | m68020up) #define m68000up (m68000 | m68010up) +#define mcf (mcf5200 | mcf5206e | mcf5307) #define mfloat (m68881 | m68882 | m68040 | m68060) #define mmmu (m68851 | m68030 | m68040 | m68060) @@ -87,7 +90,7 @@ struct m68k_opcode_alias operand; the second, the place it is stored. */ /* Kinds of operands: - Characters used: AaBCcDdFfIJkLlMmnOopQqRrSsTtUVvWXYZ0123|*~%;@!&$?/<>#^+- + Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+- D data register only. Stored as 3 bits. A address register only. Stored as 3 bits. @@ -121,6 +124,9 @@ struct m68k_opcode_alias C the CCR. No need to store it; this is just for filtering validity. S the SR. No need to store, just as with CCR. U the USP. No need to store, just as with CCR. + E the ACC. No need to store, just as with CCR. + G the MACSR. No need to store, just as with CCR. + H the MASK. No need to store, just as with CCR. I Coprocessor ID. Not printed if 1. The Coprocessor ID is always extracted from the 'd' field of word one, which means that an extended @@ -170,6 +176,9 @@ struct m68k_opcode_alias for both caches. Used in cinv and cpush. Always stored in position "d". + u Any register, with ``upper'' or ``lower'' specification. Used + in the mac instructions with size word. + The remainder are all stored as 6 bits using an address mode and a register number; they differ in which addressing modes they match. @@ -260,6 +269,8 @@ struct m68k_opcode_alias */ /* Places to put an operand, for non-general operands: + Characters used: BbCcDdghijkLlMmNnostWw123456789 + s source, low bits of first word. d dest, shifted 9 in first word 1 second word, shifted 12 @@ -293,6 +304,24 @@ struct m68k_opcode_alias C floating point coprocessor constant - 7 bits. Also used for static K-factors... j Movec register #, stored in 12 low bits of second word. + m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word + and remaining 3 bits of register shifted 9 bits in first word. + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split + with MSB shifted 6 bits in first word and remaining 3 bits of + register shifted 9 bits in first word. No upper/lower + indication is done.) Use with `R' or `u' format. + o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + M For M[S]ACw; 4 bits in low bits of first word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + N For M[S]ACw; 4 bits in low bits of second word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + h shift indicator (scale factor), 1 bit shifted 10 in second word Places to put operand, for general operands: d destination, shifted 6 bits in first word diff --git a/include/opcode/mips.h b/include/opcode/mips.h index f0a8c7ef9..68fe57a8a 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -308,6 +308,7 @@ struct mips_opcode #define INSN_ISA3 0x00000003 /* MIPS ISA 4 instruction (R8000). */ #define INSN_ISA4 0x00000004 +#define INSN_ISA5 0x00000005 /* Chip specific instructions. These are bitmasks. */ /* MIPS R4650 instruction. */ @@ -319,6 +320,31 @@ struct mips_opcode /* Toshiba R3900 instruction. */ #define INSN_3900 0x00000080 +/* 32-bit code running on a ISA3+ CPU. */ +#define INSN_GP32 0x00001000 + +/* Test for membership in an ISA including chip specific ISAs. + INSN is pointer to an element of the opcode table; ISA is the + specified ISA to test against; and CPU is the CPU specific ISA + to test, or zero if no CPU specific ISA test is desired. + The gp32 arg is set when you need to force 32-bit register usage on + a machine with 64-bit registers; see the documentation under -mgp32 + in the MIPS gas docs. */ + +#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \ + ((((insn)->membership & INSN_ISA) != 0 \ + && ((insn)->membership & INSN_ISA) <= isa \ + && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ + || (cpu == 4650 \ + && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == 4010 \ + && ((insn)->membership & INSN_4010) != 0) \ + || ((cpu == 4100 \ + || cpu == 4111 \ + ) \ + && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == 3900 \ + && ((insn)->membership & INSN_3900) != 0)) /* This is a list of macro expanded instructions. * diff --git a/include/opcode/mn10300.h b/include/opcode/mn10300.h index 34e4b0b43..12f03670f 100644 --- a/include/opcode/mn10300.h +++ b/include/opcode/mn10300.h @@ -117,6 +117,23 @@ extern const struct mn10300_operand mn10300_operands[]; #define MN10300_OPERAND_RELAX 0x4000 +#define MN10300_OPERAND_USP 0x8000 + +#define MN10300_OPERAND_SSP 0x10000 + +#define MN10300_OPERAND_MSP 0x20000 + +#define MN10300_OPERAND_PC 0x40000 + +#define MN10300_OPERAND_EPSW 0x80000 + +#define MN10300_OPERAND_RREG 0x100000 + +#define MN10300_OPERAND_XRREG 0x200000 + +#define MN10300_OPERAND_PLUS 0x400000 + +#define MN10300_OPERAND_24BIT 0x800000 /* Opcode Formats. */ #define FMT_S0 1 @@ -129,10 +146,16 @@ extern const struct mn10300_operand mn10300_operands[]; #define FMT_D2 8 #define FMT_D4 9 #define FMT_D5 10 +#define FMT_D6 11 +#define FMT_D7 12 +#define FMT_D8 13 +#define FMT_D9 14 +#define FMT_D10 15 /* Variants of the mn10300 which have additional opcodes. */ #define MN103 300 #define AM30 300 +#define AM33 330 #endif /* MN10300_H */ diff --git a/include/opcode/pj.h b/include/opcode/pj.h new file mode 100644 index 000000000..8759b627e --- /dev/null +++ b/include/opcode/pj.h @@ -0,0 +1,46 @@ +/* Definitions for decoding the picoJava opcode table. + Copyright (C) 1999 Free Software Foundation, Inc. + Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* Names used to describe the type of instruction arguments, used by + the assembler and disassembler. Attributes are encoded in various fields. */ + +/* reloc size pcrel uns */ +#define O_N 0 +#define O_16 (1<<4 | 2 | (0<<6) | (0<<3)) +#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3)) +#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3)) +#define O_8 (3<<4 | 1 | (0<<6) | (0<<3)) +#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3)) +#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3)) +#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3)) +#define O_32 (6<<4 | 4 | (0<<6) | (0<<3)) + +#define ASIZE(x) ((x) & 0x7) +#define PCREL(x) (!!((x) & (1<<6))) +#define UNS(x) (!!((x) & (1<<3))) + + +typedef struct +{ + short opcode; + short opcode_next; + char len; + unsigned char arg[2]; + const char *name; +} pj_opc_info_t; diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index a9e3b24ab..974f0dfa5 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -85,6 +85,9 @@ extern const int powerpc_num_opcodes; for the assembler's -many option, and it eliminates duplicates). */ #define PPC_OPCODE_ANY (0200) +/* Opcode is supported as part of the 64-bit bridge. */ +#define PPC_OPCODE_64_BRIDGE (0400) + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) diff --git a/include/partition.h b/include/partition.h new file mode 100644 index 000000000..f49d67a8c --- /dev/null +++ b/include/partition.h @@ -0,0 +1,81 @@ +/* List implentation of a partition of consecutive integers. + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by CodeSourcery, LLC. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* This package implements a partition of consecutive integers. The + elements are partitioned into classes. Each class is represented + by one of its elements, the canonical element, which is chosen + arbitrarily from elements in the class. The principal operations + on a partition are FIND, which takes an element, determines its + class, and returns the canonical element for that class, and UNION, + which unites the two classes that contain two given elements into a + single class. + + The list implementation used here provides constant-time finds. By + storing the size of each class with the class's canonical element, + it is able to perform unions over all the classes in the partition + in O (N log N) time. */ + +#ifndef _PARTITION_H +#define _PARTITION_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include <ansidecl.h> +#include <stdio.h> + +struct partition_elem +{ + /* The canonical element that represents the class containing this + element. */ + int class_element; + /* The next element in this class. Elements in each class form a + circular list. */ + struct partition_elem* next; + /* The number of elements in this class. Valid only if this is the + canonical element for its class. */ + unsigned class_count; +}; + +typedef struct partition_def +{ + /* The number of elements in this partition. */ + int num_elements; + /* The elements in the partition. */ + struct partition_elem elements[1]; +} *partition; + +extern partition partition_new PARAMS((int)); +extern void partition_delete PARAMS((partition)); +extern int partition_union PARAMS((partition, + int, + int)); +extern void partition_print PARAMS((partition, + FILE*)); + +/* Returns the canonical element corresponding to the class containing + ELEMENT__ in PARTITION__. */ + +#define partition_find(partition__, element__) \ + ((partition__)->elements[(element__)].class_element) + +#endif /* _PARTITION_H */ diff --git a/include/remote-sim.h b/include/remote-sim.h index a4480b49c..b32f93fdd 100644 --- a/include/remote-sim.h +++ b/include/remote-sim.h @@ -211,7 +211,27 @@ int sim_store_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int void sim_info PARAMS ((SIM_DESC sd, int verbose)); -/* Run (or resume) the simulated program. */ +/* Run (or resume) the simulated program. + + STEP, when non-zero indicates that only a single simulator cycle + should be emulated. + + SIGGNAL, if non-zero is a (HOST) SIGRC value indicating the type of + event (hardware interrupt, signal) to be delivered to the simulated + program. + + Hardware simulator: If the SIGRC value returned by + sim_stop_reason() is passed back to the simulator via SIGGNAL then + the hardware simulator shall correctly deliver the hardware event + indicated by that signal. If a value of zero is passed in then the + simulation will continue as if there were no outstanding signal. + The effect of any other SIGGNAL value is is implementation + dependant. + + Process simulator: If SIGRC is non-zero then the corresponding + signal is delivered to the simulated program and execution is then + continued. A zero SIGRC value indicates that the program should + continue as normal. */ void sim_resume PARAMS ((SIM_DESC sd, int step, int siggnal)); @@ -234,13 +254,13 @@ int sim_stop PARAMS ((SIM_DESC sd)); (SIGTRAP); a completed single step (SIGTRAP); an internal error condition (SIGABRT); an illegal instruction (SIGILL); Access to an undefined memory region (SIGSEGV); Mis-aligned memory access - (SIGBUS). + (SIGBUS). For some signals information in addition to the signal + number may be retained by the simulator (e.g. offending address), + that information is not directly accessable via this interface. - SIM_SIGNALLED: The program has stopped. The simulator has - encountered target code that requires the (HOST) signal SIGRC to be - delivered to the simulated program. Ex: `kill (getpid (), - TARGET_SIGxxx)'. Where TARGET_SIGxxx has been translated into a - host signal. FIXME: This is not always possible.. + SIM_SIGNALLED: The program has been terminated by a signal. The + simulator has encountered target code that causes the the program + to exit with signal SIGRC. SIM_RUNNING, SIM_POLLING: The return of one of these values indicates a problem internal to the simulator. */ @@ -288,15 +308,27 @@ void sim_set_callbacks PARAMS ((struct host_callback_struct *)); void sim_size PARAMS ((int i)); -/* Run a simulation with tracing enabled. +/* Single-step simulator with tracing enabled. THIS PROCEDURE IS DEPRECIATED. + THIS PROCEDURE IS EVEN MORE DEPRECATED THAN SIM_SET_TRACE GDB and NRUN do not use this interface. - This procedure does not take a SIM_DESC argument as it is - used before sim_open. */ + This procedure returns: ``0'' indicating that the simulator should + be continued using sim_trace() calls; ``1'' indicating that the + simulation has finished. */ int sim_trace PARAMS ((SIM_DESC sd)); +/* Enable tracing. + THIS PROCEDURE IS DEPRECIATED. + GDB and NRUN do not use this interface. + This procedure returns: ``0'' indicating that the simulator should + be continued using sim_trace() calls; ``1'' indicating that the + simulation has finished. */ + +void sim_set_trace PARAMS ((void)); + + /* Configure the size of the profile buffer. THIS PROCEDURE IS DEPRECIATED. GDB and NRUN do not use this interface. diff --git a/include/sim-d10v.h b/include/sim-d10v.h new file mode 100644 index 000000000..84eab2a1a --- /dev/null +++ b/include/sim-d10v.h @@ -0,0 +1,103 @@ +/* This file defines the interface between the d10v simulator and gdb. + Copyright (C) 1999 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (SIM_D10V_H) +#define SIM_D10V_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +/* GDB interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + 0x10xxxxxx: Logical data address segment (DMAP translated memory) + 0x11xxxxxx: Logical instruction address segment (IMAP translated memory) + + The remote d10v board interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + + The following translate a virtual DMAP/IMAP offset into a physical + memory segment assigning the translated address to PHYS. Since a + memory access may cross a page boundrary the number of bytes for + which the translation is applicable (or 0 for an invalid virtual + offset) is returned. */ + +enum + { + SIM_D10V_MEMORY_UNIFIED = 0x00000000, + SIM_D10V_MEMORY_INSN = 0x01000000, + SIM_D10V_MEMORY_DATA = 0x02000000, + SIM_D10V_MEMORY_DMAP = 0x10000000, + SIM_D10V_MEMORY_IMAP = 0x11000000 + }; + +extern unsigned long sim_d10v_translate_dmap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + unsigned long (*dmap_register) (int reg_nr)); + +extern unsigned long sim_d10v_translate_imap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + unsigned long (*imap_register) (int reg_nr)); + +extern unsigned long sim_d10v_translate_addr + (unsigned long vaddr, + int nr_bytes, + unsigned long *phys, + unsigned long (*dmap_register) (int reg_nr), + unsigned long (*imap_register) (int reg_nr)); + + +/* The simulator makes use of the following register information. */ + +enum + { + SIM_D10V_R0_REGNUM = 0, + SIM_D10V_CR0_REGNUM = 16, + SIM_D10V_A0_REGNUM = 32, + SIM_D10V_SPI_REGNUM = 34, + SIM_D10V_SPU_REGNUM = 35, + SIM_D10V_IMAP0_REGNUM = 36, + SIM_D10V_DMAP0_REGNUM = 38, + SIM_D10V_TS2_DMAP_REGNUM = 40 + }; + +enum + { + SIM_D10V_NR_R_REGS = 16, + SIM_D10V_NR_A_REGS = 2, + SIM_D10V_NR_IMAP_REGS = 2, + SIM_D10V_NR_DMAP_REGS = 4, + SIM_D10V_NR_CR_REGS = 16 + }; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/wait.h b/include/wait.h deleted file mode 100644 index fa3c9ccb1..000000000 --- a/include/wait.h +++ /dev/null @@ -1,63 +0,0 @@ -/* Define how to access the int that the wait system call stores. - This has been compatible in all Unix systems since time immemorial, - but various well-meaning people have defined various different - words for the same old bits in the same old int (sometimes claimed - to be a struct). We just know it's an int and we use these macros - to access the bits. */ - -/* The following macros are defined equivalently to their definitions - in POSIX.1. We fail to define WNOHANG and WUNTRACED, which POSIX.1 - <sys/wait.h> defines, since our code does not use waitpid(). We - also fail to declare wait() and waitpid(). */ - -#ifndef WIFEXITED -#define WIFEXITED(w) (((w)&0377) == 0) -#endif - -#ifndef WIFSIGNALED -#define WIFSIGNALED(w) (((w)&0377) != 0177 && ((w)&~0377) == 0) -#endif - -#ifndef WIFSTOPPED -#ifdef IBM6000 - -/* Unfortunately, the above comment (about being compatible in all Unix - systems) is not quite correct for AIX, sigh. And AIX 3.2 can generate - status words like 0x57c (sigtrap received after load), and gdb would - choke on it. */ - -#define WIFSTOPPED(w) ((w)&0x40) - -#else -#define WIFSTOPPED(w) (((w)&0377) == 0177) -#endif -#endif - -#ifndef WEXITSTATUS -#define WEXITSTATUS(w) (((w) >> 8) & 0377) /* same as WRETCODE */ -#endif - -#ifndef WTERMSIG -#define WTERMSIG(w) ((w) & 0177) -#endif - -#ifndef WSTOPSIG -#define WSTOPSIG WEXITSTATUS -#endif - -/* These are not defined in POSIX, but are used by our programs. */ - -#define WAITTYPE int - -#ifndef WCOREDUMP -#define WCOREDUMP(w) (((w)&0200) != 0) -#endif - -#ifndef WSETEXIT -#define WSETEXIT(w,status) ((w) = (0 | ((status) << 8))) -#endif - -#ifndef WSETSTOP -#define WSETSTOP(w,sig) ((w) = (0177 | ((sig) << 8))) -#endif - |