diff options
author | cvs2svn <> | 2002-10-03 23:08:54 +0400 |
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committer | cvs2svn <> | 2002-10-03 23:08:54 +0400 |
commit | d1109236e2835bec428fd7779bdb9b673aeec7fb (patch) | |
tree | 2c405c8d4572c5cc1d524047ab526b4f6939188d /include | |
parent | 481f35c8b3d9136e2430845fad71fb21fa3bc1d4 (diff) |
This commit was manufactured by cvs2svn to create branch 'drow-cplus-drow-cplus-branchpoint
branch'.
Sprout from carlton_dictionary-branch 2002-09-20 00:21:59 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch'
Cherrypick from master 2002-10-03 19:08:53 UTC Nathanael Nerode <neroden@gcc.gnu.org> '2002-10-03 Nathanael Nerode <neroden@gcc.gnu.org>':
ChangeLog
Makefile.def
Makefile.in
Makefile.tpl
configure
configure.in
include/ChangeLog
include/elf/ChangeLog
include/elf/mips.h
include/elf/x86-64.h
include/opcode/ChangeLog
include/opcode/mips.h
src-release
Delete:
include/regs/ChangeLog
Diffstat (limited to 'include')
-rw-r--r-- | include/ChangeLog | 8 | ||||
-rw-r--r-- | include/elf/ChangeLog | 8 | ||||
-rw-r--r-- | include/elf/mips.h | 3 | ||||
-rw-r--r-- | include/elf/x86-64.h | 24 | ||||
-rw-r--r-- | include/opcode/ChangeLog | 14 | ||||
-rw-r--r-- | include/opcode/mips.h | 32 | ||||
-rw-r--r-- | include/regs/ChangeLog | 0 |
7 files changed, 77 insertions, 12 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 148c9bd59..257e38193 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,11 @@ +2002-09-26 Jakub Jelinek <jakub@redhat.com> + + * elf/x86-64.h: Add TLS relocs. + +2002-09-26 Andrew Cagney <ac131313@redhat.com> + + * regs/: Delete directory. + 2002-09-19 Alexandre Oliva <aoliva@redhat.com> * libiberty.h (asprintf, vasprintf): Don't declare them if the diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 389569eab..254b2c425 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,11 @@ +2002-09-30 Gavin Romig-Koch <gavin@redhat.com> + Ken Raeburn <raeburn@cygnus.com> + Aldy Hernandez <aldyh@redhat.com> + Eric Christopher <echristo@redhat.com> + Richard Sandiford <rsandifo@redhat.com> + + * mips.h (E_MIPS_MACH_4120, E_MIPS_MACH_5400, E_MIPS_MACH_5500): New. + 2002-09-12 Roland McGrath <roland@redhat.com> * dwarf2.h: Updates from GCC version of thie file: diff --git a/include/elf/mips.h b/include/elf/mips.h index 3b6fe99ec..81451ab55 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -175,8 +175,11 @@ END_RELOC_NUMBERS (R_MIPS_maxext) #define E_MIPS_MACH_4010 0x00820000 #define E_MIPS_MACH_4100 0x00830000 #define E_MIPS_MACH_4650 0x00850000 +#define E_MIPS_MACH_4120 0x00870000 #define E_MIPS_MACH_4111 0x00880000 #define E_MIPS_MACH_SB1 0x008a0000 +#define E_MIPS_MACH_5400 0x00910000 +#define E_MIPS_MACH_5500 0x00980000 /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these diff --git a/include/elf/x86-64.h b/include/elf/x86-64.h index 74febc2d5..7e9100dba 100644 --- a/include/elf/x86-64.h +++ b/include/elf/x86-64.h @@ -1,5 +1,5 @@ /* x86_64 ELF support for BFD. - Copyright (C) 2000 Free Software Foundation, Inc. + Copyright (C) 2000, 2002 Free Software Foundation, Inc. Contributed by Jan Hubicka <jh@suse.cz> This file is part of BFD, the Binary File Descriptor library. @@ -25,22 +25,30 @@ START_RELOC_NUMBERS (elf_x86_64_reloc_type) RELOC_NUMBER (R_X86_64_NONE, 0) /* No reloc */ - RELOC_NUMBER (R_X86_64_64, 1) /* Direct 64 bit */ + RELOC_NUMBER (R_X86_64_64, 1) /* Direct 64 bit */ RELOC_NUMBER (R_X86_64_PC32, 2) /* PC relative 32 bit signed */ RELOC_NUMBER (R_X86_64_GOT32, 3) /* 32 bit GOT entry */ RELOC_NUMBER (R_X86_64_PLT32, 4) /* 32 bit PLT address */ RELOC_NUMBER (R_X86_64_COPY, 5) /* Copy symbol at runtime */ RELOC_NUMBER (R_X86_64_GLOB_DAT, 6) /* Create GOT entry */ - RELOC_NUMBER (R_X86_64_JUMP_SLOT, 7) /* Create PLT entry */ + RELOC_NUMBER (R_X86_64_JUMP_SLOT,7) /* Create PLT entry */ RELOC_NUMBER (R_X86_64_RELATIVE, 8) /* Adjust by program base */ RELOC_NUMBER (R_X86_64_GOTPCREL, 9) /* 32 bit signed pc relative offset to GOT */ - RELOC_NUMBER (R_X86_64_32, 10) /* Direct 32 bit zero extended */ - RELOC_NUMBER (R_X86_64_32S, 11) /* Direct 32 bit sign extended */ - RELOC_NUMBER (R_X86_64_16, 12) /* Direct 16 bit zero extended */ + RELOC_NUMBER (R_X86_64_32, 10) /* Direct 32 bit zero extended */ + RELOC_NUMBER (R_X86_64_32S, 11) /* Direct 32 bit sign extended */ + RELOC_NUMBER (R_X86_64_16, 12) /* Direct 16 bit zero extended */ RELOC_NUMBER (R_X86_64_PC16, 13) /* 16 bit sign extended pc relative*/ - RELOC_NUMBER (R_X86_64_8, 14) /* Direct 8 bit sign extended */ - RELOC_NUMBER (R_X86_64_PC8, 15) /* 8 bit sign extended pc relative*/ + RELOC_NUMBER (R_X86_64_8, 14) /* Direct 8 bit sign extended */ + RELOC_NUMBER (R_X86_64_PC8, 15) /* 8 bit sign extended pc relative*/ + RELOC_NUMBER (R_X86_64_DTPMOD64, 16) /* ID of module containing symbol */ + RELOC_NUMBER (R_X86_64_DTPOFF64, 17) /* Offset in TLS block */ + RELOC_NUMBER (R_X86_64_TPOFF64, 18) /* Offset in initial TLS block */ + RELOC_NUMBER (R_X86_64_TLSGD, 19) /* PC relative offset to GD GOT block */ + RELOC_NUMBER (R_X86_64_TLSLD, 20) /* PC relative offset to LD GOT block */ + RELOC_NUMBER (R_X86_64_DTPOFF32, 21) /* Offset in TLS block */ + RELOC_NUMBER (R_X86_64_GOTTPOFF, 22) /* PC relative offset to IE GOT entry */ + RELOC_NUMBER (R_X86_64_TPOFF32, 23) /* Offset in initial TLS block */ RELOC_NUMBER (R_X86_64_GNU_VTINHERIT, 250) /* GNU C++ hack */ RELOC_NUMBER (R_X86_64_GNU_VTENTRY, 251) /* GNU C++ hack */ END_RELOC_NUMBERS (R_X86_64_max) diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index b950eefc3..ab908ec92 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,17 @@ +2002-09-30 Gavin Romig-Koch <gavin@redhat.com> + Ken Raeburn <raeburn@cygnus.com> + Aldy Hernandez <aldyh@redhat.com> + Eric Christopher <echristo@redhat.com> + Richard Sandiford <rsandifo@redhat.com> + + * mips.h: Update comment for new opcodes. + (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. + (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. + (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. + (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. + (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. + Don't match CPU_R4111 with INSN_4100. + 2002-08-19 Elena Zannoni <ezannoni@redhat.com> From matthew green <mrg@redhat.com> diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 1a39640ca..3849fdce6 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -137,6 +137,11 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_MASK_ALN 0x7 #define OP_SH_VSEL 21 #define OP_MASK_VSEL 0x1f +#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, + but 0x8-0xf don't select bytes. */ +#define OP_SH_VECBYTE 22 +#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ +#define OP_SH_VECALIGN 21 /* Values in the 'VSEL' field. */ #define MDMX_FMTSEL_IMM_QH 0x1d @@ -189,6 +194,7 @@ struct mips_opcode "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) "j" 16 bit signed immediate (OP_*_DELTA) "k" 5 bit cache opcode in target register position (OP_*_CACHE) + Also used for immediate operands in vr5400 vector insns. "o" 16 bit signed offset (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA) "q" 10 bit extra breakpoint code (OP_*_CODE2) @@ -221,6 +227,9 @@ struct mips_opcode "G" 5 bit destination register (OP_*_RD) "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) "P" 5 bit performance-monitor register (OP_*_PERFREG) + "e" 5 bit vector register byte specifier (OP_*_VECBYTE) + "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) + see also "k" above Macro instructions: "A" General 32 bit expression @@ -241,11 +250,12 @@ struct mips_opcode Other: "()" parens surrounding optional value "," separates operands + "[]" brackets around index for vector-op scalar operand specifier (vr5400) Characters used so far, for quick reference when adding more: - "<>()," + "%[]<>()," "ABCDEFGHIJLMNOPQRSTUVWXYZ" - "abcdfhijklopqrstuvwxz" + "abcdefhijklopqrstuvwxz" */ /* These are the bits which may be set in the pinfo field of an @@ -362,6 +372,14 @@ struct mips_opcode #define INSN_10000 0x00100000 /* Broadcom SB-1 instruction. */ #define INSN_SB1 0x00200000 +/* NEC VR4111/VR4181 instruction. */ +#define INSN_4111 0x00400000 +/* NEC VR4120 instruction. */ +#define INSN_4120 0x00800000 +/* NEC VR5400 instruction. */ +#define INSN_5400 0x01000000 +/* NEC VR5500 instruction. */ +#define INSN_5500 0x02000000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -383,11 +401,14 @@ struct mips_opcode #define CPU_R4010 4010 #define CPU_VR4100 4100 #define CPU_R4111 4111 +#define CPU_VR4120 4120 #define CPU_R4300 4300 #define CPU_R4400 4400 #define CPU_R4600 4600 #define CPU_R4650 4650 #define CPU_R5000 5000 +#define CPU_VR5400 5400 +#define CPU_VR5500 5500 #define CPU_R6000 6000 #define CPU_R8000 8000 #define CPU_R10000 10000 @@ -407,12 +428,15 @@ struct mips_opcode (((insn)->membership & isa) != 0 \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ - || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ - && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ && ((insn)->membership & INSN_10000) != 0) \ || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ + || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ + || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ + || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ + || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ || 0) /* Please keep this term for easier source merging. */ /* This is a list of macro expanded instructions. diff --git a/include/regs/ChangeLog b/include/regs/ChangeLog deleted file mode 100644 index e69de29bb..000000000 --- a/include/regs/ChangeLog +++ /dev/null |