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authorMichael Frysinger <vapier@gentoo.org>2010-09-23 00:59:00 +0400
committerMichael Frysinger <vapier@gentoo.org>2010-09-23 00:59:00 +0400
commitd3e228722ebc8c03cb25858198de532cb896bca9 (patch)
tree5a0ea080e4c0c01d64e05cd4d098155867421759 /include
parent60376287eb7a9ca1118b6a0cb30fe749beda7f48 (diff)
opcodes/gas: blackfin: support OUTC debug insn
The disassembler has partial (but incomplete/broken) support already for the pseudo debug insn OUTC, so let's fix it up and finish it. And now that the disassembler can handle it, make sure our assembler can output it too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog4
-rwxr-xr-xinclude/opcode/bfin.h28
2 files changed, 32 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 277419459..e467f5a46 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin.h: Declare pseudoChr structs/defines.
+
2010-09-21 Mike Frysinger <vapier@gentoo.org>
* bfin.h: Strip trailing whitespace.
diff --git a/include/opcode/bfin.h b/include/opcode/bfin.h
index 925bf141a..819ba6ee2 100755
--- a/include/opcode/bfin.h
+++ b/include/opcode/bfin.h
@@ -987,6 +987,34 @@ typedef struct
PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
};
+/* pseudoChr
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+ unsigned short opcode;
+ int bits_ch;
+ int mask_ch;
+ int bits_code;
+ int mask_code;
+} PseudoChr;
+
+#define PseudoChr_opcode 0xf900
+#define PseudoChr_ch_bits 0
+#define PseudoChr_ch_mask 0xff
+#define PseudoChr_code_bits 8
+#define PseudoChr_code_mask 0xff
+
+#define init_PseudoChr \
+{ \
+ PseudoChr_opcode, \
+ PseudoChr_ch_bits, PseudoChr_ch_mask, \
+ PseudoChr_code_bits, PseudoChr_code_mask \
+};
+
/* CaCTRL
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|