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authorMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2010-09-23 19:37:45 +0400
committerMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2010-09-23 19:37:45 +0400
commitfa4115fd6e6f4b542e7c2b09264a5670eac1a5aa (patch)
tree3e02e22fbedd55d12332fd3a2e56230cba643917 /include
parent76be61ea8a8fe17e6ceb887ad2f203aa167deab0 (diff)
* gas/config/tc-arm.c (arm_ext_adiv): New variable.
(do_div): New function. (insns): Accept UDIV and SDIV in ARM state. (arm_cpus): The cortex-a15 option has all current v7-A extensions. (arm_extensions): Add 'idiv' extension. (aeabi_set_public_attributes): Update Tag_DIV_use values for the Integer Divide extension. * gas/doc/c-arm.texi: Document the idiv extension. * gas/testsuite/gas/arm/armv7-a+idiv.d: New test. * gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension. * gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test. * include/opcode/arm.h (ARM_AEXT_ADIV): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. * opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in ARM state.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog5
-rw-r--r--include/opcode/arm.h6
2 files changed, 11 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 3e845da38..135a28fac 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,4 +1,9 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm.h (ARM_AEXT_ADIV): New define.
+ (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm.h (ARM_EXT_OS): New define.
(ARM_AEXT_V6SM): Likewise.
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 4c9324d74..58cace8a3 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -52,6 +52,8 @@
#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
+#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
+ state. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
@@ -220,6 +222,10 @@
#define ARM_ARCH_V7A_MP_SEC \
ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
0)
+/* v7-a+idiv+mp+sec. */
+#define ARM_ARCH_V7A_IDIV_MP_SEC \
+ ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \
+ | ARM_EXT_DIV | ARM_EXT_ADIV, 0)
/* There are too many feature bits to fit in a single word, so use a
structure. For simplicity we put all core features in one word and