diff options
author | cvs2svn <> | 2010-08-31 11:47:52 +0400 |
---|---|---|
committer | cvs2svn <> | 2010-08-31 11:47:52 +0400 |
commit | 8011b019fc1e7dd95eb63b9b5ddcca521a5b3866 (patch) | |
tree | 68d3d6491a8b0f59c49183454b81606c5f333b37 /libgloss/bfin/include/defBF547.h | |
parent | 8fd414ffc62eedf37e576231fd6100f0d7b9c5f0 (diff) |
This commit was manufactured by cvs2svn to create tag 'cygwin-cygwin-1_7_7-release
1_7_7-release'.
Sprout from master 2010-08-31 07:47:51 UTC Corinna Vinschen <corinna@vinschen.de> ' * include/cygwin/version.h: Bump DLL minor version number to 7.'
Cherrypick from cygnus 1999-05-03 07:29:06 UTC Richard Henderson <rth@redhat.com> '19990502 sourceware import':
README
config/mt-d30v
config/mt-netware
config/mt-ospace
etc/add-log.el
etc/add-log.vi
etc/configbuild.ein
etc/configbuild.fig
etc/configbuild.jin
etc/configbuild.tin
etc/configdev.ein
etc/configdev.fig
etc/configdev.jin
etc/configdev.tin
include/aout/hppa.h
include/coff/sym.h
include/fopen-bin.h
include/fopen-same.h
include/opcode/tahoe.h
makefile.vms
Delete:
COPYING3
COPYING3.LIB
compile
config.rpath
configure.ac
djunpack.bat
include/cgen/ChangeLog
include/cgen/basic-modes.h
include/cgen/basic-ops.h
include/cgen/bitset.h
include/som/ChangeLog
include/som/aout.h
include/som/clock.h
include/som/internal.h
include/som/lst.h
include/som/reloc.h
include/vms/ChangeLog
include/vms/dcx.h
include/vms/dmt.h
include/vms/dsc.h
include/vms/dst.h
include/vms/eeom.h
include/vms/egps.h
include/vms/egsd.h
include/vms/egst.h
include/vms/egsy.h
include/vms/eiaf.h
include/vms/eicp.h
include/vms/eidc.h
include/vms/eiha.h
include/vms/eihd.h
include/vms/eihi.h
include/vms/eihs.h
include/vms/eihvn.h
include/vms/eisd.h
include/vms/emh.h
include/vms/eobjrec.h
include/vms/esdf.h
include/vms/esdfm.h
include/vms/esdfv.h
include/vms/esgps.h
include/vms/esrf.h
include/vms/etir.h
include/vms/internal.h
include/vms/lbr.h
include/vms/prt.h
include/vms/shl.h
libgloss/ChangeLog
libgloss/Makefile.in
libgloss/README
libgloss/acinclude.m4
libgloss/aclocal.m4
libgloss/arm/Makefile.in
libgloss/arm/_exit.c
libgloss/arm/_kill.c
libgloss/arm/aclocal.m4
libgloss/arm/coff-iq80310.specs
libgloss/arm/coff-pid.specs
libgloss/arm/coff-rdimon.specs
libgloss/arm/coff-rdpmon.specs
libgloss/arm/coff-redboot.ld
libgloss/arm/coff-redboot.specs
libgloss/arm/configure
libgloss/arm/configure.in
libgloss/arm/crt0.S
libgloss/arm/elf-iq80310.specs
libgloss/arm/elf-linux.specs
libgloss/arm/elf-pid.specs
libgloss/arm/elf-rdimon.specs
libgloss/arm/elf-rdpmon.specs
libgloss/arm/elf-redboot.ld
libgloss/arm/elf-redboot.specs
libgloss/arm/libcfunc.c
libgloss/arm/linux-crt0.c
libgloss/arm/linux-syscall.h
libgloss/arm/linux-syscalls0.S
libgloss/arm/linux-syscalls1.c
libgloss/arm/redboot-crt0.S
libgloss/arm/redboot-syscalls.c
libgloss/arm/swi.h
libgloss/arm/syscall.h
libgloss/arm/syscalls.c
libgloss/arm/trap.S
libgloss/bfin/Makefile.in
libgloss/bfin/aclocal.m4
libgloss/bfin/basiccrt.S
libgloss/bfin/bf512.ld
libgloss/bfin/bf514.ld
libgloss/bfin/bf516.ld
libgloss/bfin/bf518.ld
libgloss/bfin/bf522.ld
libgloss/bfin/bf523.ld
libgloss/bfin/bf524.ld
libgloss/bfin/bf525.ld
libgloss/bfin/bf526.ld
libgloss/bfin/bf527.ld
libgloss/bfin/bf531.ld
libgloss/bfin/bf532.ld
libgloss/bfin/bf533.ld
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libgloss/bfin/bf536.ld
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libgloss/bfin/bf538.ld
libgloss/bfin/bf539.ld
libgloss/bfin/bf542.ld
libgloss/bfin/bf544.ld
libgloss/bfin/bf547.ld
libgloss/bfin/bf548.ld
libgloss/bfin/bf549.ld
libgloss/bfin/bf561.ld
libgloss/bfin/bf561a.ld
libgloss/bfin/bf561b.ld
libgloss/bfin/bf561m.ld
libgloss/bfin/bfin-common-mc.ld
libgloss/bfin/bfin-common-sc.ld
libgloss/bfin/configure
libgloss/bfin/configure.in
libgloss/bfin/crt0.S
libgloss/bfin/include/blackfin.h
libgloss/bfin/include/ccblkfn.h
libgloss/bfin/include/cdefBF512.h
libgloss/bfin/include/cdefBF514.h
libgloss/bfin/include/cdefBF516.h
libgloss/bfin/include/cdefBF518.h
libgloss/bfin/include/cdefBF51x_base.h
libgloss/bfin/include/cdefBF522.h
libgloss/bfin/include/cdefBF523.h
libgloss/bfin/include/cdefBF524.h
libgloss/bfin/include/cdefBF525.h
libgloss/bfin/include/cdefBF526.h
libgloss/bfin/include/cdefBF527.h
libgloss/bfin/include/cdefBF52x_base.h
libgloss/bfin/include/cdefBF531.h
libgloss/bfin/include/cdefBF532.h
libgloss/bfin/include/cdefBF533.h
libgloss/bfin/include/cdefBF534.h
libgloss/bfin/include/cdefBF535.h
libgloss/bfin/include/cdefBF536.h
libgloss/bfin/include/cdefBF537.h
libgloss/bfin/include/cdefBF538.h
libgloss/bfin/include/cdefBF539.h
libgloss/bfin/include/cdefBF53x.h
libgloss/bfin/include/cdefBF541.h
libgloss/bfin/include/cdefBF542.h
libgloss/bfin/include/cdefBF542M.h
libgloss/bfin/include/cdefBF544.h
libgloss/bfin/include/cdefBF544M.h
libgloss/bfin/include/cdefBF547.h
libgloss/bfin/include/cdefBF547M.h
libgloss/bfin/include/cdefBF548.h
libgloss/bfin/include/cdefBF548M.h
libgloss/bfin/include/cdefBF549.h
libgloss/bfin/include/cdefBF549M.h
libgloss/bfin/include/cdefBF54x_base.h
libgloss/bfin/include/cdefBF561.h
libgloss/bfin/include/cdef_LPBlackfin.h
libgloss/bfin/include/cdefblackfin.h
libgloss/bfin/include/cplb.h
libgloss/bfin/include/cplbtab.h
libgloss/bfin/include/defBF512.h
libgloss/bfin/include/defBF514.h
libgloss/bfin/include/defBF516.h
libgloss/bfin/include/defBF518.h
libgloss/bfin/include/defBF51x_base.h
libgloss/bfin/include/defBF522.h
libgloss/bfin/include/defBF523.h
libgloss/bfin/include/defBF524.h
libgloss/bfin/include/defBF525.h
libgloss/bfin/include/defBF526.h
libgloss/bfin/include/defBF527.h
libgloss/bfin/include/defBF52x_base.h
libgloss/bfin/include/defBF531.h
libgloss/bfin/include/defBF532.h
libgloss/bfin/include/defBF533.h
libgloss/bfin/include/defBF534.h
libgloss/bfin/include/defBF535.h
libgloss/bfin/include/defBF536.h
libgloss/bfin/include/defBF537.h
libgloss/bfin/include/defBF538.h
libgloss/bfin/include/defBF539.h
libgloss/bfin/include/defBF541.h
libgloss/bfin/include/defBF542.h
libgloss/bfin/include/defBF542M.h
libgloss/bfin/include/defBF544.h
libgloss/bfin/include/defBF544M.h
libgloss/bfin/include/defBF547.h
libgloss/bfin/include/defBF547M.h
libgloss/bfin/include/defBF548.h
libgloss/bfin/include/defBF548M.h
libgloss/bfin/include/defBF549.h
libgloss/bfin/include/defBF549M.h
libgloss/bfin/include/defBF54x_base.h
libgloss/bfin/include/defBF561.h
libgloss/bfin/include/def_LPBlackfin.h
libgloss/bfin/include/defblackfin.h
libgloss/bfin/include/sys/_adi_platform.h
libgloss/bfin/include/sys/anomaly_macros_rtl.h
libgloss/bfin/include/sys/excause.h
libgloss/bfin/include/sys/exception.h
libgloss/bfin/include/sys/mc_typedef.h
libgloss/bfin/include/sys/platform.h
libgloss/bfin/include/sys/pll.h
libgloss/bfin/include/sysreg.h
libgloss/bfin/syscalls.c
libgloss/close.c
libgloss/config/default.mh
libgloss/config/default.mt
libgloss/config/dos.mh
libgloss/config/mips.mt
libgloss/config/mn10200.mt
libgloss/config/mn10300.mt
libgloss/config/ppc.mh
libgloss/config/xc16x.mt
libgloss/configure
libgloss/configure.in
libgloss/cris/Makefile.in
libgloss/cris/aclocal.m4
libgloss/cris/configure
libgloss/cris/configure.in
libgloss/cris/crt0.S
libgloss/cris/crti.c
libgloss/cris/crtn.c
libgloss/cris/gensyscalls
libgloss/cris/irqtable.S
libgloss/cris/lcrt0.c
libgloss/cris/linunistd.h
libgloss/cris/outbyte.c
libgloss/cris/setup.S
libgloss/crx/Makefile.in
libgloss/crx/_exit.c
libgloss/crx/_getenv.c
libgloss/crx/_rename.c
libgloss/crx/aclocal.m4
libgloss/crx/close.c
libgloss/crx/configure
libgloss/crx/configure.in
libgloss/crx/crt0.S
libgloss/crx/crti.S
libgloss/crx/crtn.S
libgloss/crx/dvz_hndl.c
libgloss/crx/flg_hndl.c
libgloss/crx/fstat.c
libgloss/crx/getpid.c
libgloss/crx/iad_hndl.c
libgloss/crx/intable.c
libgloss/crx/isatty.c
libgloss/crx/kill.c
libgloss/crx/lseek.c
libgloss/crx/open.c
libgloss/crx/putnum.c
libgloss/crx/read.c
libgloss/crx/sbrk.c
libgloss/crx/sim.ld
libgloss/crx/stat.c
libgloss/crx/svc_hndl.c
libgloss/crx/time.c
libgloss/crx/und_hndl.c
libgloss/crx/unlink.c
libgloss/crx/write.c
libgloss/d30v/Makefile.in
libgloss/d30v/aclocal.m4
libgloss/d30v/configure
libgloss/d30v/configure.in
libgloss/d30v/crt0.S
libgloss/d30v/inbyte.c
libgloss/d30v/outbyte.c
libgloss/d30v/syscalls.c
libgloss/debug.c
libgloss/debug.h
libgloss/doc/Makefile.in
libgloss/doc/configure
libgloss/doc/configure.in
libgloss/doc/porting.texi
libgloss/fr30/Makefile.in
libgloss/fr30/aclocal.m4
libgloss/fr30/configure
libgloss/fr30/configure.in
libgloss/fr30/crt0.s
libgloss/fr30/syscalls.c
libgloss/frv/Makefile.in
libgloss/frv/aclocal.m4
libgloss/frv/configure
libgloss/frv/configure.in
libgloss/frv/crt0.S
libgloss/frv/fstat.c
libgloss/frv/getpid.c
libgloss/frv/isatty.c
libgloss/frv/kill.c
libgloss/frv/print.c
libgloss/frv/putnum.c
libgloss/frv/sbrk.c
libgloss/frv/sim-close.S
libgloss/frv/sim-exit.S
libgloss/frv/sim-inbyte.c
libgloss/frv/sim-lseek.S
libgloss/frv/sim-open.S
libgloss/frv/sim-read.S
libgloss/frv/sim-time.c
libgloss/frv/sim-unlink.S
libgloss/frv/sim-write.S
libgloss/frv/stat.c
libgloss/fstat.c
libgloss/getpid.c
libgloss/glue.h
libgloss/hp74x/Makefile.in
libgloss/hp74x/README
libgloss/hp74x/aclocal.m4
libgloss/hp74x/checksum.c
libgloss/hp74x/configure
libgloss/hp74x/configure.in
libgloss/hp74x/crt0.s
libgloss/hp74x/debugger.h
libgloss/hp74x/debugger.s
libgloss/hp74x/diagnose.h
libgloss/hp74x/hppa-defs.h
libgloss/hp74x/hppa.ld
libgloss/hp74x/io.c
libgloss/hp74x/iva_table.h
libgloss/hp74x/iva_table.s
libgloss/hp74x/pa_stub.c
libgloss/hp74x/test.c
libgloss/i386/Makefile.in
libgloss/i386/aclocal.m4
libgloss/i386/configure
libgloss/i386/configure.in
libgloss/i386/cygmon-crt0.S
libgloss/i386/cygmon-gmon.c
libgloss/i386/cygmon-gmon.h
libgloss/i386/cygmon-salib.c
libgloss/i386/cygmon-syscall.h
libgloss/i386/cygmon.ld
libgloss/i960/Makefile.in
libgloss/i960/aclocal.m4
libgloss/i960/asm.h
libgloss/i960/configure
libgloss/i960/configure.in
libgloss/i960/crt0.c
libgloss/i960/mon-read.c
libgloss/i960/mon-syscalls.S
libgloss/i960/mon-write.c
libgloss/i960/mon960.c
libgloss/i960/mon960.ld
libgloss/i960/syscall.h
libgloss/iq2000/Makefile.in
libgloss/iq2000/_exit.c
libgloss/iq2000/access.c
libgloss/iq2000/aclocal.m4
libgloss/iq2000/chmod.c
libgloss/iq2000/chown.c
libgloss/iq2000/close.c
libgloss/iq2000/configure
libgloss/iq2000/configure.in
libgloss/iq2000/creat.c
libgloss/iq2000/crt0.S
libgloss/iq2000/crt1.c
libgloss/iq2000/execv.c
libgloss/iq2000/execve.c
libgloss/iq2000/fork.c
libgloss/iq2000/fstat.c
libgloss/iq2000/getpid.c
libgloss/iq2000/gettime.c
libgloss/iq2000/isatty.c
libgloss/iq2000/kill.c
libgloss/iq2000/lseek.c
libgloss/iq2000/open.c
libgloss/iq2000/pipe.c
libgloss/iq2000/read.c
libgloss/iq2000/sbrk.c
libgloss/iq2000/sim.ld
libgloss/iq2000/stat.c
libgloss/iq2000/test.c
libgloss/iq2000/time.c
libgloss/iq2000/times.c
libgloss/iq2000/trap.c
libgloss/iq2000/trap.h
libgloss/iq2000/unlink.c
libgloss/iq2000/utime.c
libgloss/iq2000/wait.c
libgloss/iq2000/write.c
libgloss/isatty.c
libgloss/kill.c
libgloss/libnosys/Makefile.in
libgloss/libnosys/_exit.c
libgloss/libnosys/acconfig.h
libgloss/libnosys/aclocal.m4
libgloss/libnosys/chown.c
libgloss/libnosys/close.c
libgloss/libnosys/config.h.in
libgloss/libnosys/configure
libgloss/libnosys/configure.in
libgloss/libnosys/environ.c
libgloss/libnosys/errno.c
libgloss/libnosys/execve.c
libgloss/libnosys/fork.c
libgloss/libnosys/fstat.c
libgloss/libnosys/getpid.c
libgloss/libnosys/gettod.c
libgloss/libnosys/isatty.c
libgloss/libnosys/kill.c
libgloss/libnosys/link.c
libgloss/libnosys/lseek.c
libgloss/libnosys/open.c
libgloss/libnosys/read.c
libgloss/libnosys/readlink.c
libgloss/libnosys/sbrk.c
libgloss/libnosys/stat.c
libgloss/libnosys/symlink.c
libgloss/libnosys/times.c
libgloss/libnosys/unlink.c
libgloss/libnosys/wait.c
libgloss/libnosys/warning.h
libgloss/libnosys/write.c
libgloss/lm32/Makefile.in
libgloss/lm32/aclocal.m4
libgloss/lm32/configure
libgloss/lm32/configure.in
libgloss/lm32/crt0.S
libgloss/lm32/isatty.c
libgloss/lm32/scall.S
libgloss/lm32/sim.ld
libgloss/lseek.c
libgloss/m32c/Makefile.in
libgloss/m32c/abort.S
libgloss/m32c/aclocal.m4
libgloss/m32c/argv.S
libgloss/m32c/argvlen.S
libgloss/m32c/chdir.S
libgloss/m32c/chmod.S
libgloss/m32c/close.S
libgloss/m32c/configure
libgloss/m32c/configure.in
libgloss/m32c/crt0.S
libgloss/m32c/crtn.S
libgloss/m32c/exit.S
libgloss/m32c/fstat.S
libgloss/m32c/genscript
libgloss/m32c/getpid.S
libgloss/m32c/gettimeofday.S
libgloss/m32c/heaptop.S
libgloss/m32c/isatty.S
libgloss/m32c/kill.S
libgloss/m32c/link.S
libgloss/m32c/lseek.S
libgloss/m32c/m32c.tmpl
libgloss/m32c/m32csys.h
libgloss/m32c/open.S
libgloss/m32c/read.S
libgloss/m32c/sample.c
libgloss/m32c/sbrk.c
libgloss/m32c/stat.S
libgloss/m32c/time.S
libgloss/m32c/times.S
libgloss/m32c/unlink.S
libgloss/m32c/utime.S
libgloss/m32c/varvects.S
libgloss/m32c/varvects.h
libgloss/m32c/write.S
libgloss/m32r/Makefile.in
libgloss/m32r/aclocal.m4
libgloss/m32r/chmod.c
libgloss/m32r/close.c
libgloss/m32r/configure
libgloss/m32r/configure.in
libgloss/m32r/crt0.S
libgloss/m32r/eit.h
libgloss/m32r/eva-stub.ld
libgloss/m32r/eva.ld
libgloss/m32r/exit.c
libgloss/m32r/fstat.c
libgloss/m32r/getpid.c
libgloss/m32r/isatty.c
libgloss/m32r/kill.c
libgloss/m32r/lseek.c
libgloss/m32r/m32r-lib.c
libgloss/m32r/m32r-stub.c
libgloss/m32r/mon.specs
libgloss/m32r/open.c
libgloss/m32r/raise.c
libgloss/m32r/read.c
libgloss/m32r/sbrk.c
libgloss/m32r/stat.c
libgloss/m32r/trap0.S
libgloss/m32r/trapmon0.c
libgloss/m32r/unlink.c
libgloss/m32r/utime.c
libgloss/m32r/write.c
libgloss/m68hc11/Makefile.in
libgloss/m68hc11/aclocal.m4
libgloss/m68hc11/configure
libgloss/m68hc11/configure.in
libgloss/m68hc11/crt0.S
libgloss/m68hc11/sci-inout.S
libgloss/m68hc11/sim-valid-m68hc11.ld
libgloss/m68hc11/sim-valid-m68hc12.ld
libgloss/m68hc11/syscalls.c
libgloss/m68k/Makefile.in
libgloss/m68k/README
libgloss/m68k/aclocal.m4
libgloss/m68k/asm.h
libgloss/m68k/bcc.ld
libgloss/m68k/cf-crt0.S
libgloss/m68k/cf-crt1.c
libgloss/m68k/cf-exit.c
libgloss/m68k/cf-hosted.S
libgloss/m68k/cf-isrs.c
libgloss/m68k/cf-isv.S
libgloss/m68k/cf-sbrk.c
libgloss/m68k/cf.sc
libgloss/m68k/configure
libgloss/m68k/configure.in
libgloss/m68k/cpu32bug.S
libgloss/m68k/cpu32bug.h
libgloss/m68k/crt0.S
libgloss/m68k/dtor.C
libgloss/m68k/fido-_exit.c
libgloss/m68k/fido-crt0.S
libgloss/m68k/fido-handler.c
libgloss/m68k/fido-hosted.S
libgloss/m68k/fido-sbrk.c
libgloss/m68k/fido.h
libgloss/m68k/fido.sc
libgloss/m68k/fido_profiling.h
libgloss/m68k/idp-inbyte.c
libgloss/m68k/idp-outbyte.c
libgloss/m68k/idp.ld
libgloss/m68k/idpgdb.ld
libgloss/m68k/io-close.c
libgloss/m68k/io-exit.c
libgloss/m68k/io-fstat.c
libgloss/m68k/io-gdb.c
libgloss/m68k/io-gettimeofday.c
libgloss/m68k/io-isatty.c
libgloss/m68k/io-lseek.c
libgloss/m68k/io-open.c
libgloss/m68k/io-read.c
libgloss/m68k/io-rename.c
libgloss/m68k/io-stat.c
libgloss/m68k/io-system.c
libgloss/m68k/io-time.c
libgloss/m68k/io-unlink.c
libgloss/m68k/io-write.c
libgloss/m68k/io.h
libgloss/m68k/leds.c
libgloss/m68k/leds.h
libgloss/m68k/mc68681reg.h
libgloss/m68k/mc68ec.c
libgloss/m68k/mvme-stub.c
libgloss/m68k/mvme.S
libgloss/m68k/mvme135-asm.S
libgloss/m68k/mvme135.ld
libgloss/m68k/mvme162.ld
libgloss/m68k/mvme162lx-asm.S
libgloss/m68k/sbc5204.ld
libgloss/m68k/sbc5206.ld
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libgloss/xstormy16/eva_app.c
libgloss/xstormy16/eva_app.ld
libgloss/xstormy16/eva_stub.ld
libgloss/xstormy16/fstat.c
libgloss/xstormy16/getpid.c
libgloss/xstormy16/isatty.c
libgloss/xstormy16/kill.c
libgloss/xstormy16/lseek.c
libgloss/xstormy16/open.c
libgloss/xstormy16/sim_high.ld
libgloss/xstormy16/sim_malloc_start.s
libgloss/xstormy16/sim_rom.ld
libgloss/xstormy16/stat.c
libgloss/xstormy16/syscalls.S
libgloss/xstormy16/syscalls.m4
libgloss/xstormy16/unlink.c
libgloss/xstormy16/xstormy16_stub.c
ltgcc.m4
ltoptions.m4
ltsugar.m4
ltversion.m4
lt~obsolete.m4
newlib/libc/machine/microblaze/Makefile.am
newlib/libc/machine/microblaze/Makefile.in
newlib/libc/machine/microblaze/abort.c
newlib/libc/machine/microblaze/aclocal.m4
newlib/libc/machine/microblaze/configure
newlib/libc/machine/microblaze/configure.in
newlib/libc/machine/microblaze/longjmp.S
newlib/libc/machine/microblaze/setjmp.S
newlib/libc/machine/microblaze/strcmp.c
newlib/libc/machine/microblaze/strcpy.c
newlib/libc/machine/microblaze/strlen.c
newlib/libc/machine/rx/Makefile.am
newlib/libc/machine/rx/Makefile.in
newlib/libc/machine/rx/aclocal.m4
newlib/libc/machine/rx/configure
newlib/libc/machine/rx/configure.in
newlib/libc/machine/rx/memchr.S
newlib/libc/machine/rx/memcpy.S
newlib/libc/machine/rx/memmove.S
newlib/libc/machine/rx/mempcpy.S
newlib/libc/machine/rx/memset.S
newlib/libc/machine/rx/setjmp.S
newlib/libc/machine/rx/strcat.S
newlib/libc/machine/rx/strcmp.S
newlib/libc/machine/rx/strcpy.S
newlib/libc/machine/rx/strlen.S
newlib/libc/machine/rx/strncat.S
newlib/libc/machine/rx/strncmp.S
newlib/libc/machine/rx/strncpy.S
newlib/libc/machine/xc16x/Makefile.am
newlib/libc/machine/xc16x/Makefile.in
newlib/libc/machine/xc16x/aclocal.m4
newlib/libc/machine/xc16x/configure
newlib/libc/machine/xc16x/configure.in
newlib/libc/machine/xc16x/putchar.c
newlib/libc/machine/xc16x/puts.c
newlib/libc/machine/xc16x/setjmp.S
newlib/libc/sys/linux/bits/dirent.h
newlib/libc/sys/linux/bits/initspin.h
newlib/libc/sys/linux/bits/libc-lock.h
newlib/libc/sys/linux/bits/pthreadtypes.h
newlib/libc/sys/linux/bits/typesizes.h
newlib/libc/sys/linux/net/nscd/nscd-client.h
newlib/libc/sys/linux/net/nscd/nscd_proto.h
newlib/libc/sys/rdos/Makefile.am
newlib/libc/sys/rdos/Makefile.in
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newlib/libc/sys/rdos/chown.c
newlib/libc/sys/rdos/close.c
newlib/libc/sys/rdos/config.h
newlib/libc/sys/rdos/configure
newlib/libc/sys/rdos/configure.in
newlib/libc/sys/rdos/crt0.S
newlib/libc/sys/rdos/execve.c
newlib/libc/sys/rdos/fork.c
newlib/libc/sys/rdos/fstat.c
newlib/libc/sys/rdos/getenv.c
newlib/libc/sys/rdos/getpid.c
newlib/libc/sys/rdos/gettod.c
newlib/libc/sys/rdos/isatty.c
newlib/libc/sys/rdos/kill.c
newlib/libc/sys/rdos/link.c
newlib/libc/sys/rdos/lseek.c
newlib/libc/sys/rdos/open.c
newlib/libc/sys/rdos/rdos.S
newlib/libc/sys/rdos/rdos.h
newlib/libc/sys/rdos/rdoshelp.c
newlib/libc/sys/rdos/read.c
newlib/libc/sys/rdos/readlink.c
newlib/libc/sys/rdos/sbrk.c
newlib/libc/sys/rdos/stat.c
newlib/libc/sys/rdos/symlink.c
newlib/libc/sys/rdos/times.c
newlib/libc/sys/rdos/unlink.c
newlib/libc/sys/rdos/user.def
newlib/libc/sys/rdos/wait.c
newlib/libc/sys/rdos/write.c
newlib/libm/machine/spu/Makefile.am
newlib/libm/machine/spu/Makefile.in
newlib/libm/machine/spu/aclocal.m4
newlib/libm/machine/spu/configure
newlib/libm/machine/spu/configure.in
newlib/libm/machine/spu/fe_dfl_env.c
newlib/libm/machine/spu/feclearexcept.c
newlib/libm/machine/spu/fegetenv.c
newlib/libm/machine/spu/fegetexceptflag.c
newlib/libm/machine/spu/fegetround.c
newlib/libm/machine/spu/feholdexcept.c
newlib/libm/machine/spu/feraiseexcept.c
newlib/libm/machine/spu/fesetenv.c
newlib/libm/machine/spu/fesetexceptflag.c
newlib/libm/machine/spu/fesetround.c
newlib/libm/machine/spu/fetestexcept.c
newlib/libm/machine/spu/feupdateenv.c
newlib/libm/machine/spu/headers/acos.h
newlib/libm/machine/spu/headers/acosd2.h
newlib/libm/machine/spu/headers/acosf.h
newlib/libm/machine/spu/headers/acosf4.h
newlib/libm/machine/spu/headers/acosh.h
newlib/libm/machine/spu/headers/acoshd2.h
newlib/libm/machine/spu/headers/acoshf.h
newlib/libm/machine/spu/headers/acoshf4.h
newlib/libm/machine/spu/headers/asin.h
newlib/libm/machine/spu/headers/asind2.h
newlib/libm/machine/spu/headers/asinf.h
newlib/libm/machine/spu/headers/asinf4.h
newlib/libm/machine/spu/headers/asinh.h
newlib/libm/machine/spu/headers/asinhd2.h
newlib/libm/machine/spu/headers/asinhf.h
newlib/libm/machine/spu/headers/asinhf4.h
newlib/libm/machine/spu/headers/atan.h
newlib/libm/machine/spu/headers/atan2.h
newlib/libm/machine/spu/headers/atan2d2.h
newlib/libm/machine/spu/headers/atan2f.h
newlib/libm/machine/spu/headers/atan2f4.h
newlib/libm/machine/spu/headers/atand2.h
newlib/libm/machine/spu/headers/atanf.h
newlib/libm/machine/spu/headers/atanf4.h
newlib/libm/machine/spu/headers/atanh.h
newlib/libm/machine/spu/headers/atanhd2.h
newlib/libm/machine/spu/headers/atanhf.h
newlib/libm/machine/spu/headers/atanhf4.h
newlib/libm/machine/spu/headers/cbrt.h
newlib/libm/machine/spu/headers/cbrtf.h
newlib/libm/machine/spu/headers/ceil.h
newlib/libm/machine/spu/headers/ceilf.h
newlib/libm/machine/spu/headers/copysign.h
newlib/libm/machine/spu/headers/copysignf.h
newlib/libm/machine/spu/headers/cos.h
newlib/libm/machine/spu/headers/cos_sin.h
newlib/libm/machine/spu/headers/cosd2.h
newlib/libm/machine/spu/headers/cosf.h
newlib/libm/machine/spu/headers/cosf4.h
newlib/libm/machine/spu/headers/cosh.h
newlib/libm/machine/spu/headers/coshd2.h
newlib/libm/machine/spu/headers/coshf.h
newlib/libm/machine/spu/headers/coshf4.h
newlib/libm/machine/spu/headers/divd2.h
newlib/libm/machine/spu/headers/divf4.h
newlib/libm/machine/spu/headers/dom_chkd_less_than.h
newlib/libm/machine/spu/headers/dom_chkd_negone_one.h
newlib/libm/machine/spu/headers/dom_chkf_less_than.h
newlib/libm/machine/spu/headers/dom_chkf_negone_one.h
newlib/libm/machine/spu/headers/erf.h
newlib/libm/machine/spu/headers/erf_utils.h
newlib/libm/machine/spu/headers/erfc.h
newlib/libm/machine/spu/headers/erfcd2.h
newlib/libm/machine/spu/headers/erfcf.h
newlib/libm/machine/spu/headers/erfcf4.h
newlib/libm/machine/spu/headers/erfd2.h
newlib/libm/machine/spu/headers/erff.h
newlib/libm/machine/spu/headers/erff4.h
newlib/libm/machine/spu/headers/exp.h
newlib/libm/machine/spu/headers/exp2.h
newlib/libm/machine/spu/headers/exp2d2.h
newlib/libm/machine/spu/headers/exp2f.h
newlib/libm/machine/spu/headers/exp2f4.h
newlib/libm/machine/spu/headers/expd2.h
newlib/libm/machine/spu/headers/expf.h
newlib/libm/machine/spu/headers/expf4.h
newlib/libm/machine/spu/headers/expm1.h
newlib/libm/machine/spu/headers/expm1d2.h
newlib/libm/machine/spu/headers/expm1f.h
newlib/libm/machine/spu/headers/expm1f4.h
newlib/libm/machine/spu/headers/fabs.h
newlib/libm/machine/spu/headers/fabsf.h
newlib/libm/machine/spu/headers/fdim.h
newlib/libm/machine/spu/headers/fdimf.h
newlib/libm/machine/spu/headers/feclearexcept.h
newlib/libm/machine/spu/headers/fefpscr.h
newlib/libm/machine/spu/headers/fegetenv.h
newlib/libm/machine/spu/headers/fegetexceptflag.h
newlib/libm/machine/spu/headers/fegetround.h
newlib/libm/machine/spu/headers/feholdexcept.h
newlib/libm/machine/spu/headers/feraiseexcept.h
newlib/libm/machine/spu/headers/fesetenv.h
newlib/libm/machine/spu/headers/fesetexceptflag.h
newlib/libm/machine/spu/headers/fesetround.h
newlib/libm/machine/spu/headers/fetestexcept.h
newlib/libm/machine/spu/headers/feupdateenv.h
newlib/libm/machine/spu/headers/floor.h
newlib/libm/machine/spu/headers/floord2.h
newlib/libm/machine/spu/headers/floorf.h
newlib/libm/machine/spu/headers/floorf4.h
newlib/libm/machine/spu/headers/fma.h
newlib/libm/machine/spu/headers/fmaf.h
newlib/libm/machine/spu/headers/fmax.h
newlib/libm/machine/spu/headers/fmaxf.h
newlib/libm/machine/spu/headers/fmin.h
newlib/libm/machine/spu/headers/fminf.h
newlib/libm/machine/spu/headers/fmod.h
newlib/libm/machine/spu/headers/fmodf.h
newlib/libm/machine/spu/headers/frexp.h
newlib/libm/machine/spu/headers/frexpf.h
newlib/libm/machine/spu/headers/hypot.h
newlib/libm/machine/spu/headers/hypotd2.h
newlib/libm/machine/spu/headers/hypotf.h
newlib/libm/machine/spu/headers/hypotf4.h
newlib/libm/machine/spu/headers/ilogb.h
newlib/libm/machine/spu/headers/ilogbf.h
newlib/libm/machine/spu/headers/isnan.h
newlib/libm/machine/spu/headers/isnand2.h
newlib/libm/machine/spu/headers/isnanf.h
newlib/libm/machine/spu/headers/isnanf4.h
newlib/libm/machine/spu/headers/ldexp.h
newlib/libm/machine/spu/headers/ldexpd2.h
newlib/libm/machine/spu/headers/ldexpf.h
newlib/libm/machine/spu/headers/ldexpf4.h
newlib/libm/machine/spu/headers/lgamma.h
newlib/libm/machine/spu/headers/lgammad2.h
newlib/libm/machine/spu/headers/lgammaf.h
newlib/libm/machine/spu/headers/lgammaf4.h
newlib/libm/machine/spu/headers/llrint.h
newlib/libm/machine/spu/headers/llrintf.h
newlib/libm/machine/spu/headers/llround.h
newlib/libm/machine/spu/headers/llroundf.h
newlib/libm/machine/spu/headers/log.h
newlib/libm/machine/spu/headers/log10.h
newlib/libm/machine/spu/headers/log10d2.h
newlib/libm/machine/spu/headers/log10f.h
newlib/libm/machine/spu/headers/log1p.h
newlib/libm/machine/spu/headers/log1pd2.h
newlib/libm/machine/spu/headers/log1pf.h
newlib/libm/machine/spu/headers/log1pf4.h
newlib/libm/machine/spu/headers/log2.h
newlib/libm/machine/spu/headers/log2d2.h
newlib/libm/machine/spu/headers/log2f.h
newlib/libm/machine/spu/headers/log2f4.h
newlib/libm/machine/spu/headers/logbf.h
newlib/libm/machine/spu/headers/logbf4.h
newlib/libm/machine/spu/headers/logd2.h
newlib/libm/machine/spu/headers/logf.h
newlib/libm/machine/spu/headers/logf4.h
newlib/libm/machine/spu/headers/lrint.h
newlib/libm/machine/spu/headers/lrintf.h
newlib/libm/machine/spu/headers/lround.h
newlib/libm/machine/spu/headers/lroundf.h
newlib/libm/machine/spu/headers/nearbyint.h
newlib/libm/machine/spu/headers/nearbyintf.h
newlib/libm/machine/spu/headers/nearbyintf4.h
newlib/libm/machine/spu/headers/nextafter.h
newlib/libm/machine/spu/headers/nextafterd2.h
newlib/libm/machine/spu/headers/nextafterf.h
newlib/libm/machine/spu/headers/nextafterf4.h
newlib/libm/machine/spu/headers/pow.h
newlib/libm/machine/spu/headers/powd2.h
newlib/libm/machine/spu/headers/powf.h
newlib/libm/machine/spu/headers/powf4.h
newlib/libm/machine/spu/headers/recipd2.h
newlib/libm/machine/spu/headers/recipf4.h
newlib/libm/machine/spu/headers/remainder.h
newlib/libm/machine/spu/headers/remainderf.h
newlib/libm/machine/spu/headers/remquo.h
newlib/libm/machine/spu/headers/remquof.h
newlib/libm/machine/spu/headers/rint.h
newlib/libm/machine/spu/headers/rintf.h
newlib/libm/machine/spu/headers/rintf4.h
newlib/libm/machine/spu/headers/round.h
newlib/libm/machine/spu/headers/roundf.h
newlib/libm/machine/spu/headers/scalbn.h
newlib/libm/machine/spu/headers/scalbnf.h
newlib/libm/machine/spu/headers/scalbnf4.h
newlib/libm/machine/spu/headers/signbit.h
newlib/libm/machine/spu/headers/signbitd2.h
newlib/libm/machine/spu/headers/simdmath.h
newlib/libm/machine/spu/headers/sin.h
newlib/libm/machine/spu/headers/sincos.h
newlib/libm/machine/spu/headers/sincosd2.h
newlib/libm/machine/spu/headers/sincosf.h
newlib/libm/machine/spu/headers/sincosf4.h
newlib/libm/machine/spu/headers/sind2.h
newlib/libm/machine/spu/headers/sinf.h
newlib/libm/machine/spu/headers/sinf4.h
newlib/libm/machine/spu/headers/sinh.h
newlib/libm/machine/spu/headers/sinhd2.h
newlib/libm/machine/spu/headers/sinhf.h
newlib/libm/machine/spu/headers/sinhf4.h
newlib/libm/machine/spu/headers/sqrt.h
newlib/libm/machine/spu/headers/sqrtd2.h
newlib/libm/machine/spu/headers/sqrtf.h
newlib/libm/machine/spu/headers/sqrtf4.h
newlib/libm/machine/spu/headers/tan.h
newlib/libm/machine/spu/headers/tand2.h
newlib/libm/machine/spu/headers/tanf.h
newlib/libm/machine/spu/headers/tanf4.h
newlib/libm/machine/spu/headers/tanh.h
newlib/libm/machine/spu/headers/tanhd2.h
newlib/libm/machine/spu/headers/tanhf.h
newlib/libm/machine/spu/headers/tanhf4.h
newlib/libm/machine/spu/headers/tgamma.h
newlib/libm/machine/spu/headers/tgammad2.h
newlib/libm/machine/spu/headers/tgammaf.h
newlib/libm/machine/spu/headers/tgammaf4.h
newlib/libm/machine/spu/headers/trunc.h
newlib/libm/machine/spu/headers/truncd2.h
newlib/libm/machine/spu/headers/truncf.h
newlib/libm/machine/spu/headers/truncf4.h
newlib/libm/machine/spu/headers/vec_literal.h
newlib/libm/machine/spu/llrint.c
newlib/libm/machine/spu/llrintf.c
newlib/libm/machine/spu/llround.c
newlib/libm/machine/spu/llroundf.c
newlib/libm/machine/spu/log2.c
newlib/libm/machine/spu/log2f.c
newlib/libm/machine/spu/s_asinh.c
newlib/libm/machine/spu/s_atan.c
newlib/libm/machine/spu/s_cbrt.c
newlib/libm/machine/spu/s_ceil.c
newlib/libm/machine/spu/s_copysign.c
newlib/libm/machine/spu/s_cos.c
newlib/libm/machine/spu/s_erf.c
newlib/libm/machine/spu/s_expm1.c
newlib/libm/machine/spu/s_fabs.c
newlib/libm/machine/spu/s_fdim.c
newlib/libm/machine/spu/s_floor.c
newlib/libm/machine/spu/s_fma.c
newlib/libm/machine/spu/s_fmax.c
newlib/libm/machine/spu/s_fmin.c
newlib/libm/machine/spu/s_frexp.c
newlib/libm/machine/spu/s_ilogb.c
newlib/libm/machine/spu/s_isnan.c
newlib/libm/machine/spu/s_ldexp.c
newlib/libm/machine/spu/s_log1p.c
newlib/libm/machine/spu/s_lrint.c
newlib/libm/machine/spu/s_lround.c
newlib/libm/machine/spu/s_nearbyint.c
newlib/libm/machine/spu/s_nextafter.c
newlib/libm/machine/spu/s_remquo.c
newlib/libm/machine/spu/s_rint.c
newlib/libm/machine/spu/s_round.c
newlib/libm/machine/spu/s_scalbn.c
newlib/libm/machine/spu/s_sin.c
newlib/libm/machine/spu/s_tan.c
newlib/libm/machine/spu/s_tanh.c
newlib/libm/machine/spu/s_trunc.c
newlib/libm/machine/spu/sf_asinh.c
newlib/libm/machine/spu/sf_atan.c
newlib/libm/machine/spu/sf_cbrt.c
newlib/libm/machine/spu/sf_ceil.c
newlib/libm/machine/spu/sf_copysign.c
newlib/libm/machine/spu/sf_cos.c
newlib/libm/machine/spu/sf_erf.c
newlib/libm/machine/spu/sf_expm1.c
newlib/libm/machine/spu/sf_fabs.c
newlib/libm/machine/spu/sf_fdim.c
newlib/libm/machine/spu/sf_finite.c
newlib/libm/machine/spu/sf_floor.c
newlib/libm/machine/spu/sf_fma.c
newlib/libm/machine/spu/sf_fmax.c
newlib/libm/machine/spu/sf_fmin.c
newlib/libm/machine/spu/sf_fpclassify.c
newlib/libm/machine/spu/sf_frexp.c
newlib/libm/machine/spu/sf_ilogb.c
newlib/libm/machine/spu/sf_isinf.c
newlib/libm/machine/spu/sf_isinff.c
newlib/libm/machine/spu/sf_isnan.c
newlib/libm/machine/spu/sf_isnanf.c
newlib/libm/machine/spu/sf_ldexp.c
newlib/libm/machine/spu/sf_log1p.c
newlib/libm/machine/spu/sf_logb.c
newlib/libm/machine/spu/sf_lrint.c
newlib/libm/machine/spu/sf_lround.c
newlib/libm/machine/spu/sf_nan.c
newlib/libm/machine/spu/sf_nearbyint.c
newlib/libm/machine/spu/sf_nextafter.c
newlib/libm/machine/spu/sf_remquo.c
newlib/libm/machine/spu/sf_rint.c
newlib/libm/machine/spu/sf_round.c
newlib/libm/machine/spu/sf_scalbn.c
newlib/libm/machine/spu/sf_sin.c
newlib/libm/machine/spu/sf_tan.c
newlib/libm/machine/spu/sf_tanh.c
newlib/libm/machine/spu/sf_trunc.c
newlib/libm/machine/spu/w_acos.c
newlib/libm/machine/spu/w_acosh.c
newlib/libm/machine/spu/w_asin.c
newlib/libm/machine/spu/w_atan2.c
newlib/libm/machine/spu/w_atanh.c
newlib/libm/machine/spu/w_cosh.c
newlib/libm/machine/spu/w_exp.c
newlib/libm/machine/spu/w_exp2.c
newlib/libm/machine/spu/w_fmod.c
newlib/libm/machine/spu/w_hypot.c
newlib/libm/machine/spu/w_lgamma.c
newlib/libm/machine/spu/w_log.c
newlib/libm/machine/spu/w_log10.c
newlib/libm/machine/spu/w_pow.c
newlib/libm/machine/spu/w_remainder.c
newlib/libm/machine/spu/w_sincos.c
newlib/libm/machine/spu/w_sinh.c
newlib/libm/machine/spu/w_sqrt.c
newlib/libm/machine/spu/w_tgamma.c
newlib/libm/machine/spu/wf_acos.c
newlib/libm/machine/spu/wf_acosh.c
newlib/libm/machine/spu/wf_asin.c
newlib/libm/machine/spu/wf_atan2.c
newlib/libm/machine/spu/wf_atanh.c
newlib/libm/machine/spu/wf_cosh.c
newlib/libm/machine/spu/wf_exp.c
newlib/libm/machine/spu/wf_exp2.c
newlib/libm/machine/spu/wf_fmod.c
newlib/libm/machine/spu/wf_hypot.c
newlib/libm/machine/spu/wf_lgamma.c
newlib/libm/machine/spu/wf_log.c
newlib/libm/machine/spu/wf_log10.c
newlib/libm/machine/spu/wf_pow.c
newlib/libm/machine/spu/wf_remainder.c
newlib/libm/machine/spu/wf_sincos.c
newlib/libm/machine/spu/wf_sinh.c
newlib/libm/machine/spu/wf_sqrt.c
newlib/libm/machine/spu/wf_tgamma.c
texinfo/texinfo.tex
Diffstat (limited to 'libgloss/bfin/include/defBF547.h')
-rw-r--r-- | libgloss/bfin/include/defBF547.h | 1575 |
1 files changed, 0 insertions, 1575 deletions
diff --git a/libgloss/bfin/include/defBF547.h b/libgloss/bfin/include/defBF547.h deleted file mode 100644 index a84154fe6..000000000 --- a/libgloss/bfin/include/defBF547.h +++ /dev/null @@ -1,1575 +0,0 @@ -/* - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/* -** defBF547.h -** -** Copyright (C) 2008, 2009 Analog Devices, Inc. -** -************************************************************************************ -** -** This include file contains a list of macro "defines" to enable the programmer -** to use symbolic names for register-access and bit-manipulation. -** -**/ -#ifndef _DEF_BF547_H -#define _DEF_BF547_H - -/* Include all Core registers and bit definitions */ -#include <def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */ - -/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ -#include <defBF54x_base.h> - -#ifdef _MISRA_RULES -#pragma diag(push) -#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4 ") -#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ") -#endif /* _MISRA_RULES */ - -/* The following are the #defines needed by ADSP-BF547 that are not in the common header */ - -/* Timer Registers */ - -#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ -#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ -#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ -#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ -#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ -#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ -#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ -#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ -#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ -#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ -#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ -#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ - -/* Timer Group of 3 Registers */ - -#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ -#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ -#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ - -/* SPORT0 Registers */ - -#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ -#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ -#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ -#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ -#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ -#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ -#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ -#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ - -/* EPPI0 Registers */ - -#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ -#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ -#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ -#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ -#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ -#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ -#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ -#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ -#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ -#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ - -/* UART2 Registers */ - -#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ -#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ -#define UART2_GCTL 0xffc02108 /* Global Control Register */ -#define UART2_LCR 0xffc0210c /* Line Control Register */ -#define UART2_MCR 0xffc02110 /* Modem Control Register */ -#define UART2_LSR 0xffc02114 /* Line Status Register */ -#define UART2_MSR 0xffc02118 /* Modem Status Register */ -#define UART2_SCR 0xffc0211c /* Scratch Register */ -#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ -#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ -#define UART2_THR 0xffc02128 /* Transmit Hold Register */ -#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ - -/* Two Wire Interface Registers (TWI1) */ - -#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ -#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ -#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ -#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */ -#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ -#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ - -/* SPI2 Registers */ - -#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ -#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ -#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ -#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ -#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ -#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ -#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ - - -/* ATAPI Registers */ - -#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ -#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ -#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ -#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ -#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ -#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ -#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ -#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ -#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ -#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ -#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ -#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ -#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ -#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ -#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ -#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ -#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ -#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ -#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ -#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ -#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ -#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ -#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ - -/* SDH Registers */ - -#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ -#define SDH_COMMAND 0xffc0390c /* SDH Command */ -#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ -#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ -#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ -#define SDH_STATUS 0xffc03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ -#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ -#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ -#define SDH_CFG 0xffc039c8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ -#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ - -/* HOST Port Registers */ - -#define HOST_CONTROL 0xffc03a00 /* HOSTDP Control Register */ -#define HOST_STATUS 0xffc03a04 /* HOSTDP Status Register */ -#define HOST_TIMEOUT 0xffc03a08 /* HOSTDP Acknowledge Mode Timeout Register */ - -/* USB Control Registers */ - -#define USB_FADDR 0xffc03c00 /* Function address register */ -#define USB_POWER 0xffc03c04 /* Power management register */ -#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xffc03c20 /* USB frame number */ -#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ - -/* USB Packet Control Registers */ - -#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ - -/* USB Endpoint FIFO Registers */ - -#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ - -/* USB OTG Control Registers */ - -#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ - -/* USB Phy Control Registers */ - -#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ - -/* (APHY_CNTRL is for ADI usage only) */ - -#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ - -/* (APHY_CALIB is for ADI usage only) */ - -#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ - -/* (PHY_TEST is for ADI usage only) */ - -#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ - -/* USB Endpoint 0 Control Registers */ - -#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ - -/* USB Endpoint 1 Control Registers */ - -#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ - -/* USB Endpoint 2 Control Registers */ - -#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ - -/* USB Endpoint 3 Control Registers */ - -#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ - -/* USB Endpoint 4 Control Registers */ - -#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ - -/* USB Endpoint 5 Control Registers */ - -#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ - -/* USB Endpoint 6 Control Registers */ - -#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ - -/* USB Endpoint 7 Control Registers */ - -#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ - -/* USB Channel 0 Config Registers */ - -#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ -#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ - -/* USB Channel 1 Config Registers */ - -#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ -#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ - -/* USB Channel 2 Config Registers */ - -#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ -#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ - -/* USB Channel 3 Config Registers */ - -#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ -#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ - -/* USB Channel 4 Config Registers */ - -#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ -#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ - -/* USB Channel 5 Config Registers */ - -#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ -#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ - -/* USB Channel 6 Config Registers */ - -#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ -#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ - -/* USB Channel 7 Config Registers */ - -#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ -#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -/* Keypad Registers */ - -#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ -#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ -#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ -#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ -#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ -#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ - -/* Pixel Compositor (PIXC) Registers */ - -#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ -#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ -#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ -#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ -#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ -#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ -#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ -#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ -#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ -#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ -#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ -#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ -#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ -#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ -#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for PIXC_CTL */ - -#define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 -#define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 -#define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 -#define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 -#define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 -#define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 -#define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 -#define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 -#define IMG_STAT 0x300 /* Image FIFO Status */ -#define OVR_STAT 0xc00 /* Overlay FIFO Status */ -#define WM_LVL 0x3000 /* FIFO Watermark Level */ - -/* Bit masks for PIXC_AHSTART */ - -#define A_HSTART 0xfff /* Horizontal Start Coordinates */ - -/* Bit masks for PIXC_AHEND */ - -#define A_HEND 0xfff /* Horizontal End Coordinates */ - -/* Bit masks for PIXC_AVSTART */ - -#define A_VSTART 0x3ff /* Vertical Start Coordinates */ - -/* Bit masks for PIXC_AVEND */ - -#define A_VEND 0x3ff /* Vertical End Coordinates */ - -/* Bit masks for PIXC_ATRANSP */ - -#define A_TRANSP 0xf /* Transparency Value */ - -/* Bit masks for PIXC_BHSTART */ - -#define B_HSTART 0xfff /* Horizontal Start Coordinates */ - -/* Bit masks for PIXC_BHEND */ - -#define B_HEND 0xfff /* Horizontal End Coordinates */ - -/* Bit masks for PIXC_BVSTART */ - -#define B_VSTART 0x3ff /* Vertical Start Coordinates */ - -/* Bit masks for PIXC_BVEND */ - -#define B_VEND 0x3ff /* Vertical End Coordinates */ - -/* Bit masks for PIXC_BTRANSP */ - -#define B_TRANSP 0xf /* Transparency Value */ - -/* Bit masks for PIXC_INTRSTAT */ - -#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 -#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 -#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 -#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 - -/* Bit masks for PIXC_RYCON */ - -#define A11 0x3ff /* A11 in the Coefficient Matrix */ -#define A12 0xffc00 /* A12 in the Coefficient Matrix */ -#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ -#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 - -/* Bit masks for PIXC_GUCON */ - -#define A21 0x3ff /* A21 in the Coefficient Matrix */ -#define A22 0xffc00 /* A22 in the Coefficient Matrix */ -#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ -#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 - -/* Bit masks for PIXC_BVCON */ - -#define A31 0x3ff /* A31 in the Coefficient Matrix */ -#define A32 0xffc00 /* A32 in the Coefficient Matrix */ -#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ -#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 - -/* Bit masks for PIXC_CCBIAS */ - -#define A14 0x3ff /* A14 in the Bias Vector */ -#define A24 0xffc00 /* A24 in the Bias Vector */ -#define A34 0x3ff00000 /* A34 in the Bias Vector */ - -/* Bit masks for PIXC_TC */ - -#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ -#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ -#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ - -/* Bit masks for HOST_CONTROL */ - -#define HOSTDP_EN 0x1 /* HOSTDP Enable */ -#define nHOSTDP_EN 0x0 -#define HOSTDP_END 0x2 /* Host Endianess */ -#define nHOSTDP_END 0x0 -#define HOSTDP_DATA_SIZE 0x4 /* Data Size */ -#define nHOSTDP_DATA_SIZE 0x0 -#define HOSTDP_RST 0x8 /* HOSTDP Reset */ -#define nHOSTDP_RST 0x0 -#define HRDY_OVR 0x20 /* HRDY Override */ -#define nHRDY_OVR 0x0 -#define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 -#define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 -#define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 -#define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 -#define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 - -/* Bit masks for HOST_STATUS */ - -#define DMA_RDY 0x1 /* DMA Ready */ -#define nDMA_RDY 0x0 -#define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 -#define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 -#define DMA_CMPLT 0x8 /* DMA Complete */ -#define nDMA_CMPLT 0x0 -#define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 -#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */ -#define nHOSTDP_TOUT 0x0 -#define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 -#define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 -#define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 -#define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 - -/* Bit masks for HOST_TIMEOUT */ - -#define COUNT_TIMEOUT 0x7ff /* HOSTDP Timeout count */ - -/* Bit masks for KPAD_CTL */ - -#define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 -#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ -#define nKPAD_IRQMODE 0x0 /* Interrupt Disabled */ -#define KPAD_IRQMODE_SK 0x2 /* Single key (single row, single column) press interrupt enable */ -#define KPAD_IRQMODE_MK 0x4 /* Single key press multiple key press interrupt enable */ - -#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ -#define KPAD_COLEN 0xe000 /* Column Enable Width */ - -#ifdef _MISRA_RULES -#define SET_KPAD_ROWEN(x) (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */ -#define SET_KPAD_COLEN(x) (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */ -#else -#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */ -#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */ -#endif /* _MISRA_RULES */ - - -/* Bit masks for KPAD_PRESCALE */ - -#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ - -#ifdef _MISRA_RULES -#define SET_KPAD_PRESCALE(x) ((x)&0x3Fu) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */ -#else -#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */ -#endif /* _MISRA_RULES */ - - -/* Bit masks for KPAD_MSEL */ - -#define DBON_SCALE 0xff /* Debounce Scale Value */ -#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ - -#ifdef _MISRA_RULES -#define SET_KPAD_DBON_SCALE(x) ((x)&0xFFu) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */ -#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */ -#else -#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */ -#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */ -#endif /* _MISRA_RULES */ - - -/* Bit masks for KPAD_ROWCOL */ - -#define KPAD_ROW 0xff /* Rows Pressed */ -#define KPAD_COL 0xff00 /* Columns Pressed */ - -/* Bit masks for KPAD_STAT */ - -#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 -#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ -#define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 -#define KPAD_NO_KEY 0x0 /* No Keypress Status*/ -#define KPAD_SINGLE_KEY 0x2 /* Single Keypress Status */ -#define KPAD_MKSROWCOL 0x4 /* Multiple Keypress in the same row or column Status */ -#define KPAD_MKMROWCOL 0x6 /* Multiple Keypress in the same multiple rows and multiple columns Status */ - -/* Bit masks for KPAD_SOFTEVAL */ - -#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 - -/* Bit masks for SDH_COMMAND */ - -#define CMD_IDX 0x3f /* Command Index */ -#define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 -#define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 -#define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 -#define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 -#define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 - -/* Bit masks for SDH_PWR_CTL */ - -#define PWR_ON 0x3 /* Power On */ -#if 0 -#define TBD 0x3c /* TBD */ -#endif -#define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 -#define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 - -/* Bit masks for SDH_CLK_CTL */ - -#define CLKDIV 0xff /* MC_CLK Divisor */ -#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 -#define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 -#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 -#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 - -/* Bit masks for SDH_RESP_CMD */ - -#define RESP_CMD 0x3f /* Response Command */ - -/* Bit masks for SDH_DATA_CTL */ - -#define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 -#define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 -#define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 -#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 -#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ - -/* Bit masks for SDH_STATUS */ - -#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 -#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 -#define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 -#define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 -#define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 -#define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 -#define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 -#define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 -#define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 -#define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 -#define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 -#define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 -#define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 -#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 -#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 -#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 -#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 -#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 -#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 -#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 -#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 - -/* Bit masks for SDH_STATUS_CLR */ - -#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 -#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 -#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 -#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 -#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 -#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 -#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 -#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 -#define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 -#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 -#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 - -/* Bit masks for SDH_MASK0 */ - -#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 -#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 -#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 -#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 -#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 -#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 -#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 -#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 -#define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 -#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 -#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 -#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 -#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 -#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 -#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 -#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 -#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 -#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 -#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 -#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 -#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 -#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 - -/* Bit masks for SDH_FIFO_CNT */ - -#define FIFO_COUNT 0x7fff /* FIFO Count */ - -/* Bit masks for SDH_E_STATUS */ - -#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 -#define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 - -/* Bit masks for SDH_E_MASK */ - -#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 -#define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 - -/* Bit masks for SDH_CFG */ - -#define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 -#define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 -#define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 -#define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 -#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 -#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 -#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 - -/* Bit masks for SDH_RD_WAIT_EN */ - -#define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 - -/* Bit masks for ATAPI_CONTROL */ - -#define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 -#define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 -#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 -#define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 -#define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 -#define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 -#define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 -#define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 -#define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 -#define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 -#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 -#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ - -/* Bit masks for ATAPI_STATUS */ - -#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 -#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 -#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 -#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ - -/* Bit masks for ATAPI_DEV_ADDR */ - -#define DEV_ADDR 0x1f /* Device Address */ - -/* Bit masks for ATAPI_INT_MASK */ - -#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 -#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 -#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 -#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 -#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 -#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 -#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 -#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 -#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 - -/* Bit masks for ATAPI_INT_STATUS */ - -#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 -#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 -#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 -#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 -#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 -#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 -#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 -#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 -#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 - -/* Bit masks for ATAPI_LINE_STATUS */ - -#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 -#define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 -#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 -#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 -#define ATAPI_ADDR 0x70 /* ATAPI address line status */ -#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 -#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 -#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 -#define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 -#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 - -/* Bit masks for ATAPI_SM_STATE */ - -#define PIO_CSTATE 0xf /* PIO mode state machine current state */ -#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ -#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ -#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_TERMINATE */ - -#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 - -/* Bit masks for ATAPI_REG_TIM_0 */ - -#define T2_REG 0xff /* End of cycle time for register access transfers */ -#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ - -/* Bit masks for ATAPI_PIO_TIM_0 */ - -#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ -#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ -#define T4_REG 0xf000 /* DIOW data hold */ - -/* Bit masks for ATAPI_PIO_TIM_1 */ - -#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ - -/* Bit masks for ATAPI_MULTI_TIM_0 */ - -#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ -#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ - -/* Bit masks for ATAPI_MULTI_TIM_1 */ - -#define TKW 0xff /* Selects DIOW negated pulsewidth */ -#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ - -/* Bit masks for ATAPI_MULTI_TIM_2 */ - -#define TH 0xff /* Selects DIOW data hold */ -#define TEOC 0xff00 /* Selects end of cycle for DMA */ - -/* Bit masks for ATAPI_ULTRA_TIM_0 */ - -#define TACK 0xff /* Selects setup and hold times for TACK */ -#define TENV 0xff00 /* Selects envelope time */ - -/* Bit masks for ATAPI_ULTRA_TIM_1 */ - -#define TDVS 0xff /* Selects data valid setup time */ -#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ - -/* Bit masks for ATAPI_ULTRA_TIM_2 */ - -#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ -#define TMLI 0xff00 /* Selects interlock time */ - -/* Bit masks for ATAPI_ULTRA_TIM_3 */ - -#define TZAH 0xff /* Selects minimum delay required for output */ -#define READY_PAUSE 0xff00 /* Selects ready to pause */ - -/* Bit masks for TIMER_ENABLE1 */ - -#define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 -#define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 -#define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 - -/* Bit masks for TIMER_DISABLE1 */ - -#define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 -#define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 -#define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 - -/* Bit masks for TIMER_STATUS1 */ - -#define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 -#define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 -#define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 -#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 -#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 -#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 -#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 -#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 -#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 - -/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ - -/* Bit masks for USB_FADDR */ - -#define FUNCTION_ADDRESS 0x7f /* Function address */ - -/* Bit masks for USB_POWER */ - -#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 -#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 -#define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 -#define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 -#define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 -#define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 -#define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 -#define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 - -/* Bit masks for USB_INTRTX */ - -#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 -#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 -#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 -#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 -#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 -#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 -#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 -#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 - -/* Bit masks for USB_INTRRX */ - -#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 -#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 -#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 -#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 -#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 -#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 -#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 - -/* Bit masks for USB_INTRTXE */ - -#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 -#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 -#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 -#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 -#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 -#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 -#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 -#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 - -/* Bit masks for USB_INTRRXE */ - -#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 -#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 -#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 -#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 -#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 -#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 -#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 - -/* Bit masks for USB_INTRUSB */ - -#define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 -#define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 -#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 -#define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 -#define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 -#define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 -#define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 -#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 - -/* Bit masks for USB_INTRUSBE */ - -#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 -#define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 -#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 -#define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 -#define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 -#define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 -#define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 -#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 - -/* Bit masks for USB_FRAME */ - -#define FRAME_NUMBER 0x7ff /* Frame number */ - -/* Bit masks for USB_INDEX */ - -#define SELECTED_ENDPOINT 0xf /* selected endpoint */ - -/* Bit masks for USB_GLOBAL_CTL */ - -#define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 -#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 -#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 -#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 -#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 -#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 -#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 -#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 -#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 -#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 -#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 -#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 -#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 -#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 -#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 - -/* Bit masks for USB_OTG_DEV_CTL */ - -#define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 -#define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 -#define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 -#define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 -#define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 -#define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 -#define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 -#define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 - -/* Bit masks for USB_OTG_VBUS_IRQ */ - -#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 -#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 -#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 -#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 -#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 -#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 - -/* Bit masks for USB_OTG_VBUS_MASK */ - -#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 -#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 -#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 -#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 -#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 -#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 - -/* Bit masks for USB_CSR0 */ - -#define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 -#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 -#define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 -#define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 -#define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 -#define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 -#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 -#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 -#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 -#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 -#define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 -#define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 -#define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 -#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 -#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 - -/* Bit masks for USB_COUNT0 */ - -#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ - -/* Bit masks for USB_NAKLIMIT0 */ - -#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ - -/* Bit masks for USB_TX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_RX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_TXCSR */ - -#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 -#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 -#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 -#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 -#define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 -#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 -#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 -#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 -#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 -#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 -#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 -#define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 -#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 -#define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 -#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 -#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 - -/* Bit masks for USB_TXCOUNT */ - -#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ - -/* Bit masks for USB_RXCSR */ - -#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 -#define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 -#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 -#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 -#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 -#define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 -#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 -#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 -#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 -#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 -#define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 -#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 -#define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 -#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 -#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 -#define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 -#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 -#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 -#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 -#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 - -/* Bit masks for USB_RXCOUNT */ - -#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ - -/* Bit masks for USB_TXTYPE */ - -#define TARGET_EP_NO_T 0xf /* EP number */ -#define PROTOCOL_T 0xc /* transfer type */ - -/* Bit masks for USB_TXINTERVAL */ - -#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ - -/* Bit masks for USB_RXTYPE */ - -#define TARGET_EP_NO_R 0xf /* EP number */ -#define PROTOCOL_R 0xc /* transfer type */ - -/* Bit masks for USB_RXINTERVAL */ - -#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ - -/* Bit masks for USB_DMA_INTERRUPT */ - -#define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 -#define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 -#define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 -#define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 -#define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 -#define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 -#define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 -#define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 - -/* Bit masks for USB_DMAxCONTROL */ - -#define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 -#define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 -#define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 -#define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 -#define EPNUM 0xf0 /* EP number */ -#define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 - -/* Bit masks for USB_DMAxADDRHIGH */ - -#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ - -/* Bit masks for USB_DMAxADDRLOW */ - -#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ - -/* Bit masks for USB_DMAxCOUNTHIGH */ - -#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ - -/* Bit masks for USB_DMAxCOUNTLOW */ - -#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ - -/* ******************************************* */ -/* MULTI BIT MACRO ENUMERATIONS */ -/* ******************************************* */ - -#ifdef _MISRA_RULES -#pragma diag(pop) -#endif /* _MISRA_RULES */ - -#endif /* _DEF_BF547_H */ |