2009-09-16 Mike Frysinger <michael.frysinger@analog.com>

        * bfin/include/cdefBF512.h, bfin/include/cdefBF514.h,
        bfin/include/cdefBF516.h, bfin/include/cdefBF518.h,
        bfin/include/cdefBF51x_base.h, bfin/include/cdefBF523.h,
        bfin/include/cdefBF524.h, bfin/include/cdefBF526.h,
        bfin/include/cdefBF542M.h, bfin/include/cdefBF544M.h,
        bfin/include/cdefBF547M.h, bfin/include/cdefBF548M.h,
        bfin/include/cdefBF549M.h, bfin/include/defBF512.h,
        bfin/include/defBF514.h, bfin/include/defBF516.h,
        bfin/include/defBF518.h, bfin/include/defBF51x_base.h,
        bfin/include/defBF523.h, bfin/include/defBF524.h,
        bfin/include/defBF526.h, bfin/include/defBF542M.h,
        bfin/include/defBF544M.h, bfin/include/defBF547M.h,
        bfin/include/defBF548M.h, bfin/include/defBF549M.h:
        New file.
        * bfin/include/ccblkfn.h, bfin/include/cdefBF525.h,
        bfin/include/cdefBF527.h, bfin/include/cdefBF52x_base.h,
        bfin/include/cdefBF532.h, bfin/include/cdefBF534.h,
        bfin/include/cdefBF535.h, bfin/include/cdefBF538.h,
        bfin/include/cdefBF539.h, bfin/include/cdefBF542.h,
        bfin/include/cdefBF544.h, bfin/include/cdefBF547.h,
        bfin/include/cdefBF548.h, bfin/include/cdefBF549.h,
        bfin/include/cdefBF54x_base.h, bfin/include/cdefBF561.h,
        bfin/include/cdefblackfin.h, bfin/include/cdef_LPBlackfin.h,
        bfin/include/cplb.h, bfin/include/defBF527.h,
        bfin/include/defBF52x_base.h, bfin/include/defBF532.h,
        bfin/include/defBF534.h, bfin/include/defBF535.h,
        bfin/include/defBF537.h, bfin/include/defBF538.h,
        bfin/include/defBF539.h, bfin/include/defBF542.h,
        bfin/include/defBF544.h, bfin/include/defBF547.h,
        bfin/include/defBF548.h, bfin/include/defBF549.h,
        bfin/include/defBF54x_base.h, bfin/include/defBF561.h,
        bfin/include/defblackfin.h, bfin/include/def_LPBlackfin.h,
        bfin/include/sys/_adi_platform.h,
        bfin/include/sys/anomaly_macros_rtl.h,
        bfin/include/sys/exception.h, bfin/include/sysreg.h:
        Update to Visual DSP 5.0 Update 6.

1 files changed, 18 insertions, 5 deletions

diff --git a/libgloss/bfin/include/defblackfin.h b/libgloss/bfin/include/defblackfin.h
index d55046faa..d172f38f8 100644
--- a/libgloss/bfin/include/defblackfin.h
+++ b/libgloss/bfin/include/defblackfin.h
@@ -14,7 +14,7 @@
  *
  * defblackfin.h
  *
- * Copyright (C) 2008 Analog Devices, Inc.
+ * Copyright (C) 2008, 2009 Analog Devices, Inc.
  *
  ************************************************************************/
 
@@ -33,8 +33,12 @@
 #if defined(__ADSPLPBLACKFIN__)
 #warning defblackfin.h should only be included for 535 compatible chips.
 #endif
-/* Macro parameters should be enclosed in parantheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
+/* Macro parameters should be enclosed in parentheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
+#ifdef _MISRA_RULES
+#define MK_BMSK_( x ) (1ul<<(x))    /* Make a bit mask from a bit position */
+#else
 #define MK_BMSK_( x ) (1<<(x))    /* Make a bit mask from a bit position */
+#endif /* _MISRA_RULES */
 
 /*********************************************************************************** */
 /* System Register Bits */
@@ -429,9 +433,18 @@
 
 
 /* DCPLB_DATA and ICPLB_DATA Bit Positions */
-#define CPLB_VALID_P           0x00000000  /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P            0x00000001  /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD_P         0x00000002  /*  */
+#define CPLB_VALID_P            0  /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P             1  /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P          2  /* 0=no read access, 1=read access allowed (user mode) */
+/*** DCPLB_DATA only */
+#define CPLB_USER_WR_P          3  /* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR_P          4  /* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_L1SRAM_P           5  /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
+#define CPLB_DA0ACC_P           6  /* 0=access allowed from either DAG, 1=access from DAG0 only */
+#define CPLB_DIRTY_P            7  /* 1=dirty, 0=clean */
+#define CPLB_L1_CHBL_P          12 /* 0=non-cacheable in L1, 1=cacheable in L1 */
+#define CPLB_WT_P               14 /* 0=write-back, 1=write-through */
+
 
 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
 #if !defined(__ADSPLPBLACKFIN__)