diff options
| -rw-r--r-- | include/opcode/ChangeLog | 8 | ||||
| -rw-r--r-- | include/opcode/mips.h | 6 |
2 files changed, 13 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index bfd71e055..2cbb382d5 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,11 @@ +2011-12-08 Andrew Pinski <apinski@cavium.com> + Adam Nemet <anemet@caviumnetworks.com> + + * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. + (INSN_OCTEON2): New macro. + (CPU_OCTEON2): New macro. + (OPCODE_IS_MEMBER): Add Octeon2. + 2011-11-29 Andrew Pinski <apinski@cavium.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index eb28d160f..fb9094c26 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -713,11 +713,12 @@ static const unsigned int mips_isa_table[] = { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; /* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xc3ff0e20 +#define INSN_CHIP_MASK 0xc3ff0f20 /* Cavium Networks Octeon instructions. */ #define INSN_OCTEON 0x00000800 #define INSN_OCTEONP 0x00000200 +#define INSN_OCTEON2 0x00000100 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x3c00f010 @@ -825,6 +826,7 @@ static const unsigned int mips_isa_table[] = #define CPU_LOONGSON_3A 3003 #define CPU_OCTEON 6501 #define CPU_OCTEONP 6601 +#define CPU_OCTEON2 6502 #define CPU_XLR 887682 /* decimal 'XLR' */ /* Test for membership in an ISA including chip specific ISAs. INSN @@ -863,6 +865,8 @@ static const unsigned int mips_isa_table[] = && ((insn)->membership & INSN_OCTEON) != 0) \ || (cpu == CPU_OCTEONP \ && ((insn)->membership & INSN_OCTEONP) != 0) \ + || (cpu == CPU_OCTEON2 \ + && ((insn)->membership & INSN_OCTEON2) != 0) \ || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ || 0) /* Please keep this term for easier source merging. */ |