diff options
Diffstat (limited to 'include/opcode/crx.h')
| -rw-r--r-- | include/opcode/crx.h | 123 |
1 files changed, 78 insertions, 45 deletions
diff --git a/include/opcode/crx.h b/include/opcode/crx.h index 58db2f8b3..033b268b0 100644 --- a/include/opcode/crx.h +++ b/include/opcode/crx.h @@ -41,20 +41,16 @@ typedef enum uhi, ulo, /* Processor Status Register. */ psr, - /* Configuration Register. */ - cfg, - /* Coprocessor Configuration Register. */ - cpcfg, - /* Cashe Configuration Register. */ - ccfg, /* Interrupt Base Register. */ intbase, /* Interrupt Stack Pointer Register. */ isp, + /* Configuration Register. */ + cfg, + /* Coprocessor Configuration Register. */ + cpcfg, /* Coprocessor Enable Register. */ cen, - /* Program Counter Register. */ - pc, /* Not a register. */ nullregister, MAX_REG @@ -83,13 +79,11 @@ copreg; typedef enum { - CRX_PC_REGTYPE, /* pc type */ CRX_R_REGTYPE, /* r<N> */ CRX_U_REGTYPE, /* u<N> */ CRX_C_REGTYPE, /* c<N> */ CRX_CS_REGTYPE, /* cs<N> */ - CRX_MTPR_REGTYPE, /* mtpr */ - CRX_CFG_REGTYPE /* *hi|lo, *cfg, psr */ + CRX_CFG_REGTYPE /* configuration register */ } reg_type; @@ -117,32 +111,38 @@ typedef enum argtype; /* CRX operand types : - The operand types correspond to instructions operands - - Operand Types : - cst4 - 4-bit encoded constant - iN - N-bit immediate field - d, dispsN - N-bit immediate signed displacement - dispuN - N-bit immediate unsigned displacement - absN - N-bit absolute address - rbase - 4-bit genaral-purpose register specifier - regr - 4-bit genaral-purpose register specifier - regr8 - 8-bit register address space - copregr - coprocessor register - copsregr - coprocessor special register - scl2 - 2-bit scaling factor for memory index - ridx - register index. */ + The operand types correspond to instructions operands. */ typedef enum { - dummy, cst4, disps9, - i3, i4, i5, i8, i12, i16, i32, - d5, d9, d17, d25, d33, + dummy, + /* 4-bit encoded constant. */ + cst4, + /* N-bit immediate. */ + i16, i32, + /* N-bit unsigned immediate. */ + ui3, ui4, ui5, ui16, + /* N-bit signed displacement. */ + disps9, disps17, disps25, disps32, + /* N-bit unsigned displacement. */ + dispu5, + /* N-bit escaped displacement. */ + dispe9, + /* N-bit absolute address. */ abs16, abs32, + /* Register relative. */ rbase, rbase_cst4, - rbase_dispu8, rbase_dispu12, rbase_dispu16, rbase_dispu28, rbase_dispu32, - rbase_ridx_scl2_dispu6, rbase_ridx_scl2_dispu22, - regr, regr8, copregr,copregr8,copsregr, + rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32, + /* Register index. */ + rindex_disps6, rindex_disps22, + /* 4-bit genaral-purpose register specifier. */ + regr, + /* 8-bit register address space. */ + regr8, + /* coprocessor register. */ + copregr, + /* coprocessor special register. */ + copsregr, /* Not an operand. */ nulloperand, /* Maximum supported operand. */ @@ -152,6 +152,7 @@ operand_type; /* CRX instruction types. */ +#define NO_TYPE_INS 0 #define ARITH_INS 1 #define LD_STOR_INS 2 #define BRANCH_INS 3 @@ -184,23 +185,37 @@ operand_type; #define REG_LIST CRX_INS_MAX /* The operands in binary and assembly are placed in reverse order. load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ -#define REVERSE_MATCH (REG_LIST << 1) +#define REVERSE_MATCH (1 << 6) /* Kind of displacement map used DISPU[BWD]4. */ -#define DISPUB4 (REVERSE_MATCH << 1) -#define DISPUW4 (DISPUB4 << 1) -#define DISPUD4 (DISPUW4 << 1) -#define CST4MAP (DISPUB4 | DISPUW4 | DISPUD4) +#define DISPUB4 (1 << 7) +#define DISPUW4 (1 << 8) +#define DISPUD4 (1 << 9) +#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4) /* Printing formats, where the instruction prefix isn't consecutive. */ -#define FMT_1 (DISPUD4 << 1) /* 0xF0F00000 */ -#define FMT_2 (FMT_1 << 1) /* 0xFFF0FF00 */ -#define FMT_3 (FMT_2 << 1) /* 0xFFF00F00 */ -#define FMT_4 (FMT_3 << 1) /* 0xFFF0F000 */ -#define FMT_5 (FMT_4 << 1) /* 0xFFF0FFF0 */ +#define FMT_1 (1 << 10) /* 0xF0F00000 */ +#define FMT_2 (1 << 11) /* 0xFFF0FF00 */ +#define FMT_3 (1 << 12) /* 0xFFF00F00 */ +#define FMT_4 (1 << 13) /* 0xFFF0F000 */ +#define FMT_5 (1 << 14) /* 0xFFF0FFF0 */ #define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) -#define RELAXABLE (FMT_5 << 1) +/* Indicates whether this instruction can be relaxed. */ +#define RELAXABLE (1 << 15) + +/* Indicates that instruction uses user registers (and not + general-purpose registers) as operands. */ +#define USER_REG (1 << 16) + +/* Indicates that instruction can perfom a cst4 mapping. */ +#define CST4MAP (1 << 17) + +/* Instruction shouldn't allow 'sp' usage. */ +#define NO_SP (1 << 18) + +/* Instruction shouldn't allow to push a register which is used as a rptr. */ +#define NO_RPTR (1 << 19) /* Maximum operands per instruction. */ #define MAX_OPERANDS 5 @@ -211,6 +226,24 @@ operand_type; /* Maximum instruction length. */ #define MAX_INST_LEN 256 + +/* Values defined for the flags field of a struct operand_entry. */ + +/* Operand must be an unsigned number. */ +#define OPERAND_UNSIGNED (1 << 0) +/* Operand must be a signed number. */ +#define OPERAND_SIGNED (1 << 1) +/* A cst4 operand. */ +#define OPERAND_CST4 (1 << 2) +/* Operand must be an even number. */ +#define OPERAND_EVEN (1 << 3) +/* Operand is shifted right. */ +#define OPERAND_SHIFT (1 << 4) +/* Operand is shifted right and decremented. */ +#define OPERAND_SHIFT_DEC (1 << 5) +/* Operand has reserved escape sequences. */ +#define OPERAND_ESC (1 << 6) + /* Single operand description. */ typedef struct @@ -292,6 +325,8 @@ typedef struct unsigned int bit_size; /* Argument type. */ argtype arg_type; + /* One bit syntax flags. */ + int flags; } operand_entry; @@ -390,7 +425,5 @@ extern const inst *instruction; /* Replace all appearances of 'long long int' with LONGLONG. */ typedef long long int LONGLONG; typedef unsigned long long ULONGLONG; -/* A mask for the upper 31 bits of a 64 bits type. */ -#define UPPER31_MASK 0xFFFFFFFE00000000LL #endif /* _CRX_H_ */ |