diff options
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 7ff806825..7fd4703e5 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -31,9 +31,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) Make sure you use fields that are appropriate for the instruction, - of course. + of course. - The 'i' format uses OP, RS, RT and IMMEDIATE. + The 'i' format uses OP, RS, RT and IMMEDIATE. The 'j' format uses OP and TARGET. @@ -124,7 +124,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_SH_HINT 16 #define OP_MASK_HINT 0x1f #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ -#define OP_MASK_MMI 0x3f +#define OP_MASK_MMI 0x3f #define OP_SH_MMISUB 6 #define OP_MASK_MMISUB 0x1f #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ @@ -307,6 +307,7 @@ struct mips_opcode ORs of these bits, indicatingthat they support the instructions defined at the given level. */ +#define INSN_ISA_MASK 0x0000ffff #define INSN_ISA1 0x00000010 #define INSN_ISA2 0x00000020 #define INSN_ISA3 0x00000040 @@ -357,6 +358,7 @@ struct mips_opcode #define CPU_R6000 6000 #define CPU_R8000 8000 #define CPU_R10000 10000 +#define CPU_R12000 12000 #define CPU_MIPS16 16 #define CPU_MIPS32 32 #define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K'. */ @@ -367,14 +369,15 @@ struct mips_opcode /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. + to test, or zero if no CPU specific ISA test is desired. The gp32 arg is set when you need to force 32-bit register usage on a machine with 64-bit registers; see the documentation under -mgp32 in the MIPS gas docs. */ #define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \ ((((insn)->membership & isa) != 0 \ - && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ + && ((insn)->membership & INSN_GP32 ? gp32 : 1) \ + ) \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ @@ -382,7 +385,7 @@ struct mips_opcode || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)) /* This is a list of macro expanded instructions. - + _I appended means immediate _A appended means address _AB appended means address with base register @@ -447,11 +450,11 @@ enum M_DLA_AB, M_DLI, M_DMUL, - M_DMUL_I, + M_DMUL_I, M_DMULO, - M_DMULO_I, + M_DMULO_I, M_DMULOU, - M_DMULOU_I, + M_DMULOU_I, M_DREM_3, M_DREM_3I, M_DREMU_3, @@ -506,11 +509,11 @@ enum M_LWR_AB, M_LWU_AB, M_MUL, - M_MUL_I, + M_MUL_I, M_MULO, - M_MULO_I, + M_MULO_I, M_MULOU, - M_MULOU_I, + M_MULOU_I, M_NOR_I, M_OR_I, M_REM_3, |