diff options
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 235 |
1 files changed, 101 insertions, 134 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index ef81bbe2b..89ea3e9a7 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -212,6 +212,10 @@ #define OP_OP_SDC2 0x3e #define OP_OP_SDC3 0x3f /* a.k.a. sd */ +/* MIPS VIRT ASE */ +#define OP_MASK_CODE10 0x3ff +#define OP_SH_CODE10 11 + /* Values in the 'VSEL' field. */ #define MDMX_FMTSEL_IMM_QH 0x1d #define MDMX_FMTSEL_IMM_OB 0x1e @@ -255,8 +259,6 @@ of the operand handling in GAS. The fields below only exist in the microMIPS encoding, so define each one to have an empty range. */ -#define OP_MASK_CODE10 0 -#define OP_SH_CODE10 0 #define OP_MASK_TRAP 0 #define OP_SH_TRAP 0 #define OP_MASK_OFFSET10 0 @@ -277,8 +279,6 @@ #define OP_SH_MG 0 #define OP_MASK_MH 0 #define OP_SH_MH 0 -#define OP_MASK_MI 0 -#define OP_SH_MI 0 #define OP_MASK_MJ 0 #define OP_SH_MJ 0 #define OP_MASK_ML 0 @@ -328,6 +328,10 @@ #define OP_MASK_IMMY 0 #define OP_SH_IMMY 0 +/* Enhanced VA Scheme */ +#define OP_SH_EVAOFFSET 7 +#define OP_MASK_EVAOFFSET 0x1ff + /* This structure holds information for a particular instruction. */ struct mips_opcode @@ -355,6 +359,9 @@ struct mips_opcode /* A collection of bits describing the instruction sets of which this instruction or macro is a member. */ unsigned long membership; + /* A collection of bits describing the ASE of which this instruction + or macro is a member. */ + unsigned long ase; /* A collection of bits describing the instruction sets of which this instruction or macro is not a member. */ unsigned long exclusions; @@ -368,10 +375,11 @@ struct mips_opcode Each of these characters corresponds to a mask field defined above. - "1" 5 bit sync type (OP_*_SHAMT) + "1" 5 bit sync type (OP_*_STYPE) "<" 5 bit shift amount (OP_*_SHAMT) ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) "a" 26 bit target address (OP_*_TARGET) + "+i" likewise, but flips bit 0 "b" 5 bit base register (OP_*_RS) "c" 10 bit breakpoint code (OP_*_CODE) "d" 5 bit destination register specifier (OP_*_RD) @@ -379,7 +387,6 @@ struct mips_opcode "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) "j" 16 bit signed immediate (OP_*_DELTA) "k" 5 bit cache opcode in target register position (OP_*_CACHE) - Also used for immediate operands in vr5400 vector insns. "o" 16 bit signed offset (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA) "q" 10 bit extra breakpoint code (OP_*_CODE2) @@ -438,9 +445,6 @@ struct mips_opcode "P" 5 bit performance-monitor register (OP_*_PERFREG) "e" 5 bit vector register byte specifier (OP_*_VECBYTE) "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) - see also "k" above - "+D" Combined destination register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only. Macro instructions: "A" General 32 bit expression @@ -451,13 +455,14 @@ struct mips_opcode "f" 32 bit floating point constant "l" 32 bit floating point constant in .lit4 - MDMX instruction operands (note that while these use the FP register - fields, they accept both $fN and $vN names for the registers): - "O" MDMX alignment offset (OP_*_ALN) - "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) - "X" MDMX destination register (OP_*_FD) - "Y" MDMX source register (OP_*_FS) - "Z" MDMX source register (OP_*_FT) + MDMX and VR5400 instruction operands (note that while these use the + FP register fields, the MDMX instructions accept both $fN and $vN names + for the registers): + "O" alignment offset (OP_*_ALN) + "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) + "X" destination register (OP_*_FD) + "Y" source register (OP_*_FS) + "Z" source register (OP_*_FT) DSP ASE usage: "2" 2 bit unsigned immediate for byte align (OP_*_BP) @@ -480,12 +485,14 @@ struct mips_opcode "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) "+t" 5 bit coprocessor 0 destination register (OP_*_RT) - "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only MCU ASE usage: "~" 12 bit offset (OP_*_OFFSET12) "\" 3 bit position for aset and aclr (OP_*_3BITPOS) + VIRT ASE usage: + "+J" 10-bit hypcall code (OP_*CODE10) + UDI immediates: "+1" UDI immediate bits 6-10 "+2" UDI immediate bits 6-15 @@ -500,11 +507,10 @@ struct mips_opcode "+P" Position field of cins/exts aliasing cins32/exts32. Matches if 32 <= pos < 64, otherwise skips to next candidate. "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. - "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32. - "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing - cint32/exts32. Enforces non-negative value and that - pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous - position field is "+p" or "+P". + "+s" Length-minus-one field of cins32/exts32. Requires msb position + of the field to be <= 31. + "+S" Length-minus-one field of cins/exts. Requires msb position + of the field to be <= 63. Loongson-3A: "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) @@ -513,10 +519,12 @@ struct mips_opcode "+z" 5-bit rz register (OP_*_RZ) "+Z" 5-bit fz register (OP_*_FZ) + Enhanced VA Scheme: + "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) + Other: "()" parens surrounding optional value "," separates operands - "[]" brackets around index for vector-op scalar operand specifier (vr5400) "+" Start of extension sequence. Characters used so far, for quick reference when adding more: @@ -528,8 +536,8 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234" - "ABCDEFGHIPQSTXZ" - "abcpstxz" + "ABCEFGHIJPQSXZ" + "abcijpstxz" */ /* These are the bits which may be set in the pinfo field of an @@ -673,8 +681,8 @@ struct mips_opcode #define INSN2_UNCOND_BRANCH 0x10000000 /* Is a conditional branch insn. */ #define INSN2_COND_BRANCH 0x20000000 -/* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */ -#define INSN2_WRITE_GPR_MHI 0x40000000 +/* Modifies the general purpose registers in MICROMIPSOP_*_MH. */ +#define INSN2_WRITE_GPR_MH 0x40000000 /* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */ #define INSN2_READ_GPR_MMN 0x80000000 @@ -725,19 +733,9 @@ static const unsigned int mips_isa_table[] = #define INSN_OCTEONP 0x00000200 #define INSN_OCTEON2 0x00000100 -/* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x3c00f010 - -/* DSP ASE */ -#define INSN_DSP 0x00001000 -#define INSN_DSP64 0x00002000 - /* MIPS R5900 instruction */ #define INSN_5900 0x00004000 -/* MIPS-3D ASE */ -#define INSN_MIPS3D 0x00008000 - /* MIPS R4650 instruction. */ #define INSN_4650 0x00010000 /* LSI R4010 instruction. */ @@ -759,14 +757,6 @@ static const unsigned int mips_isa_table[] = /* NEC VR5500 instruction. */ #define INSN_5500 0x02000000 -/* MDMX ASE */ -#define INSN_MDMX 0x04000000 -/* MT ASE */ -#define INSN_MT 0x08000000 -/* SmartMIPS ASE */ -#define INSN_SMARTMIPS 0x10000000 -/* DSP R2 ASE */ -#define INSN_DSPR2 0x20000000 /* ST Microelectronics Loongson 2E. */ #define INSN_LOONGSON_2E 0x40000000 /* ST Microelectronics Loongson 2F. */ @@ -774,10 +764,28 @@ static const unsigned int mips_isa_table[] = /* Loongson 3A. */ #define INSN_LOONGSON_3A 0x00000400 /* RMI Xlr instruction */ -#define INSN_XLR 0x00000020 +#define INSN_XLR 0x00000020 +/* DSP ASE */ +#define ASE_DSP 0x00000001 +#define ASE_DSP64 0x00000002 +/* DSP R2 ASE */ +#define ASE_DSPR2 0x00000004 +/* Enhanced VA Scheme */ +#define ASE_EVA 0x00000008 /* MCU (MicroController) ASE */ -#define INSN_MCU 0x00000010 +#define ASE_MCU 0x00000010 +/* MDMX ASE */ +#define ASE_MDMX 0x00000020 +/* MIPS-3D ASE */ +#define ASE_MIPS3D 0x00000040 +/* MT ASE */ +#define ASE_MT 0x00000080 +/* SmartMIPS ASE */ +#define ASE_SMARTMIPS 0x00000100 +/* Virtualization ASE */ +#define ASE_VIRT 0x00000200 +#define ASE_VIRT64 0x00000400 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -914,7 +922,7 @@ cpu_is_member (int cpu, unsigned int mask) if instruction INSN is available to the given ISA and CPU. */ static inline bfd_boolean -opcode_is_member (const struct mips_opcode *insn, int isa, int cpu) +opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) { if (!cpu_is_member (cpu, insn->exclusions)) { @@ -926,7 +934,7 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int cpu) return TRUE; /* Test for ASE compatibility. */ - if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0) + if ((ase & insn->ase) != 0) return TRUE; /* Test for processor-specific extensions. */ @@ -939,8 +947,8 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int cpu) /* This is a list of macro expanded instructions. _I appended means immediate - _A appended means address - _AB appended means address with base register + _A appended means target address of a jump + _AB appended means address with (possibly zero) base register _D appended means 64 bit floating point constant _S appended means 32 bit floating point constant. */ @@ -948,12 +956,10 @@ enum { M_ABS, M_ACLR_AB, - M_ACLR_OB, M_ADD_I, M_ADDU_I, M_AND_I, M_ASET_AB, - M_ASET_OB, M_BALIGN, M_BC1FL, M_BC1TL, @@ -1010,7 +1016,7 @@ enum M_BNE_I, M_BNEL_I, M_CACHE_AB, - M_CACHE_OB, + M_CACHEE_AB, M_DABS, M_DADD_I, M_DADDU_I, @@ -1047,73 +1053,57 @@ enum M_JALS_1, M_JALS_2, M_JALS_A, - M_L_DOB, + M_JRADDIUSP, + M_JRC, M_L_DAB, M_LA_AB, - M_LB_A, M_LB_AB, - M_LBU_A, + M_LBE_AB, M_LBU_AB, + M_LBUE_AB, M_LCA_AB, - M_LD_A, - M_LD_OB, M_LD_AB, M_LDC1_AB, M_LDC2_AB, - M_LDC2_OB, + M_LQC2_AB, M_LDC3_AB, M_LDL_AB, - M_LDL_OB, M_LDM_AB, - M_LDM_OB, M_LDP_AB, - M_LDP_OB, M_LDR_AB, - M_LDR_OB, - M_LH_A, M_LH_AB, - M_LHU_A, + M_LHE_AB, M_LHU_AB, + M_LHUE_AB, M_LI, M_LI_D, M_LI_DD, M_LI_S, M_LI_SS, M_LL_AB, - M_LL_OB, M_LLD_AB, - M_LLD_OB, + M_LLE_AB, M_LQ_AB, - M_LS_A, - M_LW_A, M_LW_AB, - M_LWC0_A, + M_LWE_AB, M_LWC0_AB, - M_LWC1_A, M_LWC1_AB, - M_LWC2_A, M_LWC2_AB, - M_LWC2_OB, - M_LWC3_A, M_LWC3_AB, - M_LWL_A, M_LWL_AB, - M_LWL_OB, + M_LWLE_AB, M_LWM_AB, - M_LWM_OB, M_LWP_AB, - M_LWP_OB, - M_LWR_A, M_LWR_AB, - M_LWR_OB, + M_LWRE_AB, M_LWU_AB, - M_LWU_OB, M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T, M_MOVE, + M_MOVEP, M_MUL, M_MUL_I, M_MULO, @@ -1123,7 +1113,7 @@ enum M_NOR_I, M_OR_I, M_PREF_AB, - M_PREF_OB, + M_PREFE_AB, M_REM_3, M_REM_3I, M_REMU_3, @@ -1137,32 +1127,22 @@ enum M_DROR_I, M_ROR_I, M_S_DA, - M_S_DOB, M_S_DAB, M_S_S, M_SAA_AB, - M_SAA_OB, M_SAAD_AB, - M_SAAD_OB, M_SC_AB, - M_SC_OB, M_SCD_AB, - M_SCD_OB, - M_SD_A, - M_SD_OB, + M_SCE_AB, M_SD_AB, M_SDC1_AB, M_SDC2_AB, - M_SDC2_OB, + M_SQC2_AB, M_SDC3_AB, M_SDL_AB, - M_SDL_OB, M_SDM_AB, - M_SDM_OB, M_SDP_AB, - M_SDP_OB, M_SDR_AB, - M_SDR_OB, M_SEQ, M_SEQ_I, M_SGE, @@ -1181,32 +1161,23 @@ enum M_SLTU_I, M_SNE, M_SNE_I, - M_SB_A, M_SB_AB, - M_SH_A, + M_SBE_AB, M_SH_AB, + M_SHE_AB, M_SQ_AB, - M_SW_A, M_SW_AB, - M_SWC0_A, + M_SWE_AB, M_SWC0_AB, - M_SWC1_A, M_SWC1_AB, - M_SWC2_A, M_SWC2_AB, - M_SWC2_OB, - M_SWC3_A, M_SWC3_AB, - M_SWL_A, M_SWL_AB, - M_SWL_OB, + M_SWLE_AB, M_SWM_AB, - M_SWM_OB, M_SWP_AB, - M_SWP_OB, - M_SWR_A, M_SWR_AB, - M_SWR_OB, + M_SWRE_AB, M_SUB_I, M_SUBU_I, M_SUBU_I_2, @@ -1218,20 +1189,13 @@ enum M_TNE_I, M_TRUNCWD, M_TRUNCWS, - M_ULD, - M_ULD_A, - M_ULH, - M_ULH_A, - M_ULHU, - M_ULHU_A, - M_ULW, - M_ULW_A, - M_USH, - M_USH_A, - M_USW, - M_USW_A, - M_USD, - M_USD_A, + M_ULD_AB, + M_ULH_AB, + M_ULHU_AB, + M_ULW_AB, + M_USH_AB, + M_USW_AB, + M_USD_AB, M_XOR_I, M_COP0, M_COP1, @@ -1336,6 +1300,7 @@ extern int bfd_mips_num_opcodes; "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) "a" 26 bit jump address + "i" likewise, but flips bit 0 "e" 11 bit extension value "l" register list for entry instruction "L" register list for exit instruction @@ -1506,8 +1471,6 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_MG 0 #define MICROMIPSOP_MASK_MH 0x7 #define MICROMIPSOP_SH_MH 7 -#define MICROMIPSOP_MASK_MI 0x7 -#define MICROMIPSOP_SH_MI 7 #define MICROMIPSOP_MASK_MJ 0x1f #define MICROMIPSOP_SH_MJ 0 #define MICROMIPSOP_MASK_ML 0x7 @@ -1627,6 +1590,10 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_FZ 0 #define MICROMIPSOP_MASK_FZ 0 +/* microMIPS Enhanced VA Scheme */ +#define MICROMIPSOP_SH_EVAOFFSET 0 +#define MICROMIPSOP_MASK_EVAOFFSET 0x1ff + /* These are the characters which may appears in the args field of a microMIPS instruction. They appear in the order in which the fields appear when the instruction is used. Commas and parentheses in the args @@ -1643,9 +1610,7 @@ extern const int bfd_mips16_num_opcodes; The same register used as both source and target. "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 - "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7 - "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7 - ("mh" and "mi" form a valid 3-bit register pair) + "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 @@ -1686,7 +1651,7 @@ extern const int bfd_mips16_num_opcodes; others too). "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) - "1" 5-bit sync type (MICROMIPSOP_*_SHAMT) + "1" 5-bit sync type (MICROMIPSOP_*_STYPE) "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) ">" shift amount between 32 and 63, stored after subtracting 32 (MICROMIPSOP_*_SHAMT) @@ -1694,6 +1659,7 @@ extern const int bfd_mips16_num_opcodes; "|" 4-bit trap code (MICROMIPSOP_*_TRAP) "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) "a" 26-bit target address (MICROMIPSOP_*_TARGET) + "+i" likewise, but flips bit 0 "b" 5-bit base register (MICROMIPSOP_*_RS) "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) @@ -1758,10 +1724,8 @@ extern const int bfd_mips16_num_opcodes; Coprocessor instructions: "E" 5-bit target register (MICROMIPSOP_*_RT) - "G" 5-bit destination register (MICROMIPSOP_*_RD) + "G" 5-bit source register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) - "+D" combined destination register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only Macro instructions: "A" general 32 bit expression @@ -1784,6 +1748,9 @@ extern const int bfd_mips16_num_opcodes; "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) + microMIPS Enhanced VA Scheme: + "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) + Other: "()" parens surrounding optional value "," separates operands @@ -1800,8 +1767,8 @@ extern const int bfd_mips16_num_opcodes; following), for quick reference when adding more: "" "" - "ABCDEFGHI" - "" + "ABCEFGHI" + "ij" Extension character sequences used so far ("m" followed by the following), for quick reference when adding more: |