diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 66 | ||||
| -rw-r--r-- | include/opcode/avr.h | 12 | ||||
| -rw-r--r-- | include/opcode/m68hc11.h | 50 | ||||
| -rw-r--r-- | include/opcode/mips.h | 52 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 43 | ||||
| -rw-r--r-- | include/opcode/sparc.h | 57 | ||||
| -rw-r--r-- | include/opcode/xgate.h | 120 |
7 files changed, 59 insertions, 341 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 1091973b2..07571e0b0 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,69 +1,3 @@ -2012-07-31 Chao-Ying Fu <fu@mips.com> - Catherine Moore <clm@codesourcery.com> - Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h: Document microMIPS DSP ASE usage. - (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for - microMIPS DSP ASE support. - (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. - (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. - (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. - (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. - (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. - (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. - (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. - -2012-07-06 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h: Fix a typo in description. - -2012-06-07 Georg-Johann Lay <avr@gjlay.de> - - * avr.h: (AVR_ISA_XCH): New define. - (AVR_ISA_XMEGA): Use it. - (XCH, LAS, LAT, LAC): New XMEGA opcodes. - -2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> - - * m68hc11.h: Add XGate definitions. - (struct m68hc11_opcode): Add xg_mask field. - -2012-05-14 Catherine Moore <clm@codesourcery.com> - Maciej W. Rozycki <macro@codesourcery.com> - Rhonda Wittels <rhonda@codesourcery.com> - - * ppc.h (PPC_OPCODE_VLE): New definition. - (PPC_OP_SA): New macro. - (PPC_OP_SE_VLE): New macro. - (PPC_OP): Use a variable shift amount. - (powerpc_operand): Update comments. - (PPC_OPSHIFT_INV): New macro. - (PPC_OPERAND_CR): Replace with... - (PPC_OPERAND_CR_BIT): ...this and - (PPC_OPERAND_CR_REG): ...this. - - -2012-05-03 Sean Keys <skeys@ipdatasys.com> - - * xgate.h: Header file for XGATE assembler. - -2012-04-27 David S. Miller <davem@davemloft.net> - - * sparc.h: Document new arg code' )' for crypto RS3 - immediates. - - * sparc.h (struct sparc_opcode): New field 'hwcaps'. - F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, - F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, - F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete. - (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC, - HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF, - HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU, - HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES, - HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1, - HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE, - HWCAP_CBCOND, HWCAP_CRC32): New defines. - 2012-03-10 Edmar Wienskoski <edmar@freescale.com> * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. diff --git a/include/opcode/avr.h b/include/opcode/avr.h index 6e86c07ba..a6d7b478d 100644 --- a/include/opcode/avr.h +++ b/include/opcode/avr.h @@ -1,6 +1,6 @@ /* Opcode table for the Atmel AVR micro controllers. - Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2012 Free Software Foundation, Inc. + Copyright 2000, 2001, 2004, 2006, 2008, 2010 Free Software Foundation, Inc. Contributed by Denis Chertykov <denisc@overta.ru> This program is free software; you can redistribute it and/or modify @@ -33,7 +33,6 @@ #define AVR_ISA_MOVW 0x1000 /* device has MOVW */ #define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */ #define AVR_ISA_DES 0x4000 /* device has DES */ -#define AVR_ISA_XCH 0x8000 /* device has XCH, LAC, LAS, LAT */ #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) @@ -53,7 +52,7 @@ #define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) #define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) #define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND) -#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES | AVR_ISA_XCH) +#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES) #define AVR_ISA_AVR1 AVR_ISA_TINY1 #define AVR_ISA_AVR2 AVR_ISA_2xxx @@ -125,6 +124,7 @@ 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) "100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b] "100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8 + "1001001xxxxx01xx" (128) 0x9[23][0-9a-f][4-7] "1001010xxxxx0100" (32) 0x9[45][0-9a-f]4 "1001010x001x1001" (4) 0x9[45][23]9 "1001010x01xx1001" (8) 0x9[45][4-7]9 @@ -265,12 +265,6 @@ AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f) AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) - /* Atomic memory operations for XMEGA. List before `sts'. */ -AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_XCH, 0x9204) -AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_XCH, 0x9205) -AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_XCH, 0x9206) -AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_XCH, 0x9207) - /* Known to be decoded as `nop' by the old core. */ AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) diff --git a/include/opcode/m68hc11.h b/include/opcode/m68hc11.h index 1a002008c..83f5a9a65 100644 --- a/include/opcode/m68hc11.h +++ b/include/opcode/m68hc11.h @@ -1,6 +1,5 @@ /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table - Copyright 1999, 2000, 2002, 2003, 2010, 2012 - Free Software Foundation, Inc. + Copyright 1999, 2000, 2002, 2003, 2010 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. @@ -38,7 +37,8 @@ of the M6811_INIT register. At init time, the I/O registers are mapped at 0x1000. Address of registers is then: - 0x1000 + M6811_xxx. */ + 0x1000 + M6811_xxx +*/ #define M6811_PORTA 0x00 /* Port A register */ #define M6811__RES1 0x01 /* Unused/Reserved */ #define M6811_PIOC 0x02 /* Parallel I/O Control register */ @@ -364,26 +364,6 @@ #define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ #define M6812_OP_IDX_P2 0x40000000 -/* XGATE defines. - These overlap with HC11/12 as above but not used at the same time. */ -#define M68XG_OP_NONE 0x0001 -#define M68XG_OP_IMM3 0x0002 -#define M68XG_OP_R 0x0004 -#define M68XG_OP_R_R 0x0008 -#define M68XG_OP_R_IMM4 0x0010 -#define M68XG_OP_R_R_R 0x0020 -#define M68XG_OP_REL9 0x0040 -#define M68XG_OP_REL10 0x0080 -#define M68XG_OP_R_R_OFFS5 0x0100 -#define M68XG_OP_RD_RB_RI 0x0200 -#define M68XG_OP_RD_RB_RIp 0x0400 -#define M68XG_OP_RD_RB_mRI 0x0800 -#define M68XG_OP_R_IMM8 0x1000 -#define M68XG_OP_R_IMM16 0x2000 -#define M68XG_OP_REG 0x4000 /* Register operand 1. */ -#define M68XG_OP_REG_2 0x8000 /* Register operand 2. */ -#define M68XG_MAX_OPERANDS 3 /* Max operands of triadic r1, r2, r3. */ - /* Markers to identify some instructions. */ #define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ #define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ @@ -394,43 +374,35 @@ #define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ #define M6812_OP_TBCC_MARKER 0x01000000 -/* XGATE markers. */ -#define M68XG_OP_B_MARKER 0x04000000 /* bXX rel9 */ -#define M68XG_OP_BRA_MARKER 0x02000000 /* bra rel10 */ - #define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ #define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ #define M6811_OP_LOW_ADDR 0x02000000 -#define M68HC12_BANK_VIRT 0x010000 -#define M68HC12_BANK_MASK 0x00003fff -#define M68HC12_BANK_BASE 0x00008000 -#define M68HC12_BANK_SHIFT 14 -#define M68HC12_BANK_PAGE_MASK 0x0ff +#define M68HC12_BANK_VIRT 0x010000 +#define M68HC12_BANK_MASK 0x00003fff +#define M68HC12_BANK_BASE 0x00008000 +#define M68HC12_BANK_SHIFT 14 +#define M68HC12_BANK_PAGE_MASK 0x0ff /* CPU identification. */ #define cpu6811 0x01 #define cpu6812 0x02 #define cpu6812s 0x04 -#define cpu9s12x 0x08 /* 9S12X main cpu. */ -#define cpuxgate 0x10 /* The XGATE module itself. */ /* The opcode table is an array of struct m68hc11_opcode. */ -struct m68hc11_opcode -{ - const char * name; /* Op-code name. */ +struct m68hc11_opcode { + const char* name; /* Op-code name */ long format; unsigned char size; - unsigned int opcode; + unsigned char opcode; unsigned char cycles_low; unsigned char cycles_high; unsigned char set_flags_mask; unsigned char clr_flags_mask; unsigned char chg_flags_mask; unsigned char arch; - unsigned int xg_mask; /* Mask with zero in register place for xgate. */ }; /* Alias definition for 68HC12. */ diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 857fc7173..fb9094c26 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1494,24 +1494,6 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_MASK_IMMY 0x1ff #define MICROMIPSOP_SH_IMMY 1 -/* MIPS DSP ASE */ -#define MICROMIPSOP_MASK_DSPACC 0x3 -#define MICROMIPSOP_SH_DSPACC 14 -#define MICROMIPSOP_MASK_DSPSFT 0x3f -#define MICROMIPSOP_SH_DSPSFT 16 -#define MICROMIPSOP_MASK_SA3 0x7 -#define MICROMIPSOP_SH_SA3 13 -#define MICROMIPSOP_MASK_SA4 0xf -#define MICROMIPSOP_SH_SA4 12 -#define MICROMIPSOP_MASK_IMM8 0xff -#define MICROMIPSOP_SH_IMM8 13 -#define MICROMIPSOP_MASK_IMM10 0x3ff -#define MICROMIPSOP_SH_IMM10 16 -#define MICROMIPSOP_MASK_WRDSP 0x3f -#define MICROMIPSOP_SH_WRDSP 14 -#define MICROMIPSOP_MASK_BP 0x3 -#define MICROMIPSOP_SH_BP 14 - /* Placeholders for fields that only exist in the traditional 32-bit instruction encoding; see the comment above for details. */ #define MICROMIPSOP_MASK_CODE20 0 @@ -1526,12 +1508,28 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_VECBYTE 0 #define MICROMIPSOP_MASK_VECALIGN 0 #define MICROMIPSOP_SH_VECALIGN 0 +#define MICROMIPSOP_MASK_DSPACC 0 +#define MICROMIPSOP_SH_DSPACC 0 #define MICROMIPSOP_MASK_DSPACC_S 0 #define MICROMIPSOP_SH_DSPACC_S 0 +#define MICROMIPSOP_MASK_DSPSFT 0 +#define MICROMIPSOP_SH_DSPSFT 0 #define MICROMIPSOP_MASK_DSPSFT_7 0 #define MICROMIPSOP_SH_DSPSFT_7 0 +#define MICROMIPSOP_MASK_SA3 0 +#define MICROMIPSOP_SH_SA3 0 +#define MICROMIPSOP_MASK_SA4 0 +#define MICROMIPSOP_SH_SA4 0 +#define MICROMIPSOP_MASK_IMM8 0 +#define MICROMIPSOP_SH_IMM8 0 +#define MICROMIPSOP_MASK_IMM10 0 +#define MICROMIPSOP_SH_IMM10 0 +#define MICROMIPSOP_MASK_WRDSP 0 +#define MICROMIPSOP_SH_WRDSP 0 #define MICROMIPSOP_MASK_RDDSP 0 #define MICROMIPSOP_SH_RDDSP 0 +#define MICROMIPSOP_MASK_BP 0 +#define MICROMIPSOP_SH_BP 0 #define MICROMIPSOP_MASK_MT_U 0 #define MICROMIPSOP_SH_MT_U 0 #define MICROMIPSOP_MASK_MT_H 0 @@ -1648,7 +1646,7 @@ extern const int bfd_mips16_num_opcodes; "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) "z" must be zero register "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) - "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) + "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10) "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes @@ -1704,18 +1702,6 @@ extern const int bfd_mips16_num_opcodes; "f" 32-bit floating point constant "l" 32-bit floating point constant in .lit4 - DSP ASE usage: - "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) - "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) - "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) - "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) - "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) - "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) - "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) - "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) - "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) - "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) - Other: "()" parens surrounding optional value "," separates operands @@ -1723,8 +1709,8 @@ extern const int bfd_mips16_num_opcodes; "m" start of microMIPS extension sequence Characters used so far, for quick reference when adding more: - "12345678 0" - "<>(),+.@\^|~" + "1234567890" + "<>(),+.\|~" "ABCDEFGHI KLMN RST V " "abcd f hijklmnopqrstuvw yz" diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 2e789d6ff..e672502e3 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -65,8 +65,6 @@ struct powerpc_opcode instructions. */ extern const struct powerpc_opcode powerpc_opcodes[]; extern const int powerpc_num_opcodes; -extern const struct powerpc_opcode vle_opcodes[]; -extern const int vle_num_opcodes; /* Values defined for the flags field of a struct powerpc_opcode. */ @@ -185,20 +183,8 @@ extern const int vle_num_opcodes; /* Opcode is supported by Thread management APU */ #define PPC_OPCODE_TMR 0x800000000ull -/* Opcode which is supported by the VLE extension. */ -#define PPC_OPCODE_VLE 0x1000000000ull - /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) - -/* A macro to determine if the instruction is a 2-byte VLE insn. */ -#define PPC_OP_SE_VLE(m) ((m) <= 0xffff) - -/* A macro to extract the major opcode from a VLE instruction. */ -#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) - -/* A macro to convert a VLE opcode to a VLE opcode segment. */ -#define VLE_OP_TO_SEG(i) ((i) >> 1) /* The operands table is an array of struct powerpc_operand. */ @@ -207,22 +193,16 @@ struct powerpc_operand /* A bitmask of bits in the operand. */ unsigned int bitm; - /* The shift operation to be applied to the operand. No shift - is made if this is zero. For positive values, the operand - is shifted left by SHIFT. For negative values, the operand - is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate - that BITM and SHIFT cannot be used to determine where the - operand goes in the insn. */ + /* How far the operand is left shifted in the instruction. + -1 to indicate that BITM and SHIFT cannot be used to determine + where the operand goes in the insn. */ int shift; /* Insertion function. This is used by the assembler. To insert an operand value into an instruction, check this field. If it is NULL, execute - if (o->shift >= 0) - i |= (op & o->bitm) << o->shift; - else - i |= (op & o->bitm) >> -o->shift; + i |= (op & o->bitm) << o->shift; (i is the instruction which we are filling in, o is a pointer to this structure, and op is the operand value). @@ -240,10 +220,7 @@ struct powerpc_operand extract this operand type from an instruction, check this field. If it is NULL, compute - if (o->shift >= 0) - op = (i >> o->shift) & o->bitm; - else - op = (i << -o->shift) & o->bitm; + op = (i >> o->shift) & o->bitm; if ((o->flags & PPC_OPERAND_SIGNED) != 0) sign_extend (op); (i is the instruction, o is a pointer to this structure, and op @@ -267,11 +244,6 @@ struct powerpc_operand extern const struct powerpc_operand powerpc_operands[]; extern const unsigned int num_powerpc_operands; -/* Use with the shift field of a struct powerpc_operand to indicate - that BITM and SHIFT cannot be used to determine where the operand - goes in the insn. */ -#define PPC_OPSHIFT_INV (-1 << 31) - /* Values defined for the flags field of a struct powerpc_operand. */ /* This operand takes signed values. */ @@ -305,7 +277,7 @@ extern const unsigned int num_powerpc_operands; cr4 4 cr5 5 cr6 6 cr7 7 These may be combined arithmetically, as in cr2*4+gt. These are only supported on the PowerPC, not the POWER. */ -#define PPC_OPERAND_CR_BIT (0x10) +#define PPC_OPERAND_CR (0x10) /* This operand names a register. The disassembler uses this to print register names with a leading 'r'. */ @@ -370,9 +342,6 @@ extern const unsigned int num_powerpc_operands; /* This operand names a vector-scalar unit register. The disassembler prints these with a leading 'vs'. */ #define PPC_OPERAND_VSR (0x100000) - -/* This is a CR FIELD that does not use symbolic names. */ -#define PPC_OPERAND_CR_REG (0x200000) /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h index b1c5e42ad..7ae3641cf 100644 --- a/include/opcode/sparc.h +++ b/include/opcode/sparc.h @@ -99,7 +99,6 @@ typedef struct sparc_opcode const char *args; /* This was called "delayed" in versions before the flags. */ unsigned int flags; - unsigned int hwcaps; short architecture; /* Bitmask of sparc_opcode_arch_val's. */ } sparc_opcode; @@ -111,39 +110,25 @@ typedef struct sparc_opcode #define F_JSR 0x00000010 /* Subroutine call. */ #define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */ #define F_FBR 0x00000040 /* Floating point branch. */ - -/* These must match the HWCAP_* values precisely. */ -#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ -#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ -#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ -#define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */ -#define HWCAP_POPC 0x00000010 /* 'popc' insn */ -#define HWCAP_VIS 0x00000020 /* VIS insns */ -#define HWCAP_VIS2 0x00000040 /* VIS2 insns */ -#define HWCAP_ASI_BLK_INIT \ - 0x00000080 /* block init ASIs */ -#define HWCAP_FMAF 0x00000100 /* fused multiply-add */ -#define HWCAP_VIS3 0x00000400 /* VIS3 insns */ -#define HWCAP_HPC 0x00000800 /* HPC insns */ -#define HWCAP_RANDOM 0x00001000 /* 'random' insn */ -#define HWCAP_TRANS 0x00002000 /* transaction insns */ -#define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */ -#define HWCAP_IMA 0x00008000 /* integer multiply-add */ -#define HWCAP_ASI_CACHE_SPARING \ - 0x00010000 /* cache sparing ASIs */ -#define HWCAP_AES 0x00020000 /* AES crypto insns */ -#define HWCAP_DES 0x00040000 /* DES crypto insns */ -#define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */ -#define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */ -#define HWCAP_MD5 0x00200000 /* MD5 hashing insns */ -#define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */ -#define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */ -#define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */ -#define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */ -#define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */ -#define HWCAP_PAUSE 0x08000000 /* Pause insn */ -#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ -#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ +#define F_MUL32 0x00000100 /* umul/umulcc/smul/smulcc insns */ +#define F_DIV32 0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */ +#define F_FSMULD 0x00000400 /* 'fsmuld' insn */ +#define F_V8PLUS 0x00000800 /* v9 insns available to 32bit */ +#define F_POPC 0x00001000 /* 'popc' insn */ +#define F_VIS 0x00002000 /* VIS insns */ +#define F_VIS2 0x00004000 /* VIS2 insns */ +#define F_ASI_BLK_INIT 0x00008000 /* block init ASIs */ +#define F_FMAF 0x00010000 /* fused multiply-add */ +#define F_VIS3 0x00020000 /* VIS3 insns */ +#define F_HPC 0x00040000 /* HPC insns */ +#define F_RANDOM 0x00080000 /* 'random' insn */ +#define F_TRANS 0x00100000 /* transaction insns */ +#define F_FJFMAU 0x00200000 /* unfused multiply-add */ +#define F_IMA 0x00400000 /* integer multiply-add */ +#define F_ASI_CACHE_SPARING \ + 0x00800000 /* cache sparing ASIs */ + +#define F_HWCAP_MASK 0x00ffff00 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a macro), which is 64 bits. It is handled as a special case. @@ -223,9 +208,7 @@ typedef struct sparc_opcode 0 32/64 bit immediate for set or setx (v9) insns _ Ancillary state register in rd (v9a) / Ancillary state register in rs1 (v9a) - ( entire floating point state register (%efsr) - ) 5 bit immediate placed in RS3 field - = 2+8 bit PC relative immediate. (v9) */ + ( entire floating point state register (%efsr). */ #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ diff --git a/include/opcode/xgate.h b/include/opcode/xgate.h deleted file mode 100644 index 77a521f83..000000000 --- a/include/opcode/xgate.h +++ /dev/null @@ -1,120 +0,0 @@ -/* xgate.h -- Freescale XGATE opcode list - Copyright 2010, 2011, 2012 Free Software Foundation, Inc. - Written by Sean Keys (skeys@ipdatasys.com) - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef _OPCODE_XGATE_H -#define _OPCODE_XGATE_H - -/* XGATE CCR flag definitions. */ -#define XGATE_N_BIT 0x08 /* XGN - Sign Flag */ -#define XGATE_Z_BIT 0x04 /* XGZ - Zero Flag */ -#define XGATE_V_BIT 0x02 /* XGV - Overflow Flag */ -#define XGATE_C_BIT 0x01 /* XGC - Carry Flag */ - -/* Access Detail Notation - V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle - P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle - r — 8-bit data read: lasts for at least one RISC core cycle - R — 16-bit data read: lasts for at least one RISC core cycle - w — 8-bit data write: lasts for at least one RISC core cycle - W — 16-bit data write: lasts for at least one RISC core cycle - A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles - f — Free cycle: no read or write, lasts for one RISC core cycles. */ -#define XGATE_CYCLE_V 0x01 -#define XGATE_CYCLE_P 0x02 -#define XGATE_CYCLE_r 0x04 -#define XGATE_CYCLE_R 0x08 -#define XGATE_CYCLE_w 0x10 -#define XGATE_CYCLE_W 0x20 -#define XGATE_CYCLE_A 0x40 -#define XGATE_CYCLE_f 0x80 - -/* Opcode format abbreviations. */ -#define XG_INH 0x0001 /* Inherent. */ -#define XG_I 0x0002 /* 3-bit immediate address. */ -#define XG_R_I 0x0004 /* Register followed by 4/8-bit immediate value. */ -#define XG_R_R 0x0008 /* Register followed by a register. */ -#define XG_R_R_R 0x0010 /* Register followed by two registers. */ -#define XG_R 0x0020 /* Single register. */ -#define XG_PC 0x0040 /* PC relative 10 or 11 bit. */ -#define XG_R_C 0x0080 /* General register followed by ccr register. */ -#define XG_C_R 0x0100 /* CCR register followed by a general register. */ -#define XG_R_P 0x0200 /* General register followed by pc register. */ -#define XG_R_R_I 0x0400 /* Two general registers followed by an immediate value. */ -#define XG_PCREL 0x0800 /* Immediate value that is relative to the current pc. */ - -/* XGATE operand formats as stored in the XGATE_opcode table. - They are only used by GAS to recognize operands. */ -#define XGATE_OP_INH "" -#define XGATE_OP_TRI "r,r,r" -#define XGATE_OP_DYA "r,r" -#define XGATE_OP_IMM16 "r,if" -#define XGATE_OP_IMM8 "r,i8" -#define XGATE_OP_IMM4 "r,i4" -#define XGATE_OP_IMM3 "i3" -#define XGATE_OP_MON "r" -#define XGATE_OP_MON_R_C "r,c" -#define XGATE_OP_MON_C_R "c,r" -#define XGATE_OP_MON_R_P "r,p" -#define XGATE_OP_IDR "r,r,+" -#define XGATE_OP_IDO5 "r,r,i5" -#define XGATE_OP_REL9 "b9" -#define XGATE_OP_REL10 "ba" -#define XGATE_OP_DYA_MON "=r" -/* Macro definitions. */ -#define XGATE_OP_IMM16mADD "r,if; addl addh" -#define XGATE_OP_IMM16mAND "r,if; andl andh" -#define XGATE_OP_IMM16mCPC "r,if; cmpl cpch" -#define XGATE_OP_IMM16mSUB "r,if; subl subh" -#define XGATE_OP_IMM16mLDW "r,if; ldl ldh" - -/* CPU variant identification. */ -#define XGATE_V1 0x1 -#define XGATE_V2 0x2 -#define XGATE_V3 0x4 - -/* Max opcodes per opcode handle. */ -#define MAX_OPCODES 0x05 - -#define MAX_DETECT_CHARS 0x10 - -/* The opcode table definitions. */ -struct xgate_opcode -{ - char * name; /* Op-code name. */ - char * constraints; /* Constraint chars. */ - char * format; /* Bit definitions. */ - unsigned int sh_format; /* Shorthand format mask. */ - unsigned int size; /* Opcode size in bytes. */ - unsigned int bin_opcode; /* Binary opcode with operands masked off. */ - unsigned char cycles_min; /* Minimum cpu cycles needed. */ - unsigned char cycles_max; /* Maximum cpu cycles needed. */ - unsigned char set_flags_mask; /* CCR flags set. */ - unsigned char clr_flags_mask; /* CCR flags cleared. */ - unsigned char chg_flags_mask; /* CCR flags changed. */ - unsigned char arch; /* CPU variant. */ -}; - -/* The opcode table. The table contains all the opcodes (all pages). - You can't rely on the order. */ -extern const struct xgate_opcode xgate_opcodes[]; -extern const int xgate_num_opcodes; - -#endif /* _OPCODE_XGATE_H */ |