diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 60 | ||||
| -rw-r--r-- | include/opcode/hppa.h | 71 | ||||
| -rw-r--r-- | include/opcode/i386.h | 461 | ||||
| -rw-r--r-- | include/opcode/m68k.h | 33 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 3 |
5 files changed, 423 insertions, 205 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 79bc3cc7c..cb8d1b854 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,63 @@ +1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. + +Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (struct pa_opcode): Add new field "flags". + (FLAGS_STRICT): Define. + +Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. + + * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. + +1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, + lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP + flag to fcomi and friends. + +Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Move integer arithmetic instructions after + integer logical instructions. + +1999-05-28 Linus Nordberg <linus.nordberg@canit.se> + + * m68k.h: Document new formats `E', `G', `H' and new places `N', + `n', `o'. + + * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' + and new places `m', `M', `h'. + +Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com + + * hppa.h (pa_opcodes): Add several processor specific system + instructions. + +Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + "addb", and "addib" to be used by the disassembler. + +1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> + + * i386.h (ReverseModrm): Remove all occurences. + (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, + movmskps, pextrw, pmovmskb, maskmovq. + Change NoSuf to FP on all MMX, XMM and AMD insns as these all + ignore the data size prefix. + + * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. + Mostly stolen from Doug Ledford <dledford@redhat.com> + +Sat May 8 23:27:35 1999 Richard Henderson <rth@cygnus.com> + + * ppc.h (PPC_OPCODE_64_BRIDGE): New. + 1999-04-14 Doug Evans <devans@casey.cygnus.com> * cgen.h (CGEN_ATTR): Delete member num_nonbools. diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h index 30ccb6ccf..f454be11b 100644 --- a/include/opcode/hppa.h +++ b/include/opcode/hppa.h @@ -43,8 +43,12 @@ struct pa_opcode unsigned long int mask; /* ... in these bits. */ char *args; enum pa_arch arch; + char flags; }; +/* Enable/disable strict syntax checking. Not currently used, but will + be necessary for PA2.0 support in the future. */ +#define FLAG_STRICT 0x1 /* All hppa opcodes are 32 bits. @@ -184,9 +188,21 @@ static const struct pa_opcode pa_opcodes[] = { "b", 0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */ { "ldi", 0x34000000, 0xffe0c000, "j,x", pa10}, /* ldo val(r0),r */ { "comib", 0x84000000, 0xfc000000, "?n5,b,w", pa10}, /* comib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comib", 0x8c000000, 0xfc000000, "?n5,b,w", pa10}, /* comib{tf}*/ { "comb", 0x80000000, 0xfc000000, "?nx,b,w", pa10}, /* comb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comb", 0x88000000, 0xfc000000, "?nx,b,w", pa10}, /* comb{tf} */ { "addb", 0xa0000000, 0xfc000000, "@nx,b,w", pa10}, /* addb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addb", 0xa8000000, 0xfc000000, "@nx,b,w", pa10}, { "addib", 0xa4000000, 0xfc000000, "@n5,b,w", pa10}, /* addib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addib", 0xac000000, 0xfc000000, "@n5,b,w", pa10}, /* addib{tf}*/ { "nop", 0x08000240, 0xffffffff, "", pa10}, /* or 0,0,0 */ { "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10}, /* or r,0,t */ { "mtsar", 0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */ @@ -261,30 +277,10 @@ static const struct pa_opcode pa_opcodes[] = { "addibf", 0xac000000, 0xfc000000, "!n5,b,w", pa10}, { "bb", 0xc4004000, 0xfc004000, "~nx,Q,w", pa10}, { "bvb", 0xc0004000, 0xffe04000, "~nx,w", pa10}, +{ "clrbts", 0xe8004005, 0xffffffff, "", pa20}, /* Computation Instructions */ -{ "add", 0x08000600, 0xfc000fe0, "dx,b,t", pa10}, -{ "addl", 0x08000a00, 0xfc000fe0, "dx,b,t", pa10}, -{ "addo", 0x08000e00, 0xfc000fe0, "dx,b,t", pa10}, -{ "addc", 0x08000700, 0xfc000fe0, "dx,b,t", pa10}, -{ "addco", 0x08000f00, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1add", 0x08000640, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1addl", 0x08000a40, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1addo", 0x08000e40, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2add", 0x08000680, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2addl", 0x08000a80, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2addo", 0x08000e80, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3add", 0x080006c0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3addl", 0x08000ac0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3addo", 0x08000ec0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sub", 0x08000400, 0xfc000fe0, "ax,b,t", pa10}, -{ "subo", 0x08000c00, 0xfc000fe0, "ax,b,t", pa10}, -{ "subb", 0x08000500, 0xfc000fe0, "ax,b,t", pa10}, -{ "subbo", 0x08000d00, 0xfc000fe0, "ax,b,t", pa10}, -{ "subt", 0x080004c0, 0xfc000fe0, "ax,b,t", pa10}, -{ "subto", 0x08000cc0, 0xfc000fe0, "ax,b,t", pa10}, -{ "ds", 0x08000440, 0xfc000fe0, "ax,b,t", pa10}, { "comclr", 0x08000880, 0xfc000fe0, "ax,b,t", pa10}, { "or", 0x08000240, 0xfc000fe0, "&x,b,t", pa10}, { "xor", 0x08000280, 0xfc000fe0, "&x,b,t", pa10}, @@ -299,9 +295,30 @@ static const struct pa_opcode pa_opcodes[] = { "addio", 0xb4000800, 0xfc000800, "di,b,x", pa10}, { "addit", 0xb0000000, 0xfc000800, "di,b,x", pa10}, { "addito", 0xb0000800, 0xfc000800, "di,b,x", pa10}, +{ "add", 0x08000600, 0xfc000fe0, "dx,b,t", pa10}, +{ "addl", 0x08000a00, 0xfc000fe0, "dx,b,t", pa10}, +{ "addo", 0x08000e00, 0xfc000fe0, "dx,b,t", pa10}, +{ "addc", 0x08000700, 0xfc000fe0, "dx,b,t", pa10}, +{ "addco", 0x08000f00, 0xfc000fe0, "dx,b,t", pa10}, +{ "sub", 0x08000400, 0xfc000fe0, "ax,b,t", pa10}, +{ "subo", 0x08000c00, 0xfc000fe0, "ax,b,t", pa10}, +{ "subb", 0x08000500, 0xfc000fe0, "ax,b,t", pa10}, +{ "subbo", 0x08000d00, 0xfc000fe0, "ax,b,t", pa10}, +{ "subt", 0x080004c0, 0xfc000fe0, "ax,b,t", pa10}, +{ "subto", 0x08000cc0, 0xfc000fe0, "ax,b,t", pa10}, +{ "ds", 0x08000440, 0xfc000fe0, "ax,b,t", pa10}, { "subi", 0x94000000, 0xfc000800, "ai,b,x", pa10}, { "subio", 0x94000800, 0xfc000800, "ai,b,x", pa10}, { "comiclr", 0x90000000, 0xfc000800, "ai,b,x", pa10}, +{ "sh1add", 0x08000640, 0xfc000fe0, "dx,b,t", pa10}, +{ "sh1addl", 0x08000a40, 0xfc000fe0, "dx,b,t", pa10}, +{ "sh1addo", 0x08000e40, 0xfc000fe0, "dx,b,t", pa10}, +{ "sh2add", 0x08000680, 0xfc000fe0, "dx,b,t", pa10}, +{ "sh2addl", 0x08000a80, 0xfc000fe0, "dx,b,t", pa10}, +{ "sh2addo", 0x08000e80, 0xfc000fe0, "dx,b,t", pa10}, +{ "sh3add", 0x080006c0, 0xfc000fe0, "dx,b,t", pa10}, +{ "sh3addl", 0x08000ac0, 0xfc000fe0, "dx,b,t", pa10}, +{ "sh3addo", 0x08000ec0, 0xfc000fe0, "dx,b,t", pa10}, /* Extract and Deposit Instructions */ @@ -332,6 +349,8 @@ static const struct pa_opcode pa_opcodes[] = { "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10}, { "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10}, { "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10}, +{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20}, +{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20}, { "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10}, { "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10}, { "sync", 0x00000400, 0xffffffff, "", pa10}, @@ -378,6 +397,16 @@ static const struct pa_opcode pa_opcodes[] = { "fice", 0x040002c0, 0xfc001fdf, "Zx(b)", pa10}, { "diag", 0x14000000, 0xfc000000, "D", pa10}, +/* These may be specific to certain versions of the PA. Joel claimed + they were 72000 (7200?) specific. However, I'm almost certain the + mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^"}, +{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x"}, +{ "tocen", 0x14403600, 0xffffffff, ""}, +{ "tocdis", 0x14401620, 0xffffffff, ""}, +{ "shdwgr", 0x14402600, 0xffffffff, ""}, +{ "grshdw", 0x14400620, 0xffffffff, ""}, + /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either the Timex FPU or the Mustang ERS (not sure which) manual. */ { "gfw", 0x04001680, 0xfc003fdf, "Zx(s,b)", pa11}, diff --git a/include/opcode/i386.h b/include/opcode/i386.h index ef8fece15..e7e78c8ea 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -42,7 +42,6 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static const template i386_optab[] = { #define X None -#define ReverseModrm (ReverseRegRegmem|Modrm) #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) @@ -84,43 +83,43 @@ static const template i386_optab[] = { { "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, { "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } }, /* move to/from control debug registers */ -{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32, 0} }, -{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32, 0} }, -{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32, 0} }, +{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, /* move with sign extend */ /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid conflict with the "movs" string move instruction. */ -{"movsbl", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg32, 0} }, -{"movsbw", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg16, 0} }, -{"movswl", 2, 0x0fbf, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} }, +{"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, +{"movsbw", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, +{"movswl", 2, 0x0fbf, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, /* Intel Syntax */ -{"movsx", 2, 0x0fbf, X, w_Suf|ReverseModrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, -{"movsx", 2, 0x0fbe, X, b_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, +{"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, /* move with zero extend */ -{"movzb", 2, 0x0fb6, X, wl_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzwl", 2, 0x0fb7, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} }, +{"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, /* Intel Syntax */ -{"movzx", 2, 0x0fb7, X, w_Suf|ReverseModrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, -{"movzx", 2, 0x0fb6, X, b_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, /* push instructions */ -{"push", 1, 0x50, X, wl_Suf|ShortForm, { WordReg,0,0 } }, +{"push", 1, 0x50, X, wl_Suf|ShortForm, { WordReg, 0, 0 } }, {"push", 1, 0xff, 6, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } }, {"push", 1, 0x6a, X, wl_Suf, { Imm8S, 0, 0} }, {"push", 1, 0x68, X, wl_Suf, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } }, -{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } }, +{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm, { SReg2, 0, 0 } }, +{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm, { SReg3, 0, 0 } }, /* push all */ {"pusha", 0, 0x60, X, wl_Suf, { 0, 0, 0 } }, /* pop instructions */ -{"pop", 1, 0x58, X, wl_Suf|ShortForm, { WordReg,0,0 } }, +{"pop", 1, 0x58, X, wl_Suf|ShortForm, { WordReg, 0, 0 } }, {"pop", 1, 0x8f, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } }, #define POP_SEG_SHORT 0x07 -{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } }, -{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } }, +{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm, { SReg2, 0, 0 } }, +{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm, { SReg3, 0, 0 } }, /* pop all */ {"popa", 0, 0x61, X, wl_Suf, { 0, 0, 0 } }, @@ -250,9 +249,9 @@ static const template i386_optab[] = { These multiplies can only be selected with single operand forms. */ {"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, {"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 2, 0x0faf, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"imul", 3, 0x6b, X, wl_Suf|ReverseModrm, { Imm8S, WordReg|WordMem, WordReg} }, -{"imul", 3, 0x69, X, wl_Suf|ReverseModrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, +{"imul", 2, 0x0faf, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"imul", 3, 0x6b, X, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, +{"imul", 3, 0x69, X, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, /* imul with 2 operands mimics imul with 3 by putting the register in both i.rm.reg & i.rm.regmem fields. regKludge enables this transformation. */ @@ -315,7 +314,7 @@ static const template i386_optab[] = { {"call", 1, 0xe8, X, wl_Suf|JumpDword, { Disp16|Disp32, 0, 0} }, {"call", 1, 0xff, 2, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, {"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, {"lcall", 1, 0xff, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, @@ -323,8 +322,8 @@ static const template i386_optab[] = { {"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} }, {"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"jmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +{"jmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} }, {"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, {"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} }, @@ -448,8 +447,8 @@ static const template i386_optab[] = { {"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} }, /* bit manipulation */ -{"bsf", 2, 0x0fbc, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"bsr", 2, 0x0fbd, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, +{"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, {"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, {"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, @@ -478,23 +477,23 @@ static const template i386_optab[] = { {"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} }, /* protection control */ -{"arpl", 2, 0x63, X, NoSuf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, -{"lar", 2, 0x0f02, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, +{"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, +{"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} }, {"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lldt", 1, 0x0f00, 2, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lmsw", 1, 0x0f01, 6, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lsl", 2, 0x0f03, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"ltr", 1, 0x0f00, 3, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} }, {"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, {"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"str", 1, 0x0f00, 1, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verr", 1, 0x0f00, 4, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verw", 1, 0x0f00, 5, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, /* floating point instructions */ @@ -767,7 +766,7 @@ static const template i386_optab[] = { /* 486 extensions */ -{"bswap", 1, 0x0fc8, X, NoSuf|ShortForm, { Reg32,0,0 } }, +{"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } }, {"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} }, @@ -782,10 +781,10 @@ static const template i386_optab[] = { {"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} }, {"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} }, {"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} }, -{"sysenter", 0, 0x0f34, X, NoSuf, { 0, 0, 0} }, -{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, +{"sysenter",0, 0x0f34, X, NoSuf, { 0, 0, 0} }, +{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, +{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, /* Pentium Pro extensions */ {"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} }, @@ -794,154 +793,244 @@ static const template i386_optab[] = { {"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* alias for ud2 */ {"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, /* 2nd. official undefined instr. */ -{"cmovo", 2, 0x0f40, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovno", 2, 0x0f41, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovb", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovc", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnae", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovae", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnc", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnb", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmove", 2, 0x0f44, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovz", 2, 0x0f44, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovne", 2, 0x0f45, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnz", 2, 0x0f45, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovbe", 2, 0x0f46, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovna", 2, 0x0f46, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmova", 2, 0x0f47, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnbe", 2, 0x0f47, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovs", 2, 0x0f48, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovns", 2, 0x0f49, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovp", 2, 0x0f4a, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnp", 2, 0x0f4b, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovl", 2, 0x0f4c, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnge", 2, 0x0f4c, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovge", 2, 0x0f4d, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnl", 2, 0x0f4d, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovle", 2, 0x0f4e, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovng", 2, 0x0f4e, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovg", 2, 0x0f4f, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnle", 2, 0x0f4f, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, - -{"fcmovb", 2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnae",2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmove", 2, 0xdac8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovbe", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovna", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovu", 2, 0xdad8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovae", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnb", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovne", 2, 0xdbc8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmova", 2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnbe",2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnu", 2, 0xdbd8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, - -{"fcomi", 2, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcomi", 0, 0xdbf1, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fcomi", 1, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fucomi", 2, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomi", 0, 0xdbe9, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fucomi", 1, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fcomip", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 0, 0xdff1, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fcompi", 1, 0xdff0, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fucomip", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 0, 0xdfe9, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fucompi", 1, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, +{"cmovo", 2, 0x0f40, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovno", 2, 0x0f41, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovb", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovc", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovae", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnc", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnb", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmove", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovz", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovne", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnz", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovbe", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovna", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmova", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovs", 2, 0x0f48, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovns", 2, 0x0f49, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovp", 2, 0x0f4a, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnp", 2, 0x0f4b, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovl", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovge", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnl", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovle", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovng", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, + +{"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, + +{"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} }, +{"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} }, +{"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} }, +{"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} }, +{"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} }, /* MMX instructions. */ -{"emms", 0, 0x0f77, X, NoSuf, { 0, 0, 0 } }, -{"movd", 2, 0x0f6e, X, NoSuf|Modrm, { Reg32|LongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, NoSuf|Modrm, { RegMMX, Reg32|LongMem, 0 } }, -{"movq", 2, 0x0f6f, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, NoSuf|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, -{"packssdw", 2, 0x0f6b, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packsswb", 2, 0x0f63, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packuswb", 2, 0x0f67, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddb", 2, 0x0ffc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddw", 2, 0x0ffd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddd", 2, 0x0ffe, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsb", 2, 0x0fec, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsw", 2, 0x0fed, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusb", 2, 0x0fdc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusw", 2, 0x0fdd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pand", 2, 0x0fdb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pandn", 2, 0x0fdf, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x0f74, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x0f75, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x0f76, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x0f64, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x0f65, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x0f66, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x0ff5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x0fe5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmullw", 2, 0x0fd5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"por", 2, 0x0feb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x0ff1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x0f71, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x0ff2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pslld", 2, 0x0f72, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x0ff3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllq", 2, 0x0f73, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x0fe1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psraw", 2, 0x0f71, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x0fe2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrad", 2, 0x0f72, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x0fd1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlw", 2, 0x0f71, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x0fd2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrld", 2, 0x0f72, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x0fd3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlq", 2, 0x0f73, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psubb", 2, 0x0ff8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubw", 2, 0x0ff9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubd", 2, 0x0ffa, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsb", 2, 0x0fe8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsw", 2, 0x0fe9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusb", 2, 0x0fd8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusw", 2, 0x0fd9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhbw",2, 0x0f68, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhwd",2, 0x0f69, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhdq",2, 0x0f6a, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklbw",2, 0x0f60, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklwd",2, 0x0f61, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckldq",2, 0x0f62, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pxor", 2, 0x0fef, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, - - +{"emms", 0, 0x0f77, X, FP, { 0, 0, 0 } }, +{"movd", 2, 0x0f6e, X, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, +{"movq", 2, 0x0f6f, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7f, X, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, +{"packssdw", 2, 0x0f6b, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packsswb", 2, 0x0f63, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packuswb", 2, 0x0f67, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddb", 2, 0x0ffc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddw", 2, 0x0ffd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddd", 2, 0x0ffe, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsb", 2, 0x0fec, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsw", 2, 0x0fed, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusb", 2, 0x0fdc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusw", 2, 0x0fdd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pand", 2, 0x0fdb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pandn", 2, 0x0fdf, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqb", 2, 0x0f74, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqw", 2, 0x0f75, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqd", 2, 0x0f76, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtb", 2, 0x0f64, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtw", 2, 0x0f65, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtd", 2, 0x0f66, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmaddwd", 2, 0x0ff5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhw", 2, 0x0fe5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmullw", 2, 0x0fd5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"por", 2, 0x0feb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x0ff1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x0f71, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"pslld", 2, 0x0ff2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pslld", 2, 0x0f72, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psllq", 2, 0x0ff3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllq", 2, 0x0f73, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psraw", 2, 0x0fe1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psraw", 2, 0x0f71, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrad", 2, 0x0fe2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrad", 2, 0x0f72, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlw", 2, 0x0fd1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlw", 2, 0x0f71, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrld", 2, 0x0fd2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrld", 2, 0x0f72, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlq", 2, 0x0fd3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlq", 2, 0x0f73, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psubb", 2, 0x0ff8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubw", 2, 0x0ff9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubd", 2, 0x0ffa, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsb", 2, 0x0fe8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsw", 2, 0x0fe9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusb", 2, 0x0fd8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusw", 2, 0x0fd9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhbw",2, 0x0f68, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhwd",2, 0x0f69, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhdq",2, 0x0f6a, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklbw",2, 0x0f60, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklwd",2, 0x0f61, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckldq",2, 0x0f62, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, + + +/* PIII Katmai New Instructions / SIMD instructions */ + +{"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"andnps", 2, 0x0f55, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andps", 2, 0x0f54, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpps", 3, 0x0fc2, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"cmpss", 3, 0xf30fc2, X, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, +{"cmpeqps", 2, 0x0fc2, 0, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqss", 2, 0xf30fc2, 0, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpltps", 2, 0x0fc2, 1, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltss", 2, 0xf30fc2, 1, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpleps", 2, 0x0fc2, 2, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpless", 2, 0xf30fc2, 2, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpunordps",2, 0x0fc2, 3, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordss",2, 0xf30fc2, 3, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpneqps", 2, 0x0fc2, 4, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqss", 2, 0xf30fc2, 4, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnltps", 2, 0x0fc2, 5, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltss", 2, 0xf30fc2, 5, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnleps", 2, 0x0fc2, 6, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnless", 2, 0xf30fc2, 6, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpordps", 2, 0x0fc2, 7, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordss", 2, 0xf30fc2, 7, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"comiss", 2, 0x0f2f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cvtpi2ps", 2, 0x0f2a, X, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtsi2ss", 2, 0xf30f2a, X, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } }, +{"cvtps2pi", 2, 0x0f2d, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtss2si", 2, 0xf30f2d, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"cvttps2pi", 2, 0x0f2c, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttss2si", 2, 0xf30f2c, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"divps", 2, 0x0f5e, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divss", 2, 0xf30f5e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ldmxcsr", 1, 0x0fae, 2, FP|Modrm, { WordMem, 0, 0 } }, +{"stmxcsr", 1, 0x0fae, 3, FP|Modrm, { WordMem, 0, 0 } }, +{"sfence", 0, 0x0faef8, X, FP, { 0, 0, 0 } }, +{"maxps", 2, 0x0f5f, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxss", 2, 0xf30f5f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"minps", 2, 0x0f5d, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minss", 2, 0xf30f5d, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f28, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f29, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhlps", 2, 0x0f12, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f16, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f17, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlhps", 2, 0x0f16, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f12, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f13, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movmskps", 2, 0x0f50, X, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"movups", 2, 0x0f10, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movups", 2, 0x0f11, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movss", 2, 0xf30f10, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movss", 2, 0xf30f11, X, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, +{"mulps", 2, 0x0f59, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulss", 2, 0xf30f59, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"orps", 2, 0x0f56, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rcpps", 2, 0x0f53, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rcpss", 2, 0xf30f53, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"rsqrtps", 2, 0x0f52, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rsqrtss", 2, 0xf30f52, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"shufps", 3, 0x0fc6, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtps", 2, 0x0f51, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtss", 2, 0xf30f51, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"subps", 2, 0x0f5c, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subss", 2, 0xf30f5c, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ucomiss", 2, 0x0f2e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"unpckhps", 2, 0x0f15, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgb", 2, 0x0fe0, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgw", 2, 0x0fe3, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pextrw", 3, 0x0fc5, X, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, +{"pinsrw", 3, 0x0fc4, X, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, +{"pmaxsw", 2, 0x0fee, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxub", 2, 0x0fde, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminsw", 2, 0x0fea, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminub", 2, 0x0fda, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmovmskb", 2, 0x0fd7, X, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, +{"pmulhuw", 2, 0x0fe4, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"psadbw", 2, 0x0ff6, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pshufw", 3, 0x0f70, X, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, +{"maskmovq", 2, 0x0ff7, X, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, +{"movntps", 2, 0x0f2b, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movntq", 2, 0x0fe7, X, FP|Modrm, { RegMMX, LLongMem, 0 } }, +{"prefetchnta", 1, 0x0f18, 0, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht0", 1, 0x0f18, 1, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht1", 1, 0x0f18, 2, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht2", 1, 0x0f18, 3, FP|Modrm, { LLongMem, 0, 0 } }, + /* AMD 3DNow! instructions */ -#define AMD_3DNOW_OPCODE 0x0f0f - -{"prefetch", 1, 0x0f0d, 0, NoSuf|Modrm, { ByteMem, 0, 0 } }, -{"prefetchw",1, 0x0f0d, 1, NoSuf|Modrm, { ByteMem, 0, 0 } }, -{"femms", 0, 0x0f0e, X, NoSuf, { 0, 0, 0 } }, -{"pavgusb", 2, 0x0f0f, 0xbf, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2id", 2, 0x0f0f, 0x1d, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfacc", 2, 0x0f0f, 0xae, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfadd", 2, 0x0f0f, 0x9e, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpeq", 2, 0x0f0f, 0xb0, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpge", 2, 0x0f0f, 0x90, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpgt", 2, 0x0f0f, 0xa0, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmax", 2, 0x0f0f, 0xa4, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmin", 2, 0x0f0f, 0x94, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmul", 2, 0x0f0f, 0xb4, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcp", 2, 0x0f0f, 0x96, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit1", 2, 0x0f0f, 0xa6, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit2", 2, 0x0f0f, 0xb6, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqit1", 2, 0x0f0f, 0xa7, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqrt", 2, 0x0f0f, 0x97, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsub", 2, 0x0f0f, 0x9a, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsubr", 2, 0x0f0f, 0xaa, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fd", 2, 0x0f0f, 0x0d, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhrw", 2, 0x0f0f, 0xb7, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, + +{"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } }, +{"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } }, +{"femms", 0, 0x0f0e, X, FP, { 0, 0, 0 } }, +{"pavgusb", 2, 0x0f0f, 0xbf, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2id", 2, 0x0f0f, 0x1d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2iw", 2, 0x0f0f, 0x1c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Unofficial! See http://www.x86.org/articles/3dnow/amd_3dnow.html */ +{"pfacc", 2, 0x0f0f, 0xae, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfadd", 2, 0x0f0f, 0x9e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpeq", 2, 0x0f0f, 0xb0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpge", 2, 0x0f0f, 0x90, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpgt", 2, 0x0f0f, 0xa0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmax", 2, 0x0f0f, 0xa4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmin", 2, 0x0f0f, 0x94, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmul", 2, 0x0f0f, 0xb4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcp", 2, 0x0f0f, 0x96, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqrt", 2, 0x0f0f, 0x97, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsub", 2, 0x0f0f, 0x9a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsubr", 2, 0x0f0f, 0xaa, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fd", 2, 0x0f0f, 0x0d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fw", 2, 0x0f0f, 0x0c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Unofficial! */ +{"pmulhrw", 2, 0x0f0f, 0xb7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pswapw", 2, 0x0f0f, 0xbb, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Unofficial! */ {NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ }; #undef X -#undef ReverseModrm #undef NoSuf #undef b_Suf #undef w_Suf @@ -1047,7 +1136,15 @@ static const reg_entry i386_regtab[] = { {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, {"mm6", RegMMX, 6}, - {"mm7", RegMMX, 7} + {"mm7", RegMMX, 7}, + {"xmm0", RegXMM, 0}, + {"xmm1", RegXMM, 1}, + {"xmm2", RegXMM, 2}, + {"xmm3", RegXMM, 3}, + {"xmm4", RegXMM, 4}, + {"xmm5", RegXMM, 5}, + {"xmm6", RegXMM, 6}, + {"xmm7", RegXMM, 7} }; #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h index ecb3f95dd..3208b77f4 100644 --- a/include/opcode/m68k.h +++ b/include/opcode/m68k.h @@ -1,5 +1,5 @@ /* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. + Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1999 Free Software Foundation. This file is part of GDB, GAS, and the GNU binutils. @@ -36,6 +36,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define m68851 0x080 #define cpu32 0x100 /* e.g., 68332 */ #define mcf5200 0x200 +#define mcf5206e 0x400 +#define mcf5307 0x800 /* handy aliases */ #define m68040up (m68040 | m68060) @@ -43,6 +45,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define m68020up (m68020 | m68030up) #define m68010up (m68010 | cpu32 | m68020up) #define m68000up (m68000 | m68010up) +#define mcf (mcf5200 | mcf5206e | mcf5307) #define mfloat (m68881 | m68882 | m68040 | m68060) #define mmmu (m68851 | m68030 | m68040 | m68060) @@ -87,7 +90,7 @@ struct m68k_opcode_alias operand; the second, the place it is stored. */ /* Kinds of operands: - Characters used: AaBCcDdFfIJkLlMmnOopQqRrSsTtUVvWXYZ0123|*~%;@!&$?/<>#^+- + Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+- D data register only. Stored as 3 bits. A address register only. Stored as 3 bits. @@ -121,6 +124,9 @@ struct m68k_opcode_alias C the CCR. No need to store it; this is just for filtering validity. S the SR. No need to store, just as with CCR. U the USP. No need to store, just as with CCR. + E the ACC. No need to store, just as with CCR. + G the MACSR. No need to store, just as with CCR. + H the MASK. No need to store, just as with CCR. I Coprocessor ID. Not printed if 1. The Coprocessor ID is always extracted from the 'd' field of word one, which means that an extended @@ -170,6 +176,9 @@ struct m68k_opcode_alias for both caches. Used in cinv and cpush. Always stored in position "d". + u Any register, with ``upper'' or ``lower'' specification. Used + in the mac instructions with size word. + The remainder are all stored as 6 bits using an address mode and a register number; they differ in which addressing modes they match. @@ -260,6 +269,8 @@ struct m68k_opcode_alias */ /* Places to put an operand, for non-general operands: + Characters used: BbCcDdghijkLlMmNnostWw123456789 + s source, low bits of first word. d dest, shifted 9 in first word 1 second word, shifted 12 @@ -293,6 +304,24 @@ struct m68k_opcode_alias C floating point coprocessor constant - 7 bits. Also used for static K-factors... j Movec register #, stored in 12 low bits of second word. + m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word + and remaining 3 bits of register shifted 9 bits in first word. + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split + with MSB shifted 6 bits in first word and remaining 3 bits of + register shifted 9 bits in first word. No upper/lower + indication is done.) Use with `R' or `u' format. + o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + M For M[S]ACw; 4 bits in low bits of first word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + N For M[S]ACw; 4 bits in low bits of second word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + h shift indicator (scale factor), 1 bit shifted 10 in second word Places to put operand, for general operands: d destination, shifted 6 bits in first word diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index a9e3b24ab..974f0dfa5 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -85,6 +85,9 @@ extern const int powerpc_num_opcodes; for the assembler's -many option, and it eliminates duplicates). */ #define PPC_OPCODE_ANY (0200) +/* Opcode is supported as part of the 64-bit bridge. */ +#define PPC_OPCODE_64_BRIDGE (0400) + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) |