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diff --git a/include/COPYING b/include/COPYING new file mode 100644 index 000000000..d60c31a97 --- /dev/null +++ b/include/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/include/ChangeLog b/include/ChangeLog new file mode 100644 index 000000000..b6c11568f --- /dev/null +++ b/include/ChangeLog @@ -0,0 +1,144 @@ +2004-09-17 Paul Brook <paul@codesourcery.com> + + * elf/arm.h: Remove R_ARM_STKCHK and R_ARM_THM_STKCHK. + Add R_ARM_TARGET2, R_ARM_PREL31, R_ARM_GOT_ABS, R_ARM_GOT_PREL, + R_ARM_GOT_BREL12, R_ARM_GOTOFF12 and R_ARM_GOTRELAX. + +2004-09-17 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_hash_entry): Move und_next into elements + of union. + +2004-09-13 Aaron W. LaFramboise <aaronavay62@aaronwl.com> + + * libiberty.h (basename): Prototype for __MINGW32__. + +2004-09-13 Paul Brook <paul@codesourcery.com> + + * elf/arm.h: Rename RELABS to TARGET1. + +2004-09-04 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (ATTRIBUTE_SENTINEL): Define. + * libiberty.h (concat, reconcat, concat_length, concat_copy, + concat_copy2): Use ATTRIBUTE_SENTINEL. + +2004-08-13 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_callbacks): Remove "error_handler". + (LD_DEFINITION_IN_DISCARDED_SECTION): Delete. + +2004-08-02 Gabriel Dos Reis <gdr@integrable-solutions.net> + + * libiberty.h (XDELETE, XDELETEVEC, XRESIZEVEC): Remove any + const-qualification before disposal. + +2004-07-24 Bernardo Innocenti <bernie@develer.com> + + * ansidecl.h (ARG_UNUSED): New Macro. + +2004-07-23 H.J. Lu <hongjiu.lu@intel.com> + + * bin-bugs.h (REPORT_BUGS_TO): Set to + "<URL:http://www.sourceware.org/bugzilla/>". + +2004-07-21 Paolo Bonzini <bonzini@gnu.org> + + * ansidecl.h (ATTRIBUTE_PURE): New. + +2004-07-13 Bernardo Innocenti <bernie@develer.com> + + * libiberty.h (XNEW, XCNEW, XNEWVEC, XCNEWVEC, XOBNEW): Move here from + libcpp/internal.h. + (XDELETE, XRESIZEVEC, XDELETEVEC, XNEWVAR, XCNEWVAR, XRESIZEVAR): New + macros. + +2004-07-13 Bernardo Innocenti <bernie@develer.com> + + * libiberty.h (ASTRDUP): Add casts required for stricter + type conversion rules of C++. + * obstack.h (obstack_free): Likewise. + +2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> + + * dis-asm.h (print_insn_crx): Declare. + +2004-06-24 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_order): Update comment. + +2004-05-11 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add relro, relro_start and + relro_end fields. + * elf/common.h (PT_GNU_EH_FRAME, PT_GNU_STACK): Add comments. + (PT_GNU_RELRO): Define. + +2004-05-04 Andreas Jaeger <aj@suse.de> + + * demangle.h: Do not use C++ reserved keyword typename as + parameter for cplus_demangle_fill_builtin_type. + +2004-04-22 Richard Henderson <rth@redhat.com> + + * hashtab.h (struct htab): Add size_prime_index. + +2004-04-13 Jeff Law <law@redhat.com> + + * hashtab.h (htab_remove_elt_with_hash): Prototype new function. + +2004-03-30 Zack Weinberg <zack@codesourcery.com> + + * hashtab.h, splay-tree.h: Use new shorter form of GTY markers. + +2004-03-25 Stan Shebs <shebs@apple.com> + + * mpw/: Remove subdirectory and everything in it. + +2004-03-23 Alan Modra <amodra@bigpond.net.au> + + PR 51. + * bfdlink.h (struct bfd_link_info): Add wrap_char. + +2004-03-20 H.J. Lu <hongjiu.lu@intel.com> + + * bfdlink.h (bfd_link_info): Correct comments for the + unresolved_syms_in_objects field. + +2004-02-24 Ian Lance Taylor <ian@wasabisystems.com> + + * dyn-string.h: Update copyright date. + +2004-02-23 Ian Lance Taylor <ian@wasabisystems.com> + + * dyn-string.h: Remove test of IN_LIBGCC2 and IN_GLIBCPP_V3 and + the associated #defines. + +2004-01-12 Ian Lance Taylor <ian@wasabisystems.com> + + * demangle.h: Instead of checking ANSI_PROTOTYPES, just include + "libiberty.h". + + * demangle.h: If ANSI_PROTOTYPES is defined, include <stddef.h>. + + * demangle.h (enum demangle_component_type): Define. + (struct demangle_operator_info): Declare. + (struct demangle_builtin_type_info): Declare. + (struct demangle_component): Define. + (cplus_demangle_fill_component): Declare. + (cplus_demangle_fill_name): Declare. + (cplus_demangle_fill_builtin_type): Declare. + (cplus_demangle_fill_operator): Declare. + (cplus_demangle_fill_extended_operator): Declare. + (cplus_demangle_fill_ctor, cplus_demangle_fill_dtor): Declare. + (cplus_demangle_v3_components): Declare. + (cplus_demangle_print): Declare. + +For older changes see ChangeLog-9103 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/include/ChangeLog-9103 b/include/ChangeLog-9103 new file mode 100644 index 000000000..670fe38b3 --- /dev/null +++ b/include/ChangeLog-9103 @@ -0,0 +1,2737 @@ +2003-12-19 Andreas Tobler <a.tobler@schweiz.ch> + + * include/fibheap.h (fibnode): Use __extension__ for + bit-fields mark and degree if __GNUC__. + +2003-12-18 Kazu Hirata <kazu@cs.umass.edu> + + * include/fibheap.h (fibnode): Use unsigned long int for + bit-fields if __GNUC__ is defined. + +2003-12-04 H.J. Lu <hongjiu.lu@intel.com> + + * bfdlink.h (bfd_link_info): Change relax_finalizing to + need_relax_finalize. + +2003-12-03 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_hash_entry): Rename "next" to "und_next". + +2003-12-02 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_info): Remove mpc860c0 field. + +2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * opcode/mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB. + +2003-11-14 Nick Clifton <nickc@redhat.com> + + * dis-asm.h (struct disassemble_info): Add new field + 'symbol_is_valid' which is a function which can tell the + disassembler to skip certain symbols as they should not be + displayed to the user. + (arm_symbol_is_valid): New prototype. This is the ARM + specific function for the symbol_is_valid field. + (generic_symbol_is_valid): New prototype. This is the default + function pointed to by the symbol_is_valid field. + +2003-11-06 Bruno Rohee <bruno@rohee.com> + + * hp-symtab.h: Fix "the the" typo. + +2003-10-24 H.J. Lu <hongjiu.lu@intel.com> + + * bfdlink.h (bfd_elf_version_expr): Add "symbol" and remove + "wildcard". + +2003-10-22 Joseph S. Myers <jsm@polyomino.org.uk> + + * obstack.h: Merge the following change from gnulib: + 2003-10-21 Paul Eggert <eggert@twinsun.com> + * obstack.h (obstack_1grow_fast): Properly parenthesize arg. + (obstack_ptr_grow_fast, obstack_int_grow_fast): + Don't use lvalue casts, as GCC plans to remove support for them + in GCC 3.5. Reported by Joseph S. Myers. This bug + was also present in the non-GCC version, indicating that this + code had always been buggy and had never been widely used. + (obstack_1grow, obstack_ptr_grow, obstack_int_grow, obstack_blank): + Use the fast variant of each macro, rather than copying the + definiens of the fast variant; that way, we'll be more likely to + catch future bugs in the fast variants. + +2003-10-22 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_elf_version_expr): Remove match field. + Add wildcard and mask fields. + (BFD_ELF_VERSION_C_TYPE): Define. + (BFD_ELF_VERSION_CXX_TYPE): Likewise. + (BFD_ELF_VERSION_JAVA_TYPE): Likewise. + (struct bfd_elf_version_expr_head): New. + (struct bfd_elf_version_tree): Add match field. + Change type of globals and locals fields + to struct bfd_elf_version_expr_head. + +2003-10-14 Bob Wilson <bob.wilson@acm.org> + + * elf/xtensa.h: Formatting. Fix comments about property section + names for linkonce sections. + +2003-09-22 Andrew Cagney <cagney@redhat.com> + + * floatformat.h (struct floatformat): Add field "is_valid". + +2003-09-15 Andrew Cagney <cagney@redhat.com> + + * floatformat.h (floatformat_to_double): Make input buffer constant. + (floatformat_from_double, floatformat_is_valid): Ditto. + +2003-09-15 Andrew Cagney <cagney@redhat.com> + + * floatformat.h (struct floatformat): Make "exp_bias" signed. + +2003-09-15 Daniel Jacobowitz <drow@mvista.com> + + * floatformat.h (floatformat_is_valid): Add prototype. + +2003-08-27 Andrew Cagney <cagney@redhat.com> + + * dis-asm.h (init_disassemble_info): Declare. + (INIT_DISASSEMBLE_INFO): Redefine as a call to + init_disassemble_info. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Ditto. + +2003-08-20 Nick Clifton <nickc@redhat.com> + + * bfdlink.h (enum report_method): New enum. Describes how to + report something. + (struct bfd_link_info): Delete fields 'no_undefined' and + 'allow_shlib_undefined'. Replace with + 'unresolved_symbols_in_objects' and + 'unresolved_symbols_in_shared_libs'. + +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h: Remove PARAMS macro. Replace PTR with void *. + * dis-asm.h: Likewise. + +2003-07-09 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h: Undef all macros before defining them. + +2003-07-06 H.J. Lu <hongjiu.lu@intel.com> + + * demangle.h: Support C++. + +2003-07-01 Zack Weinberg <zack@codesourcery.com> + + * filenames.h: New file imported from binutils. + +2003-06-30 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h: New file imported from binutils. + +2003-06-30 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h (XCHAL_HAVE_CONST16, XCHAL_HAVE_ABS, + XCHAL_HAVE_ADDX, XCHAL_HAVE_L32R): Define. + +2003-06-25 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h: Correct spelling of "relocatable". + +2003-06-22 Zack Weinberg <zack@codesourcery.com> + + * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC): Rename to + HOST_CHARSET_UNKNOWN, HOST_CHARSET_ASCII, HOST_CHARSET_EBCDIC + respectively. + +2003-06-21 Zack Weinberg <zack@codesourcery.com> + + * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC, HOST_CHARSET): + New #defines. + +2003-06-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Delete HAVE_LONG_DOUBLE GCC bootstrap support. + +2003-05-23 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add execstack and noexecstack. + * elf/common.h (PT_GNU_STACK): Define. + +2003-06-03 H.J. Lu <hongjiu.lu@intel.com> + + * bfdlink.h (LD_DEFINITION_IN_DISCARDED_SECTION): New. + +2003-05-30 Ulrich Drepper <drepper@redhat.com> + Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add pie and executable + bits. + +2003-05-21 Nick Clifton <nickc@redhat.com> + + * bfdlink.h (struct bfd_link_hash_table): Fix typo in comment. + +2003-05-15 Jim Blandy <jimb@redhat.com> + + * libiberty.h (hex_value): Make the value an unsigned int, to + avoid unexpected sign-extension when cast to unsigned types larger + than int --- like bfd_vma, on some platforms. + (_hex_value): Update declaration. + +2003-05-09 Alan Modra <amodra@bigpond.net.au> + + * xtensa-isa-internal.h (xtensa_isa_module_struct): Remove const on + gen_num_opcodes_fn return type. + +2003-05-07 Jason Merrill <jason@redhat.com> + + * hashtab.h (iterative_hash): Prototype. + (iterative_hash_object): New macro. + +2003-04-28 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_info): Add relax_finalizing. + +2003-04-23 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_callbacks): Add error_handler. + +2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com> + + * coff/tic4x.h: Namespace cleanup. Replace s/c4x/tic4x + and s/c3x/tic3x/ + * coff/tc-tic4x.h: Ditto + * opcode/tic4x.h: Ditto + +2003-04-02 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h: Remove comment indicating that this is a + generated file. + +2003-04-01 Bob Wilson <bob.wilson@acm.org> + + * dis-asm.h (print_insn_xtensa): Declare. + * xtensa-config.h: New file. + * xtensa-isa-internal.h: Likewise. + * xtensa-isa.h: Likewise. + +2003-03-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (ATTRIBUTE_NONNULL, ATTRIBUTE_NULL_PRINTF, + ATTRIBUTE_NULL_PRINTF_1, ATTRIBUTE_NULL_PRINTF_2, + ATTRIBUTE_NULL_PRINTF_3, ATTRIBUTE_NULL_PRINTF_4, + ATTRIBUTE_NULL_PRINTF_5): New. + (ATTRIBUTE_PRINTF): Add ATTRIBUTE_NONNULL. + +2003-03-17 Jan Hubicka <jh@suse.cz> + + * hashtab.h (htab_traverse_noresize): Declare. + +2003-02-27 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h: Document return value of physmem routines. + +2003-02-20 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (physmem_total, physmem_available): Prototype. + +2003-02-20 Daniel Jacobowitz <drow@mvista.com> + + * libiberty.h (lrealpath): Add declaration. + +2003-01-31 Grant Grundler <grundler@dsl2.external.hp.com> + + * hppa.h (ldwa, ldda): Add ordered opcodes. + +2003-01-26 Daniel Jacobowitz <drow@mvista.com> + + * hashtab.h (htab_alloc_with_arg, htab_free_with_arg): Add new types. + (struct htab): Add alloc_arg, alloc_with_arg_f, free_with_arg_f. + (htab_create_alloc_ex): New prototype. + (htab_set_functions_ex): New prototype. + +2003-01-25 Jakub Jelinek <jakub@redhat.com> + + * elf/sparc.h: Add TLS relocs. Move R_SPARC_REV32 to 252. + +2003-01-20 Svein E. Seldal <Svein.Seldal@solidas.com> + + * coff/tic4x.h (TICOFF_TARGET_MACHINE_GET): Fixed define bug + * coff/ti.h (TICOFF_TARGET_MACHINE_GET): Added macros + +2002-07-17 Geoffrey Keating <geoffk@redhat.com> + + * splay-tree.h (GTY): Define if undefined. + (splay_tree_allocate_fn): Return PTR for compatibility, not void *. + (struct splay_tree_node_s): Support gengtype. + (struct splay_tree_s): Likewise. Make allocate_data a PTR, + not a void *. + +2002-01-02 Ben Elliston <bje@redhat.com> + + * dis-asm.h (print_insn_iq2000): Declare. + +2002-12-24 Dmitry Diky <diwil@mail.ru> + + * dis-asm.h: Add msp430 disassembler prototype. + +2002-12-27 Chris Demetriou <cgd@broadcom.com> + + * dis-asm.h (print_mips_disassembler_options): Prototype. + +2002-12-23 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_info): Add "strip_discarded". + +2002-12-20 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_info): Replace bfd_boolean fields with + bit-fields. Rearrange to put all like types together. + +2002-11-30 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h: Replace boolean with bfd_boolean. Formatting. + +2002-11-23 Simon Burge <simonb@wasabisystems.com> + + * libiberty.h (basename): Add NetBSD to the list. + +2002-11-22 Daniel Jacobowitz <drow@mvista.com> + + * libiberty.h (make_relative_prefix): Add prototype. + +2002-11-16 Klee Dienes <kdienes@apple.com> + + * opcode/m88k.h (INSTAB): Remove 'next' field. + (instruction): Remove definition; replace with extern declaration + and mark as const. + +2002-11-14 Egor Duda <deo@logos-m.ru> + + * bfdlink.h (struct bfd_link_info): Add new boolean + field pei386_runtime_pseudo_reloc. + +2002-10-26 Roger Sayle <roger@eyesopen.com> + + * partition.h: Close the extern "C" scope when compiling with C++. + +2002-10-26 Roger Sayle <roger@eyesopen.com> + DJ Delorie <dj@redhat.com> + + PR bootstrap/8351 + * getopt.h: Avoid prototyping getopt with no arguments in C++. + +2002-10-24 Nathan Tallent <eraxxon@alumni.rice.edu> + + * ansidecl.h (__STDC__): Add (__alpha && __cplusplus) to the + list of platform compilers that may look, smell and act + like __STDC__ but that may not define it. + +2002-10-11 David O'Brien <obrien@FreeBSD.org> + + * getopt.h: getopt is in unistd.h (based on SUSv2). + +2002-09-26 Jakub Jelinek <jakub@redhat.com> + + * elf/x86-64.h: Add TLS relocs. + +2002-09-26 Andrew Cagney <ac131313@redhat.com> + + * regs/: Delete directory. + +2002-09-19 Alexandre Oliva <aoliva@redhat.com> + + * libiberty.h (asprintf, vasprintf): Don't declare them if the + corresponding HAVE_DECL_ macro is 1. + +2002-09-19 Jakub Jelinek <jakub@redhat.com> + + * elf/i386.h (R_386_TLS_TPOFF, R_386_TLS_IE, R_386_TLS_GOTIE): + Define. + +2002-09-19 Nathan Tallent <eraxxon@alumni.rice.edu> + + * dis-asm.h: Remove (errant) trailing semicolon (;) from the + extern "C" { } declaration. + +2002-09-04 Nick Clifton <nickc@redhat.com> + + * dis-asm.h (print_ppc_disassembler_options): Prototype. + +2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * coff/internal.h: Add new relocation types. + * coff/ti.h: Add file-header flags for tic4x code. + * dis-asm.h: Add standard disassembler for tic4x. + * opcode/tic4x.h: New file. + * coff/tic4x.h: New file + +2002-08-07 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_info): Add allow_undefined_version. + (bfd_elf_version_expr): Add symver and script. + +2002-07-31 Ian Dall <ian@sibyl.beware.dropbear.id.au> + + * bfdlink.h (bfd_link_common_skip_ar_symbols): New enum. + (struct bfd_link_info): Add new field 'common_skip_ar_symbols'. + +2002-07-25 Richard Sandiford <rsandifo@redhat.com> + + * opcode/mips.h (CPU_R2000): Remove. + +2002-07-19 Denis Chertykov <denisc@overta.ru> + Matthew Green <mrg@redhat.com> + + * dis-asm.h (print_insn_ip2k): Declare. + +2002-07-10 Jakub Jelinek <jakub@redhat.com> + + * elf/common.h (SHT_GNU_LIBLIST, DT_GNU_PRELINKED, + DT_GNU_CONFLICT*, DT_GNU_LIBLIST*): Define. + +2002-07-01 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_sym_chain): Declare. + (struct bfd_link_info): Add gc_sym_list. Formatting fixes. + +2002-06-25 Alan Modra <amodra@bigpond.net.au> + + * demangle.h: #include "ansidecl.h" rather than #include <ansidecl.h>. + * fibheap.h: Likewise. + * hashtab.h: Likewise. + * partition.h: Likewise. + * sort.h: Likewise. + * splay-tree.h: Likewise. + +2002-06-24 Alan Modra <amodra@bigpond.net.au> + + * libiberty.h (basename): Don't declare if HAVE_DECL_BASENAME. + * getopt.h (getopt): Don't declare if HAVE_DECL_GETOPT. + +2002-06-18 Dave Brolley <brolley@redhat.com> + + From Catherine Moore: + * dis-asm.h (print_insn_frv): New prototype. + +2002-06-09 Andrew Cagney <cagney@redhat.com> + + * remote-sim.h: Move to directory gdb/. + * callback.h: Move to directory gdb/. + +2002-06-07 Charles Wilson <cwilson@ece.gatech.edu> + + * bfdlink.h (struct bfd_link_info): Change type of + pei386_auto_import field to int so that -1 can mean enabled by + default and 1 can mean enabled by command line switch. + +2002-06-06 DJ Delorie <dj@redhat.com> + + * hashtab.h (htab): Rearrange new members for backward + compatibility. + (htab_create): Don't use a macro that requires other headers. + +2002-06-05 Geoffrey Keating <geoffk@redhat.com> + + * hashtab.h (htab_create): Restore prototype for backward + compatibility. + (htab_try_create): Likewise. + +2002-05-22 Geoffrey Keating <geoffk@redhat.com> + + * hashtab.h (struct htab): Update for change to length specifier. + +2002-05-10 Geoffrey Keating <geoffk@redhat.com> + + * hashtab.h (GTY): Define if undefined. + (htab_alloc): New typedef. + (htab_free): New typedef. + (struct htab): Support gengtype; allow user-specified memory + allocation. + (htab_create_alloc): New. + (htab_create): Replace with #define. + (htab_try_create): Delete. + +2002-05-31 Michal Ludvig <mludvig@suse.cz> + + * elf/dwarf2.h (DW_CFA_low_user, DW_CFA_high_user): Renamed + to DW_CFA_lo_user, DW_CFA_hi_user respectively. + +2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> + + * dis-asm.h: Prototype print_insn_dlx. + +2002-05-23 Andrew Cagney <ac131313@redhat.com> + + * sim-d10v.h: Delete file. Moved to include/gdb/. + +2002-05-23 Jakub Jelinek <jakub@redhat.com> + + * elf/common.h (PT_TLS, SHF_TLS, STT_TLS, DF_STATIC_TLS): Define. + * elf/ia64.h (R_IA64_LTOFF_TPREL22): Renamed from R_IA64_LTOFF_TP22. + * elf/i386.h: Add TLS relocs. + +2002-05-21 H.J. Lu (hjl@gnu.org) + + * bfdlink.h (bfd_link_info): Add allow_multiple_definition. + +2002-05-17 J"orn Rennecke <joern.rennecke@superh.com> + + * dis-asm.h (print_insn_shl, print_insn_sh64l): Remove prototype. + +2002-04-16 David S. Miller <davem@redhat.com> + + * xregex2.h (__restrict_arr): Define to __restrict on GCC + 3.1 and later. Do not redefine. + +2002-04-01 Phil Edwards <pme@gcc.gnu.org> + + * dyn-string.h: Also allow IN_GLIBCPP_V3 to redefine names. + +2002-03-10 Daniel Jacobowitz <drow@mvista.com> + + * gdb: New directory. + +2002-03-06 Andrew Cagney <ac131313@redhat.com> + + * floatformat.h (floatformat_arm_ext): Delete declaration. + +2002-02-21 Jim Blandy <jimb@redhat.com> + + Allow the user to specify functions for allocating memory for + splay tree roots and nodes. + * splay-tree.h (splay_tree_allocate_fn, splay_tree_deallocate_fn): + New types. + (splay_tree): New fields: `allocate', `deallocate', and + `allocate_data'. + (splay_tree_new_with_allocator): New function declaration. + +2002-02-15 Alan Modra <amodra@bigpond.net.au> + + Support arbitrary length fill patterns. + * bfdlink.h (enum bfd_link_order_type): Remove bfd_fill_link_order. + (struct bfd_link_order): Remove fill. Add data.size. + +2002-02-08 Alexandre Oliva <aoliva@redhat.com> + + Contribute sh64-elf. + 2000-11-25 Hans-Peter Nilsson <hpn@cygnus.com> + * dis-asm.h (print_insn_sh64): New prototype. + (print_insn_sh64l): New prototype. + (print_insn_sh64x_media): New prototype. + +2002-02-05 Frank Ch. Eigler <fche@redhat.com> + + * dis-asm.h (disassemble_info): New field `insn_sets'. + (INIT_DISASSEMBLE_INFO): Clear it. + +2002-02-05 Jason Merrill <jason@redhat.com> + + * demangle.h (cplus_demangle_v3): Add "options" parm. + (cplus_demangle_v3_type): Remove prototype. + (DMGL_VERBOSE): New macro. + (DMGL_TYPES): New macro. + +2002-02-02 H.J. Lu (hjl@gnu.org) + + * demangle.h (cplus_demangle_v3_type): New prototype. + +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * dis-asm.h : Add support for or32 targets + +2002-01-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (C_alloca): Add ATTRIBUTE_MALLOC. + +2002-01-27 David O'Brien <obrien@FreeBSD.org> + + * cgen.h (BFD_VERSION): Use BFD_VERSION_DATE instead. + +2001-12-14 Nick Clifton <nickc@cambridge.redhat.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise the + disassembler_options field (to NULL). + +2001-12-13 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add eh_frame_hdr field. + +2001-12-07 Geoffrey Keating <geoffk@redhat.com> + + * dis-asm.h (print_insn_xstormy16): Declare. + +2001-12-06 Richard Henderson <rth@redhat.com> + + * demangle.h (no_demangling): New. + (NO_DEMANGLING_STYLE_STRING): New. + +2001-11-14 Alan Modra <amodra@bigpond.net.au> + + * dis-asm.h (print_insn_i386): Declare. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * dis-asm.h: Fix comment to refer to octets rather than bytes. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * dis-asm.h (print_insn_mmix): Add prototype. + +2001-10-24 Neil Booth <neil@daikokuya.demon.co.uk> + + * safe-ctype.h (_sch_isbasic, IS_ISOBASIC): New. + +2001-10-22 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (hex_init): Revert delete. + + * libiberty.h (_hex_value): Const-ify. + (hex_init): Delete. + +2001-10-16 Christopher Faylor <cgf@redhat.com> + + * filenames.h: Add cygwin to the list of dosish style path systems. + +2001-10-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h (demangler_engine): Const-ify. + * libiberty.h (buildargv): Likewise. + +2001-10-03 Vassili Karpov <malc@pulsesoft.com> + + * bfdlink.h (struct bfd_link_info): Add nocopyreloc field. + +2001-09-24 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (reconcat): New function. + +2001-09-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (concat, concat_length, concat_copy, concat_copy2, + ACONCAT): Improve comments. + +2001-09-18 Alan Modra <amodra@bigpond.net.au> + + * objalloc.h (OBJALLOC_ALIGN): Define using offsetof. + +2001-09-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (concat_length, concat_copy, concat_copy2, + libiberty_concat_ptr, ACONCAT): New. + + * libiberty.h (ASTRDUP): New macro. + libiberty_optr, libiberty_nptr, libiberty_len): Declare. + +2001-08-29 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Update comments reflecting previous change. + +2001-08-27 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (VA_OPEN, VA_CLOSE): Allow multiple uses. + +2001-08-25 Nick Clifton <nickc@cambridge.redhat.com> + + * bfdlink.h (struct bfd_link_info): Change 'spare_dynamic_tags' to + unsigned to remove a compile time warning message. + +2001-08-24 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_hash_table_type): New. The linker hash + table type, bfd_link_generic_hash_table and + bfd_link_elf_hash_table. + (bfd_link_hash_table): Add a new field, type, for the linker + hash table type. + +2001-08-23 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add combreloc and + spare_dynamic_tags fields. + +2001-08-23 Lars Brinkhoff <lars@nocrew.org> + + * dyn-string.h, fibheap.h, partition.h, sort.h, splay-tree.h: + replace "GNU CC" with "GCC". + +2001-08-21 Richard Henderson <rth@redhat.com> + + * fibheap.h: Tidy formatting. + (fibnode_t): Limit degree to 31 bits to avoid warning. + +2001-08-20 Daniel Berlin <dan@cgsoftware.com> + + * fibheap.h: New file. Fibonacci heap. + +2001-08-20 Andrew Cagney <ac131313@redhat.com> + + * floatformat.h (floatformat_arm_ext): Document as deprecated. + (floatformat_arm_ext_big, floatformat_arm_ext_littlebyte_bigword) + (floatformat_ia64_spill_little, floatformat_ia64_quad_little) + (floatformat_ia64_spill_big, floatformat_ia64_quad_big) + (floatformat_m88110_harris_ext): Declare. + +2001-08-18 Zack Weinberg <zackw@panix.com> + + * ansidecl.h: Reorganize for readability, remove documentation + of obsolete macros, document PARAMS and VPARAMS. Add new + macros VA_OPEN, VA_CLOSE, and VA_FIXEDARG for nicer variadic + function implementation. + +2001-08-16 Richard Henderson <rth@redhat.com> + + * hashtab.h (htab_hash_string): Declare. + +2001-08-10 Andrew Cagney <ac131313@redhat.com> + + * libiberty.h (lbasename): Change function declaration to return a + const char pointer. + +2001-08-02 Mark Kettenis <kettenis@gnu.org> + + * xregex.h (_REGEX_RE_COMP): Define. + (re_comp): Define to xre_comp. + (re_exec): Define to xre_exec. + +2001-08-02 Charles Wilson <cwilson@ece.gatech.edu> + + * bfdlink.h (struct bfd_link_info): add new boolean + field pei386_auto_import. + +2001-07-18 Andreas Jaeger <aj@suse.de> + + * xregex2.h: Place under LGPL version 2.1. + +2001-07-10 Jeff Johnston <jjohnstn@redhat.com> + + * xregex.h: New file to support libiberty regex. + * xregex2.h: Ditto. + +2001-06-15 Hans-Peter Nilsson <hp@axis.com> + + * bfdlink.h (struct bfd_link_info): New member export_dynamic. + +2001-05-16 Matt Kraai <kraai@alumni.carnegiemellon.edu> + + * partition.h: Fix misspelling of `implementation'. + +2001-05-10 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (NULL_PTR): Delete. + +2001-05-07 Zack Weinberg <zackw@stanford.edu> + + * demangle.h: Use PARAMS for all prototypes. + * ternary.h: Use PARAMS for all prototypes. Use PTR, not void *. + Make arguments constant where possible. + +2001-05-07 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_max): New function. + (splay_tree_min): Likewise. + +2001-04-27 Johan Rydberg <jrydberg@opencores.org> + + * dis-asm.h (print_insn_openrisc): Add prototype. + +2001-04-15 Daniel Berlin <dan@cgsoftware.com> + + * ternary.h: New file - Ternary search tree header. + +2001-04-13 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (bfd_link_discard): Add discard_sec_merge. + +2001-04-03 Zack Weinberg <zackw@stanford.edu> + + * ansidecl.h: All logic from gcc/gansidecl.h moved here. + +2001-03-31 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (alloca): Handle setting C_ALLOCA. + +2001-03-20 Jim Blandy <jimb@redhat.com> + + * demangle.h (enum gnu_v3_constructor_kinds, + is_gnu_v3_mangled_ctor, enum gnu_v3_destructor_kinds, + is_gnu_v3_mangled_dtor): New declarations. + +2001-03-14 Nick Clifton <nickc@redhat.com> + + * ansidecl.h: Fix copyright dates. + * demangle.h: Fix copyright dates. + * floatformat.h: Fix copyright dates. + * fnmatch.h: Fix copyright dates. + * getopt.h: Fix copyright dates. + * libiberty.h: Add FSF copyright notice. + * md5.h: Fix copyright dates. + * obstack.h: Fix copyright dates. + * splay-tree.h: Fix copyright dates. + +2001-03-10 Neil Booth <neil@daikokuya.demon.co.uk> + John David Anglin <dave@hiauly1.hia.nrc.ca> + + * libiberty.h: Add lbasename. + +2001-03-06 Zack Weinberg <zackw@stanford.edu> + + * libiberty.h: Prototype C_alloca; define alloca to either + __builtin_alloca or C_alloca as appropriate. + +2001-03-01 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * safe-ctype.h (_sch_test): Cast enum bit to unsigned short int for pcc + compatibility. + +2001-02-18 lars brinkhoff <lars@nocrew.org> + + * dis-asm.h: Add PDP-11 target. + +2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * dis-asm.h: Add linux target for S/390. + +2001-01-11 Peter Targett <peter.targett@arccores.com> + + * dis-asm.h (arc_get_disassembler): Correct declaration. + +2001-01-09 Philip Blundell <philb@gnu.org> + + * bin-bugs.h (REPORT_BUGS_TO): Set to `bug-binutils@gnu.org'. + +2000-12-18 Joseph S. Myers <jsm28@cam.ac.uk> + + * COPYING: Update to current + ftp://ftp.gnu.org/pub/gnu/Licenses/COPYING-2.0 (fixes references + to 19yy as example year in copyright notice). + +2000-12-19 Hans-Peter Nilsson <hp@bitrange.com> + + * dis-asm.h (struct disassemble_info): New member "section". + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize private_data member. + Initialize section member. + +2000-12-16 Herman A.J. ten Brugge <Haj.Ten.Brugge@net.HCC.nl> + + * safe-ctype.h: Make code work on all targets and not just on + targets where a char is 8 bits. + +2000-12-10 Fred Fish <fnf@be.com> + + * bfdlink.h (struct bfd_link_info): Add new allow_shlib_undefined + member to struct for systems where it is normal to have undefined + symbols in shared libraries at runtime and the runtime linker + takes care of redirecting them. + +2000-12-07 Zack Weinberg <zack@wolery.stanford.edu> + + * safe-ctype.h: New file. + +2000-12-06 Rodney Brown <RodneyBrown@mynd.com> + + * getopt.h obstack.h: Standarize copyright statement. + +2000-12-04 Richard Henderson <rth@redhat.com> + + * demangle.h: Change "new_abi" to "v3" everywhere. + +2000-11-22 Zack Weinberg <zack@wolery.stanford.edu> + + * libiberty.h: Move #includes to top. Prototype xmalloc_failed. + +2000-11-15 Kenneth Block <kenneth.block@compaq.com> + + * demangle.h: Add gnat and java demangle styles. + +2000-11-04 Hans-Peter Nilsson <hp@bitrange.com> + + * hashtab.h (struct htab): Add member return_allocation_failure. + (htab_try_create): New prototype. Mention which functions may + return NULL when this is used. + +2000-11-03 Hans-Peter Nilsson <hp@bitrange.com> + + * hashtab.h: Change void * to PTR where necessary. + +2000-10-11 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_predecessor): Declare. + +2000-09-29 Hans-Peter Nilsson <hp@axis.com> + + * dis-asm.h: Declare cris_get_disassembler, not print_insn_cris. + Fix typo in comment. + +2000-09-28 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * alloca-conf.h: New file (copied from libiberty). + +2000-09-05 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * md5.h (md5_uint32): Choose via INT_MAX instead of UINT_MAX. + +2000-09-04 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h: Adjust formatting. + (dyn_string_insert_char): New macro. New declaration. + +2000-08-28 Jason Merrill <jason@redhat.com> + + * md5.h: New file. + +2000-08-24 Greg McGary <greg@mcgary.org> + + * libiberty.h (ARRAY_SIZE): New macro. + +2000-07-29 Nick Clifton <nickc@cygnus.com> + + * os9k.h: Add copyright notice. + Fix formatting. + +2000-07-22 Jason Eckhardt <jle@cygnus.com> + + * dis-asm.h (print_insn_i860): Add prototype. + +2000-07-20 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_info): Add new_dtags. + +2000-07-20 Hans-Peter Nilsson <hp@axis.com> + + * dis-asm.h (print_insn_cris): Declare. + +2000-07-19 H.J. Lu (hjl@gnu.org) + + * bfdlink.h (bfd_link_info): Add flags and flags_1. + +2000-06-05 DJ Delorie <dj@redhat.com> + + * MAINTAINERS: new + +2000-06-21 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h (dyn_string_init, dyn_string_new, + dyn_string_delete, dyn_string_release, dyn_string_resize, + dyn_string_clear, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring_dyn_string_eq): + Define as same name with __cxa_ prepended, if IN_LIBGCC2. + (dyn_string_init, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring): Change return type + to int. + +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * dis-asm.h (print_insn_m68hc12): Define. + (print_insn_m68hc11): Likewise. + +2000-06-18 Nick Clifton <nickc@redhat.com> + + * os9k.h: Change values of MODSYNC and CRCCON due to bug report + from Russ Magee <rmagee@home.com>. + +2000-06-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h (demangling_styles): Remove trailing comma in enum. + + * dyn-string.h (dyn_string_append_char): Change parameter from + char to int. + +2000-06-04 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h: Move here from gcc/dyn-string.h. Add new functions. + + * demangle.h (DMGL_GNU_NEW_ABI): New macro. + (DMGL_STYLE_MASK): Or in DMGL_GNU_NEW_ABI. + (current_demangling_style): Add gnu_new_abi_demangling. + (GNU_NEW_ABI_DEMANGLING_STYLE_STRING): New macro. + (GNU_NEW_ABI_DEMANGLING): Likewise. + (cplus_demangle_new_abi): New declaration. + +Tue May 30 16:53:34 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * floatformat.h (struct floatformat): Add field name. + +2000-05-26 Eli Zaretskii <eliz@is.elta.co.il> + + * filenames.h: New file. + (HAVE_DOS_BASED_FILE_SYSTEM, IS_DIR_SEPARATOR) + (IS_ABSOLUTE_PATH, FILENAME_CMP): New macros. + +2000-05-23 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * getopt.h (getopt): Also check HAVE_DECL_* when prototyping. + + * libiberty.h (basename): Likewise. + +2000-05-17 S. Bharadwaj Yadavalli <sby@scrugs.lkg.dec.com> + Rick Gorton <gorton@scrugs.lkg.dec.com> + + * bfdlink.h (struct bfd_link_info): Add emitrelocations flag. + +2000-05-08 Alan Modra <alan@linuxcare.com.au> + + * dis-asm.h (print_insn_tic54x): Declare. + +2000-05-06 Zack Weinberg <zack@wolery.cumb.org> + + * ansidecl.h: #define __extension__ to nothing if + GCC_VERSION < 2008. + +2000-05-04 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h (demangler_engine): Constify. + +Thu May 4 17:15:26 2000 Philippe De Muyter <phdm@macqel.be> + + * sort.h (sys/types.h): File included unconditionnaly. + (stddef.h): File include only #ifdef __STDC__. + +2000-05-03 Zack Weinberg <zack@wolery.cumb.org> + + * symcat.h: Remove #endif label. + +2000-04-28 Kenneth Block <block@zk3.dec.com> + Jason Merrill <jason@casey.cygnus.com> + + * demangle.h (libiberty_demanglers): new table for different styles. + (cplus_demangle_set_style): New function for setting style. + (cplus_demangle_name_to_style): New function to translate name. + +2000-04-24 Mark Mitchell <mark@codesourcery.com> + + * hashtab.h (hash_pointer): Declare. + (eq_pointer): Likewise. + +2000-04-23 Mark Mitchell <mark@codesourcery.com> + + * sort.h: New file. + +Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + + * dis-asm.h (print_insn_ia64): Declare. + +Tue Apr 18 16:22:30 2000 Richard Kenner <kenner@vlsi1.ultra.nyu.edu> + + * hashtab.h (enum insert_option): New type. + (htab_find_slot, htab_find_slot_with_hash): Use it. + +2000-04-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * symcat.h: Honor autoconf macro HAVE_STRINGIZE. Add + comments/caveats with regard to traditional C behavior. + +2000-04-05 Richard Henderson <rth@cygnus.com> + + * splay-tree.h (splay_tree_remove): Declare. + +2000-04-04 Alan Modra <alan@linuxcare.com.au> + + * bin-bugs.h (REPORT_BUGS_TO): Remove translated part. + +2000-04-03 Alan Modra <alan@linuxcare.com.au> + + * bin-bugs.h: New file. + +2000-03-30 Mark Mitchell <mark@codesourcery.com> + + * hashtab.h (hashval_t): New type. + (htab_find_with_hash): Use it as an argument. + (htab_find_slot_with_hash): Likewise. + +2000-03-27 Denis Chertykov <denisc@overta.ru> + + * dis-asm.h (print_insn_avr): Declare. + +2000-03-14 Bernd Schmidt <bernds@cygnus.co.uk> + + * hashtab.h (htab_trav): Modify type so that first arg is of type + void **. + (htab_find_with_hash, htab_find_slot_with_hash): Declare new + functions. + +2000-03-09 Alex Samuel <samuel@codesourcery.com> + + * partition.h: New file. + +2000-03-09 Zack Weinberg <zack@wolery.cumb.org> + + * hashtab.h (struct htab): Add del_f. + (htab_del): New type. + (htab_create): Add fourth argument. + +2000-03-08 Zack Weinberg <zack@wolery.cumb.org> + + * hashtab.h (hash_table_t): Rename to htab_t. + (struct hash_table): Rename to struct htab. Shorten element + names. Reorder elements by size. + (htab_hash, htab_eq, htab_trav): New typedefs for the callback + function pointers. + (hash_table_entry_t): Discard; just use void * for element + type. + +2000-03-01 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_callbacks): Add a boolean arg to + the undefined_symbol callback. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * dis-asm.h (print_insn_i370): Declare. + +Tue Feb 22 15:19:54 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_trace): Document return values. + (sim_set_trace): Declare. Deprecate. + +2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * dis-asm.h (struct disassemble_info): Change `length' param of + read_memory_func to unsigned. Change type of `buffer_length' and + `octets_per_byte' to unsigned. + (buffer_read_memory): Change `length' param to unsigned. + +2000-02-16 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Add prototypes for ARM register name functions. + +Wed Feb 9 18:45:49 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * wait.h: Delete. No longer used by GDB. + +Tue Feb 8 17:01:13 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_resume): Clarify use of SIGGNAL. + (sim_stop_reason): Clarify meaning of sim_signalled. + +2000-02-03 Timothy Wall <twall@redhat.com> + + * dis-asm.h (struct disassemble_info): Added octets_per_byte + field and initialize it to one (1). + +2000-01-27 Nick Clifton <nickc@redhat.com> + + * dis-asm.h: Add prototype for disassembler_usage(). + Add prototype for arm_disassembler_options(). + Remove prototype for arm_toggle_regnames(). + Add prototype for parse_arm_disassembler_option(). + +Sat Jan 1 19:06:52 2000 Hans-Peter Nilsson <hp@bitrange.com> + + * symcat.h (STRINGX) [!__STDC__ || ALMOST_STDC]: Change "?" to "s" + to stringify argument s. + +Wed Dec 15 11:22:56 1999 Jeffrey A Law (law@cygnus.com) + + * hp-symtab.h (HP_LANGUAGE_FORTRAN): New enumeration constant. + (HP_LANGUAGE_F77): Define using HP_LANGUAGE_FORTRAN. + +1999-12-15 Doug Evans <dje@transmeta.com> + + * dis-asm.h: Enclose in extern "C" ifdef __cplusplus. + +1999-12-05 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (struct splay_tree_node): Rename to ... + (struct splay_tree_node_s): ... this. + (struct splay_tree): Rename to ... + (struct splay_tree_s): ... this. + +1999-11-30 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (ATTRIBUTE_MALLOC): New macro. + + * libiberty.h (buildargv, dupargv, concat, choose_temp_base, + make_temp_file, xmalloc, xcalloc, xstrdup, xmemdup): Add + ATTRIBUTE_MALLOC. + (xatexit): Remove __GNUC__ check, add ATTRIBUTE_NORETURN. + +1999-11-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h: Include stdarg.h when ANSI_PROTOTYPES is defined. + (asprintf, vasprintf): Provide declarations. + +Wed Nov 10 12:43:21 1999 Philippe De Muyter <phdm@macqel.be> + Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Define and test `GCC_VERSION', not `HAVE_GCC_VERSION'. + +1999-11-04 Jimmy Guo <guo@cup.hp.com> + + * hp-symtab.h (dntt_type_fparam): Add doc_ranges, misc_kind + fields, change location type to CORE_ADDR from int. + (dntt_type_const): Name the 5th field location_type. + +Sun Oct 24 19:11:32 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-d10v.h (SIM_D10V_TS2_DMAP_REGNUM): Define. + +1999-10-23 08:51 -0700 Zack Weinberg <zack@bitmover.com> + + * hashtab.h: Give hash_table_t a struct tag. Add prototypes + for clear_hash_table_slot and traverse_hash_table. Correct + prototype of all_hash_table_collisions. + +Sat Oct 23 19:00:13 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-d10v.h: New file. + +Fri Oct 15 01:47:51 1999 Vladimir Makarov <vmakarov@loony.cygnus.com> + + * hashtab.h: New file. + +1999-10-10 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (HAVE_GCC_VERSION): New macro. Use it instead of + explicitly testing __GNUC__ and __GNUC_MINOR__. + + (ATTRIBUTE_PRINTF): Use `__format__', not `format'. + +1999-09-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (make_temp_file): Add a prototype. + +Tue Sep 14 00:35:02 1999 Marc Espie <espie@cvs.openbsd.org> + + * libiberty.h (basename): OpenBSD has a correct prototype. + (xrealloc): Remove outdated comment. + +1999-09-07 Jeff Garzik <jgarzik@pobox.com> + + * libiberty.h (xmemdup): Add prototype for new function. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * dis-asm.h (print_insn_pj): Declare. + +1999-09-01 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * obstack.h (obstack_grow, obstack_grow0): Move (char*) casts + in calls to `_obstack_memcpy' from here ... + + (_obstack_memcpy): ... to here, except in the __STDC__ case which + doesn't need it. + +1999-08-30 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (getpwd): Prototype. + +1999-08-01 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_insert): Return the new node. + +1999-07-11 Ian Lance Taylor <ian@zembu.com> + + * ansidecl.h: Copy attribute support macros from egcs. + +1999-06-22 Mark Mitchell <mark@codesourcery.com> + + * bfdlink.h (struct bfd_link_hash_entry): Add init_function and + fini_function. + +1999-06-20 Mark Mitchell <mark@codesourcery.com> + + * mips.h (Elf32_Internal_Msym): New structure. + (Elf32_External_Msym): Likewise. + (ELF32_MS_REL_INDEX): New macro. + (ELF32_MS_FLAGS): Likewise. + (ELF32_MS_INFO): Likewise. + +1999-06-14 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h (arm_toggle_regnames): New prototype. + (struct diassemble_info): New field: disassembler_options. + +1999-04-11 Richard Henderson <rth@cygnus.com> + + * bfdlink.h (bfd_elf_version_expr): Rename `match' to `pattern'. + Add `match' callback function. + +1999-04-10 Richard Henderson <rth@cygnus.com> + + * bfdlink.h (bfd_link_info): Add no_undefined. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Add prototype for print_insn_mcore. + +1999-04-02 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_compare_pointers): Declare. + +1999-03-30 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_compare_ints): Declare. + +Wed Mar 24 12:46:29 1999 Andrew Cagney <cagney@amy.cygnus.com> + + * libiberty.h (basename): Cygwin{,32} should have the prototype. + +1999-02-22 Jim Lemke <jlemke@cygnus.com> + + * bfdlink.h (bfd_link_info): add field "mpc860c0". + +Mon Feb 1 21:05:46 1999 Catherine Moore <clm@cygnus.com> + + * dis-asm.h (print_insn_i386_att): Declare. + (print_insn_i386_intel): Declare. + +1998-12-30 Michael Meissner <meissner@cygnus.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Cast STREAM and + FPRINTF_FUNC to avoid compiler warnings. + +Wed Dec 30 16:07:14 1998 David Taylor <taylor@texas.cygnus.com> + + * dis-asm.h: change void * to PTR (two places). + +Mon Dec 14 09:53:31 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h: Don't check IN_GCC anymore. + * splay-tree.h: Likewise. + +Tue Dec 8 00:30:31 1998 Elena Zannoni <ezannoni@kwikemart.cygnus.com> + + The following changes were made by Elena Zannoni + <ezannoni@kwikemart.cygnus.com> and Edith Epstein + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes made by HP; HP did not create ChangeLog entries. + + * dis-asm.h (struct disassemble_info): change the type of stream + from FILE* to void*, for use with gdb's new type GDB_FILE. + (fprintf_ftype): change FILE* parameter type to void*. + + * demangle.h: (DMGL_EDG): new macro for Kuck and Associates + (DMGL_STYLE_MASK): modify to include Kuck and Assoc style + (demangling_styles): add new edg_demangling style + (EDG_DEMANGLING_STYLE_STRING): new macro + (EDG_DEMANGLING): new macro + (DMGL_HP): new macro, for HP/aCC compiler. + (DMGL_STYLE_MASK): modify to include new HP's style. + (demangling_styles): add new hp_demangling value. + (HP_DEMANGLING_STYLE_STRING): new macro. + (ARM_DEMANGLING): coerce to int. + (HP_DEMANGLING): new macro. + + * hp-symtab.h: rewritten, from HP. + (quick_procedure): change type of language field to unsigned int + (quick_module): change type of language field to unsigned int + (struct dntt_type_svar): add field thread_specific. + (hp_language): add languages modcal and dmpascal. + +Fri Nov 20 13:14:00 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * libiberty.h (basename): Add prototype for FreeBSD. + +Fri Nov 13 19:19:11 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h: Prototype xcalloc. + +Sun Nov 8 17:42:25 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Wrap problematic macros with !IN_GCC. + + * demangle.h: Never define PARAMS(). + * splay-tree.h: Likewise. + +Sat Nov 7 18:30:20 1998 Peter Schauer <peter.schauer@regent.e-technik.tu-muenchen.de> + + * dis-asm.h (print_insn_vax): Declare. + +Sat Nov 7 16:04:03 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h: Don't include gansidecl.h. + * splay-tree.h: Likewise. + +1998-10-26 16:03 Ulrich Drepper <drepper@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add new field optimize. + +Thu Oct 22 19:58:00 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * splay-tree.h: Wrap function pointer parameter declarations in + PARAMS() macro. + +1998-10-21 Mark Mitchell <mark@markmitchell.com> + + * splay-tree.h: New file. + +Fri Oct 9 00:02:03 1998 Jeffrey A Law (law@cygnus.com) + + * Merge devo and egcs include directories. + +Sat Sep 5 12:16:33 1998 Jeffrey A Law (law@cygnus.com) + + * getopt.h, obstack.h: Updated from gcc. + +1998-08-03 Jason Molenda (jsm@bugshack.cygnus.com) + + * libiberty.h (xexit): Change decl to use modern GCC attribute + to indicate exit does not return. + +Mon Jun 1 13:48:32 1998 Jason Molenda (crash@bugshack.cygnus.com) + + * obstack.h: Update to latest FSF version. + +Tue Feb 24 13:05:02 1998 Doug Evans <devans@canuck.cygnus.com> + + * dis-asm.h (disassemble_info): Member `symbol' renamed to `symbols' + and made an "asymbol **". New member num_symbols. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Update. + +Tue Feb 17 12:32:18 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_fetch_register, sim_store_register): Add + register length parameter. Functions return actual length of + register. + +Thu Feb 12 16:29:01 1998 Ian Lance Taylor <ian@cygnus.com> + + * getopt.h: Update to latest FSF version. + +Wed Feb 11 16:56:06 1998 Doug Evans <devans@canuck.cygnus.com> + + * symcat.h: New file. + +Mon Feb 2 17:13:31 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> + + * dis-asm.h (print_insn_tic30): Declare. + +Thu Jan 22 16:23:59 1998 Fred Fish <fnf@cygnus.com> + + * dis-asm.h: Add flag INSN_HAS_RELOC to tell disassembly + function there is a reloc on this line. + +Mon Dec 8 11:22:23 1997 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Remove prototype of disasm_symaddr() as this function + no longer exists. + +Tue Dec 2 10:20:53 1997 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h (disasm_symaddr): New prototype. + +Mon Dec 1 11:29:35 1997 Doug Evans <devans@canuck.cygnus.com> + + * callback.h (CB_SYSCALL): Comment out arg names in prototypes. + +Wed Nov 26 16:47:58 1997 Michael Meissner <meissner@cygnus.com> + + * callback.h (CB_SYSCALL): Consistantly use names for prototype + arguments. + +Wed Nov 26 11:39:30 1997 Doug Evans <devans@canuck.cygnus.com> + + * callback.h (CB_SYSCALL): Change byte count arguments to + {read,write}_mem to `int'. New member `magic'. + (CB_SYSCALL_MAGIC,CB_SYSCALL_INIT): New macros. + +Tue Nov 25 01:35:52 1997 Doug Evans <devans@seba.cygnus.com> + + * callback.h (struct stat): Move forward decl up. + (host_callback): Pass stat struct pointer to stat,fstat. + (CB_SYS_nnn): Reorganize. + (CB_SYSCALL): New members p1,p2. + (cb_host_to_target_stat): Delete fourth arg. + +Sat Nov 22 23:34:15 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_stop_reason): Clarify sim_signalled SIGRC + argument. + +Mon Nov 17 14:00:51 1997 Doug Evans <devans@seba.cygnus.com> + + * callback.h (CB_TARGET_DEFS_MAP): Renamed from target_defs_map. + (host_callback): Add stat, fstat, syscall_map, errno_map, open_map, + signal_map, stat_map. + (errn_map,open_map): Renamed to cb_init_foo_map. + (cb_host_to_target_errno,cb_target_to_host_open): Renamed from + host_to_target_errno,target_to_host_open. + (cb_read_target_syscall_maps): Add prototype. + (cb_target_to_host_syscall): Likewise. + (cb_host_to_target_stat): Likewise. + (cb_syscall): Likewise. + (CB_SYS_{exit,open,close,read,write,lseek,unlink,getpid,kill,fstat, + argvlen,argv,chdir,stat,chmod,utime,time}): Define. + (CB_SYSCALL): New type. + (CB_RC): New enum. + +Fri Nov 7 10:34:09 1997 Rob Savoye <rob@darkstar.cygnus.com> + + * libiberty.h: Add extern "C" { so it can be used with C++ + programs. + * remote-sim.h: Add extern "C" { so it can be used with C++ + programs. + +Tue Oct 14 16:07:51 1997 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h (struct disassemble_info): New field + 'symbol_at_address_func'. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise new field with + generic_symbol_at_address. + +Mon Oct 13 10:17:15 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h: Clarify sim_read, sim_write MEM argument. + +Wed Sep 24 18:03:10 1997 Stu Grossman <grossman@babylon-5.cygnus.com> + + * remote-sim.h (SIM_RC): Add a bunch of new return codes for + breakpoint stuff. + * Add functions to tell the simulator to set/clear/enable/disable + intrinsic breakpoints. + +Thu Aug 28 19:41:42 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * libiberty.h (dupargv): Add prototype. + +Tue Aug 26 12:25:49 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_create_inferior): Add ABFD arg. Document. + +Mon Aug 25 10:50:51 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_open): Add ABFD arg. Document. + +Fri Aug 8 16:43:56 1997 Doug Evans <dje@canuck.cygnus.com> + + * dis-asm.h (arc_get_disassembler): Declare. + +Wed Jul 30 11:39:50 1997 Per Bothner <bothner@deneb.cygnus.com> + + * demangle.h (DMGL_JAVA): New option to request Java demangling. + +Tue Jul 22 17:59:54 1997 Ian Lance Taylor <ian@cygnus.com> + + * libiberty.h (PEXECUTE_*): Define. + (pexecute, pwait): Declare. + +Fri Jun 6 13:02:33 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_kill): Mark as depreciated. + +Fri May 23 13:43:41 1997 Fred Fish <fnf@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add task_link member. + +Thu May 22 11:32:49 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h: Review documentation. Clarify restrictions on + when functions can be called. + +Wed May 21 16:47:53 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_set_profile_size): Add prototype, document as + depreciated. + +Tue May 20 09:32:22 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_open): Add callback struct. + (sim_set_callbacks): Drop SIM_DESC argument. Document. + (sim_size): Remove recently added SIM_DESC argument. Document. + +Mon May 19 19:14:44 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h: Pass SD into sim_size. + +Thu May 15 01:24:16 1997 Mark Alexander <marka@cygnus.com> + + * obstack.h (obstack_specify_allocation_with_arg, obstack_chunkfun, + obstack_freefun): Eliminate compile warnings in gdb. + +Tue Apr 22 10:24:34 1997 Fred Fish <fnf@cygnus.com> + + * floatformat.h (floatformat_byteorders): Add comments for previous + formats and add floatformat_littlebyte_bigword, primarily for ARM. + Add declaration for floatformat_ieee_double_littlebyte_bigword. + +Fri Apr 18 13:04:49 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_stop): New interface - asynchronous + notification of a request to stop / suspend the running + simulation. + + * remote-sim.h (enum sim_stop): Add sim_running and sim_polling as + states for use internal to simulators. + + * callback.h (struct host_callback_strut): Put a magic number at + the end of the struct to allow basic checking. + (struct host_callback_struct ): Add poll_quit - so + that the console etc can be polled at regular intervals. + +Thu Apr 17 02:17:12 1997 Doug Evans <dje@canuck.cygnus.com> + + * remote-sim.h (struct _bfd): Declare. + (sim_load): Return SIM_RC. New arg `abfd'. + (sim_create_inferior): Return SIM_RC. Delete arg `start_address'. + +Wed Apr 2 17:09:12 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * remote-sim.h (sim_trace, sim_size): Make these global. They + will go away shortly. + +Wed Apr 2 15:23:49 1997 Doug Evans <dje@canuck.cygnus.com> + + * remote-sim.h (SIM_OPEN_KIND, SIM_RC): New enums. + (sim_open): New argument `kind'. + +Wed Apr 2 14:45:51 1997 Ian Lance Taylor <ian@cygnus.com> + + * COPYING: Update FSF address. + +Fri Mar 28 15:29:54 1997 Mike Meissner <meissner@cygnus.com> + + * callback.h (top level): Include stdarg.h or varargs.h if + va_start is not defined. + (host_callback_struct): Make {,e}vprintf_filtered take a va_list + instead of void *, since va_list might be an array or structure + type. + +Fri Mar 28 15:44:41 1997 H.J. Lu <hjl@gnu.ai.mit.edu> + + * libiberty.h (basename): Add prototype for glibc and linux. + +Mon Mar 17 19:22:12 1997 Ian Lance Taylor <ian@cygnus.com> + + * objalloc.h: New file. + +Mon Mar 17 14:57:55 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * remote-sim.h: New file, copied in from gdb/remote-sim.h. One + day this will be placed in a directory of its own. + +Sat Mar 15 19:00:14 1997 Ian Lance Taylor <ian@cygnus.com> + + * obstack.h: Update to current FSF version. + +Thu Mar 6 15:46:59 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * callback.h (struct host_callback_struct): Add callbacks - + flush_stdout, write_stderr, flush_stderr, vprintf_filtered, + evprintf_filtered. Delete redundant callbacks - printf_filtered. + +Thu Feb 27 23:18:27 1997 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Remove lprefix and lprefix_len + fields. + +Tue Feb 25 00:10:49 1997 Ian Lance Taylor <ian@cygnus.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize + bytes_per_chunk and display_endian. + +Mon Feb 24 17:47:02 1997 Ian Lance Taylor <ian@cygnus.com> + + From Eric Youngdale <eric@andante.jic.com>: + * bfdlink.h (struct bfd_elf_version_expr): Define. + (struct bfd_elf_version_deps): Define. + (struct bfd_elf_version_tree): Define. + +Thu Feb 6 14:20:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * dis-asm.h: (disassemble_info): Add new fields + bytes_per_chunk and display_endian to control the + display of raw instructions. + +Fri Dec 27 22:17:37 1996 Fred Fish <fnf@cygnus.com> + + * dis-asm.h (print_insn_tic80): Declare. + +Sun Dec 8 17:11:12 1996 Doug Evans <dje@canuck.cygnus.com> + + * callback.h (host_callback): New member `error'. + +Wed Nov 20 00:40:23 1996 Doug Evans <dje@canuck.cygnus.com> + + * callback.h: New file, moved here from gdb. + +Mon Nov 18 16:34:00 1996 Dawn Perchik <dawn@critters.cygnus.com> + + * libiberty.h: Checkin again; last checkin failed due to sticky tag. + +Wed Nov 13 08:22:00 1996 Dawn Perchik <dawn@critters.cygnus.com> + + * libiberty.h: Revert last commit due to conflicts with hpux + system headers. + +Tue Nov 12 16:31:00 1996 Dawn Perchik <dawn@critters.cygnus.com> + + * libiberty.h: Move prototypes from argv.c here. + +Thu Oct 31 14:56:18 1996 Doug Evans <dje@canuck.cygnus.com> + + * ansidecl.h (VPARAMS,VA_START): Define. + +Fri Oct 25 12:08:04 1996 Ian Lance Taylor <ian@cygnus.com> + + * dis-asm.h (disassemble_info): Add bytes_per_line field. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize bytes_per_line field. + +Thu Oct 24 17:10:01 1996 Ian Lance Taylor <ian@cygnus.com> + + * dis-asm.h (disassemble_info): Add symbol field. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize symbol field. + +Thu Oct 17 11:17:40 1996 Doug Evans <dje@canuck.cygnus.com> + + * dis-asm.h (print_insn_m32r): Declare. + +Mon Oct 14 23:56:52 1996 Ian Lance Taylor <ian@cygnus.com> + + * libiberty.h: Declare parameter types for xmalloc and xrealloc. + +Thu Oct 3 13:45:27 1996 Ian Lance Taylor <ian@cygnus.com> + + * fnmatch.h: New file. + +Thu Oct 3 10:33:14 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_mn10x00): Delete declaration. + (print_insn_mn10200, print_insn_mn10300): Declare. + +Wed Oct 2 21:24:43 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_mn10x00): Declare. + +Mon Sep 30 13:56:11 1996 Fred Fish <fnf@cygnus.com> + + * libiberty.h: Remove #ifndef PRIVATE_XMALLOC. + +Sat Aug 31 13:27:06 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_v850): Declare. + +Tue Aug 13 16:10:30 1996 Stu Grossman (grossman@critters.cygnus.com) + + * obstack.h: Change bcopy to memcpy. Works better on Posix + systems, which generally lack bcopy. + +Mon Aug 12 17:03:18 1996 Stu Grossman (grossman@critters.cygnus.com) + + * ansidecl.h: Change WIN32 to _WIN32. + +Fri Jul 26 13:58:18 1996 Ian Lance Taylor <ian@cygnus.com> + + * dis-asm.h: Add flavour field. + (print_insn_alpha): Declare. + (print_insn_alpha_osf, print_insn_alpha_vms): Don't declare. + (INIT_DISASSEMBLE_INFO): Initialize flavour field. + +Tue Jul 23 17:37:58 1996 Fred Fish <fnf@cygnus.com> + + * libiberty.h (PRIVATE_XMALLOC): Enclose xmalloc/xrealloc + definitions inside #ifndef so that programs that want to + can define PRIVATE_XMALLOC and then define xmalloc and + xrealloc anyway they want. + (basename): Document in source that we can't declare the + parameter type because it is declared inconsistently across + different systems. + +Mon Jul 22 13:16:13 1996 Richard Henderson <rth@tamu.edu> + + * dis-asm.h (print_insn_alpha): Don't declare. + (print_insn_alpha_osf, print_insn_alpha_vms): Declare. + +Wed Jul 17 14:45:12 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * dis-asm.h: (print_insn_d10v): Declare. + +Mon Jul 15 16:55:38 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h: Get rid of decls for print_insn_i8086, + print_insn_sparc64 and print_insn_sparclite. + * (INIT_DISASSEMBLE_INFO): Split into two pieces. One, + INIT_DISASSEMBLE_INFO_NO_ARCH inits everything except for endian, + mach, and arch. + +Fri Jul 12 10:19:27 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h (print_insn_i8086): Declare. + +Wed Jul 3 16:02:39 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h (print_insn_sparclite): Declare. + +Tue Jun 18 16:02:46 1996 Jeffrey A. Law <law@rtl.cygnus.com> + + * dis-asm.h (print_insn_h8300s): Declare. + +Tue Jun 18 15:11:33 1996 Klaus Kaempf <kkaempf@progis.de> + + * fopen-vms.h: New file. + +Tue Jun 4 18:58:16 1996 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add notice_all field. + +Fri Apr 26 10:33:12 1996 Doug Evans <dje@canuck.cygnus.com> + + * demangle.h (#ifdef IN_GCC): #include "gansidecl.h". + (PROTO,PTR,const): Delete. + +Mon Apr 22 17:27:42 1996 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add traditional_format field. + +Mon Apr 15 15:16:56 1996 Doug Evans <dje@canuck.cygnus.com> + + * libiberty.h (choose_temp_base): Add prototype. + +Tue Mar 12 17:29:46 1996 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (bfd_wrapped_link_hash_lookup): Declare. + (struct bfd_link_info): Add wrap_hash field. + +Wed Feb 14 16:49:17 1996 Martin Anantharaman <martin@mail.imech.uni-duisburg.de> + + * ieee.h (ieee_record_enum_type): Define + ieee_external_reference_info_enum. + +Fri Feb 2 17:09:25 1996 Doug Evans <dje@charmed.cygnus.com> + + * dis-asm.h (DISASM_RAW_INSN): Delete. + +Tue Jan 23 09:21:47 1996 Doug Evans <dje@charmed.cygnus.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO): Set endian to BFD_ENDIAN_UNKNOWN. + New argument FPRINTF_FUNC. + +Mon Jan 22 16:37:59 1996 Doug Evans <dje@charmed.cygnus.com> + + * dis-asm.h (disassemble_info): New members arch, mach, endian. + (INIT_DISASSEMBLE_INFO): Initialize them. + (DISASM_RAW_INSN{,FLAG}): Define. + +Thu Jan 18 11:32:38 1996 Ian Lance Taylor <ian@cygnus.com> + + * demangle.h (cplus_demangle_opname): Change opname parameter to + const char *. + (cplus_mangle_opname): Change return type and opname parameter to + const char *. + +Fri Jan 5 00:01:22 1996 Ian Lance Taylor <ian@cygnus.com> + + * ieee.h (enum ieee_record): Add ieee_asn_record_enum, + ieee_at_record_enum, ieee_ty_record_enum, ieee_atn_record_enum, + ieee_bb_record_enum, and ieee_be_record_enum. + +Wed Jan 3 13:12:09 1996 Fred Fish <fnf@cygnus.com> + + * obstack.h: Update copyright to 1996. + (_obstack_memory_used): Declare. + (obstack_memory_used): Define macro. + +Thu Dec 28 11:42:12 1995 Ian Lance Taylor <ian@cygnus.com> + + * libiberty.h (xstrdup): Declare. + +Thu Dec 21 14:47:17 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * wait.h: Protect all macros with #ifndef. + +Tue Oct 24 21:45:40 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add static_link field. + +Tue Sep 12 16:28:04 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_callbacks): Add symbol parameter to + warning callback. + +Fri Sep 1 13:11:51 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_callbacks): Change warning callback + to take BFD, section, and address arguments. + +Thu Aug 31 16:45:12 1995 steve chamberlain <sac@slash.cygnus.com> + + * bfdlink.h (struct bfd_link_info): Remove PE stuff. + +Tue Aug 22 03:18:23 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com> + + * libiberty.h: Declare xstrerror. From Pat Rankin. + +Mon Aug 21 18:11:36 1995 steve chamberlain <sac@slash.cygnus.com> + + * bfdlink.h (struct bfd_link_info): Remove PE stuff. + +Wed Aug 2 08:14:12 1995 Doug Evans <dje@canuck.cygnus.com> + + * dis-asm.h (print_insn_sparc64): Declare. + +Mon Jul 10 13:26:49 1995 Eric Youngdale <eric@aib.com> + + * bfdlink.h (struct bfd_link_info): Add new field symbolic. + +Sun Jul 2 17:48:40 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Change type of base_file to + PTR. + +Thu Jun 29 00:02:45 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * bfdlink.h (struct bfd_link_info): Added base_file member. + +Tue Jun 20 16:40:04 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * ansidecl.h: win32s is ANSI enough. + +Thu May 18 04:25:50 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com> + + Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) + + * dis-asm.h (print_insn_arm): Delete declaration. + (print_insn_{little,big}_arm): New declarations. + + * floatformat.h (floatformat_arm_ext): Declare. + +Sat May 13 10:14:08 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * bfdlink.h (subsytem, stack_heap_parameters): New. + +Thu May 4 14:36:42 1995 Jason Merrill <jason@phydeaux.cygnus.com> + + * demangle.h: Don't include ansidecl.h if IN_GCC. + +Tue Feb 21 00:37:28 1995 Jeff Law (law@snake.cs.utah.edu) + + * hp-symtab.h: Don't use bitfield enumerations, the HP C compiler + does not handle them correctly. + +Thu Feb 9 14:20:27 1995 Ian Lance Taylor <ian@cygnus.com> + + * libiberty.h (basename): Don't declare parameter type; some + systems have this in their header files. + +Wed Feb 8 17:35:38 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_hash_entry): Change format of common + symbol information, to remove restrictions on maximum size and + alignment power, by using a pointer to a structure instead. + +Mon Feb 6 14:55:32 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (enum bfd_link_hash_type): Rename bfd_link_hash_weak + to bfd_link_hash_undefweak. Add bfd_link_hash_defweak. + +Mon Jan 16 21:00:23 1995 Stan Shebs <shebs@andros.cygnus.com> + + * dis-asm.h (GDB_INIT_DISASSEMBLE_INFO, etc): Remove all + GDB-specific definitions. + +Sun Jan 15 18:39:35 1995 Steve Chamberlain <sac@splat> + + * dis-asm.h (print_insn_w65): Declare. + +Thu Jan 12 17:51:17 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * libiberty.h (hex_p): Fix sense of test. + +Wed Jan 11 22:36:40 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * libiberty.h (_hex_array_size, _hex_bad, _hex_value, hex_init, + hex_p, hex_value): New macros and declarations, for hex.c. + +Fri Jan 6 17:44:14 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * dis-asm.h: Make idempotent. + +Wed Dec 14 13:08:43 1994 Stan Shebs <shebs@andros.cygnus.com> + + * progress.h: New file, empty definitions for progress macros. + +Fri Nov 25 00:14:05 1994 Jeff Law (law@snake.cs.utah.edu) + + * hp-symtab.h: New file describing the debug symbols emitted + by the HP C compilers. + +Fri Nov 11 15:48:37 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * bfdlink.h (struct bfd_link_hash_entry): Change u.c.size from 24 + to 26 bits, and change u.c.alignment_power from 8 to 6 bits. 6 + bit in the alignment power is enough for a 64 bit address space. + +Mon Oct 31 13:02:51 1994 Stan Shebs (shebs@andros.cygnus.com) + + * demangle.h (cplus_mangle_opname): Declare. + +Tue Oct 25 11:38:02 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * bfdlink.h (struct bfd_link_callbacks): Fix comments for + multiple_common field. + +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * dis-asm.h: Add support for the ARM. + +Wed Aug 10 12:51:41 1994 Doug Evans (dje@canuck.cygnus.com) + + * libiberty.h (strsignal): Document its existence even if we + can't declare it. + +Tue Aug 2 14:40:03 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * os9k.h: Remove u_int16, u_int32, and owner_id typedefs and + expand their uses. Those names conflict with Mach headers. + +Fri Jul 22 14:17:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * bfdlink.h (struct bfd_link_hash_entry): Change u.c.size into a + bitfield. Add field u.c.alignment_power. + +Sun Jul 10 00:26:39 1994 Ian Dall (dall@hfrd.dsto.gov.au) + + * dis-asm.h: Add print_insn_ns32k declaration. + +Mon Jun 20 17:13:29 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * bfdlink.h (bfd_link_hash_table): Make creator a const pointer. + +Sat Jun 18 16:09:32 1994 Stan Shebs (shebs@andros.cygnus.com) + + * demangle.h (cplus_demangle_opname): Declare. + +Thu Jun 16 15:19:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_info): Add new field shared. + +Mon Jun 6 14:39:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_hash_entry): Remove written field: + not needed for all backends. + +Thu Apr 28 19:06:50 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * dis-asm.h (disassembler): Declare. + +Fri Apr 1 00:38:17 1994 Jim Wilson (wilson@mole.gnu.ai.mit.edu) + + * obstack.h: Delete use of IN_GCC to control whether + stddef.h or gstddef.h is included. + +Tue Mar 22 13:06:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (enum bfd_link_order_type): Add bfd_data_link_order. + (struct bfd_link_order): Add data field to union. + +Mon Mar 21 18:45:26 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Change bitsize argument + to add_to_set to reloc. Remove bitsize argument from constructor. + Comment that reloc_overflow, reloc_dangerous and unattached_reloc + must handle NULL pointers for reloc location. + (enum bfd_link_order_type): Add bfd_section_reloc_link_order and + bfd_symbol_reloc_link_order. + (struct bfd_link_order): Add reloc field to union. + (struct bfd_link_order_reloc): Define. + +Mon Mar 14 12:27:50 1994 Ian Lance Taylor (ian@cygnus.com) + + * ieee-float.h: Removed; no longer used. + +Tue Mar 1 18:10:49 1994 Kung Hsu (kung@mexican.cygnus.com) + + * os9k.h: os9000 target specific header file, the header of the + object file is used now. + +Sun Feb 27 21:52:26 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * floatformat.h: New file, intended to replace ieee-float.h. + +Sun Feb 20 17:15:42 1994 Ian Lance Taylor (ian@lisa.cygnus.com) + + * ansidecl.h (ANSI_PROTOTYPES): Define if using ANSI prototypes. + +Wed Feb 16 01:07:12 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * libiberty.h: Don't declare strsignal, to avoid conflicts with + Solaris system header files. + +Sat Feb 12 22:11:32 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * libiberty.h (xexit): Use __volatile__ to avoid losing if + compiling with gcc -traditional. + +Thu Feb 10 14:05:41 1994 Ian Lance Taylor (ian@cygnus.com) + + * libiberty.h: New file. Declares functions provided by + libiberty. + +Tue Feb 8 05:19:52 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + Handle obstack_chunk_alloc returning NULL. This allows + obstacks to be used by libraries, without forcing them + to call exit or longjmp. + * obstack.h (struct obstack): Add alloc_failed flag. + _obstack_begin, _obstack_begin_1): Declare to return int, not void. + (obstack_finish): If alloc_failed, return NULL. + (obstack_base, obstack_next_free, objstack_object_size): + If alloc_failed, return 0. + (obstack_grow, obstack_grow0, obstack_1grow, obstack_ptr_grow, + obstack_int_grow, obstack_blank): If alloc_failed, do nothing that + could corrupt the obstack. + +Mon Jan 24 15:06:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Add name, reloc_name and + addend argments to reloc_overflow callback. + +Fri Jan 21 19:13:12 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h (print_insn_big_powerpc, print_insn_little_powerpc, + print_insn_rs6000): Declare. + +Thu Jan 6 14:15:55 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Add bitsize argument to + add_to_set field. Add new callback named constructor. + +Thu Dec 30 10:44:06 1993 Ian Lance Taylor (ian@rtl.cygnus.com) + + * bfdlink.h: New file for new BFD linker backend routines. + +Mon Nov 29 10:43:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h (enum dis_insn_tyupe): Remove non-ANSI trailing comma. + +Sat Oct 2 20:42:26 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h: Move comment to right place. + +Mon Aug 9 19:03:35 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * obstack.h (obstack_chunkfun, obstack_freefun): Add defns from + previous version. Are these Cygnus local changes? + +Fri Aug 6 17:05:47 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * getopt.h, obstack.h: Update to latest FSF version. + +Mon Aug 2 14:45:29 1993 John Gilmore (gnu@cygnus.com) + + * dis-asm.h: Move enum outside of struct defn to avoid warnings. + +Mon Aug 2 08:49:30 1993 Stu Grossman (grossman at cygnus.com) + + * wait.h (WEXITSTATUS, WSTOPSIG): Mask down to 8 bits. This is + for systems that store stuff into the high 16 bits of a wait + status. + +Fri Jul 30 18:38:02 1993 John Gilmore (gnu@cygnus.com) + + * dis-asm.h: Add new fields insn_info_valid, branch_delay_insns, + data_size, insn_type, target, target2. These are used to return + information from the instruction decoders back to the calling + program. Add comments, make more readable. + +Mon Jul 19 22:14:14 1993 Fred Fish (fnf@deneb.cygnus.com) + + * nlm: New directory containing NLM/NetWare includes. + +Thu Jul 15 12:10:04 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * dis-asm.h (struct disassemble_info): New field application_data. + +Thu Jul 15 12:41:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h: Added declaration of print_insn_m88k. + +Fri Jul 2 10:31:59 1993 Ian Lance Taylor (ian@cygnus.com) + + * ansidecl.h: Use ANSI macros if __mips and _SYSTYPE_SVR4 are + defined, since RISC/OS cc handles ANSI declarations in SVR4 mode + but does not define __STDC__. + +Sun Jun 20 18:27:52 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) + + * dis-asm.h: Don't need to include ansidecl.h any more. + +Fri Jun 18 03:22:10 1993 John Gilmore (gnu@cygnus.com) + + * oasys.h: Eliminate "int8_type", "int16_type", "int32_type", and + their variants. These changes are coordinated with corresponding + changes in ../bfd/oasys.c. + +Wed Jun 16 10:43:08 1993 Fred Fish (fnf@cygnus.com) + + * bfd.h: Note that it has been removed. + +Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + Support for H8/300-H + * dis-asm.h (print_insn_h8300, print_insn_h8300h): Declare it. + +Tue Jun 1 07:35:03 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * ansidecl.h (const): Don't define it if it's already defined. + +Thu May 27 18:19:51 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * dis-asm.h (print_insn_hppa): Declare it. + + * bfd.h: Moved to bfd directory. Small stub here includes it + without requiring "-I../bfd". + +Thu Apr 29 12:06:13 1993 Ken Raeburn (raeburn@deneb.cygnus.com) + + * bfd.h: Updated with BSF_FUNCTION. + +Mon Apr 26 18:15:50 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h, dis-asm.h: Updated with Hitachi SH. + +Fri Apr 23 18:41:38 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: Updated with alpha changes. + * dis-asm.h: Added alpha. + +Fri Apr 16 17:35:30 1993 Jim Kingdon (kingdon@cygnus.com) + + * bfd.h: Update for signed bfd_*get_*. + +Thu Apr 15 09:24:21 1993 Jim Kingdon (kingdon@cygnus.com) + + * bfd.h: Updated for file_truncated error. + +Thu Apr 8 10:53:47 1993 Ian Lance Taylor (ian@cygnus.com) + + * ansidecl.h: If no ANSI, define const to be empty. + +Thu Apr 1 09:00:10 1993 Jim Kingdon (kingdon@cygnus.com) + + * dis-asm.h: Declare a29k and i960 print_insn_*. + + * dis-asm.h: Add print_address_func and related stuff. + + * dis-asm.h (dis_asm_read_memory): Fix prototype. + +Wed Mar 31 17:40:16 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h: Add print_insn_sparc. + +Wed Mar 31 17:51:42 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Updated for BFD_RELOC_MIPS_GPREL and bfd_[gs]et_gp_size + prototypes. + +Wed Mar 31 16:35:12 1993 Stu Grossman (grossman@cygnus.com) + + * dis-asm.h: (disassemble_info): Fix typo in prototype of + dis_asm_memory_error(). + +Tue Mar 30 19:09:23 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h (disassembler_info): Add read_memory_func, + memory_error_func, buffer, and length. + ({GDB_,}INIT_DISASSEMBLE_INFO): Set them. + print_insn_*: Remove second argument. + +Tue Mar 30 14:48:55 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: Update for lma field of section. + +Tue Mar 30 12:22:55 1993 Jim Kingdon (kingdon@cygnus.com) + + * ansidecl.h: Use ANSI versions on AIX regardless of __STDC__. + +Fri Mar 19 14:49:49 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * dis-asm.h: Add h8500. + +Thu Mar 18 13:49:09 1993 Per Bothner (bothner@rtl.cygnus.com) + + * ieee-float.h: Moved from ../gdb. + * dis-asm.h: New file. Interface to dis-assembler. + +Thu Mar 11 10:52:57 1993 Fred Fish (fnf@cygnus.com) + + * demangle.h (DMGL_NO_OPTS): Add define (set to 0) to use + in place of bare 0, for readability reasons. + +Tue Mar 2 17:50:11 1993 Fred Fish (fnf@cygnus.com) + + * demangle.h: Replace all references to cfront with ARM. + +Tue Feb 23 12:21:14 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update for new elements in JUMP_TABLE. + +Tue Feb 16 00:51:30 1993 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update for BFD_VERSION 2.1. + +Tue Jan 26 11:49:20 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update for SEC_IS_COMMON flag. + +Tue Jan 19 12:25:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfd.h: Update for bfd_asymbol_value bug fix. + +Fri Jan 8 16:37:18 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfd.h: Update to include ECOFF tdata and target_flavour. + +Sun Dec 27 17:52:30 1992 Fred Fish (fnf@cygnus.com) + + * bfd.h: Add declaration for bfd_get_size(). + +Tue Dec 22 22:42:46 1992 Fred Fish (fnf@cygnus.com) + + * demangle.h: Protect file from multiple inclusions with + #if !defined(DEMANGLE_H)...#define DEMANGLE_H...#endif. + +Mon Dec 21 21:25:50 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h: Update to get hppa_core_struct from bfd.c. + +Thu Dec 17 00:42:35 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update to get tekhex tdata name change from bfd. + +Mon Nov 9 23:55:42 1992 John Gilmore (gnu@cygnus.com) + + * ansidecl.h: Update comments to discourage use of EXFUN. + +Thu Nov 5 16:35:44 1992 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update to bring in SEC_SHARED_LIBRARY. + +Thu Nov 5 03:21:32 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update to match EXFUN, bfd_seclet_struct, and SDEF + cleanups in bfd. + +Wed Nov 4 07:28:05 1992 Ken Raeburn (raeburn@cygnus.com) + + * bout.h (N_CALLNAME, N_BALNAME): Define as char-type values, so + widening works consistently. + +Fri Oct 16 03:17:08 1992 John Gilmore (gnu@cygnus.com) + + * getopt.h: Update to Revised Standard FSF Version. + +Thu Oct 15 21:43:22 1992 K. Richard Pixley (rich@sendai.cygnus.com) + + * getopt.h (struct option): use the provided enum for has_arg. + + * demangle.h (AUTO_DEMANGLING, GNU_DEMANGLING, + LUCID_DEMANGLING): ultrix compilers require enums to be + enums and ints to be ints and casts where they meet. cast some + enums into ints. + +Thu Oct 15 04:35:51 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update after comment changes. + +Thu Oct 8 09:03:02 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h (bfd_get_symbol_leading_char): new macro for getting in xvec + +Thu Sep 3 09:10:50 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h (struct reloc_howto_struct): size needs to be signed if + it's going to hold negative values. + +Sun Aug 30 17:50:27 1992 Per Bothner (bothner@rtl.cygnus.com) + + * demangle.h: New file, moved from ../gdb. Made independent + of gdb. Allow demangling style option to be passed as a + parameter to cplus_demangle(), but using the + current_demangling_style global as the default. + +Sat Aug 29 10:07:55 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Merge comment change from current FSF version. + +Thu Aug 27 12:59:29 1992 Brendan Kehoe (brendan@cygnus.com) + + * bfd.h: add we32k + +Tue Aug 25 15:07:47 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: new after Z8000 stuff + +Mon Aug 17 09:01:23 1992 Ken Raeburn (raeburn@cygnus.com) + + * bfd.h: Regenerated after page/segment size changes. + +Sat Aug 1 13:46:31 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Merge changes from current FSF version. + +Mon Jul 20 21:06:23 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h (area_id, flags): Remove, replace with extra_arg, + use_extra_arg, and maybe_empty_object. + * obstack.h (OBSTACK_MAYBE_EMPTY_OBJECT, OBSTACK_MMALLOC_LIKE): + Remove, replaced by maybe_empty_object and use_extra_arg bitfields. + * obstack.h (obstack_full_begin, _obstack_begin): Remove area_id + and flags arguments. + * obstack.h (obstack_alloc_arg): New macro to set extra_arg. + +Thu Jul 16 08:12:44 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: new after adding BFD_IS_RELAXABLE + +Sat Jul 4 03:22:23 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Regen after adding BSF_FILE. + +Mon Jun 29 14:18:36 1992 Fred Fish (fnf at sunfish) + + * obstack.h: Convert bcopy() use to memcpy(), which is more + portable, more standard, and can take advantage of gcc's builtin + functions for increased performance. + +Thu Jun 25 04:46:08 1992 John Gilmore (gnu at cygnus.com) + + * ansidecl.h (PARAMS): Incorporate this macro from gdb's defs.h. + It's a cleaner way to forward-declare function prototypes. + +Fri Jun 19 15:46:32 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h: HPPA merge. + +Tue Jun 16 21:30:56 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: gratuitous white space changes merged from other prep + releases. + +Thu Jun 11 01:10:55 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Regen'd from bfd.c after removing elf_core_tdata_struct. + +Mon May 18 17:29:03 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: merged changes from make-3.62.11. + + * getopt.h: merged changes from grep-1.6 (alpha). + +Fri May 8 14:53:32 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: merged changes from bison-1.18. + +Sat Mar 14 17:25:20 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Add "area_id" and "flags" members to obstack + structure. Add obstack_chunkfun() and obstack_freefun() to + set functions explicitly. Convert maybe_empty_object to + a bit in "flags". + +Thu Feb 27 22:01:02 1992 Per Bothner (bothner@cygnus.com) + + * wait.h (WIFSTOPPED): Add IBM rs6000-specific version. + +Fri Feb 21 20:49:20 1992 John Gilmore (gnu at cygnus.com) + + * obstack.h: Add obstack_full_begin. + * bfd.h, obstack.h: Protolint. + +Thu Jan 30 01:18:42 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Remove comma from enum declaration. + +Mon Jan 27 22:01:13 1992 Steve Chamberlain (sac at cygnus.com) + + * bfd.h : new target entr, bfd_relax_section + +Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) + + * bfd.h, ieee.h: ANSIfy enums. + +Thu Dec 12 20:59:56 1991 John Gilmore (gnu at cygnus.com) + + * fopen-same.h, fopen-bin.h: New files for configuring + whether fopen distinguishes binary files or not. For use + by host-dependent config files. + +Sat Nov 30 20:46:43 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * bfd.h: change the documentation format. + + * created coff, elf and opcode and aout directories. Moved: + + aout64.h ==> aout/aout64.h + ar.h ==> aout/ar.h + a.out.encap.h ==> aout/encap.h + a.out.host.h ==> aout/host.h + a.out.hp.h ==> aout/hp.h + a.out.sun4.h ==> aout/sun4.h + ranlib.h ==> aout/ranlib.h + reloc.h ==> aout/reloc.h + stab.def ==> aout/stab.def + stab.gnu.h ==> aout/stab_gnu.h + + coff-a29k.h ==> coff/a29k.h + coff-h8300.h ==> coff/h8300.h + coff-i386.h ==> coff/i386.h + coff-i960.h ==> coff/i960.h + internalcoff.h ==> coff/internal.h + coff-m68k.h ==> coff/m68k.h + coff-m88k.h ==> coff/m88k.h + coff-mips.h ==> coff/mips.h + coff-rs6000.h ==> coff/rs6000.h + + elf-common.h ==> elf/common.h + dwarf.h ==> elf/dwarf.h + elf-external.h ==> elf/external.h + elf-internal.h ==> elf/internal.h + + a29k-opcode.h ==> opcode/a29k.h + arm-opcode.h ==> opcode/arm.h + h8300-opcode.h ==> opcode/h8300.h + i386-opcode.h ==> opcode/i386.h + i860-opcode.h ==> opcode/i860.h + i960-opcode.h ==> opcode/i960.h + m68k-opcode.h ==> opcode/m68k.h + m88k-opcode.h ==> opcode/m88k.h + mips-opcode.h ==> opcode/mips.h + np1-opcode.h ==> opcode/np1.h + ns32k-opcode.h ==> opcode/ns32k.h + pn-opcode.h ==> opcode/pn.h + pyr-opcode.h ==> opcode/pyr.h + sparc-opcode.h ==> opcode/sparc.h + tahoe-opcode.h ==> opcode/tahoe.h + vax-opcode.h ==> opcode/vax.h + + + +Wed Nov 27 10:38:31 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * internalcoff.h: (internal_scnhdr) took out #def dependency, now + s_nreloc and s_nlnno are always long. (internal_reloc): allways + has an offset field now. + +Fri Nov 22 08:12:58 1991 John Gilmore (gnu at cygnus.com) + + * coff-rs6000.h: Lint; use unsigned chars for external fields. + * internalcoff.h: Lint; cast storage classes to signed char. + +Thu Nov 21 21:01:05 1991 Per Bothner (bothner at cygnus.com) + + * stab.def: Remove the GNU extended type codes (e.g. N_SETT). + * aout64.h: The heuristic for distinguishing between + sunos-style and bsd-style ZMAGIC files (wrt. where the + text segment starts) is moved into (the default definition of) + the macro N_HEADER_IN_TEXT. This definition is only used + if no other definition is used - e.g. bfd/newsos3.c defines + N_HEADER_IN_TEXT(x) to be always 0 (as before). + +Thu Nov 21 11:53:03 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h (N_TXTADDR, N_TXTOFF, N_TXTSIZE): New definitions + that should handle all uses. LOGICAL_ versions deleted. + Eliminate N_HEADER_IN_TEXT, using a_entry to determine which + kind of zmagic a.out file we are looking at. + * coff-rs6000.h: Typo. + +Tue Nov 19 18:43:37 1991 Per Bothner (bothner at cygnus.com) + + (Note: This is a revised entry, as was aout64.h.) + * aout64.h: Some cleanups of N_TXTADDR and N_TXTOFF: + Will now work for both old- and new-style ZMAGIC files, + depending on N_HEADER_IN_TEXT macro. + Add LOGICAL_TXTADDR, LOICAL_TXTOFF and LOGICAL_TXTSIZE + that don't count the exec header as part + of the text segment, to be consistent with bfd. + * a.out.sun4.h: Simplified/fixed for previous change. + +Mon Nov 18 00:02:06 1991 Fred Fish (fnf at cygnus.com) + + * dwarf.h: Update to DWARF draft 5 version from gcc2. + +Thu Nov 14 19:44:59 1991 Per Bothner (bothner at cygnus.com) + + * stab.def: Added defs for extended GNU symbol types, + such as N_SETT. These are normally ifdef'd out (because + of conflicts with a.out.gnu.h), but are used by bfb_stab_name(). + +Thu Nov 14 19:17:03 1991 Fred Fish (fnf at cygnus.com) + + * elf-common.h: Add defines to support ELF symbol table code. + +Mon Nov 11 19:01:06 1991 Fred Fish (fnf at cygnus.com) + + * elf-internal.h, elf-external.h, elf-common.h: Add support for + note sections, which are used in ELF core files to hold copies + of various /proc structures. + +Thu Nov 7 08:58:26 1991 Steve Chamberlain (sac at cygnus.com) + + * internalcoff.h: took out the M88 dependency in the lineno + struct. + * coff-m88k.h: defines GET_LINENO_LNNO and PUT_LINENO_LNNO to use + 32bit linno entries. + * a29k-opcode.h: fixed encoding of mtacc + +Sun Nov 3 11:54:22 1991 Per Bothner (bothner at cygnus.com) + + * bfd.h: Updated from ../bfd/bfd-in.h (q.v). + +Fri Nov 1 11:13:53 1991 John Gilmore (gnu at cygnus.com) + + * internalcoff.h: Add x_csect defines. + +Fri Oct 25 03:18:20 1991 John Gilmore (gnu at cygnus.com) + + * Rename COFF-related files in `coff-ARCH.h' form. + coff-a29k.h, coff-i386.h, coff-i960.h, coff-m68k.h, coff-m88k.h, + coff-mips.h, coff-rs6000.h to be exact. + +Thu Oct 24 22:11:11 1991 John Gilmore (gnu at cygnus.com) + + RS/6000 support, by Metin G. Ozisik, Mimi Phûông-Thåo Võ, and + John Gilmore. + + * a.out.gnu.h: Update slightly. + * bfd.h: Add new error code, fix doc, add bfd_arch_rs6000. + * internalcoff.h: Add more F_ codes for filehdr. Add + rs/6000-dependent fields to aouthdr. Add storage classes + to syments. Add 6000-specific auxent. Add r_size in reloc. + * rs6000coff.c: New file. + +Thu Oct 24 04:13:20 1991 Fred Fish (fnf at cygnus.com) + + * dwarf.h: New file for dwarf support. Copied from gcc2 + distribution. + +Wed Oct 16 13:31:45 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h: Remove PAGE_SIZE defines; they are target-dependent. + Add N_FN_SEQ for N_FN symbol type used on Sequent machines. + * stab.def: Include N_FN_SEQ in table. + * bout.h: External formats of structures use unsigned chars. + +Fri Oct 11 12:40:43 1991 Steve Chamberlain (steve at cygnus.com) + + * bfd.h:upgrade from bfd.c + * internalcoff.h: add n_name, n_zeroes and n_offset macros + * amdcoff.h: Define OMAGIC and AOUTHDRSZ. + +Fri Oct 11 10:58:06 1991 Per Bothner (bothner at cygnus.com) + + * a.out.host.h: Change SEGMENT_SIZE to 0x1000 for Sony. + * bfd.h (align_power): Add (actually move) comment. + +Tue Oct 8 15:29:32 1991 Per Bothner (bothner at cygnus.com) + + * sys/h-rtbsd.h: Define MISSING_VFPRINT (for binutils/bucomm.c). + +Sun Oct 6 19:24:39 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h: Move struct internal_exec to ../bfd/libaout.h so + it can be shared by all `a.out-family' code. Rename + EXTERNAL_LIST_SIZE to EXTERNAL_NLIST_SIZE. Use basic types + for nlist members, and make strx integral rather than pointer. + More commentary on n_type values. + * bout.h: Provide a struct external_exec rather than an + internal_exec. + * m68kcoff.h: Remove `tagentries' which snuck in from the i960 + COFF port. + +Fri Oct 4 01:25:59 1991 John Gilmore (gnu at cygnus.com) + + * h8300-opcode.h: Remove `_enum' from the typedef for an enum. + * bfd.h: Update to match bfd changes. + + * sys/h-i386mach.h, sysdep.h: Add 386 Mach host support. + +Tue Oct 1 04:58:42 1991 John Gilmore (gnu at cygnus.com) + + * bfd.h, elf-common.h, elf-external.h, elf-internal.h: + Add preliminary ELF support, sufficient for GDB, from Fred Fish. + * sysdep.h, sys/h-amix.h: Support Amiga SVR4. + + * sys/h-vaxult.h: Make it work. (David Taylor <taylor@think.com>) + * a.out.vax.h: Remove unused and confusing file. + +Mon Sep 30 12:52:35 1991 Per Bothner (bothner at cygnus.com) + + * sysdep.h: Define NEWSOS3_SYS, and use it. + +Fri Sep 20 13:38:21 1991 John Gilmore (gnu at cygnus.com) + + * a.out.gnu.h (N_FN): Its value *really is* 0x1F. + Fix it, and add comments warning about or-ing N_EXT with it + and/or N_WARNING. + * aout64.h (N_FN): Fix value, add comments about N_EXT. + * stab.def (table at end): Update to show all the type + values <0x20, including low order bits. Move N_FN to + its rightful place. + +Tue Sep 17 17:41:37 1991 Stu Grossman (grossman at cygnus.com) + + * sys/h-irix3.h: sgi/irix support. + +Tue Sep 17 07:52:59 1991 John Gilmore (gnu at cygint.cygnus.com) + + * stab.def (N_DEFD): Add GNU Modula-2 debug stab, from Andrew + Beers. + +Thu Sep 12 14:12:59 1991 John Gilmore (gnu at cygint.cygnus.com) + + * internalcoff.h (SYMNMLEN, FILNMLEN, DIMNUM): Define these + for internalcoff, separately from the various external coff's. + * amdcoff.h, bcs88kcoff.h, i386coff.h, intel-coff.h, m68kcoff.h, + m88k-bcs.h: Prefix SYMNMLEN, FILNMLEN, and DIMNUM with E_'s for + the external struct definitions. + * ecoff.h: Remove these #define's, kludge no longer needed. + + * sys/h-ultra3.h: Add new Ultracomputer host. + * sysdep.h: Add ULTRA3_SYM1_SYS and use it. + +Tue Sep 10 10:11:46 1991 John Gilmore (gnu at cygint.cygnus.com) + + * i386coff.h (LINESZ): Always 6, not based on sizeof(). + (Fix from Peter Schauer <pes@regent.e-technik.tu-muenchen.de>.) + +Wed Sep 4 08:58:37 1991 John Gilmore (gnu at cygint.cygnus.com) + + * a.out.gnu.h, aout64.h: Add N_WARNING. Change N_FN to 0x0E, + to match SunOS and BSD. Add N_COMM as 0x12 for SunOS shared lib + support. + * stab.def: Add N_COMM to table, fix overlap comment. + +Tue Sep 3 06:29:20 1991 John Gilmore (gnu at cygint.cygnus.com) + + Merge with latest FSF versions of these files. + + * stab.gnu.h: Add LAST_UNUSED_STAB_CODE. + * stab.def: Update to GPL2. Move N_WARNING out, since not a + debug symbol. Change comments, and reorder table to numeric + order. Update final table comment. + (N_DSLINE, N_BSLINE): Renumber from 0x66 and 0x68, to 0x46 and 0x48. + + * obstack.h: GPL2. Merge. + +Fri Aug 23 01:54:23 1991 John Gilmore (gnu at cygint.cygnus.com) + + * a.out.gnu.h, a.out.sun4.h: Make SEGMENT_SIZE able to depend + on the particular a.out being examined. + * a.out.sun4.h: Define segment sizes for Sun-3's and Sun-4's. + * FIXME: a.out.gnu.h is almost obsolete. + * FIXME: a.out.sun4.h should be renamed a.out.sun.h now. + +Wed Aug 21 20:32:13 1991 John Gilmore (gnu at cygint.cygnus.com) + + * Start a ChangeLog for the includes directory. + + * a.out.gnu.h (N_FN): Fix value -- was 15, should be 0x1E. + * stab.def: Update allocation table in comments at end, + to reflect reality as I know it. + + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/include/MAINTAINERS b/include/MAINTAINERS new file mode 100644 index 000000000..d59a3bd7f --- /dev/null +++ b/include/MAINTAINERS @@ -0,0 +1 @@ +See ../binutils/MAINTAINERS diff --git a/include/alloca-conf.h b/include/alloca-conf.h new file mode 100644 index 000000000..9c3eea396 --- /dev/null +++ b/include/alloca-conf.h @@ -0,0 +1,24 @@ +#include "config.h" + +#if defined(__GNUC__) && !defined(C_ALLOCA) +# ifndef alloca +# define alloca __builtin_alloca +# endif +#else /* ! defined (__GNUC__) */ +# ifdef _AIX + #pragma alloca +# else +# if defined(HAVE_ALLOCA_H) && !defined(C_ALLOCA) +# include <alloca.h> +# else /* ! defined (HAVE_ALLOCA_H) */ +# ifdef __STDC__ +extern PTR alloca (size_t); +# else /* ! defined (__STDC__) */ +extern PTR alloca (); +# endif /* ! defined (__STDC__) */ +# endif /* ! defined (HAVE_ALLOCA_H) */ +# ifdef _WIN32 +# include <malloc.h> +# endif +# endif /* ! defined (_AIX) */ +#endif /* ! defined (__GNUC__) */ diff --git a/include/ansidecl.h b/include/ansidecl.h new file mode 100644 index 000000000..04c3a30bb --- /dev/null +++ b/include/ansidecl.h @@ -0,0 +1,341 @@ +/* ANSI and traditional C compatability macros + Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001 + Free Software Foundation, Inc. + This file is part of the GNU C Library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ANSI and traditional C compatibility macros + + ANSI C is assumed if __STDC__ is #defined. + + Macro ANSI C definition Traditional C definition + ----- ---- - ---------- ----------- - ---------- + ANSI_PROTOTYPES 1 not defined + PTR `void *' `char *' + PTRCONST `void *const' `char *' + LONG_DOUBLE `long double' `double' + const not defined `' + volatile not defined `' + signed not defined `' + VA_START(ap, var) va_start(ap, var) va_start(ap) + + Note that it is safe to write "void foo();" indicating a function + with no return value, in all K+R compilers we have been able to test. + + For declaring functions with prototypes, we also provide these: + + PARAMS ((prototype)) + -- for functions which take a fixed number of arguments. Use this + when declaring the function. When defining the function, write a + K+R style argument list. For example: + + char *strcpy PARAMS ((char *dest, char *source)); + ... + char * + strcpy (dest, source) + char *dest; + char *source; + { ... } + + + VPARAMS ((prototype, ...)) + -- for functions which take a variable number of arguments. Use + PARAMS to declare the function, VPARAMS to define it. For example: + + int printf PARAMS ((const char *format, ...)); + ... + int + printf VPARAMS ((const char *format, ...)) + { + ... + } + + For writing functions which take variable numbers of arguments, we + also provide the VA_OPEN, VA_CLOSE, and VA_FIXEDARG macros. These + hide the differences between K+R <varargs.h> and C89 <stdarg.h> more + thoroughly than the simple VA_START() macro mentioned above. + + VA_OPEN and VA_CLOSE are used *instead of* va_start and va_end. + Immediately after VA_OPEN, put a sequence of VA_FIXEDARG calls + corresponding to the list of fixed arguments. Then use va_arg + normally to get the variable arguments, or pass your va_list object + around. You do not declare the va_list yourself; VA_OPEN does it + for you. + + Here is a complete example: + + int + printf VPARAMS ((const char *format, ...)) + { + int result; + + VA_OPEN (ap, format); + VA_FIXEDARG (ap, const char *, format); + + result = vfprintf (stdout, format, ap); + VA_CLOSE (ap); + + return result; + } + + + You can declare variables either before or after the VA_OPEN, + VA_FIXEDARG sequence. Also, VA_OPEN and VA_CLOSE are the beginning + and end of a block. They must appear at the same nesting level, + and any variables declared after VA_OPEN go out of scope at + VA_CLOSE. Unfortunately, with a K+R compiler, that includes the + argument list. You can have multiple instances of VA_OPEN/VA_CLOSE + pairs in a single function in case you need to traverse the + argument list more than once. + + For ease of writing code which uses GCC extensions but needs to be + portable to other compilers, we provide the GCC_VERSION macro that + simplifies testing __GNUC__ and __GNUC_MINOR__ together, and various + wrappers around __attribute__. Also, __extension__ will be #defined + to nothing if it doesn't work. See below. + + This header also defines a lot of obsolete macros: + CONST, VOLATILE, SIGNED, PROTO, EXFUN, DEFUN, DEFUN_VOID, + AND, DOTS, NOARGS. Don't use them. */ + +#ifndef _ANSIDECL_H +#define _ANSIDECL_H 1 + +/* Every source file includes this file, + so they will all get the switch for lint. */ +/* LINTLIBRARY */ + +/* Using MACRO(x,y) in cpp #if conditionals does not work with some + older preprocessors. Thus we can't define something like this: + +#define HAVE_GCC_VERSION(MAJOR, MINOR) \ + (__GNUC__ > (MAJOR) || (__GNUC__ == (MAJOR) && __GNUC_MINOR__ >= (MINOR))) + +and then test "#if HAVE_GCC_VERSION(2,7)". + +So instead we use the macro below and test it against specific values. */ + +/* This macro simplifies testing whether we are using gcc, and if it + is of a particular minimum version. (Both major & minor numbers are + significant.) This macro will evaluate to 0 if we are not using + gcc at all. */ +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) +#endif /* GCC_VERSION */ + +#if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32) || (defined(__alpha) && defined(__cplusplus)) +/* All known AIX compilers implement these things (but don't always + define __STDC__). The RISC/OS MIPS compiler defines these things + in SVR4 mode, but does not define __STDC__. */ +/* eraxxon@alumni.rice.edu: The Compaq C++ compiler, unlike many other + C++ compilers, does not define __STDC__, though it acts as if this + was so. (Verified versions: 5.7, 6.2, 6.3, 6.5) */ + +#define ANSI_PROTOTYPES 1 +#define PTR void * +#define PTRCONST void *const +#define LONG_DOUBLE long double + +#define PARAMS(ARGS) ARGS +#define VPARAMS(ARGS) ARGS +#define VA_START(VA_LIST, VAR) va_start(VA_LIST, VAR) + +/* variadic function helper macros */ +/* "struct Qdmy" swallows the semicolon after VA_OPEN/VA_FIXEDARG's + use without inhibiting further decls and without declaring an + actual variable. */ +#define VA_OPEN(AP, VAR) { va_list AP; va_start(AP, VAR); { struct Qdmy +#define VA_CLOSE(AP) } va_end(AP); } +#define VA_FIXEDARG(AP, T, N) struct Qdmy + +#undef const +#undef volatile +#undef signed + +/* inline requires special treatment; it's in C99, and GCC >=2.7 supports + it too, but it's not in C89. */ +#undef inline +#if __STDC_VERSION__ > 199901L +/* it's a keyword */ +#else +# if GCC_VERSION >= 2007 +# define inline __inline__ /* __inline__ prevents -pedantic warnings */ +# else +# define inline /* nothing */ +# endif +#endif + +/* These are obsolete. Do not use. */ +#ifndef IN_GCC +#define CONST const +#define VOLATILE volatile +#define SIGNED signed + +#define PROTO(type, name, arglist) type name arglist +#define EXFUN(name, proto) name proto +#define DEFUN(name, arglist, args) name(args) +#define DEFUN_VOID(name) name(void) +#define AND , +#define DOTS , ... +#define NOARGS void +#endif /* ! IN_GCC */ + +#else /* Not ANSI C. */ + +#undef ANSI_PROTOTYPES +#define PTR char * +#define PTRCONST PTR +#define LONG_DOUBLE double + +#define PARAMS(args) () +#define VPARAMS(args) (va_alist) va_dcl +#define VA_START(va_list, var) va_start(va_list) + +#define VA_OPEN(AP, VAR) { va_list AP; va_start(AP); { struct Qdmy +#define VA_CLOSE(AP) } va_end(AP); } +#define VA_FIXEDARG(AP, TYPE, NAME) TYPE NAME = va_arg(AP, TYPE) + +/* some systems define these in header files for non-ansi mode */ +#undef const +#undef volatile +#undef signed +#undef inline +#define const +#define volatile +#define signed +#define inline + +#ifndef IN_GCC +#define CONST +#define VOLATILE +#define SIGNED + +#define PROTO(type, name, arglist) type name () +#define EXFUN(name, proto) name() +#define DEFUN(name, arglist, args) name arglist args; +#define DEFUN_VOID(name) name() +#define AND ; +#define DOTS +#define NOARGS +#endif /* ! IN_GCC */ + +#endif /* ANSI C. */ + +/* Define macros for some gcc attributes. This permits us to use the + macros freely, and know that they will come into play for the + version of gcc in which they are supported. */ + +#if (GCC_VERSION < 2007) +# define __attribute__(x) +#endif + +/* Attribute __malloc__ on functions was valid as of gcc 2.96. */ +#ifndef ATTRIBUTE_MALLOC +# if (GCC_VERSION >= 2096) +# define ATTRIBUTE_MALLOC __attribute__ ((__malloc__)) +# else +# define ATTRIBUTE_MALLOC +# endif /* GNUC >= 2.96 */ +#endif /* ATTRIBUTE_MALLOC */ + +/* Attributes on labels were valid as of gcc 2.93. */ +#ifndef ATTRIBUTE_UNUSED_LABEL +# if (GCC_VERSION >= 2093) +# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED +# else +# define ATTRIBUTE_UNUSED_LABEL +# endif /* GNUC >= 2.93 */ +#endif /* ATTRIBUTE_UNUSED_LABEL */ + +#ifndef ATTRIBUTE_UNUSED +#define ATTRIBUTE_UNUSED __attribute__ ((__unused__)) +#endif /* ATTRIBUTE_UNUSED */ + +/* Before GCC 3.4, the C++ frontend couldn't parse attributes placed after the + identifier name. */ +#if ! defined(__cplusplus) || (GCC_VERSION >= 3004) +# define ARG_UNUSED(NAME) NAME ATTRIBUTE_UNUSED +#else /* !__cplusplus || GNUC >= 3.4 */ +# define ARG_UNUSED(NAME) NAME +#endif /* !__cplusplus || GNUC >= 3.4 */ + +#ifndef ATTRIBUTE_NORETURN +#define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__)) +#endif /* ATTRIBUTE_NORETURN */ + +/* Attribute `nonnull' was valid as of gcc 3.3. */ +#ifndef ATTRIBUTE_NONNULL +# if (GCC_VERSION >= 3003) +# define ATTRIBUTE_NONNULL(m) __attribute__ ((__nonnull__ (m))) +# else +# define ATTRIBUTE_NONNULL(m) +# endif /* GNUC >= 3.3 */ +#endif /* ATTRIBUTE_NONNULL */ + +/* Attribute `pure' was valid as of gcc 3.0. */ +#ifndef ATTRIBUTE_PURE +# if (GCC_VERSION >= 3000) +# define ATTRIBUTE_PURE __attribute__ ((__pure__)) +# else +# define ATTRIBUTE_PURE +# endif /* GNUC >= 3.0 */ +#endif /* ATTRIBUTE_PURE */ + +/* Use ATTRIBUTE_PRINTF when the format specifier must not be NULL. + This was the case for the `printf' format attribute by itself + before GCC 3.3, but as of 3.3 we need to add the `nonnull' + attribute to retain this behavior. */ +#ifndef ATTRIBUTE_PRINTF +#define ATTRIBUTE_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) ATTRIBUTE_NONNULL(m) +#define ATTRIBUTE_PRINTF_1 ATTRIBUTE_PRINTF(1, 2) +#define ATTRIBUTE_PRINTF_2 ATTRIBUTE_PRINTF(2, 3) +#define ATTRIBUTE_PRINTF_3 ATTRIBUTE_PRINTF(3, 4) +#define ATTRIBUTE_PRINTF_4 ATTRIBUTE_PRINTF(4, 5) +#define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6) +#endif /* ATTRIBUTE_PRINTF */ + +/* Use ATTRIBUTE_NULL_PRINTF when the format specifier may be NULL. A + NULL format specifier was allowed as of gcc 3.3. */ +#ifndef ATTRIBUTE_NULL_PRINTF +# if (GCC_VERSION >= 3003) +# define ATTRIBUTE_NULL_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) +# else +# define ATTRIBUTE_NULL_PRINTF(m, n) +# endif /* GNUC >= 3.3 */ +# define ATTRIBUTE_NULL_PRINTF_1 ATTRIBUTE_NULL_PRINTF(1, 2) +# define ATTRIBUTE_NULL_PRINTF_2 ATTRIBUTE_NULL_PRINTF(2, 3) +# define ATTRIBUTE_NULL_PRINTF_3 ATTRIBUTE_NULL_PRINTF(3, 4) +# define ATTRIBUTE_NULL_PRINTF_4 ATTRIBUTE_NULL_PRINTF(4, 5) +# define ATTRIBUTE_NULL_PRINTF_5 ATTRIBUTE_NULL_PRINTF(5, 6) +#endif /* ATTRIBUTE_NULL_PRINTF */ + +/* Attribute `sentinel' was valid as of gcc 3.5. */ +#ifndef ATTRIBUTE_SENTINEL +# if (GCC_VERSION >= 3005) +# define ATTRIBUTE_SENTINEL __attribute__ ((__sentinel__)) +# else +# define ATTRIBUTE_SENTINEL +# endif /* GNUC >= 3.5 */ +#endif /* ATTRIBUTE_SENTINEL */ + +/* We use __extension__ in some places to suppress -pedantic warnings + about GCC extensions. This feature didn't work properly before + gcc 2.8. */ +#if GCC_VERSION < 2008 +#define __extension__ +#endif + +#endif /* ansidecl.h */ diff --git a/include/aout/ChangeLog b/include/aout/ChangeLog new file mode 100644 index 000000000..148a020e5 --- /dev/null +++ b/include/aout/ChangeLog @@ -0,0 +1,212 @@ +2004-01-06 Mark Kettenis <kettenis@gnu.org> + + * stab.def: Add N_PATCH to DO definition. + +2003-03-06 Elias Athanasopoulos <elathan@phys.uoa.gr> + + * aout64.h (BYTES_IN_WORD): Define if necessary. + +2001-09-18 Alan Modra <amodra@bigpond.net.au> + + * aout64.h: Formatting fixes. + (N_TXTADDR): Evaluate to a bfd_vma. + (N_DATADDR): Avoid negative unsigned warning. + * hp300hpux.h: Formatting fixes. + (N_DATADDR): Avoid negative unsigned warning. + +2000-04-03 Hans-Peter Nilsson <hp@axis.com> + + * aout64.h (RELOC_EXT_BITS_EXTERN_BIG): Wrap definition in #ifndef. + (RELOC_EXT_BITS_EXTERN_LITTLE): Ditto. + (RELOC_EXT_BITS_TYPE_BIG): Ditto. + (RELOC_EXT_BITS_TYPE_SH_BIG): Ditto. + (RELOC_EXT_BITS_TYPE_LITTLE): Ditto. + (RELOC_EXT_BITS_TYPE_SH_LITTLE): Ditto. + +1999-07-12 Ian Lance Taylor <ian@zembu.com> + + * aout64.h (N_SHARED_LIB): Define as 0 if TEXT_START_ADDR is + defined as 0. + +1998-06-28 Peter Schauer <pes@regent.e-technik.tu-muenchen.de> + + * stab.def: Add N_ALIAS from SunPro F77. + +1996-03-11 Ian Lance Taylor <ian@cygnus.com> + + * stab.def: Use __define_stab_duplicate rather than __define_stab + for duplicate entries N_BROWS and N_MOD2. + * stab_gnu.h (__define_stab_duplicate): Define before including + stab.def. + +1995-10-27 Niklas Hallqvist <niklas@appli.se> + + * aout64.h, host.h, hp300hpux.h, sun4.h: Changed PAGE_SIZE to + TARGET_PAGE_SIZE. + +1995-09-12 Ian Lance Taylor <ian@cygnus.com> + + * sun4.h (struct internal_sun4_dynamic_link): Change all fields + from long to unsigned long. + +1995-07-12 Ken Raeburn <raeburn@kr-pc.cygnus.com> + + * sun4.h (PAGE_SIZE): Undefine before defining. + +1994-09-04 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * aout64.h: Only define QMAGIC if it isn't already defined. + +1994-06-16 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * aout64.h (BMAGIC): Define. + +1994-06-11 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + Add weak symbols as an extension to a.out. + * aout64.h (N_WEAKU, N_WEAKA, N_WEAKT, N_WEAKD, N_WEAKB): Define. + * stab.def: Update symbol value table. + +1994-06-02 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * sun4.h (EXTERNAL_SUN4_DYNAMIC_DEBUGGER_SIZE): Correct from 28 to + 24. Fix up ld_got comment. + +1994-03-30 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * dynix3.h: Cleanup, adapt to current bfd version. + +1994-02-26 Ian Lance Taylor (ian@cygnus.com) + + * aout64.h: Add casts to avoid warnings from SVR4 cc. + +1994-02-11 Stan Shebs (shebs@andros.cygnus.com) + + * ar.h (ARMAG, ARMAGB, ARFMAG): Change '\n' to '\012', for greater + portability. + +1994-01-21 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * sun4.h: Added information about SunOS shared libraries. + +1994-01-07 Jim Kingdon (kingdon@deneb.cygnus.com) + + * aout64.h (N_TXTADDR): Add comment regarding OMAGIC and NMAGIC. + +1993-12-25 Jim Kingdon (kingdon@lioth.cygnus.com) + + * aout64.h (N_DATOFF): Don't pad (revert change of 8 Jul 1993). + +1993-11-16 Jim Kingdon (kingdon@lioth.cygnus.com) + + * aout64.h: New macros ZMAGIC_DISK_BLOCK_SIZE and N_DISK_BLOCK_SIZE + for Linux ZMAGIC. + (N_TXTOFF, N_DATOFF): Use them. + +1993-11-04 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * aout64.h (RELOC_STD_BITS_RELATIVE_LITTLE): Fixed value to match + sun3 system; used to overlap other fields. + (RELOC_STD_BITS_JMPTABLE_LITTLE): Likewise. + +1993-11-03 David J. Mackenzie (djm@thepub.cygnus.com) + + * aout64.h (RELOC_STD_BITS_BASEREL_LITTLE): Make it 0x10 (Ken's + suggestion) to avoid conflict with RELOC_STD_BITS_EXTERN_LITTLE. + +1993-10-29 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * hp300hpux.h (N_SHARED_LIB): Define to be 0. + +1993-09-13 John Gilmore (gnu@cygnus.com) + + * ar.h (ARMAP_TIME_OFFSET): Add and describe. + +Mon Aug 23 Sean Fagan (sef@cygnus.com) + + * aout64.h [ARCH_SIZE != 64]: Allow N_BADMAG to be overridden. + +1993-08-16 Jim Kingdon (kingdon@lioth.cygnus.com) + + * stab_gnu.h: Include aout/stab.def not just stab.def. + +1993-07-18 Jim Kingdon (kingdon@rtl.cygnus.com) + + * dynix3.h: New, for symmetry running dynix. + +1993-07-08 Jim Kingdon (kingdon@lioth.cygnus.com) + + * aout64.h (N_BADMAG): Recognize QMAGIC. + N_TXTOFF, N_TXTADDR, N_TXTSIZE: Special code for QMAGIC. + N_DATOFF: Pad text size if we need to. + +1993-06-18 Jim Kingdon (kingdon@lioth.cygnus.com) + + * stab.def (N_ECOML): Fix comment. + +1993-05-31 Jim Kingdon (kingdon@cygnus.com) + + * stab.def: Remove Solaris information on N_FUN stabstring grammar; + I've transferred it to gdb/doc/stabs.texinfo, where it belongs. + +1993-05-10 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * hp300hpux.h: Patch from Glenn Engel for linker problem and + compatibility fix: + (OMAGIC, NMAGIC): New definitions. + (SHAREMAGIC): Deleted. + (HPUX_DOT_O_MAGIC): New macro. + (_N_BADMAG): Adjusted. + (N_HEADER_IN_TEXT, N_DATADDR): New macros. + +1993-04-29 Ken Raeburn (raeburn@deneb.cygnus.com) + + * hp300hpux.h: New file from Glenn Engel, glenne@lsid.hp.com. + +1993-04-27 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * aout64.h (struct external_exec, *MAGIC, N_BADMAG): Don't define + if `external_exec' is already defined as a macro. + (N_DATOFF, N_TRELOFF, N_DRELOFF, N_SYMOFF, N_STROFF): Don't define + if already defined. + (struct external_nlist, EXTERNAL_NLIST_SIZE): Don't define if + `external_nlist' is already defined as a macro. + +1992-08-15 John Gilmore (gnu@cygnus.com) + + * adobe.h: Add description of a.out.adobe format. + +1992-07-03 John Gilmore (gnu at cygnus.com) + + * stab.def: Update more Solaris definitions. + * stab_gnu.h: Add N_SO language types, and Solaris basic float types. + +1992-06-14 John Gilmore (gnu at cygnus.com) + + * stab.def: Update descriptions of Solaris-2 stabs; add N_UNDF. + +1992-06-11 John Gilmore (gnu at cygnus.com) + + * stab.def: Add N_OBJ and N_OPT from Solaris-2. + +1992-01-30 John Gilmore (gnu at cygnus.com) + + * aout64.h: N_TXTSIZE needs some more parentheses. + I don't trust C precedence. + +1991-12-18 Per Bothner (bothner at cygnus.com) + + * aout64.h: Move common sunos-specific test + to recognize shared libraries into new macro N_SHARED_LIB. + Use it to simplify & reformat N_TXTADDR, N_TXTOFF, N_TXTSIZE. + +1991-11-30 Steve Chamberlain (sac at rtl.cygnus.com) + + * aout64.h, ar.h, encap.h, host.h, hp.h, ranlib.h, reloc.h, + stab.def, stab_gnu.h, sun4.h: All moved from the devo/include + directory. + + +Local Variables: +version-control: never +End: diff --git a/include/aout/adobe.h b/include/aout/adobe.h new file mode 100644 index 000000000..c751d103a --- /dev/null +++ b/include/aout/adobe.h @@ -0,0 +1,313 @@ +/* `a.out.adobe' differences from standard a.out files + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef __A_OUT_ADOBE_H__ +#define __A_OUT_ADOBE_H__ + +#define BYTES_IN_WORD 4 + +/* Struct external_exec is the same. */ + +/* This is the layout on disk of the 32-bit or 64-bit exec header. */ + +struct external_exec +{ + bfd_byte e_info[4]; /* magic number and stuff */ + bfd_byte e_text[BYTES_IN_WORD]; /* length of text section in bytes */ + bfd_byte e_data[BYTES_IN_WORD]; /* length of data section in bytes */ + bfd_byte e_bss[BYTES_IN_WORD]; /* length of bss area in bytes */ + bfd_byte e_syms[BYTES_IN_WORD]; /* length of symbol table in bytes */ + bfd_byte e_entry[BYTES_IN_WORD]; /* start address */ + bfd_byte e_trsize[BYTES_IN_WORD]; /* length of text relocation info */ + bfd_byte e_drsize[BYTES_IN_WORD]; /* length of data relocation info */ +}; + +#define EXEC_BYTES_SIZE (4 + BYTES_IN_WORD * 7) + +/* Magic numbers for a.out files */ + +#undef ZMAGIC +#define ZMAGIC 0xAD0BE /* Cute, eh? */ +#undef OMAGIC +#undef NMAGIC + +#define N_BADMAG(x) ((x).a_info != ZMAGIC) + +/* By default, segment size is constant. But some machines override this + to be a function of the a.out header (e.g. machine type). */ +#ifndef N_SEGSIZE +#define N_SEGSIZE(x) SEGMENT_SIZE +#endif +#undef N_SEGSIZE /* FIXMEXXXX */ + +/* Segment information for the a.out.Adobe format is specified after the + file header. It contains N segment descriptors, followed by one with + a type of zero. + + The actual text of the segments starts at N_TXTOFF in the file, + regardless of how many or how few segment headers there are. */ + +struct external_segdesc { + unsigned char e_type[1]; + unsigned char e_size[3]; + unsigned char e_virtbase[4]; + unsigned char e_filebase[4]; +}; + +struct internal_segdesc { + unsigned int a_type:8; /* Segment type N_TEXT, N_DATA, 0 */ + unsigned int a_size:24; /* Segment size */ + bfd_vma a_virtbase; /* Virtual address */ + unsigned int a_filebase; /* Base address in object file */ +}; + +#define N_TXTADDR(x) \ + +/* This is documented to be at 1024, but appears to really be at 2048. + FIXME?! */ +#define N_TXTOFF(x) 2048 + +#define N_TXTSIZE(x) ((x).a_text) + +#define N_DATADDR(x) + +#define N_BSSADDR(x) + +/* Offsets of the various portions of the file after the text segment. */ + +#define N_DATOFF(x) ( N_TXTOFF(x) + N_TXTSIZE(x) ) +#define N_TRELOFF(x) ( N_DATOFF(x) + (x).a_data ) +#define N_DRELOFF(x) ( N_TRELOFF(x) + (x).a_trsize ) +#define N_SYMOFF(x) ( N_DRELOFF(x) + (x).a_drsize ) +#define N_STROFF(x) ( N_SYMOFF(x) + (x).a_syms ) + +/* Symbols */ +struct external_nlist { + bfd_byte e_strx[BYTES_IN_WORD]; /* index into string table of name */ + bfd_byte e_type[1]; /* type of symbol */ + bfd_byte e_other[1]; /* misc info (usually empty) */ + bfd_byte e_desc[2]; /* description field */ + bfd_byte e_value[BYTES_IN_WORD]; /* value of symbol */ +}; + +#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD) + +struct internal_nlist { + unsigned long n_strx; /* index into string table of name */ + unsigned char n_type; /* type of symbol */ + unsigned char n_other; /* misc info (usually empty) */ + unsigned short n_desc; /* description field */ + bfd_vma n_value; /* value of symbol */ +}; + +/* The n_type field is the symbol type, containing: */ + +#define N_UNDF 0 /* Undefined symbol */ +#define N_ABS 2 /* Absolute symbol -- defined at particular addr */ +#define N_TEXT 4 /* Text sym -- defined at offset in text seg */ +#define N_DATA 6 /* Data sym -- defined at offset in data seg */ +#define N_BSS 8 /* BSS sym -- defined at offset in zero'd seg */ +#define N_COMM 0x12 /* Common symbol (visible after shared lib dynlink) */ +#define N_FN 0x1f /* File name of .o file */ +#define N_FN_SEQ 0x0C /* N_FN from Sequent compilers (sigh) */ +/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT, + N_DATA, or N_BSS. When the low-order bit of other types is set, + (e.g. N_WARNING versus N_FN), they are two different types. */ +#define N_EXT 1 /* External symbol (as opposed to local-to-this-file) */ +#define N_TYPE 0x1e +#define N_STAB 0xe0 /* If any of these bits are on, it's a debug symbol */ + +#define N_INDR 0x0a + +/* The following symbols refer to set elements. + All the N_SET[ATDB] symbols with the same name form one set. + Space is allocated for the set in the text section, and each set + elements value is stored into one word of the space. + The first word of the space is the length of the set (number of elements). + + The address of the set is made into an N_SETV symbol + whose name is the same as the name of the set. + This symbol acts like a N_DATA global symbol + in that it can satisfy undefined external references. */ + +/* These appear as input to LD, in a .o file. */ +#define N_SETA 0x14 /* Absolute set element symbol */ +#define N_SETT 0x16 /* Text set element symbol */ +#define N_SETD 0x18 /* Data set element symbol */ +#define N_SETB 0x1A /* Bss set element symbol */ + +/* This is output from LD. */ +#define N_SETV 0x1C /* Pointer to set vector in data area. */ + +/* Warning symbol. The text gives a warning message, the next symbol + in the table will be undefined. When the symbol is referenced, the + message is printed. */ + +#define N_WARNING 0x1e + +/* Relocations + + There are two types of relocation flavours for a.out systems, + standard and extended. The standard form is used on systems where the + instruction has room for all the bits of an offset to the operand, whilst + the extended form is used when an address operand has to be split over n + instructions. Eg, on the 68k, each move instruction can reference + the target with a displacement of 16 or 32 bits. On the sparc, move + instructions use an offset of 14 bits, so the offset is stored in + the reloc field, and the data in the section is ignored. +*/ + +/* This structure describes a single relocation to be performed. + The text-relocation section of the file is a vector of these structures, + all of which apply to the text section. + Likewise, the data-relocation section applies to the data section. */ + +struct reloc_std_external { + bfd_byte r_address[BYTES_IN_WORD]; /* offset of of data to relocate */ + bfd_byte r_index[3]; /* symbol table index of symbol */ + bfd_byte r_type[1]; /* relocation type */ +}; + +#define RELOC_STD_BITS_PCREL_BIG 0x80 +#define RELOC_STD_BITS_PCREL_LITTLE 0x01 + +#define RELOC_STD_BITS_LENGTH_BIG 0x60 +#define RELOC_STD_BITS_LENGTH_SH_BIG 5 /* To shift to units place */ +#define RELOC_STD_BITS_LENGTH_LITTLE 0x06 +#define RELOC_STD_BITS_LENGTH_SH_LITTLE 1 + +#define RELOC_STD_BITS_EXTERN_BIG 0x10 +#define RELOC_STD_BITS_EXTERN_LITTLE 0x08 + +#define RELOC_STD_BITS_BASEREL_BIG 0x08 +#define RELOC_STD_BITS_BASEREL_LITTLE 0x08 + +#define RELOC_STD_BITS_JMPTABLE_BIG 0x04 +#define RELOC_STD_BITS_JMPTABLE_LITTLE 0x04 + +#define RELOC_STD_BITS_RELATIVE_BIG 0x02 +#define RELOC_STD_BITS_RELATIVE_LITTLE 0x02 + +#define RELOC_STD_SIZE (BYTES_IN_WORD + 3 + 1) /* Bytes per relocation entry */ + +struct reloc_std_internal +{ + bfd_vma r_address; /* Address (within segment) to be relocated. */ + /* The meaning of r_symbolnum depends on r_extern. */ + unsigned int r_symbolnum:24; + /* Nonzero means value is a pc-relative offset + and it should be relocated for changes in its own address + as well as for changes in the symbol or section specified. */ + unsigned int r_pcrel:1; + /* Length (as exponent of 2) of the field to be relocated. + Thus, a value of 2 indicates 1<<2 bytes. */ + unsigned int r_length:2; + /* 1 => relocate with value of symbol. + r_symbolnum is the index of the symbol + in files the symbol table. + 0 => relocate with the address of a segment. + r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS + (the N_EXT bit may be set also, but signifies nothing). */ + unsigned int r_extern:1; + /* The next three bits are for SunOS shared libraries, and seem to + be undocumented. */ + unsigned int r_baserel:1; /* Linkage table relative */ + unsigned int r_jmptable:1; /* pc-relative to jump table */ + unsigned int r_relative:1; /* "relative relocation" */ + /* unused */ + unsigned int r_pad:1; /* Padding -- set to zero */ +}; + + +/* EXTENDED RELOCS */ + +struct reloc_ext_external { + bfd_byte r_address[BYTES_IN_WORD]; /* offset of of data to relocate */ + bfd_byte r_index[3]; /* symbol table index of symbol */ + bfd_byte r_type[1]; /* relocation type */ + bfd_byte r_addend[BYTES_IN_WORD]; /* datum addend */ +}; + +#define RELOC_EXT_BITS_EXTERN_BIG 0x80 +#define RELOC_EXT_BITS_EXTERN_LITTLE 0x01 + +#define RELOC_EXT_BITS_TYPE_BIG 0x1F +#define RELOC_EXT_BITS_TYPE_SH_BIG 0 +#define RELOC_EXT_BITS_TYPE_LITTLE 0xF8 +#define RELOC_EXT_BITS_TYPE_SH_LITTLE 3 + +/* Bytes per relocation entry */ +#define RELOC_EXT_SIZE (BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD) + +enum reloc_type +{ + /* simple relocations */ + RELOC_8, /* data[0:7] = addend + sv */ + RELOC_16, /* data[0:15] = addend + sv */ + RELOC_32, /* data[0:31] = addend + sv */ + /* pc-rel displacement */ + RELOC_DISP8, /* data[0:7] = addend - pc + sv */ + RELOC_DISP16, /* data[0:15] = addend - pc + sv */ + RELOC_DISP32, /* data[0:31] = addend - pc + sv */ + /* Special */ + RELOC_WDISP30, /* data[0:29] = (addend + sv - pc)>>2 */ + RELOC_WDISP22, /* data[0:21] = (addend + sv - pc)>>2 */ + RELOC_HI22, /* data[0:21] = (addend + sv)>>10 */ + RELOC_22, /* data[0:21] = (addend + sv) */ + RELOC_13, /* data[0:12] = (addend + sv) */ + RELOC_LO10, /* data[0:9] = (addend + sv) */ + RELOC_SFA_BASE, + RELOC_SFA_OFF13, + /* P.I.C. (base-relative) */ + RELOC_BASE10, /* Not sure - maybe we can do this the */ + RELOC_BASE13, /* right way now */ + RELOC_BASE22, + /* for some sort of pc-rel P.I.C. (?) */ + RELOC_PC10, + RELOC_PC22, + /* P.I.C. jump table */ + RELOC_JMP_TBL, + /* reputedly for shared libraries somehow */ + RELOC_SEGOFF16, + RELOC_GLOB_DAT, + RELOC_JMP_SLOT, + RELOC_RELATIVE, + + RELOC_11, + RELOC_WDISP2_14, + RELOC_WDISP19, + RELOC_HHI22, /* data[0:21] = (addend + sv) >> 42 */ + RELOC_HLO10, /* data[0:9] = (addend + sv) >> 32 */ + + /* 29K relocation types */ + RELOC_JUMPTARG, + RELOC_CONST, + RELOC_CONSTH, + + NO_RELOC + }; + + +struct reloc_internal { + bfd_vma r_address; /* offset of of data to relocate */ + long r_index; /* symbol table index of symbol */ + enum reloc_type r_type; /* relocation type */ + bfd_vma r_addend; /* datum addend */ +}; + +#endif /* __A_OUT_ADOBE_H__ */ diff --git a/include/aout/aout64.h b/include/aout/aout64.h new file mode 100644 index 000000000..4843410d2 --- /dev/null +++ b/include/aout/aout64.h @@ -0,0 +1,519 @@ +/* `a.out' object-file definitions, including extensions to 64-bit fields + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef __A_OUT_64_H__ +#define __A_OUT_64_H__ + +#ifndef BYTES_IN_WORD +#define BYTES_IN_WORD 4 +#endif + +/* This is the layout on disk of the 32-bit or 64-bit exec header. */ + +#ifndef external_exec +struct external_exec +{ + bfd_byte e_info[4]; /* Magic number and stuff. */ + bfd_byte e_text[BYTES_IN_WORD]; /* Length of text section in bytes. */ + bfd_byte e_data[BYTES_IN_WORD]; /* Length of data section in bytes. */ + bfd_byte e_bss[BYTES_IN_WORD]; /* Length of bss area in bytes. */ + bfd_byte e_syms[BYTES_IN_WORD]; /* Length of symbol table in bytes. */ + bfd_byte e_entry[BYTES_IN_WORD]; /* Start address. */ + bfd_byte e_trsize[BYTES_IN_WORD]; /* Length of text relocation info. */ + bfd_byte e_drsize[BYTES_IN_WORD]; /* Length of data relocation info. */ +}; + +#define EXEC_BYTES_SIZE (4 + BYTES_IN_WORD * 7) + +/* Magic numbers for a.out files. */ + +#if ARCH_SIZE==64 +#define OMAGIC 0x1001 /* Code indicating object file. */ +#define ZMAGIC 0x1002 /* Code indicating demand-paged executable. */ +#define NMAGIC 0x1003 /* Code indicating pure executable. */ + +/* There is no 64-bit QMAGIC as far as I know. */ + +#define N_BADMAG(x) (N_MAGIC(x) != OMAGIC \ + && N_MAGIC(x) != NMAGIC \ + && N_MAGIC(x) != ZMAGIC) +#else +#define OMAGIC 0407 /* Object file or impure executable. */ +#define NMAGIC 0410 /* Code indicating pure executable. */ +#define ZMAGIC 0413 /* Code indicating demand-paged executable. */ +#define BMAGIC 0415 /* Used by a b.out object. */ + +/* This indicates a demand-paged executable with the header in the text. + It is used by 386BSD (and variants) and Linux, at least. */ +#ifndef QMAGIC +#define QMAGIC 0314 +#endif +# ifndef N_BADMAG +# define N_BADMAG(x) (N_MAGIC(x) != OMAGIC \ + && N_MAGIC(x) != NMAGIC \ + && N_MAGIC(x) != ZMAGIC \ + && N_MAGIC(x) != QMAGIC) +# endif /* N_BADMAG */ +#endif + +#endif + +#ifdef QMAGIC +#define N_IS_QMAGIC(x) (N_MAGIC (x) == QMAGIC) +#else +#define N_IS_QMAGIC(x) (0) +#endif + +/* The difference between TARGET_PAGE_SIZE and N_SEGSIZE is that TARGET_PAGE_SIZE is + the finest granularity at which you can page something, thus it + controls the padding (if any) before the text segment of a ZMAGIC + file. N_SEGSIZE is the resolution at which things can be marked as + read-only versus read/write, so it controls the padding between the + text segment and the data segment (in memory; on disk the padding + between them is TARGET_PAGE_SIZE). TARGET_PAGE_SIZE and N_SEGSIZE are the same + for most machines, but different for sun3. */ + +/* By default, segment size is constant. But some machines override this + to be a function of the a.out header (e.g. machine type). */ + +#ifndef N_SEGSIZE +#define N_SEGSIZE(x) SEGMENT_SIZE +#endif + +/* Virtual memory address of the text section. + This is getting very complicated. A good reason to discard a.out format + for something that specifies these fields explicitly. But til then... + + * OMAGIC and NMAGIC files: + (object files: text for "relocatable addr 0" right after the header) + start at 0, offset is EXEC_BYTES_SIZE, size as stated. + * The text address, offset, and size of ZMAGIC files depend + on the entry point of the file: + * entry point below TEXT_START_ADDR: + (hack for SunOS shared libraries) + start at 0, offset is 0, size as stated. + * If N_HEADER_IN_TEXT(x) is true (which defaults to being the + case when the entry point is EXEC_BYTES_SIZE or further into a page): + no padding is needed; text can start after exec header. Sun + considers the text segment of such files to include the exec header; + for BFD's purposes, we don't, which makes more work for us. + start at TEXT_START_ADDR + EXEC_BYTES_SIZE, offset is EXEC_BYTES_SIZE, + size as stated minus EXEC_BYTES_SIZE. + * If N_HEADER_IN_TEXT(x) is false (which defaults to being the case when + the entry point is less than EXEC_BYTES_SIZE into a page (e.g. page + aligned)): (padding is needed so that text can start at a page boundary) + start at TEXT_START_ADDR, offset TARGET_PAGE_SIZE, size as stated. + + Specific configurations may want to hardwire N_HEADER_IN_TEXT, + for efficiency or to allow people to play games with the entry point. + In that case, you would #define N_HEADER_IN_TEXT(x) as 1 for sunos, + and as 0 for most other hosts (Sony News, Vax Ultrix, etc). + (Do this in the appropriate bfd target file.) + (The default is a heuristic that will break if people try changing + the entry point, perhaps with the ld -e flag.) + + * QMAGIC is always like a ZMAGIC for which N_HEADER_IN_TEXT is true, + and for which the starting address is TARGET_PAGE_SIZE (or should this be + SEGMENT_SIZE?) (TEXT_START_ADDR only applies to ZMAGIC, not to QMAGIC). */ + +/* This macro is only relevant for ZMAGIC files; QMAGIC always has the header + in the text. */ +#ifndef N_HEADER_IN_TEXT +#define N_HEADER_IN_TEXT(x) \ + (((x).a_entry & (TARGET_PAGE_SIZE-1)) >= EXEC_BYTES_SIZE) +#endif + +/* Sun shared libraries, not linux. This macro is only relevant for ZMAGIC + files. */ +#ifndef N_SHARED_LIB +#if defined (TEXT_START_ADDR) && TEXT_START_ADDR == 0 +#define N_SHARED_LIB(x) (0) +#else +#define N_SHARED_LIB(x) ((x).a_entry < TEXT_START_ADDR) +#endif +#endif + +/* Returning 0 not TEXT_START_ADDR for OMAGIC and NMAGIC is based on + the assumption that we are dealing with a .o file, not an + executable. This is necessary for OMAGIC (but means we don't work + right on the output from ld -N); more questionable for NMAGIC. */ + +#ifndef N_TXTADDR +#define N_TXTADDR(x) \ + (/* The address of a QMAGIC file is always one page in, \ + with the header in the text. */ \ + N_IS_QMAGIC (x) \ + ? (bfd_vma) TARGET_PAGE_SIZE + EXEC_BYTES_SIZE \ + : (N_MAGIC (x) != ZMAGIC \ + ? (bfd_vma) 0 /* Object file or NMAGIC. */ \ + : (N_SHARED_LIB (x) \ + ? (bfd_vma) 0 \ + : (N_HEADER_IN_TEXT (x) \ + ? (bfd_vma) TEXT_START_ADDR + EXEC_BYTES_SIZE \ + : (bfd_vma) TEXT_START_ADDR)))) +#endif + +/* If N_HEADER_IN_TEXT is not true for ZMAGIC, there is some padding + to make the text segment start at a certain boundary. For most + systems, this boundary is TARGET_PAGE_SIZE. But for Linux, in the + time-honored tradition of crazy ZMAGIC hacks, it is 1024 which is + not what TARGET_PAGE_SIZE needs to be for QMAGIC. */ + +#ifndef ZMAGIC_DISK_BLOCK_SIZE +#define ZMAGIC_DISK_BLOCK_SIZE TARGET_PAGE_SIZE +#endif + +#define N_DISK_BLOCK_SIZE(x) \ + (N_MAGIC(x) == ZMAGIC ? ZMAGIC_DISK_BLOCK_SIZE : TARGET_PAGE_SIZE) + +/* Offset in an a.out of the start of the text section. */ +#ifndef N_TXTOFF +#define N_TXTOFF(x) \ + (/* For {O,N,Q}MAGIC, no padding. */ \ + N_MAGIC (x) != ZMAGIC \ + ? EXEC_BYTES_SIZE \ + : (N_SHARED_LIB (x) \ + ? 0 \ + : (N_HEADER_IN_TEXT (x) \ + ? EXEC_BYTES_SIZE /* No padding. */ \ + : ZMAGIC_DISK_BLOCK_SIZE /* A page of padding. */))) +#endif +/* Size of the text section. It's always as stated, except that we + offset it to `undo' the adjustment to N_TXTADDR and N_TXTOFF + for ZMAGIC files that nominally include the exec header + as part of the first page of text. (BFD doesn't consider the + exec header to be part of the text segment.) */ +#ifndef N_TXTSIZE +#define N_TXTSIZE(x) \ + (/* For QMAGIC, we don't consider the header part of the text section. */\ + N_IS_QMAGIC (x) \ + ? (x).a_text - EXEC_BYTES_SIZE \ + : ((N_MAGIC (x) != ZMAGIC || N_SHARED_LIB (x)) \ + ? (x).a_text \ + : (N_HEADER_IN_TEXT (x) \ + ? (x).a_text - EXEC_BYTES_SIZE /* No padding. */ \ + : (x).a_text /* A page of padding. */ ))) +#endif +/* The address of the data segment in virtual memory. + It is the text segment address, plus text segment size, rounded + up to a N_SEGSIZE boundary for pure or pageable files. */ +#ifndef N_DATADDR +#define N_DATADDR(x) \ + (N_MAGIC (x) == OMAGIC \ + ? (N_TXTADDR (x) + N_TXTSIZE (x)) \ + : (N_SEGSIZE (x) + ((N_TXTADDR (x) + N_TXTSIZE (x) - 1) \ + & ~ (bfd_vma) (N_SEGSIZE (x) - 1)))) +#endif +/* The address of the BSS segment -- immediately after the data segment. */ + +#define N_BSSADDR(x) (N_DATADDR (x) + (x).a_data) + +/* Offsets of the various portions of the file after the text segment. */ + +/* For {Q,Z}MAGIC, there is padding to make the data segment start on + a page boundary. Most of the time the a_text field (and thus + N_TXTSIZE) already contains this padding. It is possible that for + BSDI and/or 386BSD it sometimes doesn't contain the padding, and + perhaps we should be adding it here. But this seems kind of + questionable and probably should be BSDI/386BSD-specific if we do + do it. + + For NMAGIC (at least for hp300 BSD, probably others), there is + padding in memory only, not on disk, so we must *not* ever pad here + for NMAGIC. */ + +#ifndef N_DATOFF +#define N_DATOFF(x) (N_TXTOFF (x) + N_TXTSIZE (x)) +#endif +#ifndef N_TRELOFF +#define N_TRELOFF(x) (N_DATOFF (x) + (x).a_data) +#endif +#ifndef N_DRELOFF +#define N_DRELOFF(x) (N_TRELOFF (x) + (x).a_trsize) +#endif +#ifndef N_SYMOFF +#define N_SYMOFF(x) (N_DRELOFF (x) + (x).a_drsize) +#endif +#ifndef N_STROFF +#define N_STROFF(x) (N_SYMOFF (x) + (x).a_syms) +#endif + +/* Symbols */ +#ifndef external_nlist +struct external_nlist +{ + bfd_byte e_strx[BYTES_IN_WORD]; /* Index into string table of name. */ + bfd_byte e_type[1]; /* Type of symbol. */ + bfd_byte e_other[1]; /* Misc info (usually empty). */ + bfd_byte e_desc[2]; /* Description field. */ + bfd_byte e_value[BYTES_IN_WORD]; /* Value of symbol. */ +}; +#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD) +#endif + +struct internal_nlist +{ + unsigned long n_strx; /* Index into string table of name. */ + unsigned char n_type; /* Type of symbol. */ + unsigned char n_other; /* Misc info (usually empty). */ + unsigned short n_desc; /* Description field. */ + bfd_vma n_value; /* Value of symbol. */ +}; + +/* The n_type field is the symbol type, containing: */ + +#define N_UNDF 0 /* Undefined symbol. */ +#define N_ABS 2 /* Absolute symbol -- defined at particular addr. */ +#define N_TEXT 4 /* Text sym -- defined at offset in text seg. */ +#define N_DATA 6 /* Data sym -- defined at offset in data seg. */ +#define N_BSS 8 /* BSS sym -- defined at offset in zero'd seg. */ +#define N_COMM 0x12 /* Common symbol (visible after shared lib dynlink). */ +#define N_FN 0x1f /* File name of .o file. */ +#define N_FN_SEQ 0x0C /* N_FN from Sequent compilers (sigh). */ +/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT, + N_DATA, or N_BSS. When the low-order bit of other types is set, + (e.g. N_WARNING versus N_FN), they are two different types. */ +#define N_EXT 1 /* External symbol (as opposed to local-to-this-file). */ +#define N_TYPE 0x1e +#define N_STAB 0xe0 /* If any of these bits are on, it's a debug symbol. */ + +#define N_INDR 0x0a + +/* The following symbols refer to set elements. + All the N_SET[ATDB] symbols with the same name form one set. + Space is allocated for the set in the text section, and each set + elements value is stored into one word of the space. + The first word of the space is the length of the set (number of elements). + + The address of the set is made into an N_SETV symbol + whose name is the same as the name of the set. + This symbol acts like a N_DATA global symbol + in that it can satisfy undefined external references. */ + +/* These appear as input to LD, in a .o file. */ +#define N_SETA 0x14 /* Absolute set element symbol. */ +#define N_SETT 0x16 /* Text set element symbol. */ +#define N_SETD 0x18 /* Data set element symbol. */ +#define N_SETB 0x1A /* Bss set element symbol. */ + +/* This is output from LD. */ +#define N_SETV 0x1C /* Pointer to set vector in data area. */ + +/* Warning symbol. The text gives a warning message, the next symbol + in the table will be undefined. When the symbol is referenced, the + message is printed. */ + +#define N_WARNING 0x1e + +/* Weak symbols. These are a GNU extension to the a.out format. The + semantics are those of ELF weak symbols. Weak symbols are always + externally visible. The N_WEAK? values are squeezed into the + available slots. The value of a N_WEAKU symbol is 0. The values + of the other types are the definitions. */ +#define N_WEAKU 0x0d /* Weak undefined symbol. */ +#define N_WEAKA 0x0e /* Weak absolute symbol. */ +#define N_WEAKT 0x0f /* Weak text symbol. */ +#define N_WEAKD 0x10 /* Weak data symbol. */ +#define N_WEAKB 0x11 /* Weak bss symbol. */ + +/* Relocations + + There are two types of relocation flavours for a.out systems, + standard and extended. The standard form is used on systems where the + instruction has room for all the bits of an offset to the operand, whilst + the extended form is used when an address operand has to be split over n + instructions. Eg, on the 68k, each move instruction can reference + the target with a displacement of 16 or 32 bits. On the sparc, move + instructions use an offset of 14 bits, so the offset is stored in + the reloc field, and the data in the section is ignored. */ + +/* This structure describes a single relocation to be performed. + The text-relocation section of the file is a vector of these structures, + all of which apply to the text section. + Likewise, the data-relocation section applies to the data section. */ + +struct reloc_std_external +{ + bfd_byte r_address[BYTES_IN_WORD]; /* Offset of of data to relocate. */ + bfd_byte r_index[3]; /* Symbol table index of symbol. */ + bfd_byte r_type[1]; /* Relocation type. */ +}; + +#define RELOC_STD_BITS_PCREL_BIG ((unsigned int) 0x80) +#define RELOC_STD_BITS_PCREL_LITTLE ((unsigned int) 0x01) + +#define RELOC_STD_BITS_LENGTH_BIG ((unsigned int) 0x60) +#define RELOC_STD_BITS_LENGTH_SH_BIG 5 +#define RELOC_STD_BITS_LENGTH_LITTLE ((unsigned int) 0x06) +#define RELOC_STD_BITS_LENGTH_SH_LITTLE 1 + +#define RELOC_STD_BITS_EXTERN_BIG ((unsigned int) 0x10) +#define RELOC_STD_BITS_EXTERN_LITTLE ((unsigned int) 0x08) + +#define RELOC_STD_BITS_BASEREL_BIG ((unsigned int) 0x08) +#define RELOC_STD_BITS_BASEREL_LITTLE ((unsigned int) 0x10) + +#define RELOC_STD_BITS_JMPTABLE_BIG ((unsigned int) 0x04) +#define RELOC_STD_BITS_JMPTABLE_LITTLE ((unsigned int) 0x20) + +#define RELOC_STD_BITS_RELATIVE_BIG ((unsigned int) 0x02) +#define RELOC_STD_BITS_RELATIVE_LITTLE ((unsigned int) 0x40) + +#define RELOC_STD_SIZE (BYTES_IN_WORD + 3 + 1) /* Bytes per relocation entry. */ + +struct reloc_std_internal +{ + bfd_vma r_address; /* Address (within segment) to be relocated. */ + /* The meaning of r_symbolnum depends on r_extern. */ + unsigned int r_symbolnum:24; + /* Nonzero means value is a pc-relative offset + and it should be relocated for changes in its own address + as well as for changes in the symbol or section specified. */ + unsigned int r_pcrel:1; + /* Length (as exponent of 2) of the field to be relocated. + Thus, a value of 2 indicates 1<<2 bytes. */ + unsigned int r_length:2; + /* 1 => relocate with value of symbol. + r_symbolnum is the index of the symbol + in files the symbol table. + 0 => relocate with the address of a segment. + r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS + (the N_EXT bit may be set also, but signifies nothing). */ + unsigned int r_extern:1; + /* The next three bits are for SunOS shared libraries, and seem to + be undocumented. */ + unsigned int r_baserel:1; /* Linkage table relative. */ + unsigned int r_jmptable:1; /* pc-relative to jump table. */ + unsigned int r_relative:1; /* "relative relocation". */ + /* unused */ + unsigned int r_pad:1; /* Padding -- set to zero. */ +}; + + +/* EXTENDED RELOCS. */ + +struct reloc_ext_external +{ + bfd_byte r_address[BYTES_IN_WORD]; /* Offset of of data to relocate. */ + bfd_byte r_index[3]; /* Symbol table index of symbol. */ + bfd_byte r_type[1]; /* Relocation type. */ + bfd_byte r_addend[BYTES_IN_WORD]; /* Datum addend. */ +}; + +#ifndef RELOC_EXT_BITS_EXTERN_BIG +#define RELOC_EXT_BITS_EXTERN_BIG ((unsigned int) 0x80) +#endif + +#ifndef RELOC_EXT_BITS_EXTERN_LITTLE +#define RELOC_EXT_BITS_EXTERN_LITTLE ((unsigned int) 0x01) +#endif + +#ifndef RELOC_EXT_BITS_TYPE_BIG +#define RELOC_EXT_BITS_TYPE_BIG ((unsigned int) 0x1F) +#endif + +#ifndef RELOC_EXT_BITS_TYPE_SH_BIG +#define RELOC_EXT_BITS_TYPE_SH_BIG 0 +#endif + +#ifndef RELOC_EXT_BITS_TYPE_LITTLE +#define RELOC_EXT_BITS_TYPE_LITTLE ((unsigned int) 0xF8) +#endif + +#ifndef RELOC_EXT_BITS_TYPE_SH_LITTLE +#define RELOC_EXT_BITS_TYPE_SH_LITTLE 3 +#endif + +/* Bytes per relocation entry. */ +#define RELOC_EXT_SIZE (BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD) + +enum reloc_type +{ + /* Simple relocations. */ + RELOC_8, /* data[0:7] = addend + sv */ + RELOC_16, /* data[0:15] = addend + sv */ + RELOC_32, /* data[0:31] = addend + sv */ + /* PC-rel displacement. */ + RELOC_DISP8, /* data[0:7] = addend - pc + sv */ + RELOC_DISP16, /* data[0:15] = addend - pc + sv */ + RELOC_DISP32, /* data[0:31] = addend - pc + sv */ + /* Special. */ + RELOC_WDISP30, /* data[0:29] = (addend + sv - pc)>>2 */ + RELOC_WDISP22, /* data[0:21] = (addend + sv - pc)>>2 */ + RELOC_HI22, /* data[0:21] = (addend + sv)>>10 */ + RELOC_22, /* data[0:21] = (addend + sv) */ + RELOC_13, /* data[0:12] = (addend + sv) */ + RELOC_LO10, /* data[0:9] = (addend + sv) */ + RELOC_SFA_BASE, + RELOC_SFA_OFF13, + /* P.I.C. (base-relative). */ + RELOC_BASE10, /* Not sure - maybe we can do this the */ + RELOC_BASE13, /* right way now */ + RELOC_BASE22, + /* For some sort of pc-rel P.I.C. (?) */ + RELOC_PC10, + RELOC_PC22, + /* P.I.C. jump table. */ + RELOC_JMP_TBL, + /* Reputedly for shared libraries somehow. */ + RELOC_SEGOFF16, + RELOC_GLOB_DAT, + RELOC_JMP_SLOT, + RELOC_RELATIVE, + + RELOC_11, + RELOC_WDISP2_14, + RELOC_WDISP19, + RELOC_HHI22, /* data[0:21] = (addend + sv) >> 42 */ + RELOC_HLO10, /* data[0:9] = (addend + sv) >> 32 */ + + /* 29K relocation types. */ + RELOC_JUMPTARG, + RELOC_CONST, + RELOC_CONSTH, + + /* All the new ones I can think of, for sparc v9. */ + RELOC_64, /* data[0:63] = addend + sv */ + RELOC_DISP64, /* data[0:63] = addend - pc + sv */ + RELOC_WDISP21, /* data[0:20] = (addend + sv - pc)>>2 */ + RELOC_DISP21, /* data[0:20] = addend - pc + sv */ + RELOC_DISP14, /* data[0:13] = addend - pc + sv */ + /* Q . + What are the other ones, + Since this is a clean slate, can we throw away the ones we dont + understand ? Should we sort the values ? What about using a + microcode format like the 68k ? */ + NO_RELOC + }; + + +struct reloc_internal +{ + bfd_vma r_address; /* Offset of of data to relocate. */ + long r_index; /* Symbol table index of symbol. */ + enum reloc_type r_type; /* Relocation type. */ + bfd_vma r_addend; /* Datum addend. */ +}; + +/* Q. + Should the length of the string table be 4 bytes or 8 bytes ? + + Q. + What about archive indexes ? */ + +#endif /* __A_OUT_64_H__ */ diff --git a/include/aout/ar.h b/include/aout/ar.h new file mode 100644 index 000000000..15d534c57 --- /dev/null +++ b/include/aout/ar.h @@ -0,0 +1,52 @@ +/* archive file definition for GNU software + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* So far this is correct for BSDish archives. Don't forget that + files must begin on an even byte boundary. */ + +#ifndef __GNU_AR_H__ +#define __GNU_AR_H__ + +/* Note that the usual '\n' in magic strings may translate to different + characters, as allowed by ANSI. '\012' has a fixed value, and remains + compatible with existing BSDish archives. */ + +#define ARMAG "!<arch>\012" /* For COFF and a.out archives */ +#define ARMAGB "!<bout>\012" /* For b.out archives */ +#define SARMAG 8 +#define ARFMAG "`\012" + +/* The ar_date field of the armap (__.SYMDEF) member of an archive + must be greater than the modified date of the entire file, or + BSD-derived linkers complain. We originally write the ar_date with + this offset from the real file's mod-time. After finishing the + file, we rewrite ar_date if it's not still greater than the mod date. */ + +#define ARMAP_TIME_OFFSET 60 + +struct ar_hdr { + char ar_name[16]; /* name of this member */ + char ar_date[12]; /* file mtime */ + char ar_uid[6]; /* owner uid; printed as decimal */ + char ar_gid[6]; /* owner gid; printed as decimal */ + char ar_mode[8]; /* file mode, printed as octal */ + char ar_size[10]; /* file size, printed as decimal */ + char ar_fmag[2]; /* should contain ARFMAG */ +}; + +#endif /* __GNU_AR_H__ */ diff --git a/include/aout/dynix3.h b/include/aout/dynix3.h new file mode 100644 index 000000000..b09d5d70e --- /dev/null +++ b/include/aout/dynix3.h @@ -0,0 +1,86 @@ +/* a.out specifics for Sequent Symmetry running Dynix 3.x + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef A_OUT_DYNIX3_H +#define A_OUT_DYNIX3_H + +#define external_exec dynix_external_exec + +/* struct exec for Dynix 3 + + a_gdtbl and a_bootstrap are only for standalone binaries. + Shared data fields are not supported by the kernel as of Dynix 3.1, + but are supported by Dynix compiler programs. */ +struct dynix_external_exec + { + unsigned char e_info[4]; + unsigned char e_text[4]; + unsigned char e_data[4]; + unsigned char e_bss[4]; + unsigned char e_syms[4]; + unsigned char e_entry[4]; + unsigned char e_trsize[4]; + unsigned char e_drsize[4]; + unsigned char e_g_code[8]; + unsigned char e_g_data[8]; + unsigned char e_g_desc[8]; + unsigned char e_shdata[4]; + unsigned char e_shbss[4]; + unsigned char e_shdrsize[4]; + unsigned char e_bootstrap[44]; + unsigned char e_reserved[12]; + unsigned char e_version[4]; + }; + +#define EXEC_BYTES_SIZE (128) + +/* All executables under Dynix are demand paged with read-only text, + Thus no NMAGIC. + + ZMAGIC has a page of 0s at virtual 0, + XMAGIC has an invalid page at virtual 0. */ +#define OMAGIC 0x12eb /* .o */ +#define ZMAGIC 0x22eb /* zero @ 0, demand load */ +#define XMAGIC 0x32eb /* invalid @ 0, demand load */ +#define SMAGIC 0x42eb /* standalone, not supported here */ + +#define N_BADMAG(x) ((OMAGIC != N_MAGIC(x)) && \ + (ZMAGIC != N_MAGIC(x)) && \ + (XMAGIC != N_MAGIC(x)) && \ + (SMAGIC != N_MAGIC(x))) + +#define N_ADDRADJ(x) ((ZMAGIC == N_MAGIC(x) || XMAGIC == N_MAGIC(x)) ? 0x1000 : 0) + +#define N_TXTOFF(x) (EXEC_BYTES_SIZE) +#define N_DATOFF(x) (N_TXTOFF(x) + N_TXTSIZE(x)) +#define N_SHDATOFF(x) (N_DATOFF(x) + (x).a_data) +#define N_TRELOFF(x) (N_SHDATOFF(x) + (x).a_shdata) +#define N_DRELOFF(x) (N_TRELOFF(x) + (x).a_trsize) +#define N_SHDRELOFF(x) (N_DRELOFF(x) + (x).a_drsize) +#define N_SYMOFF(x) (N_SHDRELOFF(x) + (x).a_shdrsize) +#define N_STROFF(x) (N_SYMOFF(x) + (x).a_syms) + +#define N_TXTADDR(x) \ + (((OMAGIC == N_MAGIC(x)) || (SMAGIC == N_MAGIC(x))) ? 0 \ + : TEXT_START_ADDR + EXEC_BYTES_SIZE) + +#define N_TXTSIZE(x) \ + (((OMAGIC == N_MAGIC(x)) || (SMAGIC == N_MAGIC(x))) ? ((x).a_text) \ + : ((x).a_text - N_ADDRADJ(x) - EXEC_BYTES_SIZE)) + +#endif /* A_OUT_DYNIX3_H */ diff --git a/include/aout/encap.h b/include/aout/encap.h new file mode 100644 index 000000000..1381557d8 --- /dev/null +++ b/include/aout/encap.h @@ -0,0 +1,135 @@ +/* Yet Another Try at encapsulating bsd object files in coff. + Copyright 1988, 1989, 1991 Free Software Foundation, Inc. + Written by Pace Willisson 12/9/88 + + This file is obsolete. It needs to be converted to just define a bunch + of stuff that BFD can use to do coff-encapsulated files. --gnu@cygnus.com + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* + * We only use the coff headers to tell the kernel + * how to exec the file. Therefore, the only fields that need to + * be filled in are the scnptr and vaddr for the text and data + * sections, and the vaddr for the bss. As far as coff is concerned, + * there is no symbol table, relocation, or line numbers. + * + * A normal bsd header (struct exec) is placed after the coff headers, + * and before the real text. I defined a the new fields 'a_machtype' + * and a_flags. If a_machtype is M_386, and a_flags & A_ENCAP is + * true, then the bsd header is preceeded by a coff header. Macros + * like N_TXTOFF and N_TXTADDR use this field to find the bsd header. + * + * The only problem is to track down the bsd exec header. The + * macros HEADER_OFFSET, etc do this. + */ + +#define N_FLAGS_COFF_ENCAPSULATE 0x20 /* coff header precedes bsd header */ + +/* Describe the COFF header used for encapsulation. */ + +struct coffheader +{ + /* filehdr */ + unsigned short f_magic; + unsigned short f_nscns; + long f_timdat; + long f_symptr; + long f_nsyms; + unsigned short f_opthdr; + unsigned short f_flags; + /* aouthdr */ + short magic; + short vstamp; + long tsize; + long dsize; + long bsize; + long entry; + long text_start; + long data_start; + struct coffscn + { + char s_name[8]; + long s_paddr; + long s_vaddr; + long s_size; + long s_scnptr; + long s_relptr; + long s_lnnoptr; + unsigned short s_nreloc; + unsigned short s_nlnno; + long s_flags; + } scns[3]; +}; + +/* Describe some of the parameters of the encapsulation, + including how to find the encapsulated BSD header. */ + +/* FIXME, this is dumb. The same tools can't handle a.outs for different + architectures, just because COFF_MAGIC is different; so you need a + separate GNU nm for every architecture!!? Unfortunately, it needs to + be this way, since the COFF_MAGIC value is determined by the kernel + we're trying to fool here. */ + +#define COFF_MAGIC_I386 0514 /* I386MAGIC */ +#define COFF_MAGIC_M68K 0520 /* MC68MAGIC */ +#define COFF_MAGIC_A29K 0x17A /* Used by asm29k cross-tools */ + +#ifdef COFF_MAGIC +short __header_offset_temp; +#define HEADER_OFFSET(f) \ + (__header_offset_temp = 0, \ + fread ((char *)&__header_offset_temp, sizeof (short), 1, (f)), \ + fseek ((f), -sizeof (short), 1), \ + __header_offset_temp==COFF_MAGIC ? sizeof(struct coffheader) : 0) +#else +#define HEADER_OFFSET(f) 0 +#endif + +#define HEADER_SEEK(f) (fseek ((f), HEADER_OFFSET((f)), 1)) + +/* Describe the characteristics of the BSD header + that appears inside the encapsulation. */ + +/* Encapsulated coff files that are linked ZMAGIC have a text segment + offset just past the header (and a matching TXTADDR), excluding + the headers from the text segment proper but keeping the physical + layout and the virtual memory layout page-aligned. + + Non-encapsulated a.out files that are linked ZMAGIC have a text + segment that starts at 0 and an N_TXTADR similarly offset to 0. + They too are page-aligned with each other, but they include the + a.out header as part of the text. + + The _N_HDROFF gets sizeof struct exec added to it, so we have + to compensate here. See <a.out.gnu.h>. */ + +#undef _N_HDROFF +#undef N_TXTADDR +#undef N_DATADDR + +#define _N_HDROFF(x) ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + sizeof (struct coffheader) : 0) + +/* Address of text segment in memory after it is loaded. */ +#define N_TXTADDR(x) \ + ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + sizeof (struct coffheader) + sizeof (struct exec) : 0) +#define SEGMENT_SIZE 0x400000 + +#define N_DATADDR(x) \ + ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + (SEGMENT_SIZE + ((N_TXTADDR(x)+(x).a_text-1) & ~(SEGMENT_SIZE-1))) : \ + (N_TXTADDR(x)+(x).a_text)) diff --git a/include/aout/host.h b/include/aout/host.h new file mode 100644 index 000000000..442981ac9 --- /dev/null +++ b/include/aout/host.h @@ -0,0 +1,42 @@ +/* host.h - Parameters about the a.out format, based on the host system + on which the program is compiled. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Address of data segment in memory after it is loaded. + It is up to you to define SEGMENT_SIZE on machines not listed here. */ +#ifndef SEGMENT_SIZE + +#if defined(hp300) || defined(pyr) +#define SEGMENT_SIZE page_size +#endif + +#ifdef sony +#define SEGMENT_SIZE 0x1000 +#endif /* Sony. */ + +#ifdef is68k +#define SEGMENT_SIZE 0x20000 +#endif + +#if defined(m68k) && defined(PORTAR) +#define TARGET_PAGE_SIZE 0x400 +#define SEGMENT_SIZE TARGET_PAGE_SIZE +#endif + +#endif /*!defined(SEGMENT_SIZE)*/ + diff --git a/include/aout/hp.h b/include/aout/hp.h new file mode 100644 index 000000000..002f49cf4 --- /dev/null +++ b/include/aout/hp.h @@ -0,0 +1,82 @@ +/* Special version of <a.out.h> for use under hp-ux. + Copyright 1988, 1991 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* THIS FILE IS OBSOLETE. It needs to be revised as a variant "external" + a.out format for use with BFD. */ + +/* The `exec' structure and overall layout must be close to HP's when + we are running on an HP system, otherwise we will not be able to + execute the resulting file. */ + +/* Allow this file to be included twice. */ +#ifndef __GNU_EXEC_MACROS__ + +struct exec +{ + unsigned short a_machtype; /* machine type */ + unsigned short a_magic; /* magic number */ + unsigned long a_spare1; + unsigned long a_spare2; + unsigned long a_text; /* length of text, in bytes */ + unsigned long a_data; /* length of data, in bytes */ + unsigned long a_bss; /* length of uninitialized data area for file, in bytes */ + unsigned long a_trsize; /* length of relocation info for text, in bytes */ + unsigned long a_drsize; /* length of relocation info for data, in bytes */ + unsigned long a_spare3; /* HP = pascal interface size */ + unsigned long a_spare4; /* HP = symbol table size */ + unsigned long a_spare5; /* HP = debug name table size */ + unsigned long a_entry; /* start address */ + unsigned long a_spare6; /* HP = source line table size */ + unsigned long a_spare7; /* HP = value table size */ + unsigned long a_syms; /* length of symbol table data in file, in bytes */ + unsigned long a_spare8; +}; + +/* Tell a.out.gnu.h not to define `struct exec'. */ +#define __STRUCT_EXEC_OVERRIDE__ + +#include "../a.out.gnu.h" + +#undef N_MAGIC +#undef N_MACHTYPE +#undef N_FLAGS +#undef N_SET_INFO +#undef N_SET_MAGIC +#undef N_SET_MACHTYPE +#undef N_SET_FLAGS + +#define N_MAGIC(exec) ((exec) . a_magic) +#define N_MACHTYPE(exec) ((exec) . a_machtype) +#define N_SET_MAGIC(exec, magic) (((exec) . a_magic) = (magic)) +#define N_SET_MACHTYPE(exec, machtype) (((exec) . a_machtype) = (machtype)) + +#undef N_BADMAG +#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x))) + +#define _N_BADMACH(x) \ +(((N_MACHTYPE (x)) != HP9000S200_ID) && \ + ((N_MACHTYPE (x)) != HP98x6_ID)) + +#define HP98x6_ID 0x20A +#define HP9000S200_ID 0x20C + +#undef _N_HDROFF +#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec))) + +#define SEGMENT_SIZE 0x1000 + +#endif /* __GNU_EXEC_MACROS__ */ diff --git a/include/aout/hp300hpux.h b/include/aout/hp300hpux.h new file mode 100644 index 000000000..11747613c --- /dev/null +++ b/include/aout/hp300hpux.h @@ -0,0 +1,119 @@ +/* Special version of <a.out.h> for use under hp-ux. + Copyright 1988, 1993, 1995, 2001 Free Software Foundation, Inc. */ + +struct hp300hpux_exec_bytes +{ + unsigned char e_info[4]; /* a_machtype/a_magic */ + unsigned char e_spare1[4]; + unsigned char e_spare2[4]; + unsigned char e_text[4]; /* length of text, in bytes */ + unsigned char e_data[4]; /* length of data, in bytes */ + unsigned char e_bss[4]; /* length of uninitialized data area , in bytes */ + unsigned char e_trsize[4]; /* length of relocation info for text, in bytes*/ + unsigned char e_drsize[4]; /* length of relocation info for data, in bytes*/ + unsigned char e_passize[4];/* HP = pascal interface size */ + unsigned char e_syms[4]; /* HP = symbol table size */ + unsigned char e_spare5[4]; /* HP = debug name table size */ + unsigned char e_entry[4]; /* start address */ + unsigned char e_spare6[4]; /* HP = source line table size */ + unsigned char e_supsize[4];/* HP = value table size */ + unsigned char e_drelocs[4]; + unsigned char e_extension[4]; /* file offset of extension */ +}; +#define EXEC_BYTES_SIZE 64 + +struct hp300hpux_nlist_bytes + { + unsigned char e_value[4]; + unsigned char e_type[1]; + unsigned char e_length[1]; /* length of ascii symbol name */ + unsigned char e_almod[2]; /* alignment mod */ + unsigned char e_shlib[2]; /* info about dynamic linking */ + }; +#define EXTERNAL_NLIST_SIZE 10 + +struct hp300hpux_reloc + { + unsigned char r_address[4];/* offset of of data to relocate */ + unsigned char r_index[2]; /* symbol table index of symbol */ + unsigned char r_type[1]; /* relocation type */ + unsigned char r_length[1]; /* length of item to reloc */ + }; + +struct hp300hpux_header_extension +{ + unsigned char e_syms[4]; + unsigned char unique_headers[12*4]; + unsigned char e_header[2]; /* type of header */ + unsigned char e_version[2]; /* version */ + unsigned char e_size[4]; /* bytes following*/ + unsigned char e_extension[4];/* file offset of next extension */ +}; +#define EXTERNAL_EXTENSION_HEADER_SIZE (16*4) + +/* hpux separates object files (0x106) and impure executables (0x107) */ +/* but the bfd code does not distinguish between them. Since we want to*/ +/* read hpux .o files, we add an special define and use it below in */ +/* offset and address calculations. */ + +#define HPUX_DOT_O_MAGIC 0x106 +#define OMAGIC 0x107 /* object file or impure executable. */ +#define NMAGIC 0x108 /* Code indicating pure executable. */ +#define ZMAGIC 0x10B /* demand-paged executable. */ + +#define N_HEADER_IN_TEXT(x) 0 + +#if 0 /* libaout.h only uses the lower 8 bits */ +#define HP98x6_ID 0x20A +#define HP9000S200_ID 0x20C +#endif +#define HP98x6_ID 0x0A +#define HP9000S200_ID 0x0C + +#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x))) + +#define N_DATADDR(x) \ + ((N_MAGIC (x) == OMAGIC || N_MAGIC (x) == HPUX_DOT_O_MAGIC) \ + ? (N_TXTADDR (x) + N_TXTSIZE (x)) \ + : (N_SEGSIZE (x) + ((N_TXTADDR (x) + N_TXTSIZE (x) - 1) \ + & ~ (bfd_vma) (N_SEGSIZE (x) - 1)))) + +#define _N_BADMACH(x) \ + (((N_MACHTYPE (x)) != HP9000S200_ID) && ((N_MACHTYPE (x)) != HP98x6_ID)) + +#define _N_BADMAG(x) (N_MAGIC(x) != HPUX_DOT_O_MAGIC \ + && N_MAGIC(x) != OMAGIC \ + && N_MAGIC(x) != NMAGIC \ + && N_MAGIC(x) != ZMAGIC ) + +#undef _N_HDROFF +#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec))) + +#undef N_DATOFF +#undef N_PASOFF +#undef N_SYMOFF +#undef N_SUPOFF +#undef N_TRELOFF +#undef N_DRELOFF +#undef N_STROFF + +#define N_DATOFF(x) ( N_TXTOFF(x) + N_TXTSIZE(x) ) +#define N_PASOFF(x) ( N_DATOFF(x) + (x).a_data) +#define N_SYMOFF(x) ( N_PASOFF(x) /* + (x).a_passize*/ ) +#define N_SUPOFF(x) ( N_SYMOFF(x) + (x).a_syms ) +#define N_TRELOFF(x) ( N_SUPOFF(x) /* + 0 (x).a_supsize*/ ) +#define N_DRELOFF(x) ( N_TRELOFF(x) + (x).a_trsize ) +#define N_EXTHOFF(x) ( N_DRELOFF(x) /* + 0 (x).a_drsize */) +#define N_STROFF(x) ( 0 /* no string table */ ) + +/* use these when the file has gnu symbol tables */ +#define N_GNU_TRELOFF(x) (N_DATOFF(x) + (x).a_data) +#define N_GNU_DRELOFF(x) (N_GNU_TRELOFF(x) + (x).a_trsize) +#define N_GNU_SYMOFF(x) (N_GNU_DRELOFF(x) + (x).a_drsize) + +#define TARGET_PAGE_SIZE 0x1000 +#define SEGMENT_SIZE 0x1000 +#define TEXT_START_ADDR 0 + +#undef N_SHARED_LIB +#define N_SHARED_LIB(x) ( 0 /* no shared libraries */ ) diff --git a/include/aout/hppa.h b/include/aout/hppa.h new file mode 100644 index 000000000..7e185de76 --- /dev/null +++ b/include/aout/hppa.h @@ -0,0 +1,7 @@ +#include "filehdr.h" +#include "aouthdr.h" +#include "scnhdr.h" +#include "spacehdr.h" +#include "syms.h" + + diff --git a/include/aout/ranlib.h b/include/aout/ranlib.h new file mode 100644 index 000000000..e4603edf6 --- /dev/null +++ b/include/aout/ranlib.h @@ -0,0 +1,62 @@ +/* ranlib.h -- archive library index member definition for GNU. + Copyright 1990, 1991 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* The Symdef member of an archive contains two things: + a table that maps symbol-string offsets to file offsets, + and a symbol-string table. All the symbol names are + run together (each with trailing null) in the symbol-string + table. There is a single longword bytecount on the front + of each of these tables. Thus if we have two symbols, + "foo" and "_bar", that are in archive members at offsets + 200 and 900, it would look like this: + 16 ; byte count of index table + 0 ; offset of "foo" in string table + 200 ; offset of foo-module in file + 4 ; offset of "bar" in string table + 900 ; offset of bar-module in file + 9 ; byte count of string table + "foo\0_bar\0" ; string table */ + +#define RANLIBMAG "__.SYMDEF" /* Archive file name containing index */ +#define RANLIBSKEW 3 /* Creation time offset */ + +/* Format of __.SYMDEF: + First, a longword containing the size of the 'symdef' data that follows. + Second, zero or more 'symdef' structures. + Third, a longword containing the length of symbol name strings. + Fourth, zero or more symbol name strings (each followed by a null). */ + +struct symdef + { + union + { + unsigned long string_offset; /* In the file */ + char *name; /* In memory, sometimes */ + } s; + /* this points to the front of the file header (AKA member header -- + a struct ar_hdr), not to the front of the file or into the file). + in other words it only tells you which file to read */ + unsigned long file_offset; + }; + +/* Compatability with BSD code */ + +#define ranlib symdef +#define ran_un s +#define ran_strx string_offset +#define ran_name name +#define ran_off file_offset diff --git a/include/aout/reloc.h b/include/aout/reloc.h new file mode 100644 index 000000000..eca3f59b2 --- /dev/null +++ b/include/aout/reloc.h @@ -0,0 +1,66 @@ +/* reloc.h -- Header file for relocation information. + Copyright 1989, 1990, 1991 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Relocation types for a.out files using reloc_info_extended + (SPARC and AMD 29000). */ + +#ifndef _RELOC_H_READ_ +#define _RELOC_H_READ_ 1 + +enum reloc_type + { + RELOC_8, RELOC_16, RELOC_32, /* simple relocations */ + RELOC_DISP8, RELOC_DISP16, RELOC_DISP32, /* pc-rel displacement */ + RELOC_WDISP30, RELOC_WDISP22, + RELOC_HI22, RELOC_22, + RELOC_13, RELOC_LO10, + RELOC_SFA_BASE, RELOC_SFA_OFF13, + RELOC_BASE10, RELOC_BASE13, RELOC_BASE22, /* P.I.C. (base-relative) */ + RELOC_PC10, RELOC_PC22, /* for some sort of pc-rel P.I.C. (?) */ + RELOC_JMP_TBL, /* P.I.C. jump table */ + RELOC_SEGOFF16, /* reputedly for shared libraries somehow */ + RELOC_GLOB_DAT, RELOC_JMP_SLOT, RELOC_RELATIVE, + RELOC_11, + RELOC_WDISP2_14, + RELOC_WDISP19, + RELOC_HHI22, + RELOC_HLO10, + + /* 29K relocation types */ + RELOC_JUMPTARG, RELOC_CONST, RELOC_CONSTH, + + RELOC_WDISP14, RELOC_WDISP21, + + NO_RELOC + }; + +#define RELOC_TYPE_NAMES \ +"8", "16", "32", "DISP8", \ +"DISP16", "DISP32", "WDISP30", "WDISP22", \ +"HI22", "22", "13", "LO10", \ +"SFA_BASE", "SFAOFF13", "BASE10", "BASE13", \ +"BASE22", "PC10", "PC22", "JMP_TBL", \ +"SEGOFF16", "GLOB_DAT", "JMP_SLOT", "RELATIVE", \ +"11", "WDISP2_14", "WDISP19", "HHI22", \ +"HLO10", \ +"JUMPTARG", "CONST", "CONSTH", "WDISP14", \ +"WDISP21", \ +"NO_RELOC" + +#endif /* _RELOC_H_READ_ */ + +/* end of reloc.h */ diff --git a/include/aout/stab.def b/include/aout/stab.def new file mode 100644 index 000000000..8188b845f --- /dev/null +++ b/include/aout/stab.def @@ -0,0 +1,271 @@ +/* Table of DBX symbol codes for the GNU system. + Copyright 1988, 1991, 1992, 1993, 1994, 1996, 1998, 2004 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* New stab from Solaris 2. This uses an n_type of 0, which in a.out files + overlaps the N_UNDF used for ordinary symbols. In ELF files, the + debug information is in a different file section, so there is no conflict. + This symbol's n_value gives the size of the string section associated + with this file. The symbol's n_strx (relative to the just-updated + string section start address) gives the name of the source file, + e.g. "foo.c", without any path information. The symbol's n_desc gives + the count of upcoming symbols associated with this file (not including + this one). */ +/* __define_stab (N_UNDF, 0x00, "UNDF") */ + +/* Global variable. Only the name is significant. + To find the address, look in the corresponding external symbol. */ +__define_stab (N_GSYM, 0x20, "GSYM") + +/* Function name for BSD Fortran. Only the name is significant. + To find the address, look in the corresponding external symbol. */ +__define_stab (N_FNAME, 0x22, "FNAME") + +/* Function name or text-segment variable for C. Value is its address. + Desc is supposedly starting line number, but GCC doesn't set it + and DBX seems not to miss it. */ +__define_stab (N_FUN, 0x24, "FUN") + +/* Data-segment variable with internal linkage. Value is its address. + "Static Sym". */ +__define_stab (N_STSYM, 0x26, "STSYM") + +/* BSS-segment variable with internal linkage. Value is its address. */ +__define_stab (N_LCSYM, 0x28, "LCSYM") + +/* Name of main routine. Only the name is significant. */ +__define_stab (N_MAIN, 0x2a, "MAIN") + +/* Solaris2: Read-only data symbols. */ +__define_stab (N_ROSYM, 0x2c, "ROSYM") + +/* Global symbol in Pascal. + Supposedly the value is its line number; I'm skeptical. */ +__define_stab (N_PC, 0x30, "PC") + +/* Number of symbols: 0, files,,funcs,lines according to Ultrix V4.0. */ +__define_stab (N_NSYMS, 0x32, "NSYMS") + +/* "No DST map for sym: name, ,0,type,ignored" according to Ultrix V4.0. */ +__define_stab (N_NOMAP, 0x34, "NOMAP") + +/* New stab from Solaris 2. Like N_SO, but for the object file. Two in + a row provide the build directory and the relative path of the .o from it. + Solaris2 uses this to avoid putting the stabs info into the linked + executable; this stab goes into the ".stab.index" section, and the debugger + reads the real stabs directly from the .o files instead. */ +__define_stab (N_OBJ, 0x38, "OBJ") + +/* New stab from Solaris 2. Options for the debugger, related to the + source language for this module. E.g. whether to use ANSI + integral promotions or traditional integral promotions. */ +__define_stab (N_OPT, 0x3c, "OPT") + +/* Register variable. Value is number of register. */ +__define_stab (N_RSYM, 0x40, "RSYM") + +/* Modula-2 compilation unit. Can someone say what info it contains? */ +__define_stab (N_M2C, 0x42, "M2C") + +/* Line number in text segment. Desc is the line number; + value is corresponding address. On Solaris2, the line number is + relative to the start of the current function. */ +__define_stab (N_SLINE, 0x44, "SLINE") + +/* Similar, for data segment. */ +__define_stab (N_DSLINE, 0x46, "DSLINE") + +/* Similar, for bss segment. */ +__define_stab (N_BSLINE, 0x48, "BSLINE") + +/* Sun's source-code browser stabs. ?? Don't know what the fields are. + Supposedly the field is "path to associated .cb file". THIS VALUE + OVERLAPS WITH N_BSLINE! */ +__define_stab_duplicate (N_BROWS, 0x48, "BROWS") + +/* GNU Modula-2 definition module dependency. Value is the modification time + of the definition file. Other is non-zero if it is imported with the + GNU M2 keyword %INITIALIZE. Perhaps N_M2C can be used if there + are enough empty fields? */ +__define_stab(N_DEFD, 0x4a, "DEFD") + +/* New in Solaris2. Function start/body/end line numbers. */ +__define_stab(N_FLINE, 0x4C, "FLINE") + +/* THE FOLLOWING TWO STAB VALUES CONFLICT. Happily, one is for Modula-2 + and one is for C++. Still,... */ +/* GNU C++ exception variable. Name is variable name. */ +__define_stab (N_EHDECL, 0x50, "EHDECL") +/* Modula2 info "for imc": name,,0,0,0 according to Ultrix V4.0. */ +__define_stab_duplicate (N_MOD2, 0x50, "MOD2") + +/* GNU C++ `catch' clause. Value is its address. Desc is nonzero if + this entry is immediately followed by a CAUGHT stab saying what exception + was caught. Multiple CAUGHT stabs means that multiple exceptions + can be caught here. If Desc is 0, it means all exceptions are caught + here. */ +__define_stab (N_CATCH, 0x54, "CATCH") + +/* Structure or union element. Value is offset in the structure. */ +__define_stab (N_SSYM, 0x60, "SSYM") + +/* Solaris2: Last stab emitted for module. */ +__define_stab (N_ENDM, 0x62, "ENDM") + +/* Name of main source file. + Value is starting text address of the compilation. + If multiple N_SO's appear, the first to contain a trailing / is the + compilation directory. The first to not contain a trailing / is the + source file name, relative to the compilation directory. Others (perhaps + resulting from cfront) are ignored. + On Solaris2, value is undefined, but desc is a source-language code. */ + +__define_stab (N_SO, 0x64, "SO") + +/* SunPro F77: Name of alias. */ +__define_stab (N_ALIAS, 0x6c, "ALIAS") + +/* Automatic variable in the stack. Value is offset from frame pointer. + Also used for type descriptions. */ +__define_stab (N_LSYM, 0x80, "LSYM") + +/* Beginning of an include file. Only Sun uses this. + In an object file, only the name is significant. + The Sun linker puts data into some of the other fields. */ +__define_stab (N_BINCL, 0x82, "BINCL") + +/* Name of sub-source file (#include file). + Value is starting text address of the compilation. */ +__define_stab (N_SOL, 0x84, "SOL") + +/* Parameter variable. Value is offset from argument pointer. + (On most machines the argument pointer is the same as the frame pointer. */ +__define_stab (N_PSYM, 0xa0, "PSYM") + +/* End of an include file. No name. + This and N_BINCL act as brackets around the file's output. + In an object file, there is no significant data in this entry. + The Sun linker puts data into some of the fields. */ +__define_stab (N_EINCL, 0xa2, "EINCL") + +/* Alternate entry point. Value is its address. */ +__define_stab (N_ENTRY, 0xa4, "ENTRY") + +/* Beginning of lexical block. + The desc is the nesting level in lexical blocks. + The value is the address of the start of the text for the block. + The variables declared inside the block *precede* the N_LBRAC symbol. + On Solaris2, the value is relative to the start of the current function. */ +__define_stab (N_LBRAC, 0xc0, "LBRAC") + +/* Place holder for deleted include file. Replaces a N_BINCL and everything + up to the corresponding N_EINCL. The Sun linker generates these when + it finds multiple identical copies of the symbols from an include file. + This appears only in output from the Sun linker. */ +__define_stab (N_EXCL, 0xc2, "EXCL") + +/* Modula-2 scope information. Can someone say what info it contains? */ +__define_stab (N_SCOPE, 0xc4, "SCOPE") + +/* Solaris2: Patch Run Time Checker. */ +__define_stab (N_PATCH, 0xd0, "PATCH") + +/* End of a lexical block. Desc matches the N_LBRAC's desc. + The value is the address of the end of the text for the block. + On Solaris2, the value is relative to the start of the current function. */ +__define_stab (N_RBRAC, 0xe0, "RBRAC") + +/* Begin named common block. Only the name is significant. */ +__define_stab (N_BCOMM, 0xe2, "BCOMM") + +/* End named common block. Only the name is significant + (and it should match the N_BCOMM). */ +__define_stab (N_ECOMM, 0xe4, "ECOMM") + +/* Member of a common block; value is offset within the common block. + This should occur within a BCOMM/ECOMM pair. */ +__define_stab (N_ECOML, 0xe8, "ECOML") + +/* Solaris2: Pascal "with" statement: type,,0,0,offset */ +__define_stab (N_WITH, 0xea, "WITH") + +/* These STAB's are used on Gould systems for Non-Base register symbols + or something like that. FIXME. I have assigned the values at random + since I don't have a Gould here. Fixups from Gould folk welcome... */ +__define_stab (N_NBTEXT, 0xF0, "NBTEXT") +__define_stab (N_NBDATA, 0xF2, "NBDATA") +__define_stab (N_NBBSS, 0xF4, "NBBSS") +__define_stab (N_NBSTS, 0xF6, "NBSTS") +__define_stab (N_NBLCS, 0xF8, "NBLCS") + +/* Second symbol entry containing a length-value for the preceding entry. + The value is the length. */ +__define_stab (N_LENG, 0xfe, "LENG") + +/* The above information, in matrix format. + + STAB MATRIX + _________________________________________________ + | 00 - 1F are not dbx stab symbols | + | In most cases, the low bit is the EXTernal bit| + + | 00 UNDEF | 02 ABS | 04 TEXT | 06 DATA | + | 01 |EXT | 03 |EXT | 05 |EXT | 07 |EXT | + + | 08 BSS | 0A INDR | 0C FN_SEQ | 0E WEAKA | + | 09 |EXT | 0B | 0D WEAKU | 0F WEAKT | + + | 10 WEAKD | 12 COMM | 14 SETA | 16 SETT | + | 11 WEAKB | 13 | 15 | 17 | + + | 18 SETD | 1A SETB | 1C SETV | 1E WARNING| + | 19 | 1B | 1D | 1F FN | + + |_______________________________________________| + | Debug entries with bit 01 set are unused. | + | 20 GSYM | 22 FNAME | 24 FUN | 26 STSYM | + | 28 LCSYM | 2A MAIN | 2C ROSYM | 2E | + | 30 PC | 32 NSYMS | 34 NOMAP | 36 | + | 38 OBJ | 3A | 3C OPT | 3E | + | 40 RSYM | 42 M2C | 44 SLINE | 46 DSLINE | + | 48 BSLINE*| 4A DEFD | 4C FLINE | 4E | + | 50 EHDECL*| 52 | 54 CATCH | 56 | + | 58 | 5A | 5C | 5E | + | 60 SSYM | 62 ENDM | 64 SO | 66 | + | 68 | 6A | 6C ALIAS | 6E | + | 70 | 72 | 74 | 76 | + | 78 | 7A | 7C | 7E | + | 80 LSYM | 82 BINCL | 84 SOL | 86 | + | 88 | 8A | 8C | 8E | + | 90 | 92 | 94 | 96 | + | 98 | 9A | 9C | 9E | + | A0 PSYM | A2 EINCL | A4 ENTRY | A6 | + | A8 | AA | AC | AE | + | B0 | B2 | B4 | B6 | + | B8 | BA | BC | BE | + | C0 LBRAC | C2 EXCL | C4 SCOPE | C6 | + | C8 | CA | CC | CE | + | D0 PATCH | D2 | D4 | D6 | + | D8 | DA | DC | DE | + | E0 RBRAC | E2 BCOMM | E4 ECOMM | E6 | + | E8 ECOML | EA WITH | EC | EE | + | F0 | F2 | F4 | F6 | + | F8 | FA | FC | FE LENG | + +-----------------------------------------------+ + * 50 EHDECL is also MOD2. + * 48 BSLINE is also BROWS. + */ diff --git a/include/aout/stab_gnu.h b/include/aout/stab_gnu.h new file mode 100644 index 000000000..c62ac6ed4 --- /dev/null +++ b/include/aout/stab_gnu.h @@ -0,0 +1,54 @@ +/* gnu_stab.h Definitions for GNU extensions to STABS + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#ifndef __GNU_STAB__ + +/* Indicate the GNU stab.h is in use. */ + +#define __GNU_STAB__ + +#define __define_stab(NAME, CODE, STRING) NAME=CODE, +#define __define_stab_duplicate(NAME, CODE, STRING) NAME=CODE, + +enum __stab_debug_code +{ +#include "aout/stab.def" +LAST_UNUSED_STAB_CODE +}; + +#undef __define_stab + +/* Definitions of "desc" field for N_SO stabs in Solaris2. */ + +#define N_SO_AS 1 +#define N_SO_C 2 +#define N_SO_ANSI_C 3 +#define N_SO_CC 4 /* C++ */ +#define N_SO_FORTRAN 5 +#define N_SO_PASCAL 6 + +/* Solaris2: Floating point type values in basic types. */ + +#define NF_NONE 0 +#define NF_SINGLE 1 /* IEEE 32-bit */ +#define NF_DOUBLE 2 /* IEEE 64-bit */ +#define NF_COMPLEX 3 /* Fortran complex */ +#define NF_COMPLEX16 4 /* Fortran double complex */ +#define NF_COMPLEX32 5 /* Fortran complex*16 */ +#define NF_LDOUBLE 6 /* Long double (whatever that is) */ + +#endif /* __GNU_STAB_ */ diff --git a/include/aout/sun4.h b/include/aout/sun4.h new file mode 100644 index 000000000..623afc131 --- /dev/null +++ b/include/aout/sun4.h @@ -0,0 +1,235 @@ +/* SPARC-specific values for a.out files + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Some systems, e.g., AIX, may have defined this in header files already + included. */ +#undef TARGET_PAGE_SIZE +#define TARGET_PAGE_SIZE 0x2000 /* 8K. aka NBPG in <sys/param.h> */ +/* Note that some SPARCs have 4K pages, some 8K, some others. */ + +#define SEG_SIZE_SPARC TARGET_PAGE_SIZE +#define SEG_SIZE_SUN3 0x20000 /* Resolution of r/w protection hw */ + +#define TEXT_START_ADDR TARGET_PAGE_SIZE /* Location 0 is not accessible */ +#define N_HEADER_IN_TEXT(x) 1 + +/* Non-default definitions of the accessor macros... */ + +/* Segment size varies on Sun-3 versus Sun-4. */ + +#define N_SEGSIZE(x) (N_MACHTYPE(x) == M_SPARC? SEG_SIZE_SPARC: \ + N_MACHTYPE(x) == M_68020? SEG_SIZE_SUN3: \ + /* Guess? */ TARGET_PAGE_SIZE) + +/* Virtual Address of text segment from the a.out file. For OMAGIC, + (almost always "unlinked .o's" these days), should be zero. + Sun added a kludge so that shared libraries linked ZMAGIC get + an address of zero if a_entry (!!!) is lower than the otherwise + expected text address. These kludges have gotta go! + For linked files, should reflect reality if we know it. */ + +/* This differs from the version in aout64.h (which we override by defining + it here) only for NMAGIC (we return TEXT_START_ADDR+EXEC_BYTES_SIZE; + they return 0). */ + +#define N_TXTADDR(x) \ + (N_MAGIC(x)==OMAGIC? 0 \ + : (N_MAGIC(x) == ZMAGIC && (x).a_entry < TEXT_START_ADDR)? 0 \ + : TEXT_START_ADDR+EXEC_BYTES_SIZE) + +/* When a file is linked against a shared library on SunOS 4, the + dynamic bit in the exec header is set, and the first symbol in the + symbol table is __DYNAMIC. Its value is the address of the + following structure. */ + +struct external_sun4_dynamic +{ + /* The version number of the structure. SunOS 4.1.x creates files + with version number 3, which is what this structure is based on. + According to gdb, version 2 is similar. I believe that version 2 + used a different type of procedure linkage table, and there may + have been other differences. */ + bfd_byte ld_version[4]; + /* The virtual address of a 28 byte structure used in debugging. + The contents are filled in at run time by ld.so. */ + bfd_byte ldd[4]; + /* The virtual address of another structure with information about + how to relocate the executable at run time. */ + bfd_byte ld[4]; +}; + +/* The size of the debugging structure pointed to by the debugger + field of __DYNAMIC. */ +#define EXTERNAL_SUN4_DYNAMIC_DEBUGGER_SIZE (24) + +/* The structure pointed to by the linker field of __DYNAMIC. As far + as I can tell, most of the addresses in this structure are offsets + within the file, but some are actually virtual addresses. */ + +struct internal_sun4_dynamic_link +{ + /* Linked list of loaded objects. This is filled in at runtime by + ld.so and probably by dlopen. */ + unsigned long ld_loaded; + + /* The address of the list of names of shared objects which must be + included at runtime. Each entry in the list is 16 bytes: the 4 + byte address of the string naming the object (e.g., for -lc this + is "c"); 4 bytes of flags--the high bit is whether to search for + the object using the library path; the 2 byte major version + number; the 2 byte minor version number; the 4 byte address of + the next entry in the list (zero if this is the last entry). The + version numbers seem to only be non-zero when doing library + searching. */ + unsigned long ld_need; + + /* The address of the path to search for the shared objects which + must be included. This points to a string in PATH format which + is generated from the -L arguments to the linker. According to + the man page, ld.so implicitly adds ${LD_LIBRARY_PATH} to the + beginning of this string and /lib:/usr/lib:/usr/local/lib to the + end. The string is terminated by a null byte. This field is + zero if there is no additional path. */ + unsigned long ld_rules; + + /* The address of the global offset table. This appears to be a + virtual address, not a file offset. The first entry in the + global offset table seems to be the virtual address of the + sun4_dynamic structure (the same value as the __DYNAMIC symbol). + The global offset table is used for PIC code to hold the + addresses of variables. A dynamically linked file which does not + itself contain PIC code has a four byte global offset table. */ + unsigned long ld_got; + + /* The address of the procedure linkage table. This appears to be a + virtual address, not a file offset. + + On a SPARC, the table is composed of 12 byte entries, each of + which consists of three instructions. The first entry is + sethi %hi(0),%g1 + jmp %g1 + nop + These instructions are changed by ld.so into a jump directly into + ld.so itself. Each subsequent entry is + save %sp, -96, %sp + call <address of first entry in procedure linkage table> + <reloc_number | 0x01000000> + The reloc_number is the number of the reloc to use to resolve + this entry. The reloc will be a JMP_SLOT reloc against some + symbol that is not defined in this object file but should be + defined in a shared object (if it is not, ld.so will report a + runtime error and exit). The constant 0x010000000 turns the + reloc number into a sethi of %g0, which does nothing since %g0 is + hardwired to zero. + + When one of these entries is executed, it winds up calling into + ld.so. ld.so looks at the reloc number, available via the return + address, to determine which entry this is. It then looks at the + reloc and patches up the entry in the table into a sethi and jmp + to the real address followed by a nop. This means that the reloc + lookup only has to happen once, and it also means that the + relocation only needs to be done if the function is actually + called. The relocation is expensive because ld.so must look up + the symbol by name. + + The size of the procedure linkage table is given by the ld_plt_sz + field. */ + unsigned long ld_plt; + + /* The address of the relocs. These are in the same format as + ordinary relocs. Symbol index numbers refer to the symbols + pointed to by ld_stab. I think the only way to determine the + number of relocs is to assume that all the bytes from ld_rel to + ld_hash contain reloc entries. */ + unsigned long ld_rel; + + /* The address of a hash table of symbols. The hash table has + roughly the same number of entries as there are dynamic symbols; + I think the only way to get the exact size is to assume that + every byte from ld_hash to ld_stab is devoted to the hash table. + + Each entry in the hash table is eight bytes. The first four + bytes are a symbol index into the dynamic symbols. The second + four bytes are the index of the next hash table entry in the + bucket. The ld_buckets field gives the number of buckets, say B. + The first B entries in the hash table each start a bucket which + is chained through the second four bytes of each entry. A value + of zero ends the chain. + + The hash function is simply + h = 0; + while (*string != '\0') + h = (h << 1) + *string++; + h &= 0x7fffffff; + + To look up a symbol, compute the hash value of the name. Take + the modulos of hash value and the number of buckets. Start at + that entry in the hash table. See if the symbol (from the first + four bytes of the hash table entry) has the name you are looking + for. If not, use the chain field (the second four bytes of the + hash table entry) to move on to the next entry in this bucket. + If the chain field is zero you have reached the end of the + bucket, and the symbol is not in the hash table. */ + unsigned long ld_hash; + + /* The address of the symbol table. This is a list of + external_nlist structures. The string indices are relative to + the ld_symbols field. I think the only way to determine the + number of symbols is to assume that all the bytes between ld_stab + and ld_symbols are external_nlist structures. */ + unsigned long ld_stab; + + /* I don't know what this is for. It seems to always be zero. */ + unsigned long ld_stab_hash; + + /* The number of buckets in the hash table. */ + unsigned long ld_buckets; + + /* The address of the symbol string table. The first string in this + string table need not be the empty string. */ + unsigned long ld_symbols; + + /* The size in bytes of the symbol string table. */ + unsigned long ld_symb_size; + + /* The size in bytes of the text segment. */ + unsigned long ld_text; + + /* The size in bytes of the procedure linkage table. */ + unsigned long ld_plt_sz; +}; + +/* The external form of the structure. */ + +struct external_sun4_dynamic_link +{ + bfd_byte ld_loaded[4]; + bfd_byte ld_need[4]; + bfd_byte ld_rules[4]; + bfd_byte ld_got[4]; + bfd_byte ld_plt[4]; + bfd_byte ld_rel[4]; + bfd_byte ld_hash[4]; + bfd_byte ld_stab[4]; + bfd_byte ld_stab_hash[4]; + bfd_byte ld_buckets[4]; + bfd_byte ld_symbols[4]; + bfd_byte ld_symb_size[4]; + bfd_byte ld_text[4]; + bfd_byte ld_plt_sz[4]; +}; diff --git a/include/bfdlink.h b/include/bfdlink.h new file mode 100644 index 000000000..5aa72d4b4 --- /dev/null +++ b/include/bfdlink.h @@ -0,0 +1,692 @@ +/* bfdlink.h -- header file for BFD link routines + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003, + 2004 Free Software Foundation, Inc. + Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef BFDLINK_H +#define BFDLINK_H + +/* Which symbols to strip during a link. */ +enum bfd_link_strip +{ + strip_none, /* Don't strip any symbols. */ + strip_debugger, /* Strip debugging symbols. */ + strip_some, /* keep_hash is the list of symbols to keep. */ + strip_all /* Strip all symbols. */ +}; + +/* Which local symbols to discard during a link. This is irrelevant + if strip_all is used. */ +enum bfd_link_discard +{ + discard_sec_merge, /* Discard local temporary symbols in SEC_MERGE + sections. */ + discard_none, /* Don't discard any locals. */ + discard_l, /* Discard local temporary symbols. */ + discard_all /* Discard all locals. */ +}; + +/* Describes the type of hash table entry structure being used. + Different hash table structure have different fields and so + support different linking features. */ +enum bfd_link_hash_table_type + { + bfd_link_generic_hash_table, + bfd_link_elf_hash_table + }; + +/* These are the possible types of an entry in the BFD link hash + table. */ + +enum bfd_link_hash_type +{ + bfd_link_hash_new, /* Symbol is new. */ + bfd_link_hash_undefined, /* Symbol seen before, but undefined. */ + bfd_link_hash_undefweak, /* Symbol is weak and undefined. */ + bfd_link_hash_defined, /* Symbol is defined. */ + bfd_link_hash_defweak, /* Symbol is weak and defined. */ + bfd_link_hash_common, /* Symbol is common. */ + bfd_link_hash_indirect, /* Symbol is an indirect link. */ + bfd_link_hash_warning /* Like indirect, but warn if referenced. */ +}; + +enum bfd_link_common_skip_ar_aymbols +{ + bfd_link_common_skip_none, + bfd_link_common_skip_text, + bfd_link_common_skip_data, + bfd_link_common_skip_all +}; + +/* The linking routines use a hash table which uses this structure for + its elements. */ + +struct bfd_link_hash_entry +{ + /* Base hash table entry structure. */ + struct bfd_hash_entry root; + + /* Type of this entry. */ + enum bfd_link_hash_type type; + + /* A union of information depending upon the type. */ + union + { + /* Nothing is kept for bfd_hash_new. */ + /* bfd_link_hash_undefined, bfd_link_hash_undefweak. */ + struct + { + /* Undefined and common symbols are kept in a linked list through + this field. This field is present in all of the union element + so that we don't need to remove entries from the list when we + change their type. Removing entries would either require the + list to be doubly linked, which would waste more memory, or + require a traversal. When an undefined or common symbol is + created, it should be added to this list, the head of which is in + the link hash table itself. As symbols are defined, they need + not be removed from the list; anything which reads the list must + doublecheck the symbol type. + + Weak symbols are not kept on this list. + + Defined and defweak symbols use this field as a reference marker. + If the field is not NULL, or this structure is the tail of the + undefined symbol list, the symbol has been referenced. If the + symbol is undefined and becomes defined, this field will + automatically be non-NULL since the symbol will have been on the + undefined symbol list. */ + struct bfd_link_hash_entry *next; + bfd *abfd; /* BFD symbol was found in. */ + } undef; + /* bfd_link_hash_defined, bfd_link_hash_defweak. */ + struct + { + struct bfd_link_hash_entry *next; + asection *section; /* Symbol section. */ + bfd_vma value; /* Symbol value. */ + } def; + /* bfd_link_hash_indirect, bfd_link_hash_warning. */ + struct + { + struct bfd_link_hash_entry *next; + struct bfd_link_hash_entry *link; /* Real symbol. */ + const char *warning; /* Warning (bfd_link_hash_warning only). */ + } i; + /* bfd_link_hash_common. */ + struct + { + struct bfd_link_hash_entry *next; + /* The linker needs to know three things about common + symbols: the size, the alignment, and the section in + which the symbol should be placed. We store the size + here, and we allocate a small structure to hold the + section and the alignment. The alignment is stored as a + power of two. We don't store all the information + directly because we don't want to increase the size of + the union; this structure is a major space user in the + linker. */ + struct bfd_link_hash_common_entry + { + unsigned int alignment_power; /* Alignment. */ + asection *section; /* Symbol section. */ + } *p; + bfd_size_type size; /* Common symbol size. */ + } c; + } u; +}; + +/* This is the link hash table. It is a derived class of + bfd_hash_table. */ + +struct bfd_link_hash_table +{ + /* The hash table itself. */ + struct bfd_hash_table table; + /* The back end which created this hash table. This indicates the + type of the entries in the hash table, which is sometimes + important information when linking object files of different + types together. */ + const bfd_target *creator; + /* A linked list of undefined and common symbols, linked through the + next field in the bfd_link_hash_entry structure. */ + struct bfd_link_hash_entry *undefs; + /* Entries are added to the tail of the undefs list. */ + struct bfd_link_hash_entry *undefs_tail; + /* The type of the link hash table. */ + enum bfd_link_hash_table_type type; +}; + +/* Look up an entry in a link hash table. If FOLLOW is TRUE, this + follows bfd_link_hash_indirect and bfd_link_hash_warning links to + the real symbol. */ +extern struct bfd_link_hash_entry *bfd_link_hash_lookup + (struct bfd_link_hash_table *, const char *, bfd_boolean create, + bfd_boolean copy, bfd_boolean follow); + +/* Look up an entry in the main linker hash table if the symbol might + be wrapped. This should only be used for references to an + undefined symbol, not for definitions of a symbol. */ + +extern struct bfd_link_hash_entry *bfd_wrapped_link_hash_lookup + (bfd *, struct bfd_link_info *, const char *, bfd_boolean, + bfd_boolean, bfd_boolean); + +/* Traverse a link hash table. */ +extern void bfd_link_hash_traverse + (struct bfd_link_hash_table *, + bfd_boolean (*) (struct bfd_link_hash_entry *, void *), + void *); + +/* Add an entry to the undefs list. */ +extern void bfd_link_add_undef + (struct bfd_link_hash_table *, struct bfd_link_hash_entry *); + +struct bfd_sym_chain +{ + struct bfd_sym_chain *next; + const char *name; +}; + +/* How to handle unresolved symbols. + There are four possibilities which are enumerated below: */ +enum report_method +{ + /* This is the initial value when then link_info structure is created. + It allows the various stages of the linker to determine whether they + allowed to set the value. */ + RM_NOT_YET_SET = 0, + RM_IGNORE, + RM_GENERATE_WARNING, + RM_GENERATE_ERROR +}; + +/* This structure holds all the information needed to communicate + between BFD and the linker when doing a link. */ + +struct bfd_link_info +{ + /* TRUE if BFD should generate a relocatable object file. */ + unsigned int relocatable: 1; + + /* TRUE if BFD should generate relocation information in the final + executable. */ + unsigned int emitrelocations: 1; + + /* TRUE if BFD should generate a "task linked" object file, + similar to relocatable but also with globals converted to + statics. */ + unsigned int task_link: 1; + + /* TRUE if BFD should generate a shared object. */ + unsigned int shared: 1; + + /* TRUE if BFD should pre-bind symbols in a shared object. */ + unsigned int symbolic: 1; + + /* TRUE if BFD should export all symbols in the dynamic symbol table + of an executable, rather than only those used. */ + unsigned int export_dynamic: 1; + + /* TRUE if shared objects should be linked directly, not shared. */ + unsigned int static_link: 1; + + /* TRUE if the output file should be in a traditional format. This + is equivalent to the setting of the BFD_TRADITIONAL_FORMAT flag + on the output file, but may be checked when reading the input + files. */ + unsigned int traditional_format: 1; + + /* TRUE if we want to produced optimized output files. This might + need much more time and therefore must be explicitly selected. */ + unsigned int optimize: 1; + + /* TRUE if ok to have multiple definition. */ + unsigned int allow_multiple_definition: 1; + + /* TRUE if ok to have version with no definition. */ + unsigned int allow_undefined_version: 1; + + /* TRUE if symbols should be retained in memory, FALSE if they + should be freed and reread. */ + unsigned int keep_memory: 1; + + /* TRUE if every symbol should be reported back via the notice + callback. */ + unsigned int notice_all: 1; + + /* TRUE if executable should not contain copy relocs. + Setting this true may result in a non-sharable text segment. */ + unsigned int nocopyreloc: 1; + + /* TRUE if the new ELF dynamic tags are enabled. */ + unsigned int new_dtags: 1; + + /* TRUE if non-PLT relocs should be merged into one reloc section + and sorted so that relocs against the same symbol come together. */ + unsigned int combreloc: 1; + + /* TRUE if .eh_frame_hdr section and PT_GNU_EH_FRAME ELF segment + should be created. */ + unsigned int eh_frame_hdr: 1; + + /* TRUE if global symbols in discarded sections should be stripped. */ + unsigned int strip_discarded: 1; + + /* TRUE if the final relax pass is needed. */ + unsigned int need_relax_finalize: 1; + + /* TRUE if generating a position independent executable. */ + unsigned int pie: 1; + + /* TRUE if generating an executable, position independent or not. */ + unsigned int executable : 1; + + /* TRUE if PT_GNU_STACK segment should be created with PF_R|PF_W|PF_X + flags. */ + unsigned int execstack: 1; + + /* TRUE if PT_GNU_STACK segment should be created with PF_R|PF_W + flags. */ + unsigned int noexecstack: 1; + + /* TRUE if PT_GNU_RELRO segment should be created. */ + unsigned int relro: 1; + + /* What to do with unresolved symbols in an object file. + When producing executables the default is GENERATE_ERROR. + When producing shared libraries the default is IGNORE. The + assumption with shared libraries is that the reference will be + resolved at load/execution time. */ + enum report_method unresolved_syms_in_objects; + + /* What to do with unresolved symbols in a shared library. + The same defaults apply. */ + enum report_method unresolved_syms_in_shared_libs; + + /* Which symbols to strip. */ + enum bfd_link_strip strip; + + /* Which local symbols to discard. */ + enum bfd_link_discard discard; + + /* Criteria for skipping symbols when detemining + whether to include an object from an archive. */ + enum bfd_link_common_skip_ar_aymbols common_skip_ar_aymbols; + + /* Char that may appear as the first char of a symbol, but should be + skipped (like symbol_leading_char) when looking up symbols in + wrap_hash. Used by PowerPC Linux for 'dot' symbols. */ + char wrap_char; + + /* Function callbacks. */ + const struct bfd_link_callbacks *callbacks; + + /* Hash table handled by BFD. */ + struct bfd_link_hash_table *hash; + + /* Hash table of symbols to keep. This is NULL unless strip is + strip_some. */ + struct bfd_hash_table *keep_hash; + + /* Hash table of symbols to report back via the notice callback. If + this is NULL, and notice_all is FALSE, then no symbols are + reported back. */ + struct bfd_hash_table *notice_hash; + + /* Hash table of symbols which are being wrapped (the --wrap linker + option). If this is NULL, no symbols are being wrapped. */ + struct bfd_hash_table *wrap_hash; + + /* The list of input BFD's involved in the link. These are chained + together via the link_next field. */ + bfd *input_bfds; + + /* If a symbol should be created for each input BFD, this is section + where those symbols should be placed. It must be a section in + the output BFD. It may be NULL, in which case no such symbols + will be created. This is to support CREATE_OBJECT_SYMBOLS in the + linker command language. */ + asection *create_object_symbols_section; + + /* List of global symbol names that are starting points for marking + sections against garbage collection. */ + struct bfd_sym_chain *gc_sym_list; + + /* If a base output file is wanted, then this points to it */ + void *base_file; + + /* The function to call when the executable or shared object is + loaded. */ + const char *init_function; + + /* The function to call when the executable or shared object is + unloaded. */ + const char *fini_function; + + /* Non-zero if auto-import thunks for DATA items in pei386 DLLs + should be generated/linked against. Set to 1 if this feature + is explicitly requested by the user, -1 if enabled by default. */ + int pei386_auto_import; + + /* Non-zero if runtime relocs for DATA items with non-zero addends + in pei386 DLLs should be generated. Set to 1 if this feature + is explicitly requested by the user, -1 if enabled by default. */ + int pei386_runtime_pseudo_reloc; + + /* How many spare .dynamic DT_NULL entries should be added? */ + unsigned int spare_dynamic_tags; + + /* May be used to set DT_FLAGS for ELF. */ + bfd_vma flags; + + /* May be used to set DT_FLAGS_1 for ELF. */ + bfd_vma flags_1; + + /* Start and end of RELRO region. */ + bfd_vma relro_start, relro_end; +}; + +/* This structures holds a set of callback functions. These are + called by the BFD linker routines. The first argument to each + callback function is the bfd_link_info structure being used. Each + function returns a boolean value. If the function returns FALSE, + then the BFD function which called it will return with a failure + indication. */ + +struct bfd_link_callbacks +{ + /* A function which is called when an object is added from an + archive. ABFD is the archive element being added. NAME is the + name of the symbol which caused the archive element to be pulled + in. */ + bfd_boolean (*add_archive_element) + (struct bfd_link_info *, bfd *abfd, const char *name); + /* A function which is called when a symbol is found with multiple + definitions. NAME is the symbol which is defined multiple times. + OBFD is the old BFD, OSEC is the old section, OVAL is the old + value, NBFD is the new BFD, NSEC is the new section, and NVAL is + the new value. OBFD may be NULL. OSEC and NSEC may be + bfd_com_section or bfd_ind_section. */ + bfd_boolean (*multiple_definition) + (struct bfd_link_info *, const char *name, + bfd *obfd, asection *osec, bfd_vma oval, + bfd *nbfd, asection *nsec, bfd_vma nval); + /* A function which is called when a common symbol is defined + multiple times. NAME is the symbol appearing multiple times. + OBFD is the BFD of the existing symbol; it may be NULL if this is + not known. OTYPE is the type of the existing symbol, which may + be bfd_link_hash_defined, bfd_link_hash_defweak, + bfd_link_hash_common, or bfd_link_hash_indirect. If OTYPE is + bfd_link_hash_common, OSIZE is the size of the existing symbol. + NBFD is the BFD of the new symbol. NTYPE is the type of the new + symbol, one of bfd_link_hash_defined, bfd_link_hash_common, or + bfd_link_hash_indirect. If NTYPE is bfd_link_hash_common, NSIZE + is the size of the new symbol. */ + bfd_boolean (*multiple_common) + (struct bfd_link_info *, const char *name, + bfd *obfd, enum bfd_link_hash_type otype, bfd_vma osize, + bfd *nbfd, enum bfd_link_hash_type ntype, bfd_vma nsize); + /* A function which is called to add a symbol to a set. ENTRY is + the link hash table entry for the set itself (e.g., + __CTOR_LIST__). RELOC is the relocation to use for an entry in + the set when generating a relocatable file, and is also used to + get the size of the entry when generating an executable file. + ABFD, SEC and VALUE identify the value to add to the set. */ + bfd_boolean (*add_to_set) + (struct bfd_link_info *, struct bfd_link_hash_entry *entry, + bfd_reloc_code_real_type reloc, bfd *abfd, asection *sec, bfd_vma value); + /* A function which is called when the name of a g++ constructor or + destructor is found. This is only called by some object file + formats. CONSTRUCTOR is TRUE for a constructor, FALSE for a + destructor. This will use BFD_RELOC_CTOR when generating a + relocatable file. NAME is the name of the symbol found. ABFD, + SECTION and VALUE are the value of the symbol. */ + bfd_boolean (*constructor) + (struct bfd_link_info *, bfd_boolean constructor, const char *name, + bfd *abfd, asection *sec, bfd_vma value); + /* A function which is called to issue a linker warning. For + example, this is called when there is a reference to a warning + symbol. WARNING is the warning to be issued. SYMBOL is the name + of the symbol which triggered the warning; it may be NULL if + there is none. ABFD, SECTION and ADDRESS identify the location + which trigerred the warning; either ABFD or SECTION or both may + be NULL if the location is not known. */ + bfd_boolean (*warning) + (struct bfd_link_info *, const char *warning, const char *symbol, + bfd *abfd, asection *section, bfd_vma address); + /* A function which is called when a relocation is attempted against + an undefined symbol. NAME is the symbol which is undefined. + ABFD, SECTION and ADDRESS identify the location from which the + reference is made. FATAL indicates whether an undefined symbol is + a fatal error or not. In some cases SECTION may be NULL. */ + bfd_boolean (*undefined_symbol) + (struct bfd_link_info *, const char *name, bfd *abfd, + asection *section, bfd_vma address, bfd_boolean fatal); + /* A function which is called when a reloc overflow occurs. NAME is + the name of the symbol or section the reloc is against, + RELOC_NAME is the name of the relocation, and ADDEND is any + addend that is used. ABFD, SECTION and ADDRESS identify the + location at which the overflow occurs; if this is the result of a + bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then + ABFD will be NULL. */ + bfd_boolean (*reloc_overflow) + (struct bfd_link_info *, const char *name, const char *reloc_name, + bfd_vma addend, bfd *abfd, asection *section, bfd_vma address); + /* A function which is called when a dangerous reloc is performed. + The canonical example is an a29k IHCONST reloc which does not + follow an IHIHALF reloc. MESSAGE is an appropriate message. + ABFD, SECTION and ADDRESS identify the location at which the + problem occurred; if this is the result of a + bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then + ABFD will be NULL. */ + bfd_boolean (*reloc_dangerous) + (struct bfd_link_info *, const char *message, + bfd *abfd, asection *section, bfd_vma address); + /* A function which is called when a reloc is found to be attached + to a symbol which is not being written out. NAME is the name of + the symbol. ABFD, SECTION and ADDRESS identify the location of + the reloc; if this is the result of a + bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then + ABFD will be NULL. */ + bfd_boolean (*unattached_reloc) + (struct bfd_link_info *, const char *name, + bfd *abfd, asection *section, bfd_vma address); + /* A function which is called when a symbol in notice_hash is + defined or referenced. NAME is the symbol. ABFD, SECTION and + ADDRESS are the value of the symbol. If SECTION is + bfd_und_section, this is a reference. */ + bfd_boolean (*notice) + (struct bfd_link_info *, const char *name, + bfd *abfd, asection *section, bfd_vma address); +}; + +/* The linker builds link_order structures which tell the code how to + include input data in the output file. */ + +/* These are the types of link_order structures. */ + +enum bfd_link_order_type +{ + bfd_undefined_link_order, /* Undefined. */ + bfd_indirect_link_order, /* Built from a section. */ + bfd_data_link_order, /* Set to explicit data. */ + bfd_section_reloc_link_order, /* Relocate against a section. */ + bfd_symbol_reloc_link_order /* Relocate against a symbol. */ +}; + +/* This is the link_order structure itself. These form a chain + attached to the section whose contents they are describing. */ + +struct bfd_link_order +{ + /* Next link_order in chain. */ + struct bfd_link_order *next; + /* Type of link_order. */ + enum bfd_link_order_type type; + /* Offset within output section. */ + bfd_vma offset; + /* Size within output section. */ + bfd_size_type size; + /* Type specific information. */ + union + { + struct + { + /* Section to include. If this is used, then + section->output_section must be the section the + link_order is attached to, section->output_offset must + equal the link_order offset field, and section->size + must equal the link_order size field. Maybe these + restrictions should be relaxed someday. */ + asection *section; + } indirect; + struct + { + /* Size of contents, or zero when contents size == size + within output section. + A non-zero value allows filling of the output section + with an arbitrary repeated pattern. */ + unsigned int size; + /* Data to put into file. */ + bfd_byte *contents; + } data; + struct + { + /* Description of reloc to generate. Used for + bfd_section_reloc_link_order and + bfd_symbol_reloc_link_order. */ + struct bfd_link_order_reloc *p; + } reloc; + } u; +}; + +/* A linker order of type bfd_section_reloc_link_order or + bfd_symbol_reloc_link_order means to create a reloc against a + section or symbol, respectively. This is used to implement -Ur to + generate relocs for the constructor tables. The + bfd_link_order_reloc structure describes the reloc that BFD should + create. It is similar to a arelent, but I didn't use arelent + because the linker does not know anything about most symbols, and + any asymbol structure it creates will be partially meaningless. + This information could logically be in the bfd_link_order struct, + but I didn't want to waste the space since these types of relocs + are relatively rare. */ + +struct bfd_link_order_reloc +{ + /* Reloc type. */ + bfd_reloc_code_real_type reloc; + + union + { + /* For type bfd_section_reloc_link_order, this is the section + the reloc should be against. This must be a section in the + output BFD, not any of the input BFDs. */ + asection *section; + /* For type bfd_symbol_reloc_link_order, this is the name of the + symbol the reloc should be against. */ + const char *name; + } u; + + /* Addend to use. The object file should contain zero. The BFD + backend is responsible for filling in the contents of the object + file correctly. For some object file formats (e.g., COFF) the + addend must be stored into in the object file, and for some + (e.g., SPARC a.out) it is kept in the reloc. */ + bfd_vma addend; +}; + +/* Allocate a new link_order for a section. */ +extern struct bfd_link_order *bfd_new_link_order (bfd *, asection *); + +/* These structures are used to describe version information for the + ELF linker. These structures could be manipulated entirely inside + BFD, but it would be a pain. Instead, the regular linker sets up + these structures, and then passes them into BFD. */ + +/* Glob pattern for a version. */ + +struct bfd_elf_version_expr +{ + /* Next glob pattern for this version. */ + struct bfd_elf_version_expr *next; + /* Glob pattern. */ + const char *pattern; + /* NULL for a glob pattern, otherwise a straight symbol. */ + const char *symbol; + /* Defined by ".symver". */ + unsigned int symver : 1; + /* Defined by version script. */ + unsigned int script : 1; + /* Pattern type. */ +#define BFD_ELF_VERSION_C_TYPE 1 +#define BFD_ELF_VERSION_CXX_TYPE 2 +#define BFD_ELF_VERSION_JAVA_TYPE 4 + unsigned int mask : 3; +}; + +struct bfd_elf_version_expr_head +{ + /* List of all patterns, both wildcards and non-wildcards. */ + struct bfd_elf_version_expr *list; + /* Hash table for non-wildcards. */ + void *htab; + /* Remaining patterns. */ + struct bfd_elf_version_expr *remaining; + /* What kind of pattern types are present in list (bitmask). */ + unsigned int mask; +}; + +/* Version dependencies. */ + +struct bfd_elf_version_deps +{ + /* Next dependency for this version. */ + struct bfd_elf_version_deps *next; + /* The version which this version depends upon. */ + struct bfd_elf_version_tree *version_needed; +}; + +/* A node in the version tree. */ + +struct bfd_elf_version_tree +{ + /* Next version. */ + struct bfd_elf_version_tree *next; + /* Name of this version. */ + const char *name; + /* Version number. */ + unsigned int vernum; + /* Regular expressions for global symbols in this version. */ + struct bfd_elf_version_expr_head globals; + /* Regular expressions for local symbols in this version. */ + struct bfd_elf_version_expr_head locals; + /* List of versions which this version depends upon. */ + struct bfd_elf_version_deps *deps; + /* Index of the version name. This is used within BFD. */ + unsigned int name_indx; + /* Whether this version tree was used. This is used within BFD. */ + int used; + /* Matching hook. */ + struct bfd_elf_version_expr *(*match) + (struct bfd_elf_version_expr_head *head, + struct bfd_elf_version_expr *prev, const char *sym); +}; + +#endif diff --git a/include/bin-bugs.h b/include/bin-bugs.h new file mode 100644 index 000000000..63901b044 --- /dev/null +++ b/include/bin-bugs.h @@ -0,0 +1,3 @@ +#ifndef REPORT_BUGS_TO +#define REPORT_BUGS_TO "<URL:http://www.sourceware.org/bugzilla/>" +#endif diff --git a/include/bout.h b/include/bout.h new file mode 100644 index 000000000..a69e280cb --- /dev/null +++ b/include/bout.h @@ -0,0 +1,191 @@ +/* This file is a modified version of 'a.out.h'. It is to be used in all + GNU tools modified to support the i80960 (or tools that operate on + object files created by such tools). + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* All i80960 development is done in a CROSS-DEVELOPMENT environment. I.e., + object code is generated on, and executed under the direction of a symbolic + debugger running on, a host system. We do not want to be subject to the + vagaries of which host it is or whether it supports COFF or a.out format, + or anything else. We DO want to: + + o always generate the same format object files, regardless of host. + + o have an 'a.out' header that we can modify for our own purposes + (the 80960 is typically an embedded processor and may require + enhanced linker support that the normal a.out.h header can't + accommodate). + + As for byte-ordering, the following rules apply: + + o Text and data that is actually downloaded to the target is always + in i80960 (little-endian) order. + + o All other numbers (in the header, symbols, relocation directives) + are in host byte-order: object files CANNOT be lifted from a + little-end host and used on a big-endian (or vice versa) without + modification. + ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER + FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO + USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <== + + o The downloader ('comm960') takes care to generate a pseudo-header + with correct (i80960) byte-ordering before shipping text and data + off to the NINDY monitor in the target systems. Symbols and + relocation info are never sent to the target. */ + +#define BMAGIC 0415 +/* We don't accept the following (see N_BADMAG macro). + They're just here so GNU code will compile. */ +#define OMAGIC 0407 /* old impure format */ +#define NMAGIC 0410 /* read-only text */ +#define ZMAGIC 0413 /* demand load format */ + +/* FILE HEADER + All 'lengths' are given as a number of bytes. + All 'alignments' are for relinkable files only; an alignment of + 'n' indicates the corresponding segment must begin at an + address that is a multiple of (2**n). */ +struct external_exec + { + /* Standard stuff */ + unsigned char e_info[4]; /* Identifies this as a b.out file */ + unsigned char e_text[4]; /* Length of text */ + unsigned char e_data[4]; /* Length of data */ + unsigned char e_bss[4]; /* Length of uninitialized data area */ + unsigned char e_syms[4]; /* Length of symbol table */ + unsigned char e_entry[4]; /* Runtime start address */ + unsigned char e_trsize[4]; /* Length of text relocation info */ + unsigned char e_drsize[4]; /* Length of data relocation info */ + + /* Added for i960 */ + unsigned char e_tload[4]; /* Text runtime load address */ + unsigned char e_dload[4]; /* Data runtime load address */ + unsigned char e_talign[1]; /* Alignment of text segment */ + unsigned char e_dalign[1]; /* Alignment of data segment */ + unsigned char e_balign[1]; /* Alignment of bss segment */ + unsigned char e_relaxable[1];/* Assembled with enough info to allow linker to relax */ + }; + +#define EXEC_BYTES_SIZE (sizeof (struct external_exec)) + +/* These macros use the a_xxx field names, since they operate on the exec + structure after it's been byte-swapped and realigned on the host machine. */ +#define N_BADMAG(x) (((x).a_info)!=BMAGIC) +#define N_TXTOFF(x) EXEC_BYTES_SIZE +#define N_DATOFF(x) ( N_TXTOFF(x) + (x).a_text ) +#define N_TROFF(x) ( N_DATOFF(x) + (x).a_data ) +#define N_TRELOFF N_TROFF +#define N_DROFF(x) ( N_TROFF(x) + (x).a_trsize ) +#define N_DRELOFF N_DROFF +#define N_SYMOFF(x) ( N_DROFF(x) + (x).a_drsize ) +#define N_STROFF(x) ( N_SYMOFF(x) + (x).a_syms ) +#define N_DATADDR(x) ( (x).a_dload ) + +/* Address of text segment in memory after it is loaded. */ +#if !defined (N_TXTADDR) +#define N_TXTADDR(x) 0 +#endif + +/* A single entry in the symbol table. */ +struct nlist + { + union + { + char* n_name; + struct nlist * n_next; + long n_strx; /* Index into string table */ + } n_un; + + unsigned char n_type; /* See below */ + char n_other; /* Used in i80960 support -- see below */ + short n_desc; + unsigned long n_value; + }; + + +/* Legal values of n_type. */ +#define N_UNDF 0 /* Undefined symbol */ +#define N_ABS 2 /* Absolute symbol */ +#define N_TEXT 4 /* Text symbol */ +#define N_DATA 6 /* Data symbol */ +#define N_BSS 8 /* BSS symbol */ +#define N_FN 31 /* Filename symbol */ + +#define N_EXT 1 /* External symbol (OR'd in with one of above) */ +#define N_TYPE 036 /* Mask for all the type bits */ +#define N_STAB 0340 /* Mask for all bits used for SDB entries */ + +/* MEANING OF 'n_other' + + If non-zero, the 'n_other' fields indicates either a leaf procedure or + a system procedure, as follows: + + 1 <= n_other <= 32 : + The symbol is the entry point to a system procedure. + 'n_value' is the address of the entry, as for any other + procedure. The system procedure number (which can be used in + a 'calls' instruction) is (n_other-1). These entries come from + '.sysproc' directives. + + n_other == N_CALLNAME + the symbol is the 'call' entry point to a leaf procedure. + The *next* symbol in the symbol table must be the corresponding + 'bal' entry point to the procedure (see following). These + entries come from '.leafproc' directives in which two different + symbols are specified (the first one is represented here). + + + n_other == N_BALNAME + the symbol is the 'bal' entry point to a leaf procedure. + These entries result from '.leafproc' directives in which only + one symbol is specified, or in which the same symbol is + specified twice. + + Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry, + but not every N_BALNAME entry must have an N_CALLNAME entry. */ +#define N_CALLNAME ((char)-1) +#define N_BALNAME ((char)-2) +#define IS_CALLNAME(x) (N_CALLNAME == (x)) +#define IS_BALNAME(x) (N_BALNAME == (x)) +#define IS_OTHER(x) ((x)>0 && (x) <=32) + +#define b_out_relocation_info relocation_info +struct relocation_info + { + int r_address; /* File address of item to be relocated. */ + unsigned +#define r_index r_symbolnum + r_symbolnum:24, /* Index of symbol on which relocation is based, + if r_extern is set. Otherwise set to + either N_TEXT, N_DATA, or N_BSS to + indicate section on which relocation is + based. */ + r_pcrel:1, /* 1 => relocate PC-relative; else absolute + On i960, pc-relative implies 24-bit + address, absolute implies 32-bit. */ + r_length:2, /* Number of bytes to relocate: + 0 => 1 byte + 1 => 2 bytes -- used for 13 bit pcrel + 2 => 4 bytes. */ + r_extern:1, + r_bsr:1, /* Something for the GNU NS32K assembler. */ + r_disp:1, /* Something for the GNU NS32K assembler. */ + r_callj:1, /* 1 if relocation target is an i960 'callj'. */ + r_relaxable:1; /* 1 if enough info is left to relax the data. */ +}; diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog new file mode 100644 index 000000000..290a5070a --- /dev/null +++ b/include/coff/ChangeLog @@ -0,0 +1,23 @@ +2004-08-13 Mark Kettenis <kettenis@gnu.org> + + * symconst.h (langMax): Fix typo in comment. + +2004-04-23 Chris Demetriou <cgd@broadcom.com> + + * mips.h (MIPS_R_RELHI, MIPS_R_RELLO, MIPS_R_SWITCH): Remove + (MIPS_R_PCREL16): Update comment. + * ecoff.h (struct ecoff_value_adjust): Remove structure. + (struct ecoff_debug_info): Remove 'adjust' member. + +2004-04-20 DJ Delorie <dj@redhat.com> + + * internal.h (R_SECREL32): Add. + +For older changes see ChangeLog-9103 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/include/coff/ChangeLog-9103 b/include/coff/ChangeLog-9103 new file mode 100644 index 000000000..d18113d52 --- /dev/null +++ b/include/coff/ChangeLog-9103 @@ -0,0 +1,1160 @@ +2003-12-02 Graham Reed <grahamr@algorithmics.com> + + * internal.h (C_WEAKEXT): Add alternative value for AIX 5.2 + based targets. + +2003-08-23 Jason Eckhardt <jle@rice.edu> + + * coff/i860.h (COFF860_R_PAIR, COFF860_R_LOW0, COFF860_R_LOW1, + COFF860_R_LOW2, COFF860_R_LOW3, COFF860_R_LOW4, COFF860_R_SPLIT0, + COFF860_R_SPLIT1, COFF860_R_SPLIT2, COFF860_R_HIGHADJ, + COFF860_R_BRADDR): Define new relocation constants and document. + Minor formatting adjustments. + +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * ti.h (GET_SCNHDR_NRELOC): Rename PTR param to LOC. + (PUT_SCNHDR_NRELOC, GET_SCNHDR_NLNNO, PUT_SCNHDR_NLNNO): Likewise. + (GET_SCNHDR_FLAGS, PUT_SCNHDR_FLAGS): Likewise. + (GET_SCNHDR_PAGE, PUT_SCNHDR_PAGE): Likewise. + +2003-07-17 Jeff Muizelaar <muizelaar@rogers.com> + + * pe.h: (IMAGE_FILE_NET_RUN_FROM_SWAP): Define. + (IMAGE_FILE_MACHINE_WCEMIPSV2): Define. + (IMAGE_FILE_MACHINE_SH3DSP): Define. + (IMAGE_FILE_MACHINE_SH3E): Define. + (IMAGE_FILE_MACHINE_SH5): Define. + (IMAGE_FILE_MACHINE_AM33): Define. + (IMAGE_FILE_MACHINE_POWERPCFP): Define. + (IMAGE_FILE_MACHINE_AXP64): Define. + (IMAGE_FILE_MACHINE_TRICORE): Define. + (IMAGE_FILE_MACHINE_CEF): Define. + (IMAGE_FILE_MACHINE_EBC): Define. + (IMAGE_FILE_MACHINE_AMD64): Define. + (IMAGE_FILE_MACHINE_M32R): Define. + (IMAGE_FILE_MACHINE_CEE): Define. + +2003-07-14 Christian Groessler <chris@groessler.org> + + * i860.h (AOUTSZ): Define for i860 coff. + +2003-06-29 Andreas Jaeger <aj@suse.de> + + * xcoff.h (struct __rtinit ): Convert to ISO C90 prototypes. + + * ecoff.h: Convert to ISO C90 prototypes. Replace PTR by void *. + +2003-04-24 Dhananjay Deshpande <dhananjayd@kpitcummins.com> + + * coff/h8300.h (H8300HNMAGIC, H8300SNMAGIC): New. + (H8300HNBADMAG, H8300SNBADMAG): New. + +2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com> + + * sh.h: Replace occurrances of 'Hitachi' with 'Renesas'. + * h8300.h: Likewise. + * h8500.h: Likewise. + +2003-03-25 Stan Cox <scox@redhat.com> + Nick Clifton <nickc@redhat.com> + + Contribute support for Intel's iWMMXt chip - an ARM variant: + + * arm.h (ARM_NOTE_SECTION): Define. + +2002-11-30 Alan Modra <amodra@bigpond.net.au> + + * ecoff.h: Replace boolean with bfd_boolean. + * xcoff.h: Likewise. + +2002-03-18 Tom Rix <trix@redhat.com> + + * rs6k64.h: Add U64_TOCMAGIC, AIX 5 64 bit magic number. + +2002-02-01 Tom Rix <trix@redhat.com> + + * xcoff.h: Conditionally support <aiaff> for pre AIX 4.3. + +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * or32.h: New file. + +2001-12-24 Tom Rix <trix@redhat.com> + + * xcoff.h (xcoff_big_format_p): Make <bigaf> the default archive + format. + (XCOFFARMAG_ELEMENT_SIZE, XCOFFARMAGBIG_ELEMENT_SIZE): Define for + archive header ascii elements. + +2001-12-17 Tom Rix <trix@redhat.com> + + * xcoff.h : Add .except and .typchk section string and styp flags. + Fix xcoff_big_format_p macro. + +2001-12-16 Tom Rix <trix@redhat.com> + + * xcoff.h : Clean up formatting. + +2002-01-15 Richard Earnshaw <rearnsha@arm.com> + + * arm.h (F_VFP_FLOAT): Define. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * ti.h: Move arch-specific stuff from here... + (COFF_ADJUST_SYM_IN/OUT): Optionally put page flag into symbol + value. + * tic54x.h: ...to here. + +2001-10-26 Christian Groessler <cpg@aladdin.de> + + * external.h (GET_LINENO_LNNO): Fix usage of H_GET_32/16. + (PUT_LINENO_LNNO): Likewise with H_PUT_32/16. + +2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> + + * ti.h (GET_SCNHDR_PAGE): Fix compile time warning. + +2001-09-18 Alan Modra <amodra@bigpond.net.au> + + * external.h (GET_LINENO_LNNO): Use H_GET_32/16. + (PUT_LINENO_LNNO): Use H_PUT_32/16. + * m88k.h (GET_LNSZ_SIZE, GET_LNSZ_LNNO, GET_SCN_NRELOC, + GET_SCN_NLINNO): Use H_GET_32. + (PUT_LNSZ_LNNO, PUT_LNSZ_SIZE, PUT_SCN_NRELOC, PUT_SCN_NLINNO): + Use H_PUT_32. + * ti.h: Formatting fixes. Make use of H_GET_* and H_PUT_* throughout. + * xcoff.h: White space changes. + +2001-09-05 Tom Rix <trix@redhat.com> + + * xcoff.h : Add XCOFF_SYSCALL32 and XCOFF_SYSCALL64 hash table flags. + +2001-08-27 Andreas Jaeger <aj@suse.de> + + * xcoff.h (struct __rtinit): Make proper prototype for rtl. + +Fri Aug 24 01:18:51 2001 J"orn Rennecke <amylaar@redhat.com> + + * internal.h (R_JMP2, R_JMPL2, R_MOVL2): Comment spelling fix. + +2001-04-05 Tom Rix <trix@redhat.com> + + * rs6000.h : move xcoff32 external structures from xcofflink. + * rs6k64.h : move xcoff64 external structures from xcofflink. + * internal.h : promote 32 bit structure elements to 64 bit + for xcoff64 support + * xcoff.h : New file. + +2001-03-23 Nick Clifton <nickc@redhat.com> + + * a29k.h: Fix compile time warning. + * external.h: Fix compile time warning. + * m88k.h: Fix compile time warning. + +2001-03-13 Nick Clifton <nickc@redhat.com> + + * external.h: New file. Common structure definitions found in + other COFF header files. + + * a29k.h: Use external.h. + * apollo.h: Use external.h. + * arm.h: Use external.h. + * h8300.h: Use external.h. + * h8500.h: Use external.h. + * i386.h: Use external.h. + * i860.h: Use external.h. + * ia64.h: Use external.h. + * m68k.h: Use external.h. + * m88k.h: Use external.h. + * mcore.h: Use external.h. + * mips.h: Use external.h. + * mipspe.h: Use external.h. + * powerpc.h: Use external.h. + * rs6000.h: Use external.h. + * rs6k64.h: Use external.h. + * sh.h: Use external.h. + * sparc.h: Use external.h. + * tic30.h: Use external.h. + * tic80.h: Use external.h. + * w65.h: Use external.h. + * we32k.h: Use external.h. + * z8k.h: Use external.h. + +2001-02-09 David Mosberger <davidm@hpl.hp.com> + + * pe.h (PEPAOUTSZ): Rename from PEP64AOUTSZ. + Rename from PEPAOUTHDR. + +2001-01-23 H.J. Lu <hjl@gnu.org> + + * pe.h (struct external_PEI_DOS_hdr): New. + (struct external_PEI_IMAGE_hdr): New. + +2000-12-11 Alan Modra <alan@linuxcare.com.au> + + * ti.h (OCTETS_PER_BYTE_POWER): Change #warning to #error. + +2000-12-08 Alan Modra <alan@linuxcare.com.au> + + * ti.h (OCTETS_PER_BYTE_POWER): Change #warn to #warning. + +2000-06-30 DJ Delorie <dj@cygnus.com> + + * pe.h: Clarify a comment. + +2000-05-05 Clinton Popetz <cpopetz@cygnus.com> + + * rs6k64.h (U802TOC64MAGIC): Change to U803XTOCMAGIC. + +2000-04-24 Clinton Popetz <cpopetz@cygnus.com> + + * rs6k64.h: New file. + +2000-04-17 Timothy Wall <twall@cygnus.com> + + * ti.h: Load page cleanup. + * intental.h: Add load page field. + +Mon Apr 17 16:44:01 2000 David Mosberger <davidm@hpl.hp.com> + + * pe.h (PEP64AOUTHDR): New header for PE+. + (PEP64AOUTSZ): New macro. + (IMAGE_SUBSYSTEM_UNKNOWN): New macro. + (IMAGE_SUBSYSTEM_NATIVE): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_GUI): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_CUI): Ditto. + (IMAGE_SUBSYSTEM_POSIX_CUI): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_CE_GUI): Ditto. + (IMAGE_SUBSYSTEM_EFI_APPLICATION): Ditto. + (IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER): Ditto. + (IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER): Ditto. + * internal.h (PE_DEF_FILE_ALIGNMENT): Define only if not defined + already. + * ia64.h: New file. + +2000-04-13 Alan Modra <alan@linuxcare.com.au> + + * ti.h (ADDR_MASK): Don't use ul suffix on constants. + (PG_MASK): Ditto. + +2000-04-11 Timothy Wall <twall@cygnus.com> + + * ti.h: Remove load page references until load pages are + reimplemented. + * tic54x.h: Ditto. + +2000-04-07 Timothy Wall <twall@cygnus.com> + + * internal.h: Fix some comments related to TI COFF (instead of tic80). + * ti.h: New. + * tic54x.h: New. + +Wed Apr 5 22:08:41 2000 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define. + +2000-03-15 Kazu Hirata <kazu@hxi.com> + + * internal.h: Fix a typo in the comment for R_MOVL2. + +2000-02-28 Nick Clifton <nickc@cygnus.com> + + * mipspe.h (MIPS_PE_MAGIC): Define. + * sh.h (SH_PE_MAGIC): Define. + +2000-02-22 Nick Clifton <nickc@cygnus.com> DJ Delorie <dj@cygnus.com> + + * sh.h: Add Windows CE definitions. + * arm.h: Add Windows CE definitions. + * mipspe.h: New file: Windows CE definitions for MIPS. + * pe.h: Add constants for ILF support. + +2000-01-05 Nick Clifton <nickc@cygnus.com> + + * pe.h: Fix formatting of comments. + (IMAGE_FILE_AGGRESSIVE_WS_TRIM): Define. + (IMAGE_FILE_LARGE_ADDRESS_AWARE): Define. + (IMAGE_FILE_16BIT_MACHINE): Define. + (IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP): Define. + (IMAGE_FILE_UP_SYSTEM_ONLY): Define. + (IMAGE_FILE_MACHINE_UNKNOWN): Define. + (IMAGE_FILE_MACHINE_ALPHA): Define. + (IMAGE_FILE_MACHINE_ALPHA64): Define. + (IMAGE_FILE_MACHINE_I386): Define. + (IMAGE_FILE_MACHINE_IA64): Define. + (IMAGE_FILE_MACHINE_M68K): Define. + (IMAGE_FILE_MACHINE_MIPS16): Define. + (IMAGE_FILE_MACHINE_MIPSFPU): Define. + (IMAGE_FILE_MACHINE_MIPSFPU16): Define. + (IMAGE_FILE_MACHINE_POWERPC): Define. + (IMAGE_FILE_MACHINE_R3000): Define. + (IMAGE_FILE_MACHINE_R4000): Define. + (IMAGE_FILE_MACHINE_R10000): Define. + (IMAGE_FILE_MACHINE_SH3): Define. + (IMAGE_FILE_MACHINE_SH4): Define. + (IMAGE_FILE_MACHINE_THUMB): Define. + +1999-09-20 Alan Modra <alan@spri.levels.unisa.edu.au> + + * internal.h: Delete bogus R_PCLONG, duplicate R_RELBYTE and + R_RELWORD, and rewrite some R_* as decimal. + +1999-09-06 Donn Terry <donn@interix.com> + + * internal.h (DTYPE): Define. + * pe.h (struct external_PEI_filehdr): Rename from + external_PE_filehdr. Define even if COFF_IMAGE_WITH_PE is not + defined. + +1999-07-17 Nick Clifton <nickc@cygnus.com> + + * arm.h (F_SOFT_FLOAT): Rename from F_SOFTFLOAT. + +1999-06-21 Philip Blundell <pb@nexus.co.uk> + + * arm.h (F_SOFTFLOAT): Define. + +1999-07-05 Nick Clifton <nickc@cygnus.com> + + * arm.h (F_ARM_5): Define. + +Wed Jun 2 18:08:18 1999 Richard Henderson <rth@cygnus.com> + + * internal.h (BEOS_EXE_IMAGE_BASE, BEOS_DLL_IMAGE_BASE): New. + +Mon May 17 13:35:35 1999 Stan Cox <scox@cygnus.com> + + * arm.h (F_PIC, F_ARM_2, F_ARM_2a, F_ARM_3, F_ARM_3M, + F_ARM_4, F_ARM_4T, F_APCS26): Changed values to distinguish + F_ARM_2a, F_ARM_3M, F_ARM_4T. + +1999-05-15 Nick Clifton <nickc@cygnus.com> + + * mcore.h (IMAGE_REL_MCORE_RVA): Define. + +1999-04-21 Nick Clifton <nickc@cygnus.com> + + * mcore.h (GET_LINENO_LNNO): New macro. + (PUT_LINENO_LNNO): New macro. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * mcore.h: New header file. Defines for Motorola's MCore + processor. + +Sun Dec 6 21:36:37 1998 Mark Elbrecht <snowball3@usa.net> + + * internal.h (C_WEAKEXT): Define. + +Wed Jan 27 13:35:35 1999 Stan Cox <scox@cygnus.com> + + * arm.h (F_PIC_INT, F_ARM_2, F_ARM_3, F_ARM_4, F_APCS26): + Changed values to avoid clashing with IMAGE_FILE_* coff header + flag values. + +Wed Apr 1 16:06:15 1998 Nick Clifton <nickc@cygnus.com> + + * internal.h: Document numbers associated with Thumb symbol + types. + +Fri Mar 27 17:16:57 1998 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (ISPTR, ISFCN, ISARY): Add casts to unsigned long. + +Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> + + * tic30.h: New file. + +Fri Dec 12 11:49:07 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (R_MPPCR15W): New relocation type, for 15 bit PC relative + offsets. + +Tue Dec 2 10:21:40 1997 Nick Clifton <nickc@cygnus.com> + + * arm.h (COFFARM): New define. + +Mon Dec 1 20:24:18 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h (R_SH_SWITCH8): New. + +Sat Nov 22 15:10:14 1997 Nick Clifton <nickc@cygnus.com> + + * internal.h (C_THUMBEXTFUNC, C_THUMBSTATFUNC): Constants to + define static and external functions. + + * arm.h: Add bits to support PIC and APCS-FLOAT type binaries, + when implemented. + +Fri Oct 3 14:25:17 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (R_PPL16B): Make constant uppercase for consistency. + +Tue Jul 22 18:18:58 1997 Robert Hoehne <robert.hoehne@Mathematik.TU-Chemnitz.DE> + + * go32exe.h: New file. + +Tue Jul 8 12:23:55 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_TARGET_ID): Add define. + * internal.h (struct internal_filehdr): Add f_target_id field. + +Tue Jun 3 16:44:18 1997 Nick Clifton <nickc@cygnus.com> + + * internal.h: Add storage classes for Thumb symbols + +Mon May 26 14:07:55 1997 Ian Lance Taylor <ian@cygnus.com> + + * tic80.h (R_PPL16B): Correct value. + +Tue May 13 10:21:14 1997 Nick Clifton <nickc@cygnus.com> + + * arm.h (constants): Added new flag bits F_APCS_26 and + F_APCS_SET for the f_flags field of the filehdr structure. Added new + flags: F_APCS26, F_ARM_2, F_ARM_3, F_ARM_7, F_ARM_7T to store + information in the flags field of the internal_f structure used by BFD + routines. + +Sat May 3 08:24:59 1997 Fred Fish <fnf@cygnus.com> + + * internal.h (C_UEXT, C_STATLAB, C_EXTLAB, C_SYSTEM): + New storage classes for TIc80. + +Fri Apr 18 11:52:55 1997 Niklas Hallqvist <niklas@appli.se> + + * alpha.h (ALPHA_ECOFF_BADMAG): Recognize *BSD/alpha magic too. + (ALPHA_R_LITERALSLEAZY): Define. + * ecoff.h (ALPHA_MAGIC_BSD): Define. + +Wed Jan 29 11:31:51 1997 Ian Lance Taylor <ian@cygnus.com> + + * i960.h (R_IPR13, R_ALIGN): Define. + +Mon Jan 27 13:34:30 1997 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): Move definitions + from here... + * i960.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): ...to here. + +Wed Jan 22 20:10:47 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80MAGIC): Renamed to TIC80_AOUTHDR_MAGIC. + +Fri Dec 27 22:05:45 1996 Fred Fish <fnf@cygnus.com> + + * tic80.h: New file for TIc80 support. + +Thu Dec 19 16:18:11 1996 Ian Lance Taylor <ian@cygnus.com> + + * arm.h (_LIT): Define. + +Fri Jun 28 12:54:38 1996 Ian Lance Taylor <ian@cygnus.com> + + * pe.h (FILHSZ): Define. + +Wed Jun 26 16:24:26 1996 Ian Lance Taylor <ian@cygnus.com> + + * All files: Define FILHSZ, AOUTSZ, AOUTHDRSZ, SCNHSZ, SYMESZ, + AUXESZ, LINESZ, RELSZ as numeric constants rather than uses of + sizeof. Define AOUTHDRSZ in all files. + * pe.h (AOUTSZ): Define by adding to AOUTHDRSZ. + +Fri Jun 21 11:17:46 1996 Richard Henderson <rth@tamu.edu> + + * alpha.h: Add declarations for relocation types added for Alpha + OSF/1 3.0. + +Tue Jun 18 16:04:29 1996 Jeffrey A. Law <law@rtl.cygnus.com> + + * h8300.h (H8300SMAGIC): Define. + (H8300SBADMAG): Define. + +Mon Jun 10 11:53:28 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_BCC_INV, R_JMP_DEL): New relocations for + relaxing in the H8/300 series. + +Thu May 16 15:49:22 1996 Ian Lance Taylor <ian@cygnus.com> + + * sh.h (R_SH_CODE, R_SH_DATA, R_SH_LABEL): Define. + +Tue May 7 00:36:39 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_JMPL2): Renamed from R_JMPL_B8 to be + consistent with other similar relocs. + + * internal.h (H8/300 specific relocs): Add comments better + explaining what each reloc is used for. + (R_MOV16B1, R_MOV16B2): Renamed from R_MOVB1 and R_MOVB2. + (R_MOV24B1, R_MOV24B2): Renamed from R_MOVLB1 and R_MOVLB2. + (R_MOVL1, R_MOVL2): New relocs. + +Fri May 3 13:01:12 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_PCRWORD_B): Define for the h8300 relaxing + linker. + +Wed May 1 19:21:03 1996 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (SCNNMLEN): Define. + (struct internal_scnhdr): Use SCNNMLEN for s_name field. + +Fri Mar 29 13:41:25 1996 Ian Lance Taylor <ian@cygnus.com> + + * pe.h: Define IMAGE_COMDAT codes. + +Wed Mar 27 17:29:42 1996 Ian Lance Taylor <ian@cygnus.com> + + * arm.h (union external_auxent): Add x_checksum, x_associated, and + x_comdat fields to x_scn struct. + * i386.h (union external_auxent): Likewise. + * powerpc.h (union external_auxent): Likewise. + * internal.h (union internal_auxent): Likewise. + +Thu Mar 21 16:25:57 1996 David Mosberger-Tang <davidm@azstarnet.com> + + * ecoff.h (struct ecoff_find_line): Add caching fields. + +Thu Mar 14 15:22:44 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_MEM_INDIRECT): New reloc for the h8300. + +Fri Feb 9 10:44:11 1996 Ian Lance Taylor <ian@cygnus.com> + + * aux-coff.h: Rename from aux.h, to avoid problems on hapless DOS + systems which think that aux is a com port. + +Mon Feb 5 18:35:00 1996 Ian Lance Taylor <ian@cygnus.com> + + * i960.h (F_I960HX): Define. + +Wed Jan 31 13:11:54 1996 Richard Henderson <rth@tamu.edu> + + * aux.h: New file. + * internal.h, m68k.h: Protect against multiple inclusion. + +Wed Nov 22 13:48:39 1995 Ian Lance Taylor <ian@cygnus.com> + + * ecoff.h (_RCONST, STYP_RCONST, RELOC_SECTION_RCONST): Define. + (NUM_RELOC_SECTIONS): Update. + * symconst.h (scRConst): Define. + +Tue Nov 14 18:54:29 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (C_NT_WEAK): Define. + +Thu Nov 9 14:08:30 1995 Ian Lance Taylor <ian@cygnus.com> + + * rs6000.h (STYP_OVRFLO): Define. + +Tue Nov 7 14:38:45 1995 Kim Knuttila <krk@cygnus.com> + + * powerpc.h (IMAGE_NT_OPTIONAL_HDR_MAGIC): Added define. + * pe.h: Added defines for file level flags + +Mon Nov 6 17:28:01 1995 Harry Dolan <dolan@ssd.intel.com> + + * i860.h: New file, based on i386.h. + +Wed Nov 1 15:25:18 1995 Manfred Hollstein KS/EF4A 60/1F/110 #40283 <manfred@lts.sel.alcatel.de> + + * m68k.h (PAGEMAGICEXECSWAPPED): Define. + (PAGEMAGICPEXECSWAPPED): Define. + (PAGEMAGICPEXECTSHLIB): Define. + (PAGEMAGICPEXECPAGED): Define. + (_COMMENT): DEFINE. + * m88k.h (_COMMENT): Define. + +Wed Oct 18 18:36:19 1995 Geoffrey Noer <noer@cygnus.com> + + * sym.h: #if 0'd out runtime_pdr struct because it chokes + Visual C++ and there aren't any references to it elsewhere in gdb. + +Mon Oct 16 11:12:24 1995 Ian Lance Taylor <ian@cygnus.com> + + * rs6000.h (SMALL_AOUTSZ): Define. + + * internal.h (XMC_TD): Define. + +Tue Oct 10 18:41:03 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (struct internal_aouthdr): Add o_cputype field. + * rs6000.h (AOUTHDR): Rename o_resv1 to o_cputype. + +Mon Oct 9 14:45:46 1995 Ian Lance Taylor <ian@cygnus.com> + + * rs6000.h (AOUTHDR): Add o_maxdata field. Add comments. + (_PAD, _LOADER): Define. + (STYP_LOADER): Define. + * internal.h (struct internal_aouthdr): Add o_maxdata field. + +Thu Oct 5 10:02:57 1995 Ian Lance Taylor <ian@cygnus.com> + + * ecoff.h: Define section name macros and STYP macros for various + Alpha sections: .got, .hash, .dynsym, .dynstr, .rel.dyn, .conflic, + .comment, .liblist, .dynamic. + +Wed Oct 4 10:56:35 1995 Kim Knuttila <krk@cygnus.com> + + * pe.h: Moved DOSMAGIC and NT_SIGNATURE defines here + * powerpc.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + Also removed other unused defines (various MAGIC ones) + * i386.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + * arm.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + * apollo.h: removed unused DEFAULT_* defines + * alpha.h: removed unused DEFAULT_* defines + * h8500.h: removed unused DEFAULT_* defines + * h8300.h: removed unused DEFAULT_* defines + * i960.h: removed unused DEFAULT_* defines + * m88k.h: removed unused DEFAULT_* defines + * we32k.h: removed unused DEFAULT_* defines + * rs6000.h: removed unused DEFAULT_* defines + * mips.h: removed unused DEFAULT_* defines + * m68k.h: removed unused DEFAULT_* defines + * z8k.h: removed unused DEFAULT_* defines + * w65.h: removed unused DEFAULT_* defines + * sparc.h: removed unused DEFAULT_* defines + * sh.h: removed unused DEFAULT_* defines + +Fri Sep 29 08:40:08 1995 Kim Knuttila <krk@cygnus.com> + + * powerpc.h: Reformatted to GNU coding conventions. + +Wed Sep 27 06:50:50 1995 Kim Knuttila <krk@nellie> + + * pe.h: added defines for more section characteristics + * powerpc.h (new file): base coff definitions for ppc PE + +Tue Sep 12 12:08:20 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (struct internal_syment): Change n_numaux field from + char to unsigned char. + +Fri Sep 1 15:39:36 1995 Kazumoto Kojima <kkojima@info.kanagawa-u.ac.jp> + + * mips.h (struct rpdr_ext): Define. + +Thu Aug 31 16:51:50 1995 steve chamberlain <sac@slash.cygnus.com> + + * internal.h (internal_aouthdr, internal_filehdr): + don't indirect the pe stuff. + +Tue Aug 29 14:16:07 1995 steve chamberlain <sac@slash.cygnus.com> + + * i386.h (NT_DEF_RESERVE, NT_DEF_COMMIT): Make the same + as 'the other' compiler. + * internal.h (NT_IMAGE_BASE): Deleted. + (NT_EXE_IMAGE_BASE, NT_DLL_IMAGE_BASE): New. + (PE_DEF_SECTION_ALIGNMENT, PE_DEF_FILE_ALIGNMENT): New. + (R_IMAGEBASE): New. + +Mon Aug 21 18:12:19 1995 steve chamberlain <sac@slash.cygnus.com> + + * internal.h: (internal_filehdr): Moved PE stuff into + internal_extra_pe_filehdr. + (internal_aouthdr): Moved PE stuff into + interanl_extra_pe_aouthdr. + +Mon Jul 24 14:05:39 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h: Move R_SH_* relocs from here... + * sh.h: ...to here. + (R_SH_SWITCH16, R_SH_SWITCH32): Define. + (R_SH_USES, R_SH_COUNT, R_SH_ALIGN): Define. + +Thu Jun 29 00:04:25 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * internal.h (NT_DEF_RESERVE, NT_DEF_COMMIT): Increase a lot. + +Tue May 16 15:08:20 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * internal.h (NT_subsystem, NT_stack_heap): Delete + +Tue May 16 15:08:20 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * internal.h (NT_subsystem, NT_stack_heap): Now extern. + +Sat May 13 10:14:08 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * pe.h: New file. + * i386.h (NT_SECTION_ALIGNMENT, NT_FILE_ALIGNMENT, + NT_DEF_RESERVE, NT_DEF_COMMIT): New. + * internal.h (internal_filehdr): New fields for PE. + (IMAGE_DATA_DIRECTORY): New. + (internal_aouthdr): New fields for PE. + +Tue Feb 14 17:59:37 1995 Ian Lance Taylor <ian@cygnus.com> + + * ecoff.h (struct ecoff_fdrtab_entry): Define. + (struct ecoff_find_line): Define. + +Sat Feb 4 14:38:03 1995 David Mosberger-Tang <davidm@piston.cs.arizona.edu> + + * sym.h (struct pdr): field "prof" added. + + * alpha.h (PDR_BITS1_PROF_*): added, macros for PDR_BITS*_RESERVED_* + updated accordingly. + +Sun Jan 15 18:38:33 1995 Steve Chamberlain <sac@splat> + + * w65.h: New file. + +Wed Nov 23 22:43:38 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * sh.h (SH_ARCH_MAGIC_BIG, SH_ARCH_MAGIC_LITTLE): New. + (SHBADMAG): Changed to suit. + +Tue Jul 26 17:46:08 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i960.h (F_I960JX): New macro. + +Wed Jul 6 00:48:57 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha.h: Add definitions for alpha file header flags, encoding + the object type of the file. + +Mon Jun 20 13:47:01 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * ecoff.h (ecoff_swap_tir_in): Remove declaration. + (ecoff_swap_tir_out): Likewise. + (ecoff_swap_rndx_in, ecoff_swap_rndx_out): Likewise. + (struct ecoff_debug_swap): Add new fields: swap_tir_in, + swap_rndx_in, swap_tir_out, swap_rndx_out, read_debug_info. + +Sun Jun 12 03:51:52 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * symconst.h: Pick up SGI define for stIndirect. + +Fri Apr 22 13:05:28 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (REGINFO): Don't define. + (struct ecoff_reginfo): Don't define. + + * sh.h (SH_ARCH_MAGIC): Rename from SHMAGIC. SHMAGIC is used by + several targets to mean a shared library. + (SHBADMAG): Corresponding change. + +Thu Apr 14 13:00:53 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (RELOC_BITS3_TYPE_BIG): Changed from 0x1e to 0x3e. + (RELOC_BITS3_TYPEHI_LITTLE): Define. + (RELOC_BITS3_TYPEHI_SH_LITTLE): Define. + (MIPS_R_PCREL16): Change value from 8 to 12 to match Irix 4. + (MIPS_R_RELHI): Define. + (MIPS_R_RELLO): Define. + (MIPS_R_SWITCH): Change value from 9 to 22. + +Thu Apr 7 14:19:35 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (MIPS_R_SWITCH): Define. + +Thu Mar 31 19:28:33 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * internal.h (internal_aouthdr): Added comments for Apollo fields. + +Thu Mar 31 16:28:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (STYP_ECOFF_LIB): Define as used on Irix 4. + +Fri Mar 25 17:16:55 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_info): Add adjust field. + (struct ecoff_value_adjust): Define. + +Tue Mar 22 13:22:47 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (MIPS_R_PCREL16): Define. + +Sat Feb 26 10:26:38 1994 Ian Lance Taylor (ian@cygnus.com) + + * ecoff.h: Add casts to avoid warnings from SVR4 cc. + +Mon Feb 21 09:48:46 1994 Ian Lance Taylor (ian@lisa.cygnus.com) + + * sym.h (struct runtime_pdr): Make field adr bfd_vma, not unsigned + long. + (SYMR): Make field value bfd_vma, not long. + +Fri Feb 4 23:35:53 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * rs6000.h (STYP_DEBUG): Define. + +Wed Feb 2 14:31:37 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (union internal_auxent): Change x_csect.x_scnlen into + a union of a long and a pointer to a symbol. XCOFF sometimes uses + this field as a symbol index. + +Mon Jan 10 23:54:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (ecoff_debug_info): Remove fields line_end, + external_dnr_end, external_pdr_end, external_sym_end, + external_opt_end, external_aux_end, ss_end, external_fdr_end. + Replace ifdbase with ifdmap. + +Wed Jan 5 17:05:36 1994 Ken Raeburn (raeburn@deneb.cygnus.com) + + * ecoff.h (STYP_EXTENDESC, STYP_COMMENT, STYP_XDATA, STYP_PDATA): + Define. + +Wed Jan 5 16:58:24 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (NUM_RELOC_SECTIONS): Define. + +Tue Dec 21 09:24:56 1993 Ken Raeburn (raeburn@rtl.cygnus.com) + + * sparc.h (struct external_reloc): Rename field r_addend to + r_offset. + +Sat Dec 11 16:12:32 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h (R_DISP7, R_SH_IMM16): New reloc types. + +Tue Nov 23 14:23:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_swap): Added *_end fields for all + the symbolic information pointers. + + * sym.h: Named the EXTR structure ecoff_extr. + +Fri Nov 19 08:21:18 1993 Ken Raeburn (raeburn@rover.cygnus.com) + + * sparc.h (RELSZ): Use correct size. + +Wed Nov 17 17:18:16 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (struct ecoff_debug_info): Define. + +Tue Nov 2 17:56:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_swap): Define. + +Thu Oct 28 17:07:50 1993 Stan Shebs (shebs@rtl.cygnus.com) + + * i386.h (I386LYNXMAGIC): Rename to LYNXCOFFMAGIC. + * m68k.h (LYNXCOFFMAGIC): Define. + * sparc.h: New file. + +Tue Oct 19 15:34:50 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * alpha.h (external_aouthdr): Split four byte padding field into + two byte bldrev field and two byte padding field. + + * ecoff.h (_LITA, _PDATA, _XDATA, STYP_LITA): Defined. + +Wed Oct 13 15:52:34 1993 Ken Raeburn (raeburn@cygnus.com) + + Sun Oct 10 17:27:10 1993 Troy Rollo (troy@cbme.unsw.edu.au) + + * internal.h: Added o_sri, o_inlib and o_vid for Apollos as well + as R_DIR16. + + * apollo.h: New file + +Mon Oct 11 17:16:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (REGINFO, struct ecoff_reginfo): Define. + +Tue Oct 5 10:52:53 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * rs6000.h: Change non-ASCII characters in comment to octal + escapes. + +Tue Sep 28 03:27:04 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * ecoff.h (_FINI, STYP_ECOFF_FINI): Add to support .fini section. + +Fri Sep 24 11:53:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (BADMAG): Recognize MIPS_MAGIC_LITTLE3 and MIPS_MAGIC_BIG3. + * ecoff.h: Define MIPS_MAGIC_LITTLE3 and MIPS_MAGIC_BIG3. + +Thu Sep 23 21:07:14 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * mips.h (BADMAG): Recognize MIPS_MAGIC_LITTLE2 and MIPS_MAGIC_BIG2. + * ecoff.h: Define MIPS_MAGIC_LITTLE2 and MIPS_MAGIC_BIG2. + +Thu Sep 16 20:27:21 1993 Jim Kingdon (kingdon@cirdan.cygnus.com) + + * sym.h, symconst.h: Add comment stating these files are not part + of GDB, GAS, etc. In 1991, when we asked rms whether we could + include these files in GDB (although they are copyrighted by + someone besides the FSF), he said it was OK if they were not + considered part of GDB. + +Fri Sep 10 17:40:35 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (AUX_PUT_ANY): Cast val argument to bfd_vma. + + * alpha.c (external_aouthdr): Need four bytes of padding between + vstamp and tsize. + +Tue Sep 7 14:20:43 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (AUX_GET_ANY, AUX_PUT_ANY): Changed to reflect further + change in bfd swapping routine names. + +Tue Sep 7 10:15:17 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * ecoff.h (AUX_GET_ANY): Change name of _do_getb32 to reflect bfd + changes. + +Fri Aug 13 14:30:32 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff.h (RELOC_SECTION_NONE): Define. + +Thu Aug 12 11:24:42 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha.h (struct external_reloc): Add r_symndx field. + (RELSZ): Correct. + (RELOC_BITS*): Correct. + (ALPHA_R_*): Define. + * ecoff.h (RELOC_SECTION_{XDATA,PDATA,FINI,LITA,ABS}): Define. + (r_extern): Undefine. + * internal.h (struct internal_reloc): Make r_vaddr bfd_vma rather + than long. Add r_extern field. + + * alpha.h (PDR_BITS*): Define. + * sym.h (PDR): Give correct names to new fields. + + * ecoff.h: Moved MIPS reloc definitions from here... + * mips.h: to here. + +Mon Aug 2 16:37:14 1993 Stu Grossman (grossman at cygnus.com) + + * i386.h: Add Lynx magic number. + +Tue Aug 3 11:17:53 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha.h: Corrected external symbolic debugging structures to + match actual usage. + * internal.h (internal_filehdr, internal_aouthdr, + internal_scnhdr): Changed type of some fields to bfd_vma so they + can hold 64 bits. + * sym.h (HDRR, FDR, PDR, EXTR): Likewise. + (PDR): Added new fields found on Alpha. + * symconst.h (magicSym2): Define; new value found on Alpha. + + * ecoff.h: New file. + * alpha.h, mips.h: Moved common information into ecoff.h. Moved + external structure definitions in from ecoff-ext.h. + * ecoff-ext.h: Removed; information now in alpha.h and mips.h. + +Sun Jul 18 21:43:59 1993 Jim Kingdon (kingdon@rtl.cygnus.com) + + * i386.h: Recognize I386PTXMAGIC. + +Fri Jul 16 09:54:35 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (MIPS_AOUT_{OZ}MAGIC): Renamed from {OZ}MAGIC. + +Thu Jul 15 12:23:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k.h (union external_auxent): Move x_fcn back inside x_fcnary. + ({GET,PUT}_FCN_{LNNOPTR,ENDNDX}): Adjust accordingly. + +Sun Jul 11 18:00:18 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * m68k.h: Define MC68KBCSMAGIC. + +Thu Jun 10 11:46:28 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (_INIT, STYP_MIPS_INIT): Define (used on Irix4). + (STYP_OTHER_LOAD): Define as STYP_MIPS_INIT. + +Wed Jun 9 15:09:09 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (OMAGIC): Define. + +Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + Support for H8/300-H + * h8300.h: New magic number. + * internal.h: New relocations. + +Mon Apr 26 18:04:47 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h, sh.h: Support for SH. + +Sat Apr 24 21:34:59 1993 Jim Kingdon (kingdon@cygnus.com) + + * a29k.h: Define _LIT. + +Fri Apr 23 18:41:23 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * alpha.h: New file. + +Thu Apr 8 12:36:34 1993 Ian Lance Taylor (ian@cygnus.com) + + * internal.h (C_SHADOW, C_VERSION): Copied in from m88k.h. + * m88k.h, i386.h, we32k.h: Don't define all the storage classes; + they're already in internal.h. + +Wed Apr 7 11:51:24 1993 Jim Kingdon (kingdon@cygnus.com) + + * internal.h: Change n_sclass to unsigned char. + Change C_EFCN to 0xff, change RS/6000 dbx symbols + to no longer be signed. + +Fri Mar 19 14:52:56 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: Add H8/500 reloc types. + +Wed Mar 17 09:46:03 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff-ext.h (AUX_PUT_ANY): Don't use void values in branches of + conditional expression. + +Thu Mar 4 14:12:06 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff-ext.h (AUX_GET_*): Rewrote to use new macro AUX_GET_ANY. + (AUX_PUT_*): New macros corresponding to the AUX_GET macros. + (ecoff_swap_tir_out): Added prototype. + + * mips.h (N_BTMASK, N_TMASK, N_BTSHFT, N_TSHIFT): Define; these + are needed to interpret gcc debugging output. + +Tue Feb 9 07:43:27 1993 Ian Lance Taylor (ian@cygnus.com) + + * we32k.h (BTYPE, ISPTR, ISFCN, ISARY, DECREF): Removed + more definitions duplicated in internal.h. + +Wed Feb 3 09:18:24 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (RELOC_BITS3_TYPE_*): Correct for big endian machines. + +Mon Jan 25 11:35:51 1993 Ian Lance Taylor (ian@cygnus.com) + + * internal.h (internal_aouthdr): Added additional fields used only + by MIPS ECOFF. + +Thu Jan 21 10:28:38 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (AOUTHDR): Added additional fields used by ECOFF. + +Tue Jan 19 12:21:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i386.h, we32k.h (N_*, T_*, DT_*): Removed still more definitions + duplicated in internal.h. + + * mips.h (RELOC_SECTION_*, ECOFF_R_*): Defined constants for ECOFF + relocs. + +Fri Jan 15 18:17:00 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff-ext.h: Added prototypes for new ECOFF swapping functions. + (opt_ext): New structure. + * mips.h (ZMAGIC): Defined to be 0413. + (_LIB): Defined to be ".lib" + (external_reloc): MIPS ECOFF relocs are only 8 bytes. Added + macros to aid in swapping. + +Fri Jan 8 16:19:26 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff-ext.h: Added prototypes for ECOFF swapping functions. + * internal.h (internal_scnhdr): Always provide s_align field, not + just on i960. + (internal_reloc): Always provide r_size field, not just on + RS/6000. + * mips.h (_RDATA, _SDATA, _SBSS, _LIT4, _LIT8, STYP_RDATA, + STYP_SDATA, STYP_SBSS, STYP_LIT4, STYP_LIT8): Defined. + (CODE_MASK, MIPS_IS_STAB, MIPS_MARK_STAB, MIPS_UNMARK_STAB, + STABS_SYMBOL): Moved in from gdb/mipsread.c. + +Wed Jan 6 14:01:46 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i386.h, we32k.h: removed STYP_* defines, since they duplicated + those in internal.h. + +Tue Dec 29 15:40:07 1992 Ian Lance Taylor (ian@cygnus.com) + + * i386.h: define I386AIXMAGIC for Danbury AIX PS/2 compiler. + +Sat Dec 12 16:07:57 1992 Ian Lance Taylor (ian@cygnus.com) + + * i386.h: don't define BTYPE, ISPTR, ISFCN, ISARY, DECREF: they + are defined in internal.h. + +Thu Nov 12 09:52:01 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: (internal_reloc): r_offset is now a long. + * z8k.h: slight comment enhancement + +Wed Sep 30 07:46:08 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: changed z8k reloc types + +Fri Aug 28 10:16:31 1992 Brendan Kehoe (brendan@cygnus.com) + + * we32k.h: new file + +Thu Aug 27 13:00:01 1992 Brendan Kehoe (brendan@cygnus.com) + + * symconst.h: comment out cruft at the end of #endif + +Tue Aug 25 15:06:49 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: added #define for STYP_LIT, removed from a29k and + h8300. + + * z8k.h: added z8000 support + +Thu Jul 16 16:32:00 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: added R_RELLONG_NEG reloc type + +Fri Jun 12 20:11:04 1992 John Gilmore (gnu at cygnus.com) + + * symconst.h: Fix unterminated comment. + +Wed Jun 10 07:57:49 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * i386.h: a.out magic numbers from + mohring@informatik.tu-muenchen.de + +Mon Jun 8 20:13:33 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h, mips.h: Use unsigned chars everywhere. + (Suggested by Antti Miettinen.) + +Tue Apr 14 15:18:44 1992 John Gilmore (gnu at cygnus.com) + + * sym.h: Add comments. + * symconst.h: Merge with Fred's changes. + +Tue Apr 14 14:30:05 1992 Fred Fish (fnf@cygnus.com) + + * symconst.h: Pick up SGI defines for stStruct, stUnion, stEnum, + langCplusplus, and langCplusplusV2. + +Thu Apr 2 19:47:43 1992 John Gilmore (gnu at cygnus.com) + + * sym.h, symconst.h: MIPS has provided redistributable versions + of these files. Thanks! + * ecoff-ext.h: Add weakext bit to match new sym.h. + +Fri Mar 6 00:10:46 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h: Add relative file descriptors. + +Thu Feb 27 11:53:04 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h: New file for external (in-file) form of ecoff + symbol structures. + +Thu Feb 6 11:33:32 1992 Steve Chamberlain (sac at rtl.cygnus.com) + + * h8300.h: made the external_lineno l_lnno field 4 bytes wide. + andded GET/PUT_LINENO_LNNO macros + +Sat Nov 30 20:38:35 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * a29k.h, h8300.h, i386.h, i960.h, internal.h, m68k.h, m88k.h, + mips.h, rs6000.h: Move from above coff-<foo>.h. + + +Local Variables: +version-control: never +End: diff --git a/include/coff/a29k.h b/include/coff/a29k.h new file mode 100644 index 000000000..673e71696 --- /dev/null +++ b/include/coff/a29k.h @@ -0,0 +1,148 @@ +/* COFF spec for AMD 290*0 + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Contributed by David Wood @ New York University. */ + +#ifndef AMD +# define AMD +#endif + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* +** Magic numbers for Am29000 +** (AT&T will assign the "real" magic number) +*/ + +#define SIPFBOMAGIC 0572 /* Am29000 (Byte 0 is MSB) */ +#define SIPRBOMAGIC 0573 /* Am29000 (Byte 0 is LSB) */ + +#define A29K_MAGIC_BIG SIPFBOMAGIC +#define A29K_MAGIC_LITTLE SIPRBOMAGIC +#define A29KBADMAG(x) ( ((x).f_magic != A29K_MAGIC_BIG) && \ + ((x).f_magic != A29K_MAGIC_LITTLE)) + +#define OMAGIC A29K_MAGIC_BIG +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** File header flags currently known to us. +** +** Am29000 will use the F_AR32WR and F_AR32W flags to indicate +** the byte ordering in the file. +*/ + +/*--------------------------------------------------------------*/ + + +/* aouthdr magic numbers */ +#define NMAGIC 0410 /* separate i/d executable */ +#define SHMAGIC 0406 /* NYU/Ultra3 shared data executable + (writable text) */ +#undef _ETEXT +#define _ETEXT "_etext" + +/*--------------------------------------------------------------*/ + + +/* More names of "special" sections. */ +#define _LIT ".lit" + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Section types - with additional section type for global +** registers which will be relocatable for the Am29000. +** +** In instances where it is necessary for a linker to produce an +** output file which contains text or data not based at virtual +** address 0, e.g. for a ROM, then the linker should accept +** address base information as command input and use PAD sections +** to skip over unused addresses. +*/ + +#define STYP_BSSREG 0x1200 /* Global register area (like STYP_INFO) */ +#define STYP_ENVIR 0x2200 /* Environment (like STYP_INFO) */ +#define STYP_ABS 0x4000 /* Absolute (allocated, not reloc, loaded) */ + +/*--------------------------------------------------------------*/ + +/* +** Relocation information declaration and related definitions +*/ + +struct external_reloc +{ + char r_vaddr[4]; /* (virtual) address of reference */ + char r_symndx[4]; /* index into symbol table */ + char r_type[2]; /* relocation type */ +}; + +#define RELOC struct external_reloc +#define RELSZ 10 /* sizeof (RELOC) */ + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Relocation types for the Am29000 +*/ + +#define R_ABS 0 /* reference is absolute */ + +#define R_IREL 030 /* instruction relative (jmp/call) */ +#define R_IABS 031 /* instruction absolute (jmp/call) */ +#define R_ILOHALF 032 /* instruction low half (const) */ +#define R_IHIHALF 033 /* instruction high half (consth) part 1 */ +#define R_IHCONST 034 /* instruction high half (consth) part 2 */ + /* constant offset of R_IHIHALF relocation */ +#define R_BYTE 035 /* relocatable byte value */ +#define R_HWORD 036 /* relocatable halfword value */ +#define R_WORD 037 /* relocatable word value */ + +#define R_IGLBLRC 040 /* instruction global register RC */ +#define R_IGLBLRA 041 /* instruction global register RA */ +#define R_IGLBLRB 042 /* instruction global register RB */ + +/* +NOTE: +All the "I" forms refer to 29000 instruction formats. The linker is +expected to know how the numeric information is split and/or aligned +within the instruction word(s). R_BYTE works for instructions, too. + +If the parameter to a CONSTH instruction is a relocatable type, two +relocation records are written. The first has an r_type of R_IHIHALF +(33 octal) and a normal r_vaddr and r_symndx. The second relocation +record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which +is redundant), and an r_symndx containing the 32-bit constant offset +to the relocation instead of the actual symbol table index. This +second record is always written, even if the constant offset is zero. +The constant fields of the instruction are set to zero. +*/ + +/*--------------------------------------------------------------*/ + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Storage class definitions - new classes for global registers. +*/ + +#define C_GLBLREG 19 /* global register */ +#define C_EXTREG 20 /* external global register */ +#define C_DEFREG 21 /* ext. def. of global register */ diff --git a/include/coff/alpha.h b/include/coff/alpha.h new file mode 100644 index 000000000..e5210a569 --- /dev/null +++ b/include/coff/alpha.h @@ -0,0 +1,382 @@ +/* ECOFF support on Alpha machines. + coff/ecoff.h must be included before this file. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + unsigned char f_magic[2]; /* magic number */ + unsigned char f_nscns[2]; /* number of sections */ + unsigned char f_timdat[4]; /* time & date stamp */ + unsigned char f_symptr[8]; /* file pointer to symtab */ + unsigned char f_nsyms[4]; /* number of symtab entries */ + unsigned char f_opthdr[2]; /* sizeof(optional hdr) */ + unsigned char f_flags[2]; /* flags */ +}; + +/* Magic numbers are defined in coff/ecoff.h. */ +#define ALPHA_ECOFF_BADMAG(x) \ + ((x).f_magic != ALPHA_MAGIC && (x).f_magic != ALPHA_MAGIC_BSD) + +/* The object type is encoded in the f_flags. */ +#define F_ALPHA_OBJECT_TYPE_MASK 0x3000 +#define F_ALPHA_NO_SHARED 0x1000 +#define F_ALPHA_SHARABLE 0x2000 +#define F_ALPHA_CALL_SHARED 0x3000 + +#define FILHDR struct external_filehdr +#define FILHSZ 24 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct external_aouthdr +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char bldrev[2]; /* ?? */ + unsigned char padding[2]; /* pad to quadword boundary */ + unsigned char tsize[8]; /* text size in bytes */ + unsigned char dsize[8]; /* initialized data " " */ + unsigned char bsize[8]; /* uninitialized data " " */ + unsigned char entry[8]; /* entry pt. */ + unsigned char text_start[8]; /* base of text used for this file */ + unsigned char data_start[8]; /* base of data used for this file */ + unsigned char bss_start[8]; /* base of bss used for this file */ + unsigned char gprmask[4]; /* bitmask of general registers used */ + unsigned char fprmask[4]; /* bitmask of floating point registers used */ + unsigned char gp_value[8]; /* value for gp register */ +} AOUTHDR; + +/* compute size of a header */ + +#define AOUTSZ 80 +#define AOUTHDRSZ 80 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + unsigned char s_name[8]; /* section name */ + unsigned char s_paddr[8]; /* physical address, aliased s_nlib */ + unsigned char s_vaddr[8]; /* virtual address */ + unsigned char s_size[8]; /* section size */ + unsigned char s_scnptr[8]; /* file ptr to raw data for section */ + unsigned char s_relptr[8]; /* file ptr to relocation */ + unsigned char s_lnnoptr[8]; /* file ptr to line numbers */ + unsigned char s_nreloc[2]; /* number of relocation entries */ + unsigned char s_nlnno[2]; /* number of line number entries*/ + unsigned char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 64 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + unsigned char r_vaddr[8]; + unsigned char r_symndx[4]; + unsigned char r_bits[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + +/* Constants to unpack the r_bits field. The Alpha seems to always be + little endian, so I haven't bothered to define big endian variants + of these. */ + +#define RELOC_BITS0_TYPE_LITTLE 0xff +#define RELOC_BITS0_TYPE_SH_LITTLE 0 + +#define RELOC_BITS1_EXTERN_LITTLE 0x01 + +#define RELOC_BITS1_OFFSET_LITTLE 0x7e +#define RELOC_BITS1_OFFSET_SH_LITTLE 1 + +#define RELOC_BITS1_RESERVED_LITTLE 0x80 +#define RELOC_BITS1_RESERVED_SH_LITTLE 7 +#define RELOC_BITS2_RESERVED_LITTLE 0xff +#define RELOC_BITS2_RESERVED_SH_LEFT_LITTLE 1 +#define RELOC_BITS3_RESERVED_LITTLE 0x03 +#define RELOC_BITS3_RESERVED_SH_LEFT_LITTLE 9 + +#define RELOC_BITS3_SIZE_LITTLE 0xfc +#define RELOC_BITS3_SIZE_SH_LITTLE 2 + +/* The r_type field in a reloc is one of the following values. */ +#define ALPHA_R_IGNORE 0 +#define ALPHA_R_REFLONG 1 +#define ALPHA_R_REFQUAD 2 +#define ALPHA_R_GPREL32 3 +#define ALPHA_R_LITERAL 4 +#define ALPHA_R_LITUSE 5 +#define ALPHA_R_GPDISP 6 +#define ALPHA_R_BRADDR 7 +#define ALPHA_R_HINT 8 +#define ALPHA_R_SREL16 9 +#define ALPHA_R_SREL32 10 +#define ALPHA_R_SREL64 11 +#define ALPHA_R_OP_PUSH 12 +#define ALPHA_R_OP_STORE 13 +#define ALPHA_R_OP_PSUB 14 +#define ALPHA_R_OP_PRSHIFT 15 +#define ALPHA_R_GPVALUE 16 +#define ALPHA_R_GPRELHIGH 17 +#define ALPHA_R_GPRELLOW 18 +#define ALPHA_R_IMMED 19 + +/* Overloaded reloc value used by Net- and OpenBSD. */ +#define ALPHA_R_LITERALSLEAZY 17 + +/* With ALPHA_R_LITUSE, the r_size field is one of the following values. */ +#define ALPHA_R_LU_BASE 1 +#define ALPHA_R_LU_BYTOFF 2 +#define ALPHA_R_LU_JSR 3 + +/* With ALPHA_R_IMMED, the r_size field is one of the following values. */ +#define ALPHA_R_IMMED_GP_16 1 +#define ALPHA_R_IMMED_GP_HI32 2 +#define ALPHA_R_IMMED_SCN_HI32 3 +#define ALPHA_R_IMMED_BR_HI32 4 +#define ALPHA_R_IMMED_LO32 5 + +/********************** SYMBOLIC INFORMATION **********************/ + +/* Written by John Gilmore. */ + +/* ECOFF uses COFF-like section structures, but its own symbol format. + This file defines the symbol format in fields whose size and alignment + will not vary on different host systems. */ + +/* File header as a set of bytes */ + +struct hdr_ext +{ + unsigned char h_magic[2]; + unsigned char h_vstamp[2]; + unsigned char h_ilineMax[4]; + unsigned char h_idnMax[4]; + unsigned char h_ipdMax[4]; + unsigned char h_isymMax[4]; + unsigned char h_ioptMax[4]; + unsigned char h_iauxMax[4]; + unsigned char h_issMax[4]; + unsigned char h_issExtMax[4]; + unsigned char h_ifdMax[4]; + unsigned char h_crfd[4]; + unsigned char h_iextMax[4]; + unsigned char h_cbLine[8]; + unsigned char h_cbLineOffset[8]; + unsigned char h_cbDnOffset[8]; + unsigned char h_cbPdOffset[8]; + unsigned char h_cbSymOffset[8]; + unsigned char h_cbOptOffset[8]; + unsigned char h_cbAuxOffset[8]; + unsigned char h_cbSsOffset[8]; + unsigned char h_cbSsExtOffset[8]; + unsigned char h_cbFdOffset[8]; + unsigned char h_cbRfdOffset[8]; + unsigned char h_cbExtOffset[8]; +}; + +/* File descriptor external record */ + +struct fdr_ext +{ + unsigned char f_adr[8]; + unsigned char f_cbLineOffset[8]; + unsigned char f_cbLine[8]; + unsigned char f_cbSs[8]; + unsigned char f_rss[4]; + unsigned char f_issBase[4]; + unsigned char f_isymBase[4]; + unsigned char f_csym[4]; + unsigned char f_ilineBase[4]; + unsigned char f_cline[4]; + unsigned char f_ioptBase[4]; + unsigned char f_copt[4]; + unsigned char f_ipdFirst[4]; + unsigned char f_cpd[4]; + unsigned char f_iauxBase[4]; + unsigned char f_caux[4]; + unsigned char f_rfdBase[4]; + unsigned char f_crfd[4]; + unsigned char f_bits1[1]; + unsigned char f_bits2[3]; + unsigned char f_padding[4]; +}; + +#define FDR_BITS1_LANG_BIG 0xF8 +#define FDR_BITS1_LANG_SH_BIG 3 +#define FDR_BITS1_LANG_LITTLE 0x1F +#define FDR_BITS1_LANG_SH_LITTLE 0 + +#define FDR_BITS1_FMERGE_BIG 0x04 +#define FDR_BITS1_FMERGE_LITTLE 0x20 + +#define FDR_BITS1_FREADIN_BIG 0x02 +#define FDR_BITS1_FREADIN_LITTLE 0x40 + +#define FDR_BITS1_FBIGENDIAN_BIG 0x01 +#define FDR_BITS1_FBIGENDIAN_LITTLE 0x80 + +#define FDR_BITS2_GLEVEL_BIG 0xC0 +#define FDR_BITS2_GLEVEL_SH_BIG 6 +#define FDR_BITS2_GLEVEL_LITTLE 0x03 +#define FDR_BITS2_GLEVEL_SH_LITTLE 0 + +/* We ignore the `reserved' field in bits2. */ + +/* Procedure descriptor external record */ + +struct pdr_ext { + unsigned char p_adr[8]; + unsigned char p_cbLineOffset[8]; + unsigned char p_isym[4]; + unsigned char p_iline[4]; + unsigned char p_regmask[4]; + unsigned char p_regoffset[4]; + unsigned char p_iopt[4]; + unsigned char p_fregmask[4]; + unsigned char p_fregoffset[4]; + unsigned char p_frameoffset[4]; + unsigned char p_lnLow[4]; + unsigned char p_lnHigh[4]; + unsigned char p_gp_prologue[1]; + unsigned char p_bits1[1]; + unsigned char p_bits2[1]; + unsigned char p_localoff[1]; + unsigned char p_framereg[2]; + unsigned char p_pcreg[2]; +}; + +#define PDR_BITS1_GP_USED_BIG 0x80 +#define PDR_BITS1_REG_FRAME_BIG 0x40 +#define PDR_BITS1_PROF_BIG 0x20 +#define PDR_BITS1_RESERVED_BIG 0x1f +#define PDR_BITS1_RESERVED_SH_LEFT_BIG 8 +#define PDR_BITS2_RESERVED_BIG 0xff +#define PDR_BITS2_RESERVED_SH_BIG 0 + +#define PDR_BITS1_GP_USED_LITTLE 0x01 +#define PDR_BITS1_REG_FRAME_LITTLE 0x02 +#define PDR_BITS1_PROF_LITTLE 0x04 +#define PDR_BITS1_RESERVED_LITTLE 0xf8 +#define PDR_BITS1_RESERVED_SH_LITTLE 3 +#define PDR_BITS2_RESERVED_LITTLE 0xff +#define PDR_BITS2_RESERVED_SH_LEFT_LITTLE 5 + +/* Line numbers */ + +struct line_ext { + unsigned char l_line[4]; +}; + +/* Symbol external record */ + +struct sym_ext { + unsigned char s_value[8]; + unsigned char s_iss[4]; + unsigned char s_bits1[1]; + unsigned char s_bits2[1]; + unsigned char s_bits3[1]; + unsigned char s_bits4[1]; +}; + +#define SYM_BITS1_ST_BIG 0xFC +#define SYM_BITS1_ST_SH_BIG 2 +#define SYM_BITS1_ST_LITTLE 0x3F +#define SYM_BITS1_ST_SH_LITTLE 0 + +#define SYM_BITS1_SC_BIG 0x03 +#define SYM_BITS1_SC_SH_LEFT_BIG 3 +#define SYM_BITS1_SC_LITTLE 0xC0 +#define SYM_BITS1_SC_SH_LITTLE 6 + +#define SYM_BITS2_SC_BIG 0xE0 +#define SYM_BITS2_SC_SH_BIG 5 +#define SYM_BITS2_SC_LITTLE 0x07 +#define SYM_BITS2_SC_SH_LEFT_LITTLE 2 + +#define SYM_BITS2_RESERVED_BIG 0x10 +#define SYM_BITS2_RESERVED_LITTLE 0x08 + +#define SYM_BITS2_INDEX_BIG 0x0F +#define SYM_BITS2_INDEX_SH_LEFT_BIG 16 +#define SYM_BITS2_INDEX_LITTLE 0xF0 +#define SYM_BITS2_INDEX_SH_LITTLE 4 + +#define SYM_BITS3_INDEX_SH_LEFT_BIG 8 +#define SYM_BITS3_INDEX_SH_LEFT_LITTLE 4 + +#define SYM_BITS4_INDEX_SH_LEFT_BIG 0 +#define SYM_BITS4_INDEX_SH_LEFT_LITTLE 12 + +/* External symbol external record */ + +struct ext_ext { + struct sym_ext es_asym; + unsigned char es_bits1[1]; + unsigned char es_bits2[3]; + unsigned char es_ifd[4]; +}; + +#define EXT_BITS1_JMPTBL_BIG 0x80 +#define EXT_BITS1_JMPTBL_LITTLE 0x01 + +#define EXT_BITS1_COBOL_MAIN_BIG 0x40 +#define EXT_BITS1_COBOL_MAIN_LITTLE 0x02 + +#define EXT_BITS1_WEAKEXT_BIG 0x20 +#define EXT_BITS1_WEAKEXT_LITTLE 0x04 + +/* Dense numbers external record */ + +struct dnr_ext { + unsigned char d_rfd[4]; + unsigned char d_index[4]; +}; + +/* Relative file descriptor */ + +struct rfd_ext { + unsigned char rfd[4]; +}; + +/* Optimizer symbol external record */ + +struct opt_ext { + unsigned char o_bits1[1]; + unsigned char o_bits2[1]; + unsigned char o_bits3[1]; + unsigned char o_bits4[1]; + struct rndx_ext o_rndx; + unsigned char o_offset[4]; +}; + +#define OPT_BITS2_VALUE_SH_LEFT_BIG 16 +#define OPT_BITS2_VALUE_SH_LEFT_LITTLE 0 + +#define OPT_BITS3_VALUE_SH_LEFT_BIG 8 +#define OPT_BITS3_VALUE_SH_LEFT_LITTLE 8 + +#define OPT_BITS4_VALUE_SH_LEFT_BIG 0 +#define OPT_BITS4_VALUE_SH_LEFT_LITTLE 16 diff --git a/include/coff/apollo.h b/include/coff/apollo.h new file mode 100644 index 000000000..46284594b --- /dev/null +++ b/include/coff/apollo.h @@ -0,0 +1,124 @@ +/* coff information for Apollo M68K + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DO_NOT_DEFINE_AOUTHDR +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Motorola 68000/68008/68010/68020 */ +#define MC68MAGIC 0520 +#define MC68KWRMAGIC 0520 /* writeable text segments */ +#define MC68TVMAGIC 0521 +#define MC68KROMAGIC 0521 /* readonly shareable text segments */ +#define MC68KPGMAGIC 0522 /* demand paged text segments */ +#define M68MAGIC 0210 +#define M68TVMAGIC 0211 + +/* Apollo 68000-based machines have a different magic number. This comes + * from /usr/include/apollo/filehdr.h + */ +#define APOLLOM68KMAGIC 0627 + +#define OMAGIC M68MAGIC +#define M68KBADMAG(x) (((x).f_magic!=MC68MAGIC) && ((x).f_magic!=MC68KWRMAGIC) && ((x).f_magic!=MC68TVMAGIC) && \ + ((x).f_magic!=MC68KROMAGIC) && ((x).f_magic!=MC68KPGMAGIC) && ((x).f_magic!=M68MAGIC) && ((x).f_magic!=M68TVMAGIC) && \ + ((x).f_magic!=APOLLOM68KMAGIC) ) + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ + char o_sri[4]; /* Apollo specific - .sri data pointer */ + char o_inlib[4]; /* Apollo specific - .inlib data pointer */ + char vid[8]; /* Apollo specific - 64 bit version ID */ +} +AOUTHDR; + +#define APOLLO_COFF_VERSION_NUMBER 1 /* the value of the aouthdr magic */ +#define AOUTHDRSZ 44 +#define AOUTSZ 44 + +/* Apollo allowa for larger section names by allowing + them to be in the string table. */ + +/* If s_zeores is all zeroes, s_offset gives the real + location of the name in the string table. */ + +#define s_zeroes section_name.s_name +#define s_offset (section_name.s_name+4) + +/* More names of "special" sections. */ +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" +#define _LINES ".lines" +#define _BLOCKS ".blocks" +#define _SRI ".sri" /* Static Resource Information (systype, + et al.) */ +#define _MIR ".mir" /* Module Information Records */ +#define _APTV ".aptv" /* Apollo-style transfer vectors. */ +#define _INLIB ".inlib" /* Shared Library information */ +#define _RWDI ".rwdi" /* Read/write data initialization directives for + compressed sections */ +#define _UNWIND ".unwind" /* Stack unwind information */ + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +#ifdef M68K_COFF_OFFSET + char r_offset[4]; +#endif + +}; + +#define RELOC struct external_reloc + +#ifdef M68K_COFF_OFFSET +#define RELSZ 14 +#else +#define RELSZ 10 +#endif + +/* Apollo specific STYP flags */ + +#define STYP_RELOCATED_NOT_LOADED 0x00010000 /* Section is relocated normally during linking, but need + not be loaded during program execution */ +#define STYP_DEBUG 0x00020000 /* debug section */ +#define STYP_OVERLAY 0x00040000 /* Section is overlayed */ +#define STYP_INSTRUCTION 0x00200000 /* Section contains executable code */ + +#define STYP_ZERO 0x00800000 /* Section is initialized to zero */ +#define STYP_INSTALLED 0x02000000 /* Section should be installable in KGT */ +#define STYP_LOOK_INSTALLED 0x04000000 /* Look for section in KGT */ +#define STYP_SECALIGN1 0x08000000 /* Specially aligned section */ +#define STYP_SECALIGN2 0x10000000 /* " " " */ +#define STYP_COMPRESSED 0x20000000 /* No section data per se (s_scnptr = 0), but there are + initialization directives for it in .rwdi section + (used in conjunction with STYP_BSS) */ diff --git a/include/coff/arm.h b/include/coff/arm.h new file mode 100644 index 000000000..8b90228ca --- /dev/null +++ b/include/coff/arm.h @@ -0,0 +1,128 @@ +/* ARM COFF support for BFD. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define COFFARM 1 + +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_INTERWORK file supports switching between ARM and Thumb instruction sets + F_INTERWORK_SET the F_INTERWORK bit is valid + F_APCS_FLOAT code passes float arguments in float registers + F_PIC code is reentrant/position-independent + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) + F_APCS_26 file uses 26 bit ARM Procedure Calling Standard + F_APCS_SET the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised + F_SOFT_FLOAT code does not use floating point instructions. */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) +#define F_INTERWORK (0x0010) +#define F_INTERWORK_SET (0x0020) +#define F_APCS_FLOAT (0x0040) +#undef F_AR16WR +#define F_PIC (0x0080) +#define F_AR32WR (0x0100) +#define F_APCS_26 (0x0400) +#define F_APCS_SET (0x0800) +#define F_SOFT_FLOAT (0x2000) +#define F_VFP_FLOAT (0x4000) + +/* Bits stored in flags field of the internal_f structure */ + +#define F_INTERWORK (0x0010) +#define F_APCS_FLOAT (0x0040) +#define F_PIC (0x0080) +#define F_APCS26 (0x1000) +#define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400) +#define F_ARM_2 (0x0400) +#define F_ARM_2a (0x0800) +#define F_ARM_3 (0x0c00) +#define F_ARM_3M (0x4000) +#define F_ARM_4 (0x4400) +#define F_ARM_4T (0x4800) +#define F_ARM_5 (0x4c00) + +/* + ARMMAGIC ought to encoded the procesor type, + but it is too late to change it now, instead + the flags field of the internal_f structure + is used as shown above. + + XXX - NC 5/6/97. */ + +#define ARMMAGIC 0xa00 /* I just made this up */ + +#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC)) + +#define ARMPEMAGIC 0x1c0 +#define THUMBPEMAGIC 0x1c2 + +#undef ARMBADMAG +#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC) && ((x).f_magic != ARMPEMAGIC) && ((x).f_magic != THUMBPEMAGIC)) + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/* We use the .rdata section to hold read only data. */ +#define _LIT ".rdata" + +/********************** RELOCATION DIRECTIVES **********************/ +#ifdef ARM_WINCE +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + +#else +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_offset[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 +#endif + +#define ARM_NOTE_SECTION ".note" diff --git a/include/coff/aux-coff.h b/include/coff/aux-coff.h new file mode 100644 index 000000000..f8536c9e7 --- /dev/null +++ b/include/coff/aux-coff.h @@ -0,0 +1,48 @@ +/* Modifications of internal.h and m68k.h needed by A/UX + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Suggested by Ian Lance Taylor <ian@cygnus.com> */ + +#ifndef GNU_COFF_AUX_H +#define GNU_COFF_AUX_H 1 + +#include "coff/internal.h" +#include "coff/m68k.h" + +/* Section contains 64-byte padded pathnames of shared libraries */ +#undef STYP_LIB +#define STYP_LIB 0x200 + +/* Section contains shared library initialization code */ +#undef STYP_INIT +#define STYP_INIT 0x400 + +/* Section contains .ident information */ +#undef STYP_IDENT +#define STYP_IDENT 0x800 + +/* Section types used by bfd and gas not defined (directly) by A/UX */ +#undef STYP_OVER +#define STYP_OVER 0 +#undef STYP_INFO +#define STYP_INFO STYP_IDENT + +/* Traditional name of the section tagged with STYP_LIB */ +#define _LIB ".lib" + +#endif /* GNU_COFF_AUX_H */ diff --git a/include/coff/ecoff.h b/include/coff/ecoff.h new file mode 100644 index 000000000..1a39fcbd6 --- /dev/null +++ b/include/coff/ecoff.h @@ -0,0 +1,408 @@ +/* Generic ECOFF support. + This does not include symbol information, found in sym.h and + symconst.h. + + Copyright 2001, 2002, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef ECOFF_H +#define ECOFF_H + +/* Mips magic numbers used in filehdr. MIPS_MAGIC_LITTLE is used on + little endian machines. MIPS_MAGIC_BIG is used on big endian + machines. Where is MIPS_MAGIC_1 from? */ +#define MIPS_MAGIC_1 0x0180 +#define MIPS_MAGIC_LITTLE 0x0162 +#define MIPS_MAGIC_BIG 0x0160 + +/* These are the magic numbers used for MIPS code compiled at ISA + level 2. */ +#define MIPS_MAGIC_LITTLE2 0x0166 +#define MIPS_MAGIC_BIG2 0x0163 + +/* These are the magic numbers used for MIPS code compiled at ISA + level 3. */ +#define MIPS_MAGIC_LITTLE3 0x142 +#define MIPS_MAGIC_BIG3 0x140 + +/* Alpha magic numbers used in filehdr. */ +#define ALPHA_MAGIC 0x183 +#define ALPHA_MAGIC_BSD 0x185 + +/* Magic numbers used in a.out header. */ +#define ECOFF_AOUT_OMAGIC 0407 /* not demand paged (ld -N). */ +#define ECOFF_AOUT_ZMAGIC 0413 /* demand load format, eg normal ld output */ + +/* Names of special sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _RDATA ".rdata" +#define _SDATA ".sdata" +#define _SBSS ".sbss" +#define _LITA ".lita" +#define _LIT4 ".lit4" +#define _LIT8 ".lit8" +#define _LIB ".lib" +#define _INIT ".init" +#define _FINI ".fini" +#define _PDATA ".pdata" +#define _XDATA ".xdata" +#define _GOT ".got" +#define _HASH ".hash" +#define _DYNSYM ".dynsym" +#define _DYNSTR ".dynstr" +#define _RELDYN ".rel.dyn" +#define _CONFLIC ".conflic" +#define _COMMENT ".comment" +#define _LIBLIST ".liblist" +#define _DYNAMIC ".dynamic" +#define _RCONST ".rconst" + +/* ECOFF uses some additional section flags. */ +#define STYP_RDATA 0x100 +#define STYP_SDATA 0x200 +#define STYP_SBSS 0x400 +#define STYP_GOT 0x1000 +#define STYP_DYNAMIC 0x2000 +#define STYP_DYNSYM 0x4000 +#define STYP_RELDYN 0x8000 +#define STYP_DYNSTR 0x10000 +#define STYP_HASH 0x20000 +#define STYP_LIBLIST 0x40000 +#define STYP_CONFLIC 0x100000 +#define STYP_ECOFF_FINI 0x1000000 +#define STYP_EXTENDESC 0x2000000 /* 0x02FFF000 bits => scn type, rest clr */ +#define STYP_LITA 0x4000000 +#define STYP_LIT8 0x8000000 +#define STYP_LIT4 0x10000000 +#define STYP_ECOFF_LIB 0x40000000 +#define STYP_ECOFF_INIT 0x80000000 +#define STYP_OTHER_LOAD (STYP_ECOFF_INIT | STYP_ECOFF_FINI) + +/* extended section types */ +#define STYP_COMMENT 0x2100000 +#define STYP_RCONST 0x2200000 +#define STYP_XDATA 0x2400000 +#define STYP_PDATA 0x2800000 + +/* The linker needs a section to hold small common variables while + linking. There is no convenient way to create it when the linker + needs it, so we always create one for each BFD. We then avoid + writing it out. */ +#define SCOMMON ".scommon" + +/* If the extern bit in a reloc is 1, then r_symndx is an index into + the external symbol table. If the extern bit is 0, then r_symndx + indicates a section, and is one of the following values. */ +#define RELOC_SECTION_NONE 0 +#define RELOC_SECTION_TEXT 1 +#define RELOC_SECTION_RDATA 2 +#define RELOC_SECTION_DATA 3 +#define RELOC_SECTION_SDATA 4 +#define RELOC_SECTION_SBSS 5 +#define RELOC_SECTION_BSS 6 +#define RELOC_SECTION_INIT 7 +#define RELOC_SECTION_LIT8 8 +#define RELOC_SECTION_LIT4 9 +#define RELOC_SECTION_XDATA 10 +#define RELOC_SECTION_PDATA 11 +#define RELOC_SECTION_FINI 12 +#define RELOC_SECTION_LITA 13 +#define RELOC_SECTION_ABS 14 +#define RELOC_SECTION_RCONST 15 + +#define NUM_RELOC_SECTIONS 16 + +/********************** STABS **********************/ + +/* gcc uses mips-tfile to output type information in special stabs + entries. These must match the corresponding definition in + gcc/config/mips.h. At some point, these should probably go into a + shared include file, but currently gcc and gdb do not share any + directories. */ +#define CODE_MASK 0x8F300 +#define ECOFF_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) +#define ECOFF_MARK_STAB(code) ((code)+CODE_MASK) +#define ECOFF_UNMARK_STAB(code) ((code)-CODE_MASK) +#define STABS_SYMBOL "@stabs" + +/********************** COFF **********************/ + +/* gcc also uses mips-tfile to output COFF debugging information. + These are the values it uses when outputting the .type directive. + These should also be in a shared include file. */ +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +/********************** AUX **********************/ + +/* The auxiliary type information is the same on all known ECOFF + targets. I can't see any reason that it would ever change, so I am + going to gamble and define the external structures here, in the + target independent ECOFF header file. The internal forms are + defined in coff/sym.h, which was originally donated by MIPS + Computer Systems. */ + +/* Type information external record */ + +struct tir_ext { + unsigned char t_bits1[1]; + unsigned char t_tq45[1]; + unsigned char t_tq01[1]; + unsigned char t_tq23[1]; +}; + +#define TIR_BITS1_FBITFIELD_BIG ((unsigned int) 0x80) +#define TIR_BITS1_FBITFIELD_LITTLE ((unsigned int) 0x01) + +#define TIR_BITS1_CONTINUED_BIG ((unsigned int) 0x40) +#define TIR_BITS1_CONTINUED_LITTLE ((unsigned int) 0x02) + +#define TIR_BITS1_BT_BIG ((unsigned int) 0x3F) +#define TIR_BITS1_BT_SH_BIG 0 +#define TIR_BITS1_BT_LITTLE ((unsigned int) 0xFC) +#define TIR_BITS1_BT_SH_LITTLE 2 + +#define TIR_BITS_TQ4_BIG ((unsigned int) 0xF0) +#define TIR_BITS_TQ4_SH_BIG 4 +#define TIR_BITS_TQ5_BIG ((unsigned int) 0x0F) +#define TIR_BITS_TQ5_SH_BIG 0 +#define TIR_BITS_TQ4_LITTLE ((unsigned int) 0x0F) +#define TIR_BITS_TQ4_SH_LITTLE 0 +#define TIR_BITS_TQ5_LITTLE ((unsigned int) 0xF0) +#define TIR_BITS_TQ5_SH_LITTLE 4 + +#define TIR_BITS_TQ0_BIG ((unsigned int) 0xF0) +#define TIR_BITS_TQ0_SH_BIG 4 +#define TIR_BITS_TQ1_BIG ((unsigned int) 0x0F) +#define TIR_BITS_TQ1_SH_BIG 0 +#define TIR_BITS_TQ0_LITTLE ((unsigned int) 0x0F) +#define TIR_BITS_TQ0_SH_LITTLE 0 +#define TIR_BITS_TQ1_LITTLE ((unsigned int) 0xF0) +#define TIR_BITS_TQ1_SH_LITTLE 4 + +#define TIR_BITS_TQ2_BIG ((unsigned int) 0xF0) +#define TIR_BITS_TQ2_SH_BIG 4 +#define TIR_BITS_TQ3_BIG ((unsigned int) 0x0F) +#define TIR_BITS_TQ3_SH_BIG 0 +#define TIR_BITS_TQ2_LITTLE ((unsigned int) 0x0F) +#define TIR_BITS_TQ2_SH_LITTLE 0 +#define TIR_BITS_TQ3_LITTLE ((unsigned int) 0xF0) +#define TIR_BITS_TQ3_SH_LITTLE 4 + +/* Relative symbol external record */ + +struct rndx_ext { + unsigned char r_bits[4]; +}; + +#define RNDX_BITS0_RFD_SH_LEFT_BIG 4 +#define RNDX_BITS1_RFD_BIG ((unsigned int) 0xF0) +#define RNDX_BITS1_RFD_SH_BIG 4 + +#define RNDX_BITS0_RFD_SH_LEFT_LITTLE 0 +#define RNDX_BITS1_RFD_LITTLE ((unsigned int) 0x0F) +#define RNDX_BITS1_RFD_SH_LEFT_LITTLE 8 + +#define RNDX_BITS1_INDEX_BIG ((unsigned int) 0x0F) +#define RNDX_BITS1_INDEX_SH_LEFT_BIG 16 +#define RNDX_BITS2_INDEX_SH_LEFT_BIG 8 +#define RNDX_BITS3_INDEX_SH_LEFT_BIG 0 + +#define RNDX_BITS1_INDEX_LITTLE ((unsigned int) 0xF0) +#define RNDX_BITS1_INDEX_SH_LITTLE 4 +#define RNDX_BITS2_INDEX_SH_LEFT_LITTLE 4 +#define RNDX_BITS3_INDEX_SH_LEFT_LITTLE 12 + +/* Auxiliary symbol information external record */ + +union aux_ext { + struct tir_ext a_ti; + struct rndx_ext a_rndx; + unsigned char a_dnLow[4]; + unsigned char a_dnHigh[4]; + unsigned char a_isym[4]; + unsigned char a_iss[4]; + unsigned char a_width[4]; + unsigned char a_count[4]; +}; + +#define AUX_GET_ANY(bigend, ax, field) \ + ((bigend) ? bfd_getb32 ((ax)->field) : bfd_getl32 ((ax)->field)) + +#define AUX_GET_DNLOW(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_dnLow) +#define AUX_GET_DNHIGH(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_dnHigh) +#define AUX_GET_ISYM(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_isym) +#define AUX_GET_ISS(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_iss) +#define AUX_GET_WIDTH(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_width) +#define AUX_GET_COUNT(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_count) + +#define AUX_PUT_ANY(bigend, val, ax, field) \ + ((bigend) \ + ? (bfd_putb32 ((bfd_vma) (val), (ax)->field), 0) \ + : (bfd_putl32 ((bfd_vma) (val), (ax)->field), 0)) + +#define AUX_PUT_DNLOW(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_dnLow) +#define AUX_PUT_DNHIGH(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_dnHigh) +#define AUX_PUT_ISYM(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_isym) +#define AUX_PUT_ISS(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_iss) +#define AUX_PUT_WIDTH(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_width) +#define AUX_PUT_COUNT(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_count) + +/********************** SYMBOLS **********************/ + +/* For efficiency, gdb deals directly with the unswapped symbolic + information (that way it only takes the time to swap information + that it really needs to read). gdb originally retrieved the + information directly from the BFD backend information, but that + strategy, besides being sort of ugly, does not work for MIPS ELF, + which also uses ECOFF debugging information. This structure holds + pointers to the (mostly) unswapped symbolic information. */ + +struct ecoff_debug_info +{ + /* The swapped ECOFF symbolic header. */ + HDRR symbolic_header; + + /* Pointers to the unswapped symbolic information. Note that the + pointers to external structures point to different sorts of + information on different ECOFF targets. The ecoff_debug_swap + structure provides the sizes of the structures and the functions + needed to swap the information in and out. These pointers are + all pointers to arrays, not single structures. They will be NULL + if there are no instances of the relevant structure. These + fields are also used by the assembler to output ECOFF debugging + information. */ + unsigned char *line; + void *external_dnr; /* struct dnr_ext */ + void *external_pdr; /* struct pdr_ext */ + void *external_sym; /* struct sym_ext */ + void *external_opt; /* struct opt_ext */ + union aux_ext *external_aux; + char *ss; + char *ssext; + void *external_fdr; /* struct fdr_ext */ + void *external_rfd; /* struct rfd_ext */ + void *external_ext; /* struct ext_ext */ + + /* These fields are used when linking. They may disappear at some + point. */ + char *ssext_end; + void *external_ext_end; + + /* When linking, this field holds a mapping from the input FDR + numbers to the output numbers, and is used when writing out the + external symbols. It is NULL if no mapping is required. */ + RFDT *ifdmap; + + /* The swapped FDR information. Currently this is never NULL, but + code using this structure should probably double-check in case + this changes in the future. This is a pointer to an array, not a + single structure. */ + FDR *fdr; +}; + +/* These structures are used by the ECOFF find_nearest_line function. */ + +struct ecoff_fdrtab_entry +{ + /* Base address in .text of this FDR. */ + bfd_vma base_addr; + FDR *fdr; +}; + +struct ecoff_find_line +{ + /* Allocated memory to hold function and file names. */ + char *find_buffer; + + /* FDR table, sorted by address: */ + long fdrtab_len; + struct ecoff_fdrtab_entry *fdrtab; + + /* Cache entry for most recently found line information. The sect + field is NULL if this cache does not contain valid information. */ + struct + { + asection *sect; + bfd_vma start; + bfd_vma stop; + const char *filename; + const char *functionname; + unsigned int line_num; + } cache; +}; + +/********************** SWAPPING **********************/ + +/* The generic ECOFF code needs to be able to swap debugging + information in and out in the specific format used by a particular + ECOFF implementation. This structure provides the information + needed to do this. */ + +struct ecoff_debug_swap +{ + /* Symbol table magic number. */ + int sym_magic; + /* Alignment of debugging information. E.g., 4. */ + bfd_size_type debug_align; + /* Sizes of external symbolic information. */ + bfd_size_type external_hdr_size; + bfd_size_type external_dnr_size; + bfd_size_type external_pdr_size; + bfd_size_type external_sym_size; + bfd_size_type external_opt_size; + bfd_size_type external_fdr_size; + bfd_size_type external_rfd_size; + bfd_size_type external_ext_size; + /* Functions to swap in external symbolic data. */ + void (*swap_hdr_in) (bfd *, void *, HDRR *); + void (*swap_dnr_in) (bfd *, void *, DNR *); + void (*swap_pdr_in) (bfd *, void *, PDR *); + void (*swap_sym_in) (bfd *, void *, SYMR *); + void (*swap_opt_in) (bfd *, void *, OPTR *); + void (*swap_fdr_in) (bfd *, void *, FDR *); + void (*swap_rfd_in) (bfd *, void *, RFDT *); + void (*swap_ext_in) (bfd *, void *, EXTR *); + void (*swap_tir_in) (int, const struct tir_ext *, TIR *); + void (*swap_rndx_in) (int, const struct rndx_ext *, RNDXR *); + /* Functions to swap out external symbolic data. */ + void (*swap_hdr_out) (bfd *, const HDRR *, void *); + void (*swap_dnr_out) (bfd *, const DNR *, void *); + void (*swap_pdr_out) (bfd *, const PDR *, void *); + void (*swap_sym_out) (bfd *, const SYMR *, void *); + void (*swap_opt_out) (bfd *, const OPTR *, void *); + void (*swap_fdr_out) (bfd *, const FDR *, void *); + void (*swap_rfd_out) (bfd *, const RFDT *, void *); + void (*swap_ext_out) (bfd *, const EXTR *, void *); + void (*swap_tir_out) (int, const TIR *, struct tir_ext *); + void (*swap_rndx_out) (int, const RNDXR *, struct rndx_ext *); + /* Function to read symbol data and set up pointers in + ecoff_debug_info structure. The section argument is used for + ELF, not straight ECOFF. */ + bfd_boolean (*read_debug_info) (bfd *, asection *, struct ecoff_debug_info *); +}; + +#endif /* ! defined (ECOFF_H) */ diff --git a/include/coff/external.h b/include/coff/external.h new file mode 100644 index 000000000..19636dab7 --- /dev/null +++ b/include/coff/external.h @@ -0,0 +1,254 @@ +/* external.h -- External COFF structures + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef COFF_EXTERNAL_H +#define COFF_EXTERNAL_H + +#ifndef DO_NOT_DEFINE_FILHDR +/********************** FILE HEADER **********************/ + +struct external_filehdr + { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + }; + +#define FILHDR struct external_filehdr +#define FILHSZ 20 +#endif + +#ifndef DO_NOT_DEFINE_AOUTHDR +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct external_aouthdr + { + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ + } +AOUTHDR; + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 +#endif + +#ifndef DO_NOT_DEFINE_SCNHDR +/********************** SECTION HEADER **********************/ + +struct external_scnhdr + { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries */ + char s_flags[4]; /* flags */ + }; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* Names of "special" sections. */ + +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _COMMENT ".comment" +#define _LIB ".lib" +#endif /* not DO_NOT_DEFINE_SCNHDR */ + +#ifndef DO_NOT_DEFINE_LINENO + +/********************** LINE NUMBERS **********************/ + +#ifndef L_LNNO_SIZE +#error L_LNNO_SIZE needs to be defined +#endif + +/* 1 line number entry for every "breakpointable" source line in a section. + Line numbers are grouped on a per function basis; first entry in a function + grouping will have l_lnno = 0 and in place of physical address will be the + symbol table index of the function name. */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + + char l_lnno[L_LNNO_SIZE]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ (4 + L_LNNO_SIZE) + +#if L_LNNO_SIZE == 4 +#define GET_LINENO_LNNO(abfd, ext) H_GET_32 (abfd, (ext->l_lnno)) +#define PUT_LINENO_LNNO(abfd, val, ext) H_PUT_32 (abfd, val, (ext->l_lnno)) +#endif +#if L_LNNO_SIZE == 2 +#define GET_LINENO_LNNO(abfd, ext) H_GET_16 (abfd, (ext->l_lnno)) +#define PUT_LINENO_LNNO(abfd, val, ext) H_PUT_16 (abfd, val, (ext->l_lnno)) +#endif + +#endif /* not DO_NOT_DEFINE_LINENO */ + +#ifndef DO_NOT_DEFINE_SYMENT +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#ifndef E_FILNMLEN +#define E_FILNMLEN 14 +#endif +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 + +#ifndef N_BTMASK +#define N_BTMASK 0xf +#endif + +#ifndef N_TMASK +#define N_TMASK 0x30 +#endif + +#ifndef N_BTSHFT +#define N_BTSHFT 4 +#endif + +#ifndef N_TSHIFT +#define N_TSHIFT 2 +#endif + +#endif /* not DO_NOT_DEFINE_SYMENT */ + +#ifndef DO_NOT_DEFINE_AUXENT + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + + char x_fsize[4]; /* size of function */ + + } x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + + char x_tvndx[2]; /* tv index */ + + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ +#ifdef INCLUDE_COMDAT_FIELDS_IN_AUXENT + char x_checksum[4]; /* section COMDAT checksum */ + char x_associated[2]; /* COMDAT associated section index */ + char x_comdat[1]; /* COMDAT selection number */ +#endif + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +}; + +#define AUXENT union external_auxent +#define AUXESZ 18 + +#define _ETEXT "etext" + +#endif /* not DO_NOT_DEFINE_AUXENT */ + +#endif /* COFF_EXTERNAL_H */ diff --git a/include/coff/go32exe.h b/include/coff/go32exe.h new file mode 100644 index 000000000..ccd5c917d --- /dev/null +++ b/include/coff/go32exe.h @@ -0,0 +1,37 @@ +/* COFF information for PC running go32. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define STUBSIZE 2048 + +struct external_filehdr_go32_exe + { + char stub[STUBSIZE];/* the stub to load the image */ + /* the standard COFF header */ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + }; + +#undef FILHDR +#define FILHDR struct external_filehdr_go32_exe +#undef FILHSZ +#define FILHSZ STUBSIZE+20 diff --git a/include/coff/h8300.h b/include/coff/h8300.h new file mode 100644 index 000000000..908848c18 --- /dev/null +++ b/include/coff/h8300.h @@ -0,0 +1,54 @@ +/* coff information for Renesas H8/300 and H8/300-H + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define H8300MAGIC 0x8300 +#define H8300HMAGIC 0x8301 +#define H8300SMAGIC 0x8302 +#define H8300HNMAGIC 0x8303 +#define H8300SNMAGIC 0x8304 + +#define H8300BADMAG(x) (((x).f_magic != H8300MAGIC)) +#define H8300HBADMAG(x) (((x).f_magic != H8300HMAGIC)) +#define H8300SBADMAG(x) (((x).f_magic != H8300SMAGIC)) +#define H8300HNBADMAG(x) (((x).f_magic != H8300HNMAGIC)) +#define H8300SNBADMAG(x) (((x).f_magic != H8300SNMAGIC)) + +/* Relocation directives. */ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/include/coff/h8500.h b/include/coff/h8500.h new file mode 100644 index 000000000..62968cad9 --- /dev/null +++ b/include/coff/h8500.h @@ -0,0 +1,46 @@ +/* coff information for Renesas H8/500 + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define H8500MAGIC 0x8500 + +#define H8500BADMAG(x) ((0xffff && ((x).f_magic) != H8500MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/include/coff/i386.h b/include/coff/i386.h new file mode 100644 index 000000000..484a3b1e9 --- /dev/null +++ b/include/coff/i386.h @@ -0,0 +1,71 @@ +/* coff information for Intel 386/486. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +#define I386MAGIC 0x14c +#define I386PTXMAGIC 0x154 +#define I386AIXMAGIC 0x175 + +/* This is Lynx's all-platform magic number for executables. */ + +#define LYNXCOFFMAGIC 0415 + +#define I386BADMAG(x) ( ((x).f_magic != I386MAGIC) \ + && (x).f_magic != I386AIXMAGIC \ + && (x).f_magic != I386PTXMAGIC \ + && (x).f_magic != LYNXCOFFMAGIC) + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/include/coff/i860.h b/include/coff/i860.h new file mode 100644 index 000000000..c7072b26b --- /dev/null +++ b/include/coff/i860.h @@ -0,0 +1,86 @@ +/* COFF information for the Intel i860. + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file was hacked from i386.h [dolan@ssd.intel.com] */ + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +#define I860MAGIC 0x14d + +#define I860BADMAG(x) ((x).f_magic != I860MAGIC) + +#undef AOUTSZ +#define AOUTSZ 36 + +/* FIXME: What are the a.out magic numbers? */ + +#define _ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + +/* The relocation directory entry types. + PAIR : The low half that follows relates to the preceeding HIGH[ADJ]. + HIGH : The high half of a 32-bit constant. + LOWn : The low half, insn bits 15..(n-1), 2^n-byte aligned. + SPLITn : The low half, insn bits 20..16 and 10..(n-1), 2^n-byte aligned. + HIGHADJ: Similar to HIGH, but with adjustment. + BRADDR : 26-bit branch displacement. + + Note: The Intel assembler manual lists LOW4 as one of the + relocation types, but it appears to be useless for the i860. + We will recognize it anyway, just in case it actually appears in + any object files. */ + +enum { + COFF860_R_PAIR = 0x1c, + COFF860_R_HIGH = 0x1e, + COFF860_R_LOW0 = 0x1f, + COFF860_R_LOW1 = 0x20, + COFF860_R_LOW2 = 0x21, + COFF860_R_LOW3 = 0x22, + COFF860_R_LOW4 = 0x23, + COFF860_R_SPLIT0 = 0x24, + COFF860_R_SPLIT1 = 0x25, + COFF860_R_SPLIT2 = 0x26, + COFF860_R_HIGHADJ = 0x27, + COFF860_R_BRADDR = 0x28 +}; + diff --git a/include/coff/i960.h b/include/coff/i960.h new file mode 100644 index 000000000..b9d167e25 --- /dev/null +++ b/include/coff/i960.h @@ -0,0 +1,319 @@ +/* coff information for 80960. Origins: Intel corp, natch. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* NOTE: Tagentries (cf TAGBITS) are no longer used by the 960 */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define OMAGIC (0407) /* old impure format. data immediately + follows text. both sections are rw. */ +#define NMAGIC (0410) /* split i&d, read-only text */ + +/* +* Intel 80960 (I960) processor flags. +* F_I960TYPE == mask for processor type field. +*/ + +#define F_I960TYPE (0xf000) +#define F_I960CORE (0x1000) +#define F_I960KB (0x2000) +#define F_I960SB (0x2000) +#define F_I960MC (0x3000) +#define F_I960XA (0x4000) +#define F_I960CA (0x5000) +#define F_I960KA (0x6000) +#define F_I960SA (0x6000) +#define F_I960JX (0x7000) +#define F_I960HX (0x8000) + + +/** i80960 Magic Numbers +*/ + +#define I960ROMAGIC (0x160) /* read-only text segments */ +#define I960RWMAGIC (0x161) /* read-write text segments */ + +#define I960BADMAG(x) (((x).f_magic!=I960ROMAGIC) && ((x).f_magic!=I960RWMAGIC)) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + unsigned long phys_addr; + unsigned long bitarray; +} TAGBITS; + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ + char tagentries[4]; /* number of tag entries to follow */ +} +AOUTHDR; + +/* return a pointer to the tag bits array */ + +#define TAGPTR(aout) ((TAGBITS *) (&(aout.tagentries)+1)) + +/* compute size of a header */ + +/*#define AOUTSZ(aout) (sizeof(AOUTHDR)+(aout.tagentries*sizeof(TAGBITS)))*/ +#define AOUTSZ 32 +#define AOUTHDRSZ 32 + + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ + char s_align[4]; /* section alignment */ +}; + + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 44 + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + + char l_lnno[2]; /* line number */ + char padding[2]; /* force alignment */ +}; + + +#define LINENO struct external_lineno +#define LINESZ 8 + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + + char e_value[4]; + char e_scnum[2]; + char e_flags[2]; + char e_type[4]; + char e_sclass[1]; + char e_numaux[1]; + char pad2[2]; +}; + +#define N_BTMASK (0x1f) +#define N_TMASK (0x60) +#define N_BTSHFT (5) +#define N_TSHIFT (2) + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + + char x_fsize[4]; /* size of function */ + + } x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + + char x_tvndx[2]; /* tv index */ + + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + /****************************************** + * I960-specific *2nd* aux. entry formats + ******************************************/ + struct + { + /* This is a very old typo that keeps getting propagated. */ +#define x_stdindx x_stindx + char x_stindx[4]; /* sys. table entry */ + } x_sc; /* system call entry */ + + struct + { + char x_balntry[4]; /* BAL entry point */ + } x_bal; /* BAL-callable function */ + + struct + { + char x_timestamp[4]; /* time stamp */ + char x_idstring[20]; /* producer identity string */ + + } x_ident; /* Producer ident info */ +}; + +#define SYMENT struct external_syment +#define SYMESZ 24 +#define AUXENT union external_auxent +#define AUXESZ 24 + +# define _ETEXT "_etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char pad[2]; +}; + +/* r_type values for the i960. */ + +/* The i960 uses R_RELLONG, which is defined in internal.h as 0x11. + It is an absolute 32 bit relocation. */ + +#define R_IPRMED (0x19) /* 24-bit ip-relative relocation */ +#define R_OPTCALL (0x1b) /* 32-bit optimizable call (leafproc/sysproc) */ +#define R_OPTCALLX (0x1c) /* 64-bit optimizable call (leafproc/sysproc) */ + +/* The following relocation types are defined use by relaxing linkers, + which convert 32 bit calls (which require a 64 bit instruction) + into 24 bit calls (which require a 32 bit instruction) when + possible. It will be possible whenever the target of the call is + within a 24 bit range of the call instruction. + + It is always safe to ignore these relocations. They only serve to + mark points which the relaxing linker will have to consider. The + assembler must ensure that the correct code is generated even if + the relocations are ignored. In particular, this means that the + R_IPR13 relocation may not appear with an external symbol. */ + +#define R_IPR13 (0x1d) /* 13 bit ip-relative branch */ +#define R_ALIGN (0x1e) /* alignment marker. This has no + associated symbol. Instead, the + r_symndx field indicates the + require alignment at this point in + the file. It must be a power of 2. */ + +#define RELOC struct external_reloc +#define RELSZ 12 + diff --git a/include/coff/ia64.h b/include/coff/ia64.h new file mode 100644 index 000000000..f7ff0ee22 --- /dev/null +++ b/include/coff/ia64.h @@ -0,0 +1,88 @@ +/* coff information for HP/Intel IA-64. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DO_NOT_DEFINE_AOUTHDR +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +#define IA64MAGIC 0x200 + +#define IA64BADMAG(x) (((x).f_magic != IA64MAGIC)) + +/* Bits for f_flags: + * F_RELFLG relocation info stripped from file + * F_EXEC file is executable (no unresolved external references) + * F_LNNO line numbers stripped from file + * F_LSYMS local symbols stripped from file + * F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) + */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +/********************** AOUT "OPTIONAL HEADER" **********************/ +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ +#ifndef BFD64 + char data_start[4]; /* base of data used for this file */ +#endif +} +AOUTHDR; + +#define PE32MAGIC 0x10b /* 32-bit image */ +#define PE32PMAGIC 0x20b /* 32-bit image inside 64-bit address space */ + +#define PE32PBADMAG(x) (((x).f_magic != PE32PMAGIC)) + +#define AOUTSZ 108 +#define AOUTHDRSZ 108 + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/include/coff/internal.h b/include/coff/internal.h new file mode 100644 index 000000000..710e932c7 --- /dev/null +++ b/include/coff/internal.h @@ -0,0 +1,746 @@ +/* Internal format of COFF object file data structures, for GNU BFD. + This file is part of BFD, the Binary File Descriptor library. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef GNU_COFF_INTERNAL_H +#define GNU_COFF_INTERNAL_H 1 + +/* First, make "signed char" work, even on old compilers. */ +#ifndef signed +#ifndef __STDC__ +#define signed /**/ +#endif +#endif + +/********************** FILE HEADER **********************/ + +/* extra stuff in a PE header. */ + +struct internal_extra_pe_filehdr +{ + /* DOS header data follows for PE stuff */ + unsigned short e_magic; /* Magic number, 0x5a4d */ + unsigned short e_cblp; /* Bytes on last page of file, 0x90 */ + unsigned short e_cp; /* Pages in file, 0x3 */ + unsigned short e_crlc; /* Relocations, 0x0 */ + unsigned short e_cparhdr; /* Size of header in paragraphs, 0x4 */ + unsigned short e_minalloc; /* Minimum extra paragraphs needed, 0x0 */ + unsigned short e_maxalloc; /* Maximum extra paragraphs needed, 0xFFFF */ + unsigned short e_ss; /* Initial (relative) SS value, 0x0 */ + unsigned short e_sp; /* Initial SP value, 0xb8 */ + unsigned short e_csum; /* Checksum, 0x0 */ + unsigned short e_ip; /* Initial IP value, 0x0 */ + unsigned short e_cs; /* Initial (relative) CS value, 0x0 */ + unsigned short e_lfarlc; /* File address of relocation table, 0x40 */ + unsigned short e_ovno; /* Overlay number, 0x0 */ + unsigned short e_res[4]; /* Reserved words, all 0x0 */ + unsigned short e_oemid; /* OEM identifier (for e_oeminfo), 0x0 */ + unsigned short e_oeminfo; /* OEM information; e_oemid specific, 0x0 */ + unsigned short e_res2[10]; /* Reserved words, all 0x0 */ + bfd_vma e_lfanew; /* File address of new exe header, 0x80 */ + unsigned long dos_message[16]; /* text which always follows dos header */ + bfd_vma nt_signature; /* required NT signature, 0x4550 */ +}; + +struct internal_filehdr +{ + struct internal_extra_pe_filehdr pe; + + /* Standard coff internal info. */ + unsigned short f_magic; /* magic number */ + unsigned short f_nscns; /* number of sections */ + long f_timdat; /* time & date stamp */ + bfd_vma f_symptr; /* file pointer to symtab */ + long f_nsyms; /* number of symtab entries */ + unsigned short f_opthdr; /* sizeof(optional hdr) */ + unsigned short f_flags; /* flags */ + unsigned short f_target_id; /* (TI COFF specific) */ +}; + + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR16WR file is 16-bit little-endian + F_AR32WR file is 32-bit little-endian + F_AR32W file is 32-bit big-endian + F_DYNLOAD rs/6000 aix: dynamically loadable w/imports & exports + F_SHROBJ rs/6000 aix: file is a shared object + F_DLL PE format DLL. */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) +#define F_AR16WR (0x0080) +#define F_AR32WR (0x0100) +#define F_AR32W (0x0200) +#define F_DYNLOAD (0x1000) +#define F_SHROBJ (0x2000) +#define F_DLL (0x2000) + +/* Extra structure which is used in the optional header. */ +typedef struct _IMAGE_DATA_DIRECTORY +{ + bfd_vma VirtualAddress; + long Size; +} IMAGE_DATA_DIRECTORY; +#define IMAGE_NUMBEROF_DIRECTORY_ENTRIES 16 + +/* Default image base for NT. */ +#define NT_EXE_IMAGE_BASE 0x400000 +#define NT_DLL_IMAGE_BASE 0x10000000 + +/* Default image base for BeOS. */ +#define BEOS_EXE_IMAGE_BASE 0x80000000 +#define BEOS_DLL_IMAGE_BASE 0x10000000 + +/* Extra stuff in a PE aouthdr */ + +#define PE_DEF_SECTION_ALIGNMENT 0x1000 +#ifndef PE_DEF_FILE_ALIGNMENT +# define PE_DEF_FILE_ALIGNMENT 0x200 +#endif + +struct internal_extra_pe_aouthdr +{ + /* PE stuff */ + bfd_vma ImageBase; /* address of specific location in memory that + file is located, NT default 0x10000 */ + + bfd_vma SectionAlignment; /* section alignment default 0x1000 */ + bfd_vma FileAlignment; /* file alignment default 0x200 */ + short MajorOperatingSystemVersion; /* minimum version of the operating */ + short MinorOperatingSystemVersion; /* system req'd for exe, default to 1*/ + short MajorImageVersion; /* user defineable field to store version of */ + short MinorImageVersion; /* exe or dll being created, default to 0 */ + short MajorSubsystemVersion; /* minimum subsystem version required to */ + short MinorSubsystemVersion; /* run exe; default to 3.1 */ + long Reserved1; /* seems to be 0 */ + long SizeOfImage; /* size of memory to allocate for prog */ + long SizeOfHeaders; /* size of PE header and section table */ + long CheckSum; /* set to 0 */ + short Subsystem; + + /* type of subsystem exe uses for user interface, + possible values: + 1 - NATIVE Doesn't require a subsystem + 2 - WINDOWS_GUI runs in Windows GUI subsystem + 3 - WINDOWS_CUI runs in Windows char sub. (console app) + 5 - OS2_CUI runs in OS/2 character subsystem + 7 - POSIX_CUI runs in Posix character subsystem */ + short DllCharacteristics; /* flags for DLL init, use 0 */ + bfd_vma SizeOfStackReserve; /* amount of memory to reserve */ + bfd_vma SizeOfStackCommit; /* amount of memory initially committed for + initial thread's stack, default is 0x1000 */ + bfd_vma SizeOfHeapReserve; /* amount of virtual memory to reserve and */ + bfd_vma SizeOfHeapCommit; /* commit, don't know what to defaut it to */ + long LoaderFlags; /* can probably set to 0 */ + long NumberOfRvaAndSizes; /* number of entries in next entry, 16 */ + IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; +}; + +/********************** AOUT "OPTIONAL HEADER" **********************/ +struct internal_aouthdr +{ + short magic; /* type of file */ + short vstamp; /* version stamp */ + bfd_vma tsize; /* text size in bytes, padded to FW bdry*/ + bfd_vma dsize; /* initialized data " " */ + bfd_vma bsize; /* uninitialized data " " */ + bfd_vma entry; /* entry pt. */ + bfd_vma text_start; /* base of text used for this file */ + bfd_vma data_start; /* base of data used for this file */ + + /* i960 stuff */ + unsigned long tagentries; /* number of tag entries to follow */ + + /* RS/6000 stuff */ + bfd_vma o_toc; /* address of TOC */ + short o_snentry; /* section number for entry point */ + short o_sntext; /* section number for text */ + short o_sndata; /* section number for data */ + short o_sntoc; /* section number for toc */ + short o_snloader; /* section number for loader section */ + short o_snbss; /* section number for bss */ + short o_algntext; /* max alignment for text */ + short o_algndata; /* max alignment for data */ + short o_modtype; /* Module type field, 1R,RE,RO */ + short o_cputype; /* Encoded CPU type */ + bfd_vma o_maxstack; /* max stack size allowed. */ + bfd_vma o_maxdata; /* max data size allowed. */ + + /* ECOFF stuff */ + bfd_vma bss_start; /* Base of bss section. */ + bfd_vma gp_value; /* GP register value. */ + unsigned long gprmask; /* General registers used. */ + unsigned long cprmask[4]; /* Coprocessor registers used. */ + unsigned long fprmask; /* Floating pointer registers used. */ + + /* Apollo stuff */ + long o_inlib; /* inlib data */ + long o_sri; /* Static Resource Information */ + long vid[2]; /* Version id */ + + struct internal_extra_pe_aouthdr pe; +}; + +/********************** STORAGE CLASSES **********************/ + +/* This used to be defined as -1, but now n_sclass is unsigned. */ +#define C_EFCN 0xff /* physical end of function */ +#define C_NULL 0 +#define C_AUTO 1 /* automatic variable */ +#define C_EXT 2 /* external symbol */ +#define C_STAT 3 /* static */ +#define C_REG 4 /* register variable */ +#define C_EXTDEF 5 /* external definition */ +#define C_LABEL 6 /* label */ +#define C_ULABEL 7 /* undefined label */ +#define C_MOS 8 /* member of structure */ +#define C_ARG 9 /* function argument */ +#define C_STRTAG 10 /* structure tag */ +#define C_MOU 11 /* member of union */ +#define C_UNTAG 12 /* union tag */ +#define C_TPDEF 13 /* type definition */ +#define C_USTATIC 14 /* undefined static */ +#define C_ENTAG 15 /* enumeration tag */ +#define C_MOE 16 /* member of enumeration */ +#define C_REGPARM 17 /* register parameter */ +#define C_FIELD 18 /* bit field */ +#define C_AUTOARG 19 /* auto argument */ +#define C_LASTENT 20 /* dummy entry (end of block) */ +#define C_BLOCK 100 /* ".bb" or ".eb" */ +#define C_FCN 101 /* ".bf" or ".ef" */ +#define C_EOS 102 /* end of structure */ +#define C_FILE 103 /* file name */ +#define C_LINE 104 /* line # reformatted as symbol table entry */ +#define C_ALIAS 105 /* duplicate tag */ +#define C_HIDDEN 106 /* ext symbol in dmert public lib */ + +#if defined _AIX52 || defined AIX_WEAK_SUPPORT +#define C_WEAKEXT 111 /* weak symbol -- AIX standard. */ +#else +#define C_WEAKEXT 127 /* weak symbol -- GNU extension. */ +#endif + +/* New storage classes for TI COFF */ +#define C_UEXT 19 /* Tentative external definition */ +#define C_STATLAB 20 /* Static load time label */ +#define C_EXTLAB 21 /* External load time label */ +#define C_SYSTEM 23 /* System Wide variable */ + +/* New storage classes for WINDOWS_NT */ +#define C_SECTION 104 /* section name */ +#define C_NT_WEAK 105 /* weak external */ + + /* New storage classes for 80960 */ + +/* C_LEAFPROC is obsolete. Use C_LEAFEXT or C_LEAFSTAT */ +#define C_LEAFPROC 108 /* Leaf procedure, "call" via BAL */ + +#define C_SCALL 107 /* Procedure reachable via system call */ +#define C_LEAFEXT 108 /* External leaf */ +#define C_LEAFSTAT 113 /* Static leaf */ +#define C_OPTVAR 109 /* Optimized variable */ +#define C_DEFINE 110 /* Preprocessor #define */ +#define C_PRAGMA 111 /* Advice to compiler or linker */ +#define C_SEGMENT 112 /* 80960 segment name */ + + /* Storage classes for m88k */ +#define C_SHADOW 107 /* shadow symbol */ +#define C_VERSION 108 /* coff version symbol */ + + /* New storage classes for RS/6000 */ +#define C_HIDEXT 107 /* Un-named external symbol */ +#define C_BINCL 108 /* Marks beginning of include file */ +#define C_EINCL 109 /* Marks ending of include file */ + + /* storage classes for stab symbols for RS/6000 */ +#define C_GSYM (0x80) +#define C_LSYM (0x81) +#define C_PSYM (0x82) +#define C_RSYM (0x83) +#define C_RPSYM (0x84) +#define C_STSYM (0x85) +#define C_TCSYM (0x86) +#define C_BCOMM (0x87) +#define C_ECOML (0x88) +#define C_ECOMM (0x89) +#define C_DECL (0x8c) +#define C_ENTRY (0x8d) +#define C_FUN (0x8e) +#define C_BSTAT (0x8f) +#define C_ESTAT (0x90) + +/* Storage classes for Thumb symbols */ +#define C_THUMBEXT (128 + C_EXT) /* 130 */ +#define C_THUMBSTAT (128 + C_STAT) /* 131 */ +#define C_THUMBLABEL (128 + C_LABEL) /* 134 */ +#define C_THUMBEXTFUNC (C_THUMBEXT + 20) /* 150 */ +#define C_THUMBSTATFUNC (C_THUMBSTAT + 20) /* 151 */ + +/********************** SECTION HEADER **********************/ + +#define SCNNMLEN (8) + +struct internal_scnhdr +{ + char s_name[SCNNMLEN]; /* section name */ + + /* Physical address, aliased s_nlib. + In the pei format, this field is the virtual section size + (the size of the section after being loaded int memory), + NOT the physical address. */ + bfd_vma s_paddr; + + bfd_vma s_vaddr; /* virtual address */ + bfd_vma s_size; /* section size */ + bfd_vma s_scnptr; /* file ptr to raw data for section */ + bfd_vma s_relptr; /* file ptr to relocation */ + bfd_vma s_lnnoptr; /* file ptr to line numbers */ + unsigned long s_nreloc; /* number of relocation entries */ + unsigned long s_nlnno; /* number of line number entries*/ + long s_flags; /* flags */ + long s_align; /* used on I960 */ + unsigned char s_page; /* TI COFF load page */ +}; + +/* s_flags "type". */ +#define STYP_REG (0x0000) /* "regular": allocated, relocated, loaded */ +#define STYP_DSECT (0x0001) /* "dummy": relocated only*/ +#define STYP_NOLOAD (0x0002) /* "noload": allocated, relocated, not loaded */ +#define STYP_GROUP (0x0004) /* "grouped": formed of input sections */ +#define STYP_PAD (0x0008) /* "padding": not allocated, not relocated, loaded */ +#define STYP_COPY (0x0010) /* "copy": for decision function used by field update; not allocated, not relocated, + loaded; reloc & lineno entries processed normally */ +#define STYP_TEXT (0x0020) /* section contains text only */ +#define S_SHRSEG (0x0020) /* In 3b Update files (output of ogen), sections which appear in SHARED segments of the Pfile + will have the S_SHRSEG flag set by ogen, to inform dufr that updating 1 copy of the proc. will + update all process invocations. */ +#define STYP_DATA (0x0040) /* section contains data only */ +#define STYP_BSS (0x0080) /* section contains bss only */ +#define S_NEWFCN (0x0100) /* In a minimal file or an update file, a new function (as compared with a replaced function) */ +#define STYP_INFO (0x0200) /* comment: not allocated not relocated, not loaded */ +#define STYP_OVER (0x0400) /* overlay: relocated not allocated or loaded */ +#define STYP_LIB (0x0800) /* for .lib: same as INFO */ +#define STYP_MERGE (0x2000) /* merge section -- combines with text, data or bss sections only */ +#define STYP_REVERSE_PAD (0x4000) /* section will be padded with no-op instructions + wherever padding is necessary and there is a + word of contiguous bytes beginning on a word + boundary. */ + +#define STYP_LIT 0x8020 /* Literal data (like STYP_TEXT) */ + + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + Line numbers are grouped on a per function basis; first entry in a function + grouping will have l_lnno = 0 and in place of physical address will be the + symbol table index of the function name. */ + +struct internal_lineno +{ + union + { + bfd_signed_vma l_symndx; /* function name symbol index, iff l_lnno == 0*/ + bfd_signed_vma l_paddr; /* (physical) address of line number */ + } l_addr; + unsigned long l_lnno; /* line number */ +}; + +/********************** SYMBOLS **********************/ + +#define SYMNMLEN 8 /* # characters in a symbol name */ +#define FILNMLEN 14 /* # characters in a file name */ +#define DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct internal_syment +{ + union + { + char _n_name[SYMNMLEN]; /* old COFF version */ + struct + { + long _n_zeroes; /* new == 0 */ + long _n_offset; /* offset into string table */ + } _n_n; + char *_n_nptr[2]; /* allows for overlaying */ + } _n; + bfd_vma n_value; /* value of symbol */ + short n_scnum; /* section number */ + unsigned short n_flags; /* copy of flags from filhdr */ + unsigned short n_type; /* type and derived type */ + unsigned char n_sclass; /* storage class */ + unsigned char n_numaux; /* number of aux. entries */ +}; + +#define n_name _n._n_name +#define n_zeroes _n._n_n._n_zeroes +#define n_offset _n._n_n._n_offset + +/* Relocatable symbols have number of the section in which they are defined, + or one of the following: */ + +#define N_UNDEF ((short)0) /* undefined symbol */ +#define N_ABS ((short)-1) /* value of symbol is absolute */ +#define N_DEBUG ((short)-2) /* debugging symbol -- value is meaningless */ +#define N_TV ((short)-3) /* indicates symbol needs preload transfer vector */ +#define P_TV ((short)-4) /* indicates symbol needs postload transfer vector*/ + +/* Type of a symbol, in low N bits of the word. */ + +#define T_NULL 0 +#define T_VOID 1 /* function argument (only used by compiler) */ +#define T_CHAR 2 /* character */ +#define T_SHORT 3 /* short integer */ +#define T_INT 4 /* integer */ +#define T_LONG 5 /* long integer */ +#define T_FLOAT 6 /* floating point */ +#define T_DOUBLE 7 /* double word */ +#define T_STRUCT 8 /* structure */ +#define T_UNION 9 /* union */ +#define T_ENUM 10 /* enumeration */ +#define T_MOE 11 /* member of enumeration*/ +#define T_UCHAR 12 /* unsigned character */ +#define T_USHORT 13 /* unsigned short */ +#define T_UINT 14 /* unsigned integer */ +#define T_ULONG 15 /* unsigned long */ +#define T_LNGDBL 16 /* long double */ + +/* Derived types, in n_type. */ + +#define DT_NON (0) /* no derived type */ +#define DT_PTR (1) /* pointer */ +#define DT_FCN (2) /* function */ +#define DT_ARY (3) /* array */ + +#define BTYPE(x) ((x) & N_BTMASK) +#define DTYPE(x) (((x) & N_TMASK) >> N_BTSHFT) + +#define ISPTR(x) \ + (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_PTR << N_BTSHFT)) +#define ISFCN(x) \ + (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_FCN << N_BTSHFT)) +#define ISARY(x) \ + (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_ARY << N_BTSHFT)) +#define ISTAG(x) \ + ((x) == C_STRTAG || (x) == C_UNTAG || (x) == C_ENTAG) +#define DECREF(x) \ + ((((x) >> N_TSHIFT) & ~ N_BTMASK) | ((x) & N_BTMASK)) + +union internal_auxent +{ + struct + { + + union + { + long l; /* str, un, or enum tag indx */ + struct coff_ptr_struct *p; + } x_tagndx; + + union + { + struct + { + unsigned short x_lnno; /* declaration line number */ + unsigned short x_size; /* str/union/array size */ + } x_lnsz; + long x_fsize; /* size of function */ + } x_misc; + + union + { + struct + { /* if ISFCN, tag, or .bb */ + bfd_signed_vma x_lnnoptr; /* ptr to fcn line # */ + union + { /* entry ndx past block end */ + long l; + struct coff_ptr_struct *p; + } x_endndx; + } x_fcn; + + struct + { /* if ISARY, up to 4 dimen. */ + unsigned short x_dimen[DIMNUM]; + } x_ary; + } x_fcnary; + + unsigned short x_tvndx; /* tv index */ + } x_sym; + + union + { + char x_fname[FILNMLEN]; + struct + { + long x_zeroes; + long x_offset; + } x_n; + } x_file; + + struct + { + long x_scnlen; /* section length */ + unsigned short x_nreloc; /* # relocation entries */ + unsigned short x_nlinno; /* # line numbers */ + unsigned long x_checksum; /* section COMDAT checksum for PE */ + unsigned short x_associated; /* COMDAT associated section index for PE */ + unsigned char x_comdat; /* COMDAT selection number for PE */ + } x_scn; + + struct + { + long x_tvfill; /* tv fill value */ + unsigned short x_tvlen; /* length of .tv */ + unsigned short x_tvran[2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + /****************************************** + * RS/6000-specific auxent - last auxent for every external symbol + ******************************************/ + struct + { + union + { /* csect length or enclosing csect */ + bfd_signed_vma l; + struct coff_ptr_struct *p; + } x_scnlen; + long x_parmhash; /* parm type hash index */ + unsigned short x_snhash; /* sect num with parm hash */ + unsigned char x_smtyp; /* symbol align and type */ + /* 0-4 - Log 2 of alignment */ + /* 5-7 - symbol type */ + unsigned char x_smclas; /* storage mapping class */ + long x_stab; /* dbx stab info index */ + unsigned short x_snstab; /* sect num with dbx stab */ + } x_csect; /* csect definition information */ + +/* x_smtyp values: */ + +#define SMTYP_ALIGN(x) ((x) >> 3) /* log2 of alignment */ +#define SMTYP_SMTYP(x) ((x) & 0x7) /* symbol type */ +/* Symbol type values: */ +#define XTY_ER 0 /* External reference */ +#define XTY_SD 1 /* Csect definition */ +#define XTY_LD 2 /* Label definition */ +#define XTY_CM 3 /* .BSS */ +#define XTY_EM 4 /* Error message */ +#define XTY_US 5 /* "Reserved for internal use" */ + +/* x_smclas values: */ + +#define XMC_PR 0 /* Read-only program code */ +#define XMC_RO 1 /* Read-only constant */ +#define XMC_DB 2 /* Read-only debug dictionary table */ +#define XMC_TC 3 /* Read-write general TOC entry */ +#define XMC_UA 4 /* Read-write unclassified */ +#define XMC_RW 5 /* Read-write data */ +#define XMC_GL 6 /* Read-only global linkage */ +#define XMC_XO 7 /* Read-only extended operation */ +#define XMC_SV 8 /* Read-only supervisor call */ +#define XMC_BS 9 /* Read-write BSS */ +#define XMC_DS 10 /* Read-write descriptor csect */ +#define XMC_UC 11 /* Read-write unnamed Fortran common */ +#define XMC_TI 12 /* Read-only traceback index csect */ +#define XMC_TB 13 /* Read-only traceback table csect */ +/* 14 ??? */ +#define XMC_TC0 15 /* Read-write TOC anchor */ +#define XMC_TD 16 /* Read-write data in TOC */ + + /****************************************** + * I960-specific *2nd* aux. entry formats + ******************************************/ + struct + { + /* This is a very old typo that keeps getting propagated. */ +#define x_stdindx x_stindx + long x_stindx; /* sys. table entry */ + } x_sc; /* system call entry */ + + struct + { + unsigned long x_balntry; /* BAL entry point */ + } x_bal; /* BAL-callable function */ + + struct + { + unsigned long x_timestamp; /* time stamp */ + char x_idstring[20]; /* producer identity string */ + } x_ident; /* Producer ident info */ + +}; + +/********************** RELOCATION DIRECTIVES **********************/ + +struct internal_reloc +{ + bfd_vma r_vaddr; /* Virtual address of reference */ + long r_symndx; /* Index into symbol table */ + unsigned short r_type; /* Relocation type */ + unsigned char r_size; /* Used by RS/6000 and ECOFF */ + unsigned char r_extern; /* Used by ECOFF */ + unsigned long r_offset; /* Used by Alpha ECOFF, SPARC, others */ +}; + +#define R_DIR16 1 +#define R_REL24 5 +#define R_DIR32 6 +#define R_IMAGEBASE 7 +#define R_SECREL32 11 +#define R_RELBYTE 15 +#define R_RELWORD 16 +#define R_RELLONG 17 +#define R_PCRBYTE 18 +#define R_PCRWORD 19 +#define R_PCRLONG 20 +#define R_PCR24 21 +#define R_IPRSHORT 24 +#define R_IPRLONG 26 +#define R_GETSEG 29 +#define R_GETPA 30 +#define R_TAGWORD 31 +#define R_JUMPTARG 32 /* strange 29k 00xx00xx reloc */ +#define R_PARTLS16 32 +#define R_PARTMS8 33 + +#define R_PCR16L 128 +#define R_PCR26L 129 +#define R_VRT16 130 +#define R_HVRT16 131 +#define R_LVRT16 132 +#define R_VRT32 133 + + +/* This reloc identifies mov.b instructions with a 16bit absolute + address. The linker tries to turn insns with this reloc into + an absolute 8-bit address. */ +#define R_MOV16B1 0x41 + +/* This reloc identifies mov.b instructions which had a 16bit + absolute address which have been shortened into a 8-bit + absolute address. */ +#define R_MOV16B2 0x42 + +/* This reloc identifies jmp insns with a 16bit target address; + the linker tries to turn these insns into bra insns with + an 8bit pc-relative target. */ +#define R_JMP1 0x43 + +/* This reloc identifies a bra with an 8-bit pc-relative + target that was formerly a jmp insn with a 16bit target. */ +#define R_JMP2 0x44 + +/* ??? */ +#define R_RELLONG_NEG 0x45 + +/* This reloc identifies jmp insns with a 24bit target address; + the linker tries to turn these insns into bra insns with + an 8bit pc-relative target. */ +#define R_JMPL1 0x46 + +/* This reloc identifies a bra with an 8-bit pc-relative + target that was formerly a jmp insn with a 24bit target. */ +#define R_JMPL2 0x47 + +/* This reloc identifies mov.b instructions with a 24bit absolute + address. The linker tries to turn insns with this reloc into + an absolute 8-bit address. */ + +#define R_MOV24B1 0x48 + +/* This reloc identifies mov.b instructions which had a 24bit + absolute address which have been shortened into a 8-bit + absolute address. */ +#define R_MOV24B2 0x49 + +/* An h8300 memory indirect jump/call. Forces the address of the jump/call + target into the function vector (in page zero), and the address of the + vector entry to be placed in the jump/call instruction. */ +#define R_MEM_INDIRECT 0x4a + +/* This reloc identifies a 16bit pc-relative branch target which was + shortened into an 8bit pc-relative branch target. */ +#define R_PCRWORD_B 0x4b + +/* This reloc identifies mov.[wl] instructions with a 32/24 bit + absolute address; the linker may turn this into a mov.[wl] + insn with a 16bit absolute address. */ +#define R_MOVL1 0x4c + +/* This reloc identifies mov.[wl] insns which formerly had + a 32/24bit absolute address and now have a 16bit absolute address. */ +#define R_MOVL2 0x4d + +/* This reloc identifies a bCC:8 which will have it's condition + inverted and its target redirected to the target of the branch + in the following insn. */ +#define R_BCC_INV 0x4e + +/* This reloc identifies a jmp instruction that has been deleted. */ +#define R_JMP_DEL 0x4f + +/* Z8k modes */ +#define R_IMM16 0x01 /* 16 bit abs */ +#define R_JR 0x02 /* jr 8 bit disp */ +#define R_IMM4L 0x23 /* low nibble */ +#define R_IMM8 0x22 /* 8 bit abs */ +#define R_IMM32 R_RELLONG /* 32 bit abs */ +#define R_CALL R_DA /* Absolute address which could be a callr */ +#define R_JP R_DA /* Absolute address which could be a jp */ +#define R_REL16 0x04 /* 16 bit PC rel */ +#define R_CALLR 0x05 /* callr 12 bit disp */ +#define R_SEG 0x10 /* set if in segmented mode */ +#define R_IMM4H 0x24 /* high nibble */ +#define R_DISP7 0x25 /* djnz displacement */ + +/* H8500 modes */ + +#define R_H8500_IMM8 1 /* 8 bit immediate */ +#define R_H8500_IMM16 2 /* 16 bit immediate */ +#define R_H8500_PCREL8 3 /* 8 bit pcrel */ +#define R_H8500_PCREL16 4 /* 16 bit pcrel */ +#define R_H8500_HIGH8 5 /* high 8 bits of 24 bit address */ +#define R_H8500_LOW16 7 /* low 16 bits of 24 bit immediate */ +#define R_H8500_IMM24 6 /* 24 bit immediate */ +#define R_H8500_IMM32 8 /* 32 bit immediate */ +#define R_H8500_HIGH16 9 /* high 16 bits of 32 bit immediate */ + +/* W65 modes */ + +#define R_W65_ABS8 1 /* addr & 0xff */ +#define R_W65_ABS16 2 /* addr & 0xffff */ +#define R_W65_ABS24 3 /* addr & 0xffffff */ + +#define R_W65_ABS8S8 4 /* (addr >> 8) & 0xff */ +#define R_W65_ABS8S16 5 /* (addr >> 16) & 0xff */ + +#define R_W65_ABS16S8 6 /* (addr >> 8) & 0ffff */ +#define R_W65_ABS16S16 7 /* (addr >> 16) & 0ffff */ + +#define R_W65_PCR8 8 +#define R_W65_PCR16 9 + +#define R_W65_DP 10 /* direct page 8 bits only */ + +#endif /* GNU_COFF_INTERNAL_H */ diff --git a/include/coff/m68k.h b/include/coff/m68k.h new file mode 100644 index 000000000..5c5f758f5 --- /dev/null +++ b/include/coff/m68k.h @@ -0,0 +1,81 @@ +/* coff information for M68K + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef GNU_COFF_M68K_H +#define GNU_COFF_M68K_H 1 + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Motorola 68000/68008/68010/68020 */ +#define MC68MAGIC 0520 +#define MC68KWRMAGIC 0520 /* writeable text segments */ +#define MC68TVMAGIC 0521 +#define MC68KROMAGIC 0521 /* readonly shareable text segments */ +#define MC68KPGMAGIC 0522 /* demand paged text segments */ +#define M68MAGIC 0210 +#define M68TVMAGIC 0211 + +/* This is the magic of the Bull dpx/2 */ +#define MC68KBCSMAGIC 0526 + +/* This is Lynx's all-platform magic number for executables. */ + +#define LYNXCOFFMAGIC 0415 + +#define OMAGIC M68MAGIC + +/* This intentionally does not include MC68KBCSMAGIC; it only includes + magic numbers which imply that names do not have underscores. */ +#define M68KBADMAG(x) (((x).f_magic != MC68MAGIC) \ + && ((x).f_magic != MC68KWRMAGIC) \ + && ((x).f_magic != MC68TVMAGIC) \ + && ((x).f_magic != MC68KROMAGIC) \ + && ((x).f_magic != MC68KPGMAGIC) \ + && ((x).f_magic != M68MAGIC) \ + && ((x).f_magic != M68TVMAGIC) \ + && ((x).f_magic != LYNXCOFFMAGIC)) + +/* Magic numbers for the a.out header. */ + +#define PAGEMAGICEXECSWAPPED 0407 /* executable (swapped) */ +#define PAGEMAGICPEXECSWAPPED 0410 /* pure executable (swapped) */ +#define PAGEMAGICPEXECTSHLIB 0443 /* pure executable (target shared library) */ +#define PAGEMAGICPEXECPAGED 0413 /* pure executable (paged) */ + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +#ifdef M68K_COFF_OFFSET + char r_offset[4]; +#endif +}; + +#define RELOC struct external_reloc + +#ifdef M68K_COFF_OFFSET +#define RELSZ 14 +#else +#define RELSZ 10 +#endif + +#endif /* GNU_COFF_M68K_H */ diff --git a/include/coff/m88k.h b/include/coff/m88k.h new file mode 100644 index 000000000..331d97c92 --- /dev/null +++ b/include/coff/m88k.h @@ -0,0 +1,196 @@ +/* coff information for 88k bcs + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DO_NOT_DEFINE_SCNHDR +#define L_LNNO_SIZE 4 +#define DO_NOT_DEFINE_SYMENT +#define DO_NOT_DEFINE_AUXENT +#include "coff/external.h" + +#define MC88MAGIC 0540 /* 88k BCS executable */ +#define MC88DMAGIC 0541 /* DG/UX executable */ +#define MC88OMAGIC 0555 /* Object file */ + +#define MC88BADMAG(x) (((x).f_magic != MC88MAGIC) \ + && ((x).f_magic != MC88DMAGIC) \ + && ((x).f_magic != MC88OMAGIC)) + +#define PAGEMAGIC3 0414 /* Split i&d, zero mapped */ +#define PAGEMAGICBCS 0413 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[4]; /* number of relocation entries */ + char s_nlnno[4]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 44 + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _COMMENT ".comment" + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + + } e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; + char pad2[2]; +}; + +#define N_BTMASK 017 +#define N_TMASK 060 +#define N_BTSHFT 4 +#define N_TSHIFT 2 + +/* Note that this isn't the same shape as other coffs */ +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + /* 4 */ + + union + { + char x_fsize[4]; /* size of function */ + + struct + { + char x_lnno[4]; /* declaration line number */ + char x_size[4]; /* str/union/array size */ + } x_lnsz; + + } x_misc; + + /* 12 */ + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + /* 20 */ + + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[4]; /* # relocation entries */ + char x_nlinno[4]; /* # line numbers */ + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +}; + +#define GET_LNSZ_SIZE(abfd, ext) \ + H_GET_32 (abfd, ext->x_sym.x_misc.x_lnsz.x_size) +#define GET_LNSZ_LNNO(abfd, ext) \ + H_GET_32 (abfd, ext->x_sym.x_misc.x_lnsz.x_lnno) +#define PUT_LNSZ_LNNO(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_sym.x_misc.x_lnsz.x_lnno) +#define PUT_LNSZ_SIZE(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_sym.x_misc.x_lnsz.x_size) +#define GET_SCN_NRELOC(abfd, ext) \ + H_GET_32 (abfd, ext->x_scn.x_nreloc) +#define GET_SCN_NLINNO(abfd, ext) \ + H_GET_32 (abfd, ext->x_scn.x_nlinno) +#define PUT_SCN_NRELOC(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_scn.x_nreloc) +#define PUT_SCN_NLINNO(abfd, in, ext) \ + H_PUT_32 (abfd,in, ext->x_scn.x_nlinno) + +#define SYMENT struct external_syment +#define SYMESZ 20 +#define AUXENT union external_auxent +#define AUXESZ 20 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_offset[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 12 + +#define NO_TVNDX diff --git a/include/coff/mcore.h b/include/coff/mcore.h new file mode 100644 index 000000000..980cf133d --- /dev/null +++ b/include/coff/mcore.h @@ -0,0 +1,71 @@ +/* Motorola MCore support for BFD. + Copyright 1999 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MCore COFF/PE ABI. */ + +#ifndef _COFF_MORE_H +#define _COFF_MORE_H + +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +#define MCOREMAGIC 0xb00 /* I just made this up */ + +#define MCOREBADMAG(x) (((x).f_magic != MCOREMAGIC)) + +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +#define IMAGE_REL_MCORE_ABSOLUTE 0x0000 +#define IMAGE_REL_MCORE_ADDR32 0x0001 +#define IMAGE_REL_MCORE_PCREL_IMM8BY4 0x0002 +#define IMAGE_REL_MCORE_PCREL_IMM11BY2 0x0003 +#define IMAGE_REL_MCORE_PCREL_IMM4BY2 0x0004 +#define IMAGE_REL_MCORE_PCREL_32 0x0005 +#define IMAGE_REL_MCORE_PCREL_JSR_IMM11BY2 0x0006 +#define IMAGE_REL_MCORE_RVA 0x0007 + +#define PEMCORE + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* From winnt.h */ +#define IMAGE_NT_OPTIONAL_HDR_MAGIC 0x10b + +/* Define some NT default values. */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +struct external_reloc +{ + char r_vaddr [4]; + char r_symndx [4]; + char r_type [2]; + char r_offset [4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 + +#endif /* __COFF_MCORE_H */ diff --git a/include/coff/mips.h b/include/coff/mips.h new file mode 100644 index 000000000..bec8da2d3 --- /dev/null +++ b/include/coff/mips.h @@ -0,0 +1,343 @@ +/* ECOFF support on MIPS machines. + coff/ecoff.h must be included before this file. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DO_NOT_DEFINE_AOUTHDR +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +/* Magic numbers are defined in coff/ecoff.h. */ +#define MIPS_ECOFF_BADMAG(x) (((x).f_magic!=MIPS_MAGIC_1) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE) &&\ + ((x).f_magic!=MIPS_MAGIC_BIG) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE2) && \ + ((x).f_magic!=MIPS_MAGIC_BIG2) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE3) && \ + ((x).f_magic!=MIPS_MAGIC_BIG3)) + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct external_aouthdr +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char tsize[4]; /* text size in bytes, padded to FW bdry*/ + unsigned char dsize[4]; /* initialized data " " */ + unsigned char bsize[4]; /* uninitialized data " " */ + unsigned char entry[4]; /* entry pt. */ + unsigned char text_start[4]; /* base of text used for this file */ + unsigned char data_start[4]; /* base of data used for this file */ + unsigned char bss_start[4]; /* base of bss used for this file */ + unsigned char gprmask[4]; /* ?? */ + unsigned char cprmask[4][4]; /* ?? */ + unsigned char gp_value[4]; /* value for gp register */ +} AOUTHDR; + +/* compute size of a header */ + +#define AOUTSZ 56 +#define AOUTHDRSZ 56 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc + { + unsigned char r_vaddr[4]; + unsigned char r_bits[4]; + }; + +#define RELOC struct external_reloc +#define RELSZ 8 + +/* MIPS ECOFF uses a packed 8 byte format for relocs. These constants + are used to unpack the r_bits field. */ + +#define RELOC_BITS0_SYMNDX_SH_LEFT_BIG 16 +#define RELOC_BITS0_SYMNDX_SH_LEFT_LITTLE 0 + +#define RELOC_BITS1_SYMNDX_SH_LEFT_BIG 8 +#define RELOC_BITS1_SYMNDX_SH_LEFT_LITTLE 8 + +#define RELOC_BITS2_SYMNDX_SH_LEFT_BIG 0 +#define RELOC_BITS2_SYMNDX_SH_LEFT_LITTLE 16 + +/* Originally, ECOFF used four bits for the reloc type and had three + reserved bits. Irix 4 added another bit for the reloc type, which + was easy because it was big endian and one of the spare bits became + the new most significant bit. To make this also work for little + endian ECOFF, we need to wrap one of the reserved bits around to + become the most significant bit of the reloc type. */ +#define RELOC_BITS3_TYPE_BIG 0x3E +#define RELOC_BITS3_TYPE_SH_BIG 1 +#define RELOC_BITS3_TYPE_LITTLE 0x78 +#define RELOC_BITS3_TYPE_SH_LITTLE 3 +#define RELOC_BITS3_TYPEHI_LITTLE 0x04 +#define RELOC_BITS3_TYPEHI_SH_LITTLE 2 + +#define RELOC_BITS3_EXTERN_BIG 0x01 +#define RELOC_BITS3_EXTERN_LITTLE 0x80 + +/* The r_type field in a reloc is one of the following values. I + don't know if any other values can appear. These seem to be all + that occur in the Ultrix 4.2 libraries. */ +#define MIPS_R_IGNORE 0 +#define MIPS_R_REFHALF 1 +#define MIPS_R_REFWORD 2 +#define MIPS_R_JMPADDR 3 +#define MIPS_R_REFHI 4 +#define MIPS_R_REFLO 5 +#define MIPS_R_GPREL 6 +#define MIPS_R_LITERAL 7 + +/* FIXME: This relocation is used (internally only) to represent branches + when assembling. It should never appear in output files, and + be removed. (It used to be used for embedded-PIC support.) */ +#define MIPS_R_PCREL16 12 + +/********************** STABS **********************/ + +#define MIPS_IS_STAB ECOFF_IS_STAB +#define MIPS_MARK_STAB ECOFF_MARK_STAB +#define MIPS_UNMARK_STAB ECOFF_UNMARK_STAB + +/********************** SYMBOLIC INFORMATION **********************/ + +/* Written by John Gilmore. */ + +/* ECOFF uses COFF-like section structures, but its own symbol format. + This file defines the symbol format in fields whose size and alignment + will not vary on different host systems. */ + +/* File header as a set of bytes */ + +struct hdr_ext +{ + unsigned char h_magic[2]; + unsigned char h_vstamp[2]; + unsigned char h_ilineMax[4]; + unsigned char h_cbLine[4]; + unsigned char h_cbLineOffset[4]; + unsigned char h_idnMax[4]; + unsigned char h_cbDnOffset[4]; + unsigned char h_ipdMax[4]; + unsigned char h_cbPdOffset[4]; + unsigned char h_isymMax[4]; + unsigned char h_cbSymOffset[4]; + unsigned char h_ioptMax[4]; + unsigned char h_cbOptOffset[4]; + unsigned char h_iauxMax[4]; + unsigned char h_cbAuxOffset[4]; + unsigned char h_issMax[4]; + unsigned char h_cbSsOffset[4]; + unsigned char h_issExtMax[4]; + unsigned char h_cbSsExtOffset[4]; + unsigned char h_ifdMax[4]; + unsigned char h_cbFdOffset[4]; + unsigned char h_crfd[4]; + unsigned char h_cbRfdOffset[4]; + unsigned char h_iextMax[4]; + unsigned char h_cbExtOffset[4]; +}; + +/* File descriptor external record */ + +struct fdr_ext +{ + unsigned char f_adr[4]; + unsigned char f_rss[4]; + unsigned char f_issBase[4]; + unsigned char f_cbSs[4]; + unsigned char f_isymBase[4]; + unsigned char f_csym[4]; + unsigned char f_ilineBase[4]; + unsigned char f_cline[4]; + unsigned char f_ioptBase[4]; + unsigned char f_copt[4]; + unsigned char f_ipdFirst[2]; + unsigned char f_cpd[2]; + unsigned char f_iauxBase[4]; + unsigned char f_caux[4]; + unsigned char f_rfdBase[4]; + unsigned char f_crfd[4]; + unsigned char f_bits1[1]; + unsigned char f_bits2[3]; + unsigned char f_cbLineOffset[4]; + unsigned char f_cbLine[4]; +}; + +#define FDR_BITS1_LANG_BIG 0xF8 +#define FDR_BITS1_LANG_SH_BIG 3 +#define FDR_BITS1_LANG_LITTLE 0x1F +#define FDR_BITS1_LANG_SH_LITTLE 0 + +#define FDR_BITS1_FMERGE_BIG 0x04 +#define FDR_BITS1_FMERGE_LITTLE 0x20 + +#define FDR_BITS1_FREADIN_BIG 0x02 +#define FDR_BITS1_FREADIN_LITTLE 0x40 + +#define FDR_BITS1_FBIGENDIAN_BIG 0x01 +#define FDR_BITS1_FBIGENDIAN_LITTLE 0x80 + +#define FDR_BITS2_GLEVEL_BIG 0xC0 +#define FDR_BITS2_GLEVEL_SH_BIG 6 +#define FDR_BITS2_GLEVEL_LITTLE 0x03 +#define FDR_BITS2_GLEVEL_SH_LITTLE 0 + +/* We ignore the `reserved' field in bits2. */ + +/* Procedure descriptor external record */ + +struct pdr_ext +{ + unsigned char p_adr[4]; + unsigned char p_isym[4]; + unsigned char p_iline[4]; + unsigned char p_regmask[4]; + unsigned char p_regoffset[4]; + unsigned char p_iopt[4]; + unsigned char p_fregmask[4]; + unsigned char p_fregoffset[4]; + unsigned char p_frameoffset[4]; + unsigned char p_framereg[2]; + unsigned char p_pcreg[2]; + unsigned char p_lnLow[4]; + unsigned char p_lnHigh[4]; + unsigned char p_cbLineOffset[4]; +}; + +/* Runtime procedure table */ + +struct rpdr_ext +{ + unsigned char p_adr[4]; + unsigned char p_regmask[4]; + unsigned char p_regoffset[4]; + unsigned char p_fregmask[4]; + unsigned char p_fregoffset[4]; + unsigned char p_frameoffset[4]; + unsigned char p_framereg[2]; + unsigned char p_pcreg[2]; + unsigned char p_irpss[4]; + unsigned char p_reserved[4]; + unsigned char p_exception_info[4]; +}; + +/* Line numbers */ + +struct line_ext +{ + unsigned char l_line[4]; +}; + +/* Symbol external record */ + +struct sym_ext +{ + unsigned char s_iss[4]; + unsigned char s_value[4]; + unsigned char s_bits1[1]; + unsigned char s_bits2[1]; + unsigned char s_bits3[1]; + unsigned char s_bits4[1]; +}; + +#define SYM_BITS1_ST_BIG 0xFC +#define SYM_BITS1_ST_SH_BIG 2 +#define SYM_BITS1_ST_LITTLE 0x3F +#define SYM_BITS1_ST_SH_LITTLE 0 + +#define SYM_BITS1_SC_BIG 0x03 +#define SYM_BITS1_SC_SH_LEFT_BIG 3 +#define SYM_BITS1_SC_LITTLE 0xC0 +#define SYM_BITS1_SC_SH_LITTLE 6 + +#define SYM_BITS2_SC_BIG 0xE0 +#define SYM_BITS2_SC_SH_BIG 5 +#define SYM_BITS2_SC_LITTLE 0x07 +#define SYM_BITS2_SC_SH_LEFT_LITTLE 2 + +#define SYM_BITS2_RESERVED_BIG 0x10 +#define SYM_BITS2_RESERVED_LITTLE 0x08 + +#define SYM_BITS2_INDEX_BIG 0x0F +#define SYM_BITS2_INDEX_SH_LEFT_BIG 16 +#define SYM_BITS2_INDEX_LITTLE 0xF0 +#define SYM_BITS2_INDEX_SH_LITTLE 4 + +#define SYM_BITS3_INDEX_SH_LEFT_BIG 8 +#define SYM_BITS3_INDEX_SH_LEFT_LITTLE 4 + +#define SYM_BITS4_INDEX_SH_LEFT_BIG 0 +#define SYM_BITS4_INDEX_SH_LEFT_LITTLE 12 + +/* External symbol external record */ + +struct ext_ext +{ + unsigned char es_bits1[1]; + unsigned char es_bits2[1]; + unsigned char es_ifd[2]; + struct sym_ext es_asym; +}; + +#define EXT_BITS1_JMPTBL_BIG 0x80 +#define EXT_BITS1_JMPTBL_LITTLE 0x01 + +#define EXT_BITS1_COBOL_MAIN_BIG 0x40 +#define EXT_BITS1_COBOL_MAIN_LITTLE 0x02 + +#define EXT_BITS1_WEAKEXT_BIG 0x20 +#define EXT_BITS1_WEAKEXT_LITTLE 0x04 + +/* Dense numbers external record */ + +struct dnr_ext +{ + unsigned char d_rfd[4]; + unsigned char d_index[4]; +}; + +/* Relative file descriptor */ + +struct rfd_ext +{ + unsigned char rfd[4]; +}; + +/* Optimizer symbol external record */ + +struct opt_ext +{ + unsigned char o_bits1[1]; + unsigned char o_bits2[1]; + unsigned char o_bits3[1]; + unsigned char o_bits4[1]; + struct rndx_ext o_rndx; + unsigned char o_offset[4]; +}; + +#define OPT_BITS2_VALUE_SH_LEFT_BIG 16 +#define OPT_BITS2_VALUE_SH_LEFT_LITTLE 0 + +#define OPT_BITS3_VALUE_SH_LEFT_BIG 8 +#define OPT_BITS3_VALUE_SH_LEFT_LITTLE 8 + +#define OPT_BITS4_VALUE_SH_LEFT_BIG 0 +#define OPT_BITS4_VALUE_SH_LEFT_LITTLE 16 diff --git a/include/coff/mipspe.h b/include/coff/mipspe.h new file mode 100644 index 000000000..9b4ffab70 --- /dev/null +++ b/include/coff/mipspe.h @@ -0,0 +1,66 @@ +/* coff information for Windows CE with MIPS VR4111 + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +#define MIPS_ARCH_MAGIC_WINCE 0x0166 /* Windows CE - little endian */ +#define MIPS_PE_MAGIC 0x010b + +#define MIPSBADMAG(x) ((x).f_magic != MIPS_ARCH_MAGIC_WINCE) + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + +/* MIPS PE relocation types. */ + +#define MIPS_R_ABSOLUTE 0 /* ignored */ +#define MIPS_R_REFHALF 1 +#define MIPS_R_REFWORD 2 +#define MIPS_R_JMPADDR 3 +#define MIPS_R_REFHI 4 /* PAIR follows */ +#define MIPS_R_REFLO 5 +#define MIPS_R_GPREL 6 +#define MIPS_R_LITERAL 7 /* same as GPREL */ +#define MIPS_R_SECTION 10 +#define MIPS_R_SECREL 11 +#define MIPS_R_SECRELLO 12 +#define MIPS_R_SECRELHI 13 /* PAIR follows */ +#define MIPS_R_RVA 34 /* 0x22 */ +#define MIPS_R_PAIR 37 /* 0x25 - symndx is really a signed 16-bit addend */ diff --git a/include/coff/or32.h b/include/coff/or32.h new file mode 100644 index 000000000..c2797aa90 --- /dev/null +++ b/include/coff/or32.h @@ -0,0 +1,287 @@ +/* COFF specification for OpenRISC 1000. + Copyright (C) 1993-2000, 2002 Free Software Foundation, Inc. + Contributed by David Wood @ New York University. + Modified by Johan Rydberg, <johan.rydberg@netinsight.se> + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef OR32 +# define OR32 +#endif + +/* File Header and related definitions. */ +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/* Magic numbers for OpenRISC 1000. As it is know we use the + numbers for Am29000. + + (AT&T will assign the "real" magic number). */ +#define SIPFBOMAGIC 0572 /* Am29000 (Byte 0 is MSB). */ +#define SIPRBOMAGIC 0573 /* Am29000 (Byte 0 is LSB). */ + +#define OR32_MAGIC_BIG SIPFBOMAGIC +#define OR32_MAGIC_LITTLE SIPRBOMAGIC +#define OR32BADMAG(x) (((x).f_magic!=OR32_MAGIC_BIG) && \ + ((x).f_magic!=OR32_MAGIC_LITTLE)) + +#define OMAGIC OR32_MAGIC_BIG + +/* Optional (a.out) header. */ +typedef struct external_aouthdr +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry */ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} AOUTHDR; + +#define AOUTSZ 28 +#define AOUTHDRSZ 28 + +/* aouthdr magic numbers. */ +#define NMAGIC 0410 /* separate i/d executable. */ +#define SHMAGIC 0406 /* NYU/Ultra3 shared data executable + (writable text). */ + +#define _ETEXT "_etext" + +/* Section header and related definitions. */ +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries */ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* Names of "special" sections: */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _LIT ".lit" + +/* Section types - with additional section type for global + registers which will be relocatable for the OpenRISC 1000. + + In instances where it is necessary for a linker to produce an + output file which contains text or data not based at virtual + address 0, e.g. for a ROM, then the linker should accept + address base information as command input and use PAD sections + to skip over unused addresses. */ +#define STYP_BSSREG 0x1200 /* Global register area (like STYP_INFO) */ +#define STYP_ENVIR 0x2200 /* Environment (like STYP_INFO) */ +#define STYP_ABS 0x4000 /* Absolute (allocated, not reloc, loaded) */ + +/* Relocation information declaration and related definitions: */ +struct external_reloc +{ + char r_vaddr[4]; /* (virtual) address of reference */ + char r_symndx[4]; /* index into symbol table */ + char r_type[2]; /* relocation type */ +}; + +#define RELOC struct external_reloc +#define RELSZ 10 /* sizeof (RELOC) */ + +/* Relocation types for the OpenRISC 1000: */ + +#define R_ABS 0 /* reference is absolute */ +#define R_IREL 030 /* instruction relative (jmp/call) */ +#define R_IABS 031 /* instruction absolute (jmp/call) */ +#define R_ILOHALF 032 /* instruction low half (const) */ +#define R_IHIHALF 033 /* instruction high half (consth) part 1 */ +#define R_IHCONST 034 /* instruction high half (consth) part 2 */ + /* constant offset of R_IHIHALF relocation */ +#define R_BYTE 035 /* relocatable byte value */ +#define R_HWORD 036 /* relocatable halfword value */ +#define R_WORD 037 /* relocatable word value */ + +#define R_IGLBLRC 040 /* instruction global register RC */ +#define R_IGLBLRA 041 /* instruction global register RA */ +#define R_IGLBLRB 042 /* instruction global register RB */ + +/* + NOTE: + All the "I" forms refer to 29000 instruction formats. The linker is + expected to know how the numeric information is split and/or aligned + within the instruction word(s). R_BYTE works for instructions, too. + + If the parameter to a CONSTH instruction is a relocatable type, two + relocation records are written. The first has an r_type of R_IHIHALF + (33 octal) and a normal r_vaddr and r_symndx. The second relocation + record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which + is redundant), and an r_symndx containing the 32-bit constant offset + to the relocation instead of the actual symbol table index. This + second record is always written, even if the constant offset is zero. + The constant fields of the instruction are set to zero. */ + +/* Line number entry declaration and related definitions: */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } + l_addr; + + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 /* sizeof (LINENO) */ + +/* Symbol entry declaration and related definitions: */ +#define E_SYMNMLEN 8 /* Number of characters in a symbol name */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + struct + { + char e_zeroes[4]; + char e_offset[4]; + } + e; + } + e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 + +/* Storage class definitions - new classes for global registers: */ +#define C_GLBLREG 19 /* global register */ +#define C_EXTREG 20 /* external global register */ +#define C_DEFREG 21 /* ext. def. of global register */ + +/* Derived symbol mask/shifts: */ +#define N_BTMASK (0xf) +#define N_BTSHFT (4) +#define N_TMASK (0x30) +#define N_TSHIFT (2) + +/* Auxiliary symbol table entry declaration and related + definitions. */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } + x_lnsz; + + char x_fsize[4]; /* size of function */ + } + x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } + x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } + x_ary; + } + x_fcnary; + + char x_tvndx[2]; /* tv index */ + } + x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } + x_n; + } + x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } + x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } + x_tv; /* info about .tv section + (in auxent of symbol .tv)) */ +}; + +#define AUXENT union external_auxent +#define AUXESZ 18 diff --git a/include/coff/pe.h b/include/coff/pe.h new file mode 100644 index 000000000..363d30737 --- /dev/null +++ b/include/coff/pe.h @@ -0,0 +1,313 @@ +/* pe.h - PE COFF header information + + Copyright 2000, 2001, 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#ifndef _PE_H +#define _PE_H + +/* NT specific file attributes. */ +#define IMAGE_FILE_RELOCS_STRIPPED 0x0001 +#define IMAGE_FILE_EXECUTABLE_IMAGE 0x0002 +#define IMAGE_FILE_LINE_NUMS_STRIPPED 0x0004 +#define IMAGE_FILE_LOCAL_SYMS_STRIPPED 0x0008 +#define IMAGE_FILE_AGGRESSIVE_WS_TRIM 0x0010 +#define IMAGE_FILE_LARGE_ADDRESS_AWARE 0x0020 +#define IMAGE_FILE_16BIT_MACHINE 0x0040 +#define IMAGE_FILE_BYTES_REVERSED_LO 0x0080 +#define IMAGE_FILE_32BIT_MACHINE 0x0100 +#define IMAGE_FILE_DEBUG_STRIPPED 0x0200 +#define IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP 0x0400 +#define IMAGE_FILE_NET_RUN_FROM_SWAP 0x0800 +#define IMAGE_FILE_SYSTEM 0x1000 +#define IMAGE_FILE_DLL 0x2000 +#define IMAGE_FILE_UP_SYSTEM_ONLY 0x4000 +#define IMAGE_FILE_BYTES_REVERSED_HI 0x8000 + +/* Additional flags to be set for section headers to allow the NT loader to + read and write to the section data (to replace the addresses of data in + dlls for one thing); also to execute the section in .text's case. */ +#define IMAGE_SCN_MEM_DISCARDABLE 0x02000000 +#define IMAGE_SCN_MEM_EXECUTE 0x20000000 +#define IMAGE_SCN_MEM_READ 0x40000000 +#define IMAGE_SCN_MEM_WRITE 0x80000000 + +/* Section characteristics added for ppc-nt. */ + +#define IMAGE_SCN_TYPE_NO_PAD 0x00000008 /* Reserved. */ + +#define IMAGE_SCN_CNT_CODE 0x00000020 /* Section contains code. */ +#define IMAGE_SCN_CNT_INITIALIZED_DATA 0x00000040 /* Section contains initialized data. */ +#define IMAGE_SCN_CNT_UNINITIALIZED_DATA 0x00000080 /* Section contains uninitialized data. */ + +#define IMAGE_SCN_LNK_OTHER 0x00000100 /* Reserved. */ +#define IMAGE_SCN_LNK_INFO 0x00000200 /* Section contains comments or some other type of information. */ +#define IMAGE_SCN_LNK_REMOVE 0x00000800 /* Section contents will not become part of image. */ +#define IMAGE_SCN_LNK_COMDAT 0x00001000 /* Section contents comdat. */ + +#define IMAGE_SCN_MEM_FARDATA 0x00008000 + +#define IMAGE_SCN_MEM_PURGEABLE 0x00020000 +#define IMAGE_SCN_MEM_16BIT 0x00020000 +#define IMAGE_SCN_MEM_LOCKED 0x00040000 +#define IMAGE_SCN_MEM_PRELOAD 0x00080000 + +#define IMAGE_SCN_ALIGN_1BYTES 0x00100000 +#define IMAGE_SCN_ALIGN_2BYTES 0x00200000 +#define IMAGE_SCN_ALIGN_4BYTES 0x00300000 +#define IMAGE_SCN_ALIGN_8BYTES 0x00400000 +#define IMAGE_SCN_ALIGN_16BYTES 0x00500000 /* Default alignment if no others are specified. */ +#define IMAGE_SCN_ALIGN_32BYTES 0x00600000 +#define IMAGE_SCN_ALIGN_64BYTES 0x00700000 + +#define IMAGE_SCN_LNK_NRELOC_OVFL 0x01000000 /* Section contains extended relocations. */ +#define IMAGE_SCN_MEM_NOT_CACHED 0x04000000 /* Section is not cachable. */ +#define IMAGE_SCN_MEM_NOT_PAGED 0x08000000 /* Section is not pageable. */ +#define IMAGE_SCN_MEM_SHARED 0x10000000 /* Section is shareable. */ + +/* COMDAT selection codes. */ + +#define IMAGE_COMDAT_SELECT_NODUPLICATES (1) /* Warn if duplicates. */ +#define IMAGE_COMDAT_SELECT_ANY (2) /* No warning. */ +#define IMAGE_COMDAT_SELECT_SAME_SIZE (3) /* Warn if different size. */ +#define IMAGE_COMDAT_SELECT_EXACT_MATCH (4) /* Warn if different. */ +#define IMAGE_COMDAT_SELECT_ASSOCIATIVE (5) /* Base on other section. */ + +/* Machine numbers. */ + +#define IMAGE_FILE_MACHINE_UNKNOWN 0x0000 +#define IMAGE_FILE_MACHINE_ALPHA 0x0184 +#define IMAGE_FILE_MACHINE_ALPHA64 0x0284 +#define IMAGE_FILE_MACHINE_AM33 0x01d3 +#define IMAGE_FILE_MACHINE_AMD64 0x8664 +#define IMAGE_FILE_MACHINE_ARM 0x01c0 +#define IMAGE_FILE_MACHINE_AXP64 IMAGE_FILE_MACHINE_ALPHA64 +#define IMAGE_FILE_MACHINE_CEE 0xc0ee +#define IMAGE_FILE_MACHINE_CEF 0x0cef +#define IMAGE_FILE_MACHINE_EBC 0x0ebc +#define IMAGE_FILE_MACHINE_I386 0x014c +#define IMAGE_FILE_MACHINE_IA64 0x0200 +#define IMAGE_FILE_MACHINE_M32R 0x9041 +#define IMAGE_FILE_MACHINE_M68K 0x0268 +#define IMAGE_FILE_MACHINE_MIPS16 0x0266 +#define IMAGE_FILE_MACHINE_MIPSFPU 0x0366 +#define IMAGE_FILE_MACHINE_MIPSFPU16 0x0466 +#define IMAGE_FILE_MACHINE_POWERPC 0x01f0 +#define IMAGE_FILE_MACHINE_POWERPCFP 0x01f1 +#define IMAGE_FILE_MACHINE_R10000 0x0168 +#define IMAGE_FILE_MACHINE_R3000 0x0162 +#define IMAGE_FILE_MACHINE_R4000 0x0166 +#define IMAGE_FILE_MACHINE_SH3 0x01a2 +#define IMAGE_FILE_MACHINE_SH3DSP 0x01a3 +#define IMAGE_FILE_MACHINE_SH3E 0x01a4 +#define IMAGE_FILE_MACHINE_SH4 0x01a6 +#define IMAGE_FILE_MACHINE_SH5 0x01a8 +#define IMAGE_FILE_MACHINE_THUMB 0x01c2 +#define IMAGE_FILE_MACHINE_TRICORE 0x0520 +#define IMAGE_FILE_MACHINE_WCEMIPSV2 0x0169 + +#define IMAGE_SUBSYSTEM_UNKNOWN 0 +#define IMAGE_SUBSYSTEM_NATIVE 1 +#define IMAGE_SUBSYSTEM_WINDOWS_GUI 2 +#define IMAGE_SUBSYSTEM_WINDOWS_CUI 3 +#define IMAGE_SUBSYSTEM_POSIX_CUI 7 +#define IMAGE_SUBSYSTEM_WINDOWS_CE_GUI 9 +#define IMAGE_SUBSYSTEM_EFI_APPLICATION 10 +#define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11 +#define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12 + +/* Magic values that are true for all dos/nt implementations. */ +#define DOSMAGIC 0x5a4d +#define NT_SIGNATURE 0x00004550 + +/* NT allows long filenames, we want to accommodate this. + This may break some of the bfd functions. */ +#undef FILNMLEN +#define FILNMLEN 18 /* # characters in a file name. */ + +struct external_PEI_DOS_hdr +{ + /* DOS header fields - always at offset zero in the EXE file. */ + char e_magic[2]; /* Magic number, 0x5a4d. */ + char e_cblp[2]; /* Bytes on last page of file, 0x90. */ + char e_cp[2]; /* Pages in file, 0x3. */ + char e_crlc[2]; /* Relocations, 0x0. */ + char e_cparhdr[2]; /* Size of header in paragraphs, 0x4. */ + char e_minalloc[2]; /* Minimum extra paragraphs needed, 0x0. */ + char e_maxalloc[2]; /* Maximum extra paragraphs needed, 0xFFFF. */ + char e_ss[2]; /* Initial (relative) SS value, 0x0. */ + char e_sp[2]; /* Initial SP value, 0xb8. */ + char e_csum[2]; /* Checksum, 0x0. */ + char e_ip[2]; /* Initial IP value, 0x0. */ + char e_cs[2]; /* Initial (relative) CS value, 0x0. */ + char e_lfarlc[2]; /* File address of relocation table, 0x40. */ + char e_ovno[2]; /* Overlay number, 0x0. */ + char e_res[4][2]; /* Reserved words, all 0x0. */ + char e_oemid[2]; /* OEM identifier (for e_oeminfo), 0x0. */ + char e_oeminfo[2]; /* OEM information; e_oemid specific, 0x0. */ + char e_res2[10][2]; /* Reserved words, all 0x0. */ + char e_lfanew[4]; /* File address of new exe header, usually 0x80. */ + char dos_message[16][4]; /* Other stuff, always follow DOS header. */ +}; + +struct external_PEI_IMAGE_hdr +{ + char nt_signature[4]; /* required NT signature, 0x4550. */ + + /* From standard header. */ + char f_magic[2]; /* Magic number. */ + char f_nscns[2]; /* Number of sections. */ + char f_timdat[4]; /* Time & date stamp. */ + char f_symptr[4]; /* File pointer to symtab. */ + char f_nsyms[4]; /* Number of symtab entries. */ + char f_opthdr[2]; /* Sizeof(optional hdr). */ + char f_flags[2]; /* Flags. */ +}; + +struct external_PEI_filehdr +{ + /* DOS header fields - always at offset zero in the EXE file. */ + char e_magic[2]; /* Magic number, 0x5a4d. */ + char e_cblp[2]; /* Bytes on last page of file, 0x90. */ + char e_cp[2]; /* Pages in file, 0x3. */ + char e_crlc[2]; /* Relocations, 0x0. */ + char e_cparhdr[2]; /* Size of header in paragraphs, 0x4. */ + char e_minalloc[2]; /* Minimum extra paragraphs needed, 0x0. */ + char e_maxalloc[2]; /* Maximum extra paragraphs needed, 0xFFFF. */ + char e_ss[2]; /* Initial (relative) SS value, 0x0. */ + char e_sp[2]; /* Initial SP value, 0xb8. */ + char e_csum[2]; /* Checksum, 0x0. */ + char e_ip[2]; /* Initial IP value, 0x0. */ + char e_cs[2]; /* Initial (relative) CS value, 0x0. */ + char e_lfarlc[2]; /* File address of relocation table, 0x40. */ + char e_ovno[2]; /* Overlay number, 0x0. */ + char e_res[4][2]; /* Reserved words, all 0x0. */ + char e_oemid[2]; /* OEM identifier (for e_oeminfo), 0x0. */ + char e_oeminfo[2]; /* OEM information; e_oemid specific, 0x0. */ + char e_res2[10][2]; /* Reserved words, all 0x0. */ + char e_lfanew[4]; /* File address of new exe header, usually 0x80. */ + char dos_message[16][4]; /* Other stuff, always follow DOS header. */ + + /* Note: additional bytes may be inserted before the signature. Use + the e_lfanew field to find the actual location of the NT signature. */ + + char nt_signature[4]; /* required NT signature, 0x4550. */ + + /* From standard header. */ + char f_magic[2]; /* Magic number. */ + char f_nscns[2]; /* Number of sections. */ + char f_timdat[4]; /* Time & date stamp. */ + char f_symptr[4]; /* File pointer to symtab. */ + char f_nsyms[4]; /* Number of symtab entries. */ + char f_opthdr[2]; /* Sizeof(optional hdr). */ + char f_flags[2]; /* Flags. */ +}; + +#ifdef COFF_IMAGE_WITH_PE + +/* The filehdr is only weird in images. */ + +#undef FILHDR +#define FILHDR struct external_PEI_filehdr +#undef FILHSZ +#define FILHSZ 152 + +#endif /* COFF_IMAGE_WITH_PE */ + +/* 32-bit PE a.out header: */ + +typedef struct +{ + AOUTHDR standard; + + /* NT extra fields; see internal.h for descriptions. */ + char ImageBase[4]; + char SectionAlignment[4]; + char FileAlignment[4]; + char MajorOperatingSystemVersion[2]; + char MinorOperatingSystemVersion[2]; + char MajorImageVersion[2]; + char MinorImageVersion[2]; + char MajorSubsystemVersion[2]; + char MinorSubsystemVersion[2]; + char Reserved1[4]; + char SizeOfImage[4]; + char SizeOfHeaders[4]; + char CheckSum[4]; + char Subsystem[2]; + char DllCharacteristics[2]; + char SizeOfStackReserve[4]; + char SizeOfStackCommit[4]; + char SizeOfHeapReserve[4]; + char SizeOfHeapCommit[4]; + char LoaderFlags[4]; + char NumberOfRvaAndSizes[4]; + /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ + char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars. */ +} PEAOUTHDR; +#undef AOUTSZ +#define AOUTSZ (AOUTHDRSZ + 196) + +/* Like PEAOUTHDR, except that the "standard" member has no BaseOfData + (aka data_start) member and that some of the members are 8 instead + of just 4 bytes long. */ +typedef struct +{ + AOUTHDR standard; + + /* NT extra fields; see internal.h for descriptions. */ + char ImageBase[8]; + char SectionAlignment[4]; + char FileAlignment[4]; + char MajorOperatingSystemVersion[2]; + char MinorOperatingSystemVersion[2]; + char MajorImageVersion[2]; + char MinorImageVersion[2]; + char MajorSubsystemVersion[2]; + char MinorSubsystemVersion[2]; + char Reserved1[4]; + char SizeOfImage[4]; + char SizeOfHeaders[4]; + char CheckSum[4]; + char Subsystem[2]; + char DllCharacteristics[2]; + char SizeOfStackReserve[8]; + char SizeOfStackCommit[8]; + char SizeOfHeapReserve[8]; + char SizeOfHeapCommit[8]; + char LoaderFlags[4]; + char NumberOfRvaAndSizes[4]; + /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ + char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars. */ +} PEPAOUTHDR; +#define PEPAOUTSZ 240 + +#undef E_FILNMLEN +#define E_FILNMLEN 18 /* # characters in a file name. */ + +/* Import Tyoes fot ILF format object files.. */ +#define IMPORT_CODE 0 +#define IMPORT_DATA 1 +#define IMPORT_CONST 2 + +/* Import Name Tyoes for ILF format object files. */ +#define IMPORT_ORDINAL 0 +#define IMPORT_NAME 1 +#define IMPORT_NAME_NOPREFIX 2 +#define IMPORT_NAME_UNDECORATE 3 + +#endif /* _PE_H */ diff --git a/include/coff/powerpc.h b/include/coff/powerpc.h new file mode 100644 index 000000000..1d4d6fb05 --- /dev/null +++ b/include/coff/powerpc.h @@ -0,0 +1,58 @@ +/* Basic coff information for the PowerPC + Based on coff/rs6000.h, coff/i386.h and others. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Initial release: Kim Knuttila (krk@cygnus.com) */ +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +/* extra NT defines */ +#define PPCMAGIC 0760 /* peeked on aa PowerPC Windows NT box */ +#define DOSMAGIC 0x5a4d /* from arm.h, i386.h */ +#define NT_SIGNATURE 0x00004550 /* from arm.h, i386.h */ + +/* from winnt.h */ +#define IMAGE_NT_OPTIONAL_HDR_MAGIC 0x10b + +#define PPCBADMAG(x) ((x).f_magic != PPCMAGIC) + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/include/coff/rs6000.h b/include/coff/rs6000.h new file mode 100644 index 000000000..0c3486114 --- /dev/null +++ b/include/coff/rs6000.h @@ -0,0 +1,267 @@ +/* IBM RS/6000 "XCOFF" file definitions for BFD. + Copyright (C) 1990, 1991 Free Software Foundation, Inc. + FIXME: Can someone provide a transliteration of this name into ASCII? + Using the following chars caused a compiler warning on HIUX (so I replaced + them with octal escapes), and isn't useful without an understanding of what + character set it is. + Written by Mimi Ph\373\364ng-Th\345o V\365 of IBM + and John Gilmore of Cygnus Support. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + + /* IBM RS/6000 */ +#define U802WRMAGIC 0730 /* writeable text segments **chh** */ +#define U802ROMAGIC 0735 /* readonly sharable text segments */ +#define U802TOCMAGIC 0737 /* readonly text segments and TOC */ + +#define BADMAG(x) \ + ((x).f_magic != U802ROMAGIC && (x).f_magic != U802WRMAGIC && \ + (x).f_magic != U802TOCMAGIC) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char tsize[4]; /* text size in bytes, padded to FW bdry */ + unsigned char dsize[4]; /* initialized data " " */ + unsigned char bsize[4]; /* uninitialized data " " */ + unsigned char entry[4]; /* entry pt. */ + unsigned char text_start[4]; /* base of text used for this file */ + unsigned char data_start[4]; /* base of data used for this file */ + unsigned char o_toc[4]; /* address of TOC */ + unsigned char o_snentry[2]; /* section number of entry point */ + unsigned char o_sntext[2]; /* section number of .text section */ + unsigned char o_sndata[2]; /* section number of .data section */ + unsigned char o_sntoc[2]; /* section number of TOC */ + unsigned char o_snloader[2]; /* section number of .loader section */ + unsigned char o_snbss[2]; /* section number of .bss section */ + unsigned char o_algntext[2]; /* .text alignment */ + unsigned char o_algndata[2]; /* .data alignment */ + unsigned char o_modtype[2]; /* module type (??) */ + unsigned char o_cputype[2]; /* cpu type */ + unsigned char o_maxstack[4]; /* max stack size (??) */ + unsigned char o_maxdata[4]; /* max data size (??) */ + unsigned char o_resv2[12]; /* reserved */ +} +AOUTHDR; + +#define AOUTSZ 72 +#define SMALL_AOUTSZ (28) +#define AOUTHDRSZ 72 + +/********************** SECTION HEADER **********************/ + + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + struct { + unsigned char x_scnlen[4]; + unsigned char x_parmhash[4]; + unsigned char x_snhash[2]; + unsigned char x_smtyp[1]; + unsigned char x_smclas[1]; + unsigned char x_stab[4]; + unsigned char x_snstab[2]; + } x_csect; + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 +#define DBXMASK 0x80 /* for dbx storage mask */ +#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK) + + + +/********************** RELOCATION DIRECTIVES **********************/ + + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_size[1]; + char r_type[1]; +}; + + +#define RELOC struct external_reloc +#define RELSZ 10 + +#define DEFAULT_DATA_SECTION_ALIGNMENT 4 +#define DEFAULT_BSS_SECTION_ALIGNMENT 4 +#define DEFAULT_TEXT_SECTION_ALIGNMENT 4 +/* For new sections we havn't heard of before */ +#define DEFAULT_SECTION_ALIGNMENT 4 + +/* The ldhdr structure. This appears at the start of the .loader + section. */ + +struct external_ldhdr +{ + bfd_byte l_version[4]; + bfd_byte l_nsyms[4]; + bfd_byte l_nreloc[4]; + bfd_byte l_istlen[4]; + bfd_byte l_nimpid[4]; + bfd_byte l_impoff[4]; + bfd_byte l_stlen[4]; + bfd_byte l_stoff[4]; +}; + +#define LDHDRSZ (8 * 4) + +struct external_ldsym +{ + union + { + bfd_byte _l_name[SYMNMLEN]; + struct + { + bfd_byte _l_zeroes[4]; + bfd_byte _l_offset[4]; + } _l_l; + } _l; + bfd_byte l_value[4]; + bfd_byte l_scnum[2]; + bfd_byte l_smtype[1]; + bfd_byte l_smclas[1]; + bfd_byte l_ifile[4]; + bfd_byte l_parm[4]; +}; + +#define LDSYMSZ (8 + 3 * 4 + 2 + 2) + +struct external_ldrel +{ + bfd_byte l_vaddr[4]; + bfd_byte l_symndx[4]; + bfd_byte l_rtype[2]; + bfd_byte l_rsecnm[2]; +}; + +#define LDRELSZ (2 * 4 + 2 * 2) diff --git a/include/coff/rs6k64.h b/include/coff/rs6k64.h new file mode 100644 index 000000000..47d080213 --- /dev/null +++ b/include/coff/rs6k64.h @@ -0,0 +1,260 @@ +/* IBM RS/6000 "XCOFF64" file definitions for BFD. + Copyright (C) 2000, 2002 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[8]; /* file pointer to symtab */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_nsyms[4]; /* number of symtab entries */ +}; + +/* IBM RS/6000. */ +#define U803XTOCMAGIC 0757 /* Aix 4.3 64-bit XCOFF */ +#define U64_TOCMAGIC 0767 /* AIX 5+ 64-bit XCOFF */ +#define BADMAG(x) ((x).f_magic != U803XTOCMAGIC && (x).f_magic != U64_TOCMAGIC) + +#define FILHDR struct external_filehdr +#define FILHSZ 24 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char o_debugger[4]; /* reserved */ + unsigned char text_start[8]; /* base of text used for this file */ + unsigned char data_start[8]; /* base of data used for this file */ + unsigned char o_toc[8]; /* address of TOC */ + unsigned char o_snentry[2]; /* section number of entry point */ + unsigned char o_sntext[2]; /* section number of .text section */ + unsigned char o_sndata[2]; /* section number of .data section */ + unsigned char o_sntoc[2]; /* section number of TOC */ + unsigned char o_snloader[2]; /* section number of .loader section */ + unsigned char o_snbss[2]; /* section number of .bss section */ + unsigned char o_algntext[2]; /* .text alignment */ + unsigned char o_algndata[2]; /* .data alignment */ + unsigned char o_modtype[2]; /* module type (??) */ + unsigned char o_cputype[2]; /* cpu type */ + unsigned char o_resv2[4]; /* reserved */ + unsigned char tsize[8]; /* text size bytes, padded to FW bdry */ + unsigned char dsize[8]; /* initialized data " " */ + unsigned char bsize[8]; /* uninitialized data " " */ + unsigned char entry[8]; /* entry pt. */ + unsigned char o_maxstack[8]; /* max stack size (??) */ + unsigned char o_maxdata[8]; /* max data size (??) */ + unsigned char o_resv3[16]; /* reserved */ +} +AOUTHDR; + +#define AOUTSZ 120 +#define SMALL_AOUTSZ (0) +#define AOUTHDRSZ 72 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[8]; /* physical address, aliased s_nlib */ + char s_vaddr[8]; /* virtual address */ + char s_size[8]; /* section size */ + char s_scnptr[8]; /* file ptr to raw data for section */ + char s_relptr[8]; /* file ptr to relocation */ + char s_lnnoptr[8]; /* file ptr to line numbers */ + char s_nreloc[4]; /* number of relocation entries */ + char s_nlnno[4]; /* number of line number entries*/ + char s_flags[4]; /* flags */ + char s_pad[4]; /* padding */ +}; + +#define SCNHDR struct external_scnhdr + +#define SCNHSZ 72 + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + Line numbers are grouped on a per function basis; first entry in a function + grouping will have l_lnno = 0 and in place of physical address will be the + symbol table index of the function name. */ + +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[8]; /* (physical) address of line number */ + } l_addr; + + char l_lnno[4]; /* line number */ +}; + +#define LINENO struct external_lineno + +#define LINESZ 12 + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + char e_value[8]; + char e_offset[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +union external_auxent +{ + struct { + union { + struct { + char x_lnno[4]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + struct { + char x_lnnoptr[8];/* ptr to fcn line */ + char x_fsize[4]; /* size of function */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + } x_fcnary; + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + char x_pad[6]; + unsigned char x_ftype[1]; + unsigned char x_resv[2]; + } x_n; + } x_file; + + struct { + char x_exptr[8]; + char x_fsize[4]; + char x_endndx[4]; + char x_pad[1]; + } x_except; + + struct { + unsigned char x_scnlen_lo[4]; + unsigned char x_parmhash[4]; + unsigned char x_snhash[2]; + unsigned char x_smtyp[1]; + unsigned char x_smclas[1]; + unsigned char x_scnlen_hi[4]; + unsigned char x_pad[1]; + } x_csect; + + struct { + char x_pad[17]; + char x_auxtype[1]; + } x_auxtype; +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 +#define DBXMASK 0x80 /* for dbx storage mask */ +#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK) + +/* Values for auxtype field in XCOFF64, taken from AIX 4.3 sym.h. */ +#define _AUX_EXCEPT 255 +#define _AUX_FCN 254 +#define _AUX_SYM 253 +#define _AUX_FILE 252 +#define _AUX_CSECT 251 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[8]; + char r_symndx[4]; + char r_size[1]; + char r_type[1]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 + +#define DEFAULT_DATA_SECTION_ALIGNMENT 4 +#define DEFAULT_BSS_SECTION_ALIGNMENT 4 +#define DEFAULT_TEXT_SECTION_ALIGNMENT 4 +/* For new sections we havn't heard of before */ +#define DEFAULT_SECTION_ALIGNMENT 4 + +/* The ldhdr structure. This appears at the start of the .loader + section. */ + +struct external_ldhdr +{ + bfd_byte l_version[4]; + bfd_byte l_nsyms[4]; + bfd_byte l_nreloc[4]; + bfd_byte l_istlen[4]; + bfd_byte l_nimpid[4]; + bfd_byte l_stlen[4]; + bfd_byte l_impoff[8]; + bfd_byte l_stoff[8]; + bfd_byte l_symoff[8]; + bfd_byte l_rldoff[8]; +}; +#define LDHDRSZ (56) + +struct external_ldsym +{ + bfd_byte l_value[8]; + bfd_byte l_offset[4]; + bfd_byte l_scnum[2]; + bfd_byte l_smtype[1]; + bfd_byte l_smclas[1]; + bfd_byte l_ifile[4]; + bfd_byte l_parm[4]; +}; + +#define LDSYMSZ (24) + +struct external_ldrel +{ + bfd_byte l_vaddr[8]; + bfd_byte l_rtype[2]; + bfd_byte l_rsecnm[2]; + bfd_byte l_symndx[4]; +}; + +#define LDRELSZ (16) diff --git a/include/coff/sh.h b/include/coff/sh.h new file mode 100644 index 000000000..d20834ca6 --- /dev/null +++ b/include/coff/sh.h @@ -0,0 +1,147 @@ +/* coff information for Renesas SH + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifdef COFF_WITH_PE +#define L_LNNO_SIZE 2 +#else +#define L_LNNO_SIZE 4 +#endif +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +#define SH_ARCH_MAGIC_BIG 0x0500 +#define SH_ARCH_MAGIC_LITTLE 0x0550 /* Little endian SH */ +#define SH_ARCH_MAGIC_WINCE 0x01a2 /* Windows CE - little endian */ +#define SH_PE_MAGIC 0x010b + +#define SHBADMAG(x) \ + (((x).f_magic != SH_ARCH_MAGIC_BIG) && \ + ((x).f_magic != SH_ARCH_MAGIC_WINCE) && \ + ((x).f_magic != SH_ARCH_MAGIC_LITTLE)) + +/* Define some NT default values. */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +#ifndef COFF_WITH_PE +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; +#else +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; +#endif + +#define RELOC struct external_reloc +#ifdef COFF_WITH_PE +#define RELSZ 10 +#else +#define RELSZ 16 +#endif + +/* SH relocation types. Not all of these are actually used. */ + +#define R_SH_UNUSED 0 /* only used internally */ +#define R_SH_IMM32CE 2 /* 32 bit immediate for WinCE */ +#define R_SH_PCREL8 3 /* 8 bit pcrel */ +#define R_SH_PCREL16 4 /* 16 bit pcrel */ +#define R_SH_HIGH8 5 /* high 8 bits of 24 bit address */ +#define R_SH_LOW16 7 /* low 16 bits of 24 bit immediate */ +#define R_SH_IMM24 6 /* 24 bit immediate */ +#define R_SH_PCDISP8BY4 9 /* PC rel 8 bits *4 +ve */ +#define R_SH_PCDISP8BY2 10 /* PC rel 8 bits *2 +ve */ +#define R_SH_PCDISP8 11 /* 8 bit branch */ +#define R_SH_PCDISP 12 /* 12 bit branch */ +#define R_SH_IMM32 14 /* 32 bit immediate */ +#define R_SH_IMM8 16 /* 8 bit immediate */ +#define R_SH_IMAGEBASE 16 /* Windows CE */ +#define R_SH_IMM8BY2 17 /* 8 bit immediate *2 */ +#define R_SH_IMM8BY4 18 /* 8 bit immediate *4 */ +#define R_SH_IMM4 19 /* 4 bit immediate */ +#define R_SH_IMM4BY2 20 /* 4 bit immediate *2 */ +#define R_SH_IMM4BY4 21 /* 4 bit immediate *4 */ +#define R_SH_PCRELIMM8BY2 22 /* PC rel 8 bits *2 unsigned */ +#define R_SH_PCRELIMM8BY4 23 /* PC rel 8 bits *4 unsigned */ +#define R_SH_IMM16 24 /* 16 bit immediate */ + +/* The switch table reloc types are used for relaxing. They are + generated for expressions such as + .word L1 - L2 + The r_offset field holds the difference between the reloc address + and L2. */ +#define R_SH_SWITCH8 33 /* 8 bit switch table entry */ +#define R_SH_SWITCH16 25 /* 16 bit switch table entry */ +#define R_SH_SWITCH32 26 /* 32 bit switch table entry */ + +/* The USES reloc type is used for relaxing. The compiler will + generate .uses pseudo-ops when it finds a function call which it + can relax. The r_offset field of the USES reloc holds the PC + relative offset to the instruction which loads the register used in + the function call. */ +#define R_SH_USES 27 /* .uses pseudo-op */ + +/* The COUNT reloc type is used for relaxing. The assembler will + generate COUNT relocs for addresses referred to by the register + loads associated with USES relocs. The r_offset field of the COUNT + reloc holds the number of times the address is referenced in the + object file. */ +#define R_SH_COUNT 28 /* Count of constant pool uses */ + +/* The ALIGN reloc type is used for relaxing. The r_offset field is + the power of two to which subsequent portions of the object file + must be aligned. */ +#define R_SH_ALIGN 29 /* .align pseudo-op */ + +/* The CODE and DATA reloc types are used for aligning load and store + instructions. The assembler will generate a CODE reloc before a + block of instructions. It will generate a DATA reloc before data. + A section should be processed assuming it contains data, unless a + CODE reloc is seen. The only relevant pieces of information in the + CODE and DATA relocs are the section and the address. The symbol + and offset are meaningless. */ +#define R_SH_CODE 30 /* start of code */ +#define R_SH_DATA 31 /* start of data */ + +/* The LABEL reloc type is used for aligning load and store + instructions. The assembler will generate a LABEL reloc for each + label within a block of instructions. This permits the linker to + avoid swapping instructions which are the targets of branches. */ +#define R_SH_LABEL 32 /* label */ + +/* NB: R_SH_SWITCH8 is 33 */ + +#define R_SH_LOOP_START 34 +#define R_SH_LOOP_END 35 diff --git a/include/coff/sparc.h b/include/coff/sparc.h new file mode 100644 index 000000000..ac524d6c2 --- /dev/null +++ b/include/coff/sparc.h @@ -0,0 +1,155 @@ +/* coff information for Sparc. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file is an amalgamation of several standard include files that + define coff format, such as filehdr.h, aouthdr.h, and so forth. In + addition, all datatypes have been translated into character arrays of + (presumed) equivalent size. This is necessary so that this file can + be used with different systems while still yielding the same results. */ + +#define L_LNNO_SIZE 2 +#define DO_NOT_DEFINE_SYMENT +#define DO_NOT_DEFINE_AUXENT +#include "coff/external.h" + +#define F_RELFLG (0x0001) /* relocation info stripped */ +#define F_EXEC (0x0002) /* file is executable */ +#define F_LNNO (0x0004) /* line numbers stripped */ +#define F_LSYMS (0x0008) /* local symbols stripped */ + +#define SPARCMAGIC (0540) + +/* This is Lynx's all-platform magic number for executables. */ + +#define LYNXCOFFMAGIC (0415) + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* More names of "special" sections. */ + +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN (8) /* # characters in a symbol name */ +#define E_FILNMLEN (14) /* # characters in a file name */ +#define E_DIMNUM (4) /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; +#if 0 /* of doubtful value */ + char e_nptr[2][4]; + struct { + char e_leading_zero[1]; + char e_dbx_type[1]; + char e_dbx_desc[2]; + } e_dbx; +#endif + } e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; + char padding[2]; +}; + +#define N_BTMASK (0xf) +#define N_TMASK (0x30) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +union external_auxent +{ + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* .tv section info (in auxent of sym .tv)) */ + + char x_fill[20]; /* forces to 20-byte size */ +}; + +#define SYMENT struct external_syment +#define SYMESZ 20 +#define AUXENT union external_auxent +#define AUXESZ 20 + +#define _ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_spare[2]; + char r_offset[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + diff --git a/include/coff/sym.h b/include/coff/sym.h new file mode 100644 index 000000000..76204af59 --- /dev/null +++ b/include/coff/sym.h @@ -0,0 +1,484 @@ +/* Declarations of internal format of MIPS ECOFF symbols. + Originally contributed by MIPS Computer Systems and Third Eye Software. + Changes contributed by Cygnus Support are in the public domain. + + This file is just aggregated with the files that make up the GNU + release; it is not considered part of GAS, GDB, or other GNU + programs. */ + +/* + * |-----------------------------------------------------------| + * | Copyright (c) 1992, 1991, 1990 MIPS Computer Systems, Inc.| + * | MIPS Computer Systems, Inc. grants reproduction and use | + * | rights to all parties, PROVIDED that this comment is | + * | maintained in the copy. | + * |-----------------------------------------------------------| + */ +#ifndef _SYM_H +#define _SYM_H + +/* (C) Copyright 1984 by Third Eye Software, Inc. + * + * Third Eye Software, Inc. grants reproduction and use rights to + * all parties, PROVIDED that this comment is maintained in the copy. + * + * Third Eye makes no claims about the applicability of this + * symbol table to a particular use. + */ + +/* + * This file contains the definition of the Third Eye Symbol Table. + * + * Symbols are assumed to be in 'encounter order' - i.e. the order that + * the things they represent were encountered by the compiler/assembler/loader. + * EXCEPT for globals! These are assumed to be bunched together, + * probably right after the last 'normal' symbol. Globals ARE sorted + * in ascending order. + * + * ----------------------------------------------------------------------- + * A brief word about Third Eye naming/use conventions: + * + * All arrays and index's are 0 based. + * All "ifooMax" values are the highest legal value PLUS ONE. This makes + * them good for allocating arrays, etc. All checks are "ifoo < ifooMax". + * + * "isym" Index into the SYMbol table. + * "ipd" Index into the Procedure Descriptor array. + * "ifd" Index into the File Descriptor array. + * "iss" Index into String Space. + * "cb" Count of Bytes. + * "rgPd" array whose domain is "0..ipdMax-1" and RanGe is PDR. + * "rgFd" array whose domain is "0..ifdMax-1" and RanGe is FDR. + */ + + +/* + * Symbolic Header (HDR) structure. + * As long as all the pointers are set correctly, + * we don't care WHAT order the various sections come out in! + * + * A file produced solely for the use of CDB will probably NOT have + * any instructions or data areas in it, as these are available + * in the original. + */ + +typedef struct { + short magic; /* to verify validity of the table */ + short vstamp; /* version stamp */ + long ilineMax; /* number of line number entries */ + bfd_vma cbLine; /* number of bytes for line number entries */ + bfd_vma cbLineOffset; /* offset to start of line number entries*/ + long idnMax; /* max index into dense number table */ + bfd_vma cbDnOffset; /* offset to start dense number table */ + long ipdMax; /* number of procedures */ + bfd_vma cbPdOffset; /* offset to procedure descriptor table */ + long isymMax; /* number of local symbols */ + bfd_vma cbSymOffset; /* offset to start of local symbols*/ + long ioptMax; /* max index into optimization symbol entries */ + bfd_vma cbOptOffset; /* offset to optimization symbol entries */ + long iauxMax; /* number of auxillary symbol entries */ + bfd_vma cbAuxOffset; /* offset to start of auxillary symbol entries*/ + long issMax; /* max index into local strings */ + bfd_vma cbSsOffset; /* offset to start of local strings */ + long issExtMax; /* max index into external strings */ + bfd_vma cbSsExtOffset; /* offset to start of external strings */ + long ifdMax; /* number of file descriptor entries */ + bfd_vma cbFdOffset; /* offset to file descriptor table */ + long crfd; /* number of relative file descriptor entries */ + bfd_vma cbRfdOffset; /* offset to relative file descriptor table */ + long iextMax; /* max index into external symbols */ + bfd_vma cbExtOffset; /* offset to start of external symbol entries*/ + /* If you add machine dependent fields, add them here */ + } HDRR, *pHDRR; +#define cbHDRR sizeof(HDRR) +#define hdrNil ((pHDRR)0) + +/* + * The FDR and PDR structures speed mapping of address <-> name. + * They are sorted in ascending memory order and are kept in + * memory by CDB at runtime. + */ + +/* + * File Descriptor + * + * There is one of these for EVERY FILE, whether compiled with + * full debugging symbols or not. The name of a file should be + * the path name given to the compiler. This allows the user + * to simply specify the names of the directories where the COMPILES + * were done, and we will be able to find their files. + * A field whose comment starts with "R - " indicates that it will be + * setup at runtime. + */ +typedef struct fdr { + bfd_vma adr; /* memory address of beginning of file */ + long rss; /* file name (of source, if known) */ + long issBase; /* file's string space */ + bfd_vma cbSs; /* number of bytes in the ss */ + long isymBase; /* beginning of symbols */ + long csym; /* count file's of symbols */ + long ilineBase; /* file's line symbols */ + long cline; /* count of file's line symbols */ + long ioptBase; /* file's optimization entries */ + long copt; /* count of file's optimization entries */ + unsigned short ipdFirst;/* start of procedures for this file */ + short cpd; /* count of procedures for this file */ + long iauxBase; /* file's auxiliary entries */ + long caux; /* count of file's auxiliary entries */ + long rfdBase; /* index into the file indirect table */ + long crfd; /* count file indirect entries */ + unsigned lang: 5; /* language for this file */ + unsigned fMerge : 1; /* whether this file can be merged */ + unsigned fReadin : 1; /* true if it was read in (not just created) */ + unsigned fBigendian : 1;/* if set, was compiled on big endian machine */ + /* aux's will be in compile host's sex */ + unsigned glevel : 2; /* level this file was compiled with */ + unsigned reserved : 22; /* reserved for future use */ + bfd_vma cbLineOffset; /* byte offset from header for this file ln's */ + bfd_vma cbLine; /* size of lines for this file */ + } FDR, *pFDR; +#define cbFDR sizeof(FDR) +#define fdNil ((pFDR)0) +#define ifdNil -1 +#define ifdTemp 0 +#define ilnNil -1 + + +/* + * Procedure Descriptor + * + * There is one of these for EVERY TEXT LABEL. + * If a procedure is in a file with full symbols, then isym + * will point to the PROC symbols, else it will point to the + * global symbol for the label. + */ + +typedef struct pdr { + bfd_vma adr; /* memory address of start of procedure */ + long isym; /* start of local symbol entries */ + long iline; /* start of line number entries*/ + long regmask; /* save register mask */ + long regoffset; /* save register offset */ + long iopt; /* start of optimization symbol entries*/ + long fregmask; /* save floating point register mask */ + long fregoffset; /* save floating point register offset */ + long frameoffset; /* frame size */ + short framereg; /* frame pointer register */ + short pcreg; /* offset or reg of return pc */ + long lnLow; /* lowest line in the procedure */ + long lnHigh; /* highest line in the procedure */ + bfd_vma cbLineOffset; /* byte offset for this procedure from the fd base */ + /* These fields are new for 64 bit ECOFF. */ + unsigned gp_prologue : 8; /* byte size of GP prologue */ + unsigned gp_used : 1; /* true if the procedure uses GP */ + unsigned reg_frame : 1; /* true if register frame procedure */ + unsigned prof : 1; /* true if compiled with -pg */ + unsigned reserved : 13; /* reserved: must be zero */ + unsigned localoff : 8; /* offset of local variables from vfp */ + } PDR, *pPDR; +#define cbPDR sizeof(PDR) +#define pdNil ((pPDR) 0) +#define ipdNil -1 + +/* + * The structure of the runtime procedure descriptor created by the loader + * for use by the static exception system. + */ +/* + * If 0'd out because exception_info chokes Visual C++ and because there + * don't seem to be any references to this structure elsewhere in gdb. + */ +#if 0 +typedef struct runtime_pdr { + bfd_vma adr; /* memory address of start of procedure */ + long regmask; /* save register mask */ + long regoffset; /* save register offset */ + long fregmask; /* save floating point register mask */ + long fregoffset; /* save floating point register offset */ + long frameoffset; /* frame size */ + short framereg; /* frame pointer register */ + short pcreg; /* offset or reg of return pc */ + long irpss; /* index into the runtime string table */ + long reserved; + struct exception_info *exception_info;/* pointer to exception array */ +} RPDR, *pRPDR; +#define cbRPDR sizeof(RPDR) +#define rpdNil ((pRPDR) 0) +#endif + +/* + * Line Numbers + * + * Line Numbers are segregated from the normal symbols because they + * are [1] smaller , [2] are of no interest to your + * average loader, and [3] are never needed in the middle of normal + * scanning and therefore slow things down. + * + * By definition, the first LINER for any given procedure will have + * the first line of a procedure and represent the first address. + */ + +typedef long LINER, *pLINER; +#define lineNil ((pLINER)0) +#define cbLINER sizeof(LINER) +#define ilineNil -1 + + + +/* + * The Symbol Structure (GFW, to those who Know!) + */ + +typedef struct { + long iss; /* index into String Space of name */ + bfd_vma value; /* value of symbol */ + unsigned st : 6; /* symbol type */ + unsigned sc : 5; /* storage class - text, data, etc */ + unsigned reserved : 1; /* reserved */ + unsigned index : 20; /* index into sym/aux table */ + } SYMR, *pSYMR; +#define symNil ((pSYMR)0) +#define cbSYMR sizeof(SYMR) +#define isymNil -1 +#define indexNil 0xfffff +#define issNil -1 +#define issNull 0 + + +/* The following converts a memory resident string to an iss. + * This hack is recognized in SbFIss, in sym.c of the debugger. + */ +#define IssFSb(sb) (0x80000000 | ((unsigned long)(sb))) + +/* E X T E R N A L S Y M B O L R E C O R D + * + * Same as the SYMR except it contains file context to determine where + * the index is. + */ +typedef struct ecoff_extr { + unsigned jmptbl:1; /* symbol is a jump table entry for shlibs */ + unsigned cobol_main:1; /* symbol is a cobol main procedure */ + unsigned weakext:1; /* symbol is weak external */ + unsigned reserved:13; /* reserved for future use */ + int ifd; /* where the iss and index fields point into */ + SYMR asym; /* symbol for the external */ + } EXTR, *pEXTR; +#define extNil ((pEXTR)0) +#define cbEXTR sizeof(EXTR) + + +/* A U X I L L A R Y T Y P E I N F O R M A T I O N */ + +/* + * Type Information Record + */ +typedef struct { + unsigned fBitfield : 1; /* set if bit width is specified */ + unsigned continued : 1; /* indicates additional TQ info in next AUX */ + unsigned bt : 6; /* basic type */ + unsigned tq4 : 4; + unsigned tq5 : 4; + /* ---- 16 bit boundary ---- */ + unsigned tq0 : 4; + unsigned tq1 : 4; /* 6 type qualifiers - tqPtr, etc. */ + unsigned tq2 : 4; + unsigned tq3 : 4; + } TIR, *pTIR; +#define cbTIR sizeof(TIR) +#define tiNil ((pTIR)0) +#define itqMax 6 + +/* + * Relative symbol record + * + * If the rfd field is 4095, the index field indexes into the global symbol + * table. + */ + +typedef struct { + unsigned rfd : 12; /* index into the file indirect table */ + unsigned index : 20; /* index int sym/aux/iss tables */ + } RNDXR, *pRNDXR; +#define cbRNDXR sizeof(RNDXR) +#define rndxNil ((pRNDXR)0) + +/* dense numbers or sometimes called block numbers are stored in this type, + * a rfd of 0xffffffff is an index into the global table. + */ +typedef struct { + unsigned long rfd; /* index into the file table */ + unsigned long index; /* index int sym/aux/iss tables */ + } DNR, *pDNR; +#define cbDNR sizeof(DNR) +#define dnNil ((pDNR)0) + + + +/* + * Auxillary information occurs only if needed. + * It ALWAYS occurs in this order when present. + + isymMac used by stProc only + TIR type info + TIR additional TQ info (if first TIR was not enough) + rndx if (bt == btStruct,btUnion,btEnum,btSet,btRange, + btTypedef): + rsym.index == iaux for btSet or btRange + else rsym.index == isym + dimLow btRange, btSet + dimMac btRange, btSet + rndx0 As many as there are tq arrays + dimLow0 + dimHigh0 + ... + rndxMax-1 + dimLowMax-1 + dimHighMax-1 + width in bits if (bit field), width in bits. + */ +#define cAuxMax (6 + (idimMax*3)) + +/* a union of all possible info in the AUX universe */ +typedef union { + TIR ti; /* type information record */ + RNDXR rndx; /* relative index into symbol table */ + long dnLow; /* low dimension */ + long dnHigh; /* high dimension */ + long isym; /* symbol table index (end of proc) */ + long iss; /* index into string space (not used) */ + long width; /* width for non-default sized struc fields */ + long count; /* count of ranges for variant arm */ + } AUXU, *pAUXU; +#define cbAUXU sizeof(AUXU) +#define auxNil ((pAUXU)0) +#define iauxNil -1 + + +/* + * Optimization symbols + * + * Optimization symbols contain some overlap information with the normal + * symbol table. In particular, the proc information + * is somewhat redundant but necessary to easily find the other information + * present. + * + * All of the offsets are relative to the beginning of the last otProc + */ + +typedef struct { + unsigned ot: 8; /* optimization type */ + unsigned value: 24; /* address where we are moving it to */ + RNDXR rndx; /* points to a symbol or opt entry */ + unsigned long offset; /* relative offset this occured */ + } OPTR, *pOPTR; +#define optNil ((pOPTR) 0) +#define cbOPTR sizeof(OPTR) +#define ioptNil -1 + +/* + * File Indirect + * + * When a symbol is referenced across files the following procedure is used: + * 1) use the file index to get the File indirect entry. + * 2) use the file indirect entry to get the File descriptor. + * 3) add the sym index to the base of that file's sym table + * + */ + +typedef long RFDT, *pRFDT; +#define cbRFDT sizeof(RFDT) +#define rfdNil -1 + +/* + * The file indirect table in the mips loader is known as an array of FITs. + * This is done to keep the code in the loader readable in the area where + * these tables are merged. Note this is only a name change. + */ +typedef long FIT, *pFIT; +#define cbFIT sizeof(FIT) +#define ifiNil -1 +#define fiNil ((pFIT) 0) + +#ifdef _LANGUAGE_PASCAL +#define ifdNil -1 +#define ilnNil -1 +#define ipdNil -1 +#define ilineNil -1 +#define isymNil -1 +#define indexNil 16#fffff +#define issNil -1 +#define issNull 0 +#define itqMax 6 +#define iauxNil -1 +#define ioptNil -1 +#define rfdNil -1 +#define ifiNil -1 +#endif /* _LANGUAGE_PASCAL */ + + +/* Dense numbers + * + * Rather than use file index, symbol index pairs to represent symbols + * and globals, we use dense number so that they can be easily embeded + * in intermediate code and the programs that process them can + * use direct access tabls instead of hash table (which would be + * necesary otherwise because of the sparse name space caused by + * file index, symbol index pairs. Dense number are represented + * by RNDXRs. + */ + +/* + * The following table defines the meaning of each SYM field as + * a function of the "st". (scD/B == scData OR scBss) + * + * Note: the value "isymMac" is used by symbols that have the concept + * of enclosing a block of related information. This value is the + * isym of the first symbol AFTER the end associated with the primary + * symbol. For example if a procedure was at isym==90 and had an + * isymMac==155, the associated end would be at isym==154, and the + * symbol at 155 would probably (although not necessarily) be the + * symbol for the next procedure. This allows rapid skipping over + * internal information of various sorts. "stEnd"s ALWAYS have the + * isym of the primary symbol that started the block. + * + +ST SC VALUE INDEX +-------- ------ -------- ------ +stFile scText address isymMac +stLabel scText address --- +stGlobal scD/B address iaux +stStatic scD/B address iaux +stParam scAbs offset iaux +stLocal scAbs offset iaux +stProc scText address iaux (isymMac is first AUX) +stStaticProc scText address iaux (isymMac is first AUX) + +stMember scNil ordinal --- (if member of enum) + (mipsread thinks the case below has a bit, not byte, offset.) +stMember scNil byte offset iaux (if member of struct/union) +stMember scBits bit offset iaux (bit field spec) + +stBlock scText address isymMac (text block) + (the code seems to think that rather than scNil, we see scInfo for + the two cases below.) +stBlock scNil cb isymMac (struct/union member define) +stBlock scNil cMembers isymMac (enum member define) + + (New types added by SGI to simplify things:) +stStruct scInfo cb isymMac (struct type define) +stUnion scInfo cb isymMac (union type define) +stEnum scInfo cMembers isymMac (enum type define) + +stEnd scText address isymStart +stEnd scNil ------- isymStart (struct/union/enum) + +stTypedef scNil ------- iaux +stRegReloc sc??? value old register number +stForward sc??? new address isym to original symbol + +stConstant scInfo value --- (scalar) +stConstant scInfo iss --- (complex, e.g. string) + + * + */ +#endif diff --git a/include/coff/symconst.h b/include/coff/symconst.h new file mode 100644 index 000000000..3e45705f4 --- /dev/null +++ b/include/coff/symconst.h @@ -0,0 +1,177 @@ +/* Declarations of constants for internal format of MIPS ECOFF symbols. + Originally contributed by MIPS Computer Systems and Third Eye Software. + Changes contributed by Cygnus Support are in the public domain. + + This file is just aggregated with the files that make up the GNU + release; it is not considered part of GAS, GDB, or other GNU + programs. */ + +/* + * |-----------------------------------------------------------| + * | Copyright (c) 1992, 1991, 1990 MIPS Computer Systems, Inc.| + * | MIPS Computer Systems, Inc. grants reproduction and use | + * | rights to all parties, PROVIDED that this comment is | + * | maintained in the copy. | + * |-----------------------------------------------------------| + */ + +/* (C) Copyright 1984 by Third Eye Software, Inc. + * + * Third Eye Software, Inc. grants reproduction and use rights to + * all parties, PROVIDED that this comment is maintained in the copy. + * + * Third Eye makes no claims about the applicability of this + * symbol table to a particular use. + */ + +/* glevels for field in FDR */ +#define GLEVEL_0 2 +#define GLEVEL_1 1 +#define GLEVEL_2 0 /* for upward compat reasons. */ +#define GLEVEL_3 3 + +/* magic number fo symheader */ +#define magicSym 0x7009 +/* The Alpha uses this value instead, for some reason. */ +#define magicSym2 0x1992 + +/* Language codes */ +#define langC 0 +#define langPascal 1 +#define langFortran 2 +#define langAssembler 3 /* one Assembley inst might map to many mach */ +#define langMachine 4 +#define langNil 5 +#define langAda 6 +#define langPl1 7 +#define langCobol 8 +#define langStdc 9 /* FIXME: Collides with SGI langCplusplus */ +#define langCplusplus 9 /* FIXME: Collides with langStdc */ +#define langCplusplusV2 10 /* SGI addition */ +#define langMax 11 /* maximum allowed 32 -- 5 bits */ + +/* The following are value definitions for the fields in the SYMR */ + +/* + * Storage Classes + */ + +#define scNil 0 +#define scText 1 /* text symbol */ +#define scData 2 /* initialized data symbol */ +#define scBss 3 /* un-initialized data symbol */ +#define scRegister 4 /* value of symbol is register number */ +#define scAbs 5 /* value of symbol is absolute */ +#define scUndefined 6 /* who knows? */ +#define scCdbLocal 7 /* variable's value is IN se->va.?? */ +#define scBits 8 /* this is a bit field */ +#define scCdbSystem 9 /* variable's value is IN CDB's address space */ +#define scDbx 9 /* overlap dbx internal use */ +#define scRegImage 10 /* register value saved on stack */ +#define scInfo 11 /* symbol contains debugger information */ +#define scUserStruct 12 /* address in struct user for current process */ +#define scSData 13 /* load time only small data */ +#define scSBss 14 /* load time only small common */ +#define scRData 15 /* load time only read only data */ +#define scVar 16 /* Var parameter (fortran,pascal) */ +#define scCommon 17 /* common variable */ +#define scSCommon 18 /* small common */ +#define scVarRegister 19 /* Var parameter in a register */ +#define scVariant 20 /* Variant record */ +#define scSUndefined 21 /* small undefined(external) data */ +#define scInit 22 /* .init section symbol */ +#define scBasedVar 23 /* Fortran or PL/1 ptr based var */ +#define scXData 24 /* exception handling data */ +#define scPData 25 /* Procedure section */ +#define scFini 26 /* .fini section */ +#define scRConst 27 /* .rconst section */ +#define scMax 32 + + +/* + * Symbol Types + */ + +#define stNil 0 /* Nuthin' special */ +#define stGlobal 1 /* external symbol */ +#define stStatic 2 /* static */ +#define stParam 3 /* procedure argument */ +#define stLocal 4 /* local variable */ +#define stLabel 5 /* label */ +#define stProc 6 /* " " Procedure */ +#define stBlock 7 /* beginnning of block */ +#define stEnd 8 /* end (of anything) */ +#define stMember 9 /* member (of anything - struct/union/enum */ +#define stTypedef 10 /* type definition */ +#define stFile 11 /* file name */ +#define stRegReloc 12 /* register relocation */ +#define stForward 13 /* forwarding address */ +#define stStaticProc 14 /* load time only static procs */ +#define stConstant 15 /* const */ +#define stStaParam 16 /* Fortran static parameters */ + /* These new symbol types have been recently added to SGI machines. */ +#define stStruct 26 /* Beginning of block defining a struct type */ +#define stUnion 27 /* Beginning of block defining a union type */ +#define stEnum 28 /* Beginning of block defining an enum type */ +#define stIndirect 34 /* Indirect type specification */ + /* Pseudo-symbols - internal to debugger */ +#define stStr 60 /* string */ +#define stNumber 61 /* pure number (ie. 4 NOR 2+2) */ +#define stExpr 62 /* 2+2 vs. 4 */ +#define stType 63 /* post-coersion SER */ +#define stMax 64 + +/* definitions for fields in TIR */ + +/* type qualifiers for ti.tq0 -> ti.(itqMax-1) */ +#define tqNil 0 /* bt is what you see */ +#define tqPtr 1 /* pointer */ +#define tqProc 2 /* procedure */ +#define tqArray 3 /* duh */ +#define tqFar 4 /* longer addressing - 8086/8 land */ +#define tqVol 5 /* volatile */ +#define tqConst 6 /* const */ +#define tqMax 8 + +/* basic types as seen in ti.bt */ +#define btNil 0 /* undefined (also, enum members) */ +#define btAdr 1 /* address - integer same size as pointer */ +#define btChar 2 /* character */ +#define btUChar 3 /* unsigned character */ +#define btShort 4 /* short */ +#define btUShort 5 /* unsigned short */ +#define btInt 6 /* int */ +#define btUInt 7 /* unsigned int */ +#define btLong 8 /* long */ +#define btULong 9 /* unsigned long */ +#define btFloat 10 /* float (real) */ +#define btDouble 11 /* Double (real) */ +#define btStruct 12 /* Structure (Record) */ +#define btUnion 13 /* Union (variant) */ +#define btEnum 14 /* Enumerated */ +#define btTypedef 15 /* defined via a typedef, isymRef points */ +#define btRange 16 /* subrange of int */ +#define btSet 17 /* pascal sets */ +#define btComplex 18 /* fortran complex */ +#define btDComplex 19 /* fortran double complex */ +#define btIndirect 20 /* forward or unnamed typedef */ +#define btFixedDec 21 /* Fixed Decimal */ +#define btFloatDec 22 /* Float Decimal */ +#define btString 23 /* Varying Length Character String */ +#define btBit 24 /* Aligned Bit String */ +#define btPicture 25 /* Picture */ +#define btVoid 26 /* void */ +#define btLongLong 27 /* long long */ +#define btULongLong 28 /* unsigned long long */ +#define btMax 64 + +#if (_MFG == _MIPS) +/* optimization type codes */ +#define otNil 0 +#define otReg 1 /* move var to reg */ +#define otBlock 2 /* begin basic block */ +#define otProc 3 /* procedure */ +#define otInline 4 /* inline procedure */ +#define otEnd 5 /* whatever you started */ +#define otMax 6 /* KEEP UP TO DATE */ +#endif /* (_MFG == _MIPS) */ diff --git a/include/coff/ti.h b/include/coff/ti.h new file mode 100644 index 000000000..a15fe717a --- /dev/null +++ b/include/coff/ti.h @@ -0,0 +1,473 @@ +/* COFF information for TI COFF support. Definitions in this file should be + customized in a target-specific file, and then this file included (see + tic54x.h for an example). + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#ifndef COFF_TI_H +#define COFF_TI_H + +/* Note "coff/external.h is not used because TI adds extra fields to the structures. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr + { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_target_id[2]; /* magic no. (TI COFF-specific) */ + }; + +/* COFF0 has magic number in f_magic, and omits f_target_id from the file + header; for later versions, f_magic is 0xC1 for COFF1 and 0xC2 for COFF2 + and the target-specific magic number is found in f_target_id */ + +#define TICOFF0MAGIC TI_TARGET_ID +#define TICOFF1MAGIC 0x00C1 +#define TICOFF2MAGIC 0x00C2 +#define TICOFF_AOUT_MAGIC 0x0108 /* magic number in optional header */ +#define TICOFF 1 /* customize coffcode.h */ + +/* The target_id field changes depending on the particular CPU target */ +/* for COFF0, the target id appeared in f_magic, where COFFX magic is now */ +#ifndef TI_TARGET_ID +#error "TI_TARGET_ID needs to be defined for your CPU" +#endif + +/* Which bfd_arch to use... */ +#ifndef TICOFF_TARGET_ARCH +#error "TICOFF_TARGET_ARCH needs to be defined for your CPU" +#endif + +#ifndef TICOFF_TARGET_MACHINE_GET +#define TICOFF_TARGET_MACHINE_GET(FLAGS) 0 +#endif + +#ifndef TICOFF_TARGET_MACHINE_SET +#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) +#endif + +/* Default to COFF2 for file output */ +#ifndef TICOFF_DEFAULT_MAGIC +#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC +#endif + +/* This value is made available in the rare case where a bfd is unavailable */ +#ifndef OCTETS_PER_BYTE_POWER +#error "OCTETS_PER_BYTE_POWER not defined for this CPU" +#else +#define OCTETS_PER_BYTE (1<<OCTETS_PER_BYTE_POWER) +#endif + +/* default alignment is on a byte (not octet!) boundary */ +#ifndef COFF_DEFAULT_SECTION_ALIGNMENT_POWER +#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 0 +#endif + +/* TI COFF encodes the section alignment in the section header flags */ +#define COFF_ALIGN_IN_SECTION_HEADER 1 +#define COFF_ALIGN_IN_S_FLAGS 1 +/* requires a power-of-two argument */ +#define COFF_ENCODE_ALIGNMENT(S,X) ((S).s_flags |= (((unsigned)(X)&0xF)<<8)) +/* result is a power of two */ +#define COFF_DECODE_ALIGNMENT(X) (((X)>>8)&0xF) + +#define COFF0_P(ABFD) (bfd_coff_filhsz(ABFD) == FILHSZ_V0) +#define COFF2_P(ABFD) (bfd_coff_scnhsz(ABFD) != SCNHSZ_V01) + +#define COFF0_BADMAG(x) ((x).f_magic != TICOFF0MAGIC) +#define COFF1_BADMAG(x) ((x).f_magic != TICOFF1MAGIC || (x).f_target_id != TI_TARGET_ID) +#define COFF2_BADMAG(x) ((x).f_magic != TICOFF2MAGIC || (x).f_target_id != TI_TARGET_ID) + +/* we need to read/write an extra field in the coff file header */ +#ifndef COFF_ADJUST_FILEHDR_IN_POST +#define COFF_ADJUST_FILEHDR_IN_POST(abfd, src, dst) \ + do \ + { \ + ((struct internal_filehdr *)(dst))->f_target_id = \ + H_GET_16 (abfd, ((FILHDR *)(src))->f_target_id); \ + } \ + while (0) +#endif + +#ifndef COFF_ADJUST_FILEHDR_OUT_POST +#define COFF_ADJUST_FILEHDR_OUT_POST(abfd, src, dst) \ + do \ + { \ + H_PUT_16 (abfd, ((struct internal_filehdr *)(src))->f_target_id, \ + ((FILHDR *)(dst))->f_target_id); \ + } \ + while (0) +#endif + +#define FILHDR struct external_filehdr +#define FILHSZ 22 +#define FILHSZ_V0 20 /* COFF0 omits target_id field */ + +/* File header flags */ +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_VERS (0x0010) /* TMS320C4x code */ +/* F_LSYMS needs to be redefined in your source file */ +#define F_LSYMS_TICOFF (0x0010) /* normal COFF is 0x8 */ + +#define F_10 0x00 /* file built for TMS320C1x devices */ +#define F_20 0x10 /* file built for TMS320C2x devices */ +#define F_25 0x20 /* file built for TMS320C2x/C5x devices */ +#define F_LENDIAN 0x0100 /* 16 bits/word, LSB first */ +#define F_SYMMERGE 0x1000 /* duplicate symbols were removed */ + +/********************** OPTIONAL HEADER **********************/ + + +typedef struct +{ + char magic[2]; /* type of file (0x108) */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 + + +/********************** SECTION HEADER **********************/ +/* COFF0, COFF1 */ +struct external_scnhdr_v01 { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size (in WORDS) */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[2]; /* flags */ + char s_reserved[1]; /* reserved */ + char s_page[1]; /* section page number (LOAD) */ +}; + +/* COFF2 */ +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size (in WORDS) */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[4]; /* number of relocation entries */ + char s_nlnno[4]; /* number of line number entries*/ + char s_flags[4]; /* flags */ + char s_reserved[2]; /* reserved */ + char s_page[2]; /* section page number (LOAD) */ +}; + +/* + * Special section flags + */ + +/* TI COFF defines these flags; + STYP_CLINK: the section should be excluded from the final + linker output if there are no references found to any symbol in the section + STYP_BLOCK: the section should be blocked, i.e. if the section would cross + a page boundary, it is started at a page boundary instead. + TI COFF puts the section alignment power of two in the section flags + e.g. 2**N is alignment, flags |= (N & 0xF) << 8 +*/ +#define STYP_CLINK (0x4000) +#define STYP_BLOCK (0x1000) +#define STYP_ALIGN (0x0F00) /* TI COFF stores section alignment here */ + +#define SCNHDR_V01 struct external_scnhdr_v01 +#define SCNHDR struct external_scnhdr +#define SCNHSZ_V01 40 /* for v0 and v1 */ +#define SCNHSZ 48 + +/* COFF2 changes the offsets and sizes of these fields + Assume we're dealing with the COFF2 scnhdr structure, and adjust + accordingly + */ +#define GET_SCNHDR_NRELOC(ABFD, LOC) \ + (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, LOC)) +#define PUT_SCNHDR_NRELOC(ABFD, VAL, LOC) \ + (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, LOC)) +#define GET_SCNHDR_NLNNO(ABFD, LOC) \ + (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, (LOC) - 2)) +#define PUT_SCNHDR_NLNNO(ABFD, VAL, LOC) \ + (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, (LOC) - 2)) +#define GET_SCNHDR_FLAGS(ABFD, LOC) \ + (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, (LOC) - 4)) +#define PUT_SCNHDR_FLAGS(ABFD, VAL, LOC) \ + (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, (LOC) - 4)) +#define GET_SCNHDR_PAGE(ABFD, LOC) \ + (COFF2_P (ABFD) ? H_GET_16 (ABFD, LOC) : (unsigned) H_GET_8 (ABFD, (LOC) - 7)) +/* on output, make sure that the "reserved" field is zero */ +#define PUT_SCNHDR_PAGE(ABFD, VAL, LOC) \ + (COFF2_P (ABFD) \ + ? H_PUT_16 (ABFD, VAL, LOC) \ + : H_PUT_8 (ABFD, VAL, (LOC) - 7), H_PUT_8 (ABFD, 0, (LOC) - 8)) + +/* TI COFF stores section size as number of bytes (address units, not octets), + so adjust to be number of octets, which is what BFD expects */ +#define GET_SCNHDR_SIZE(ABFD, SZP) \ + (H_GET_32 (ABFD, SZP) * bfd_octets_per_byte (ABFD)) +#define PUT_SCNHDR_SIZE(ABFD, SZ, SZP) \ + H_PUT_32 (ABFD, (SZ) / bfd_octets_per_byte (ABFD), SZP) + +#define COFF_ADJUST_SCNHDR_IN_POST(ABFD, EXT, INT) \ + do \ + { \ + ((struct internal_scnhdr *)(INT))->s_page = \ + GET_SCNHDR_PAGE (ABFD, ((SCNHDR *)(EXT))->s_page); \ + } \ + while (0) + +/* The line number and reloc overflow checking in coff_swap_scnhdr_out in + coffswap.h doesn't use PUT_X for s_nlnno and s_nreloc. + Due to different sized v0/v1/v2 section headers, we have to re-write these + fields. + */ +#define COFF_ADJUST_SCNHDR_OUT_POST(ABFD, INT, EXT) \ + do \ + { \ + PUT_SCNHDR_NLNNO (ABFD, ((struct internal_scnhdr *)(INT))->s_nlnno, \ + ((SCNHDR *)(EXT))->s_nlnno); \ + PUT_SCNHDR_NRELOC (ABFD, ((struct internal_scnhdr *)(INT))->s_nreloc,\ + ((SCNHDR *)(EXT))->s_nreloc); \ + PUT_SCNHDR_FLAGS (ABFD, ((struct internal_scnhdr *)(INT))->s_flags, \ + ((SCNHDR *)(EXT))->s_flags); \ + PUT_SCNHDR_PAGE (ABFD, ((struct internal_scnhdr *)(INT))->s_page, \ + ((SCNHDR *)(EXT))->s_page); \ + } \ + while (0) + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _CINIT ".cinit" /* initialized C data */ +#define _SCONST ".const" /* constants */ +#define _SWITCH ".switch" /* switch tables */ +#define _STACK ".stack" /* C stack */ +#define _SYSMEM ".sysmem" /* used for malloc et al. syscalls */ + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +/* NOTE: this is what a local label looks like in assembly source; what it + looks like in COFF output is undefined */ +#define TICOFF_LOCAL_LABEL_P(NAME) \ +((NAME[0] == '$' && NAME[1] >= '0' && NAME[1] <= '9' && NAME[2] == '\0') \ + || NAME[strlen(NAME)-1] == '?') + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + +/* section lengths are in target bytes (not host bytes) */ +#define GET_SCN_SCNLEN(ABFD, EXT) \ + (H_GET_32 (ABFD, (EXT)->x_scn.x_scnlen) * bfd_octets_per_byte (ABFD)) +#define PUT_SCN_SCNLEN(ABFD, INT, EXT) \ + H_PUT_32 (ABFD, (INT) / bfd_octets_per_byte (ABFD), (EXT)->x_scn.x_scnlen) + +/* lnsz size is in bits in COFF file, in bytes in BFD */ +#define GET_LNSZ_SIZE(abfd, ext) \ + (H_GET_16 (abfd, ext->x_sym.x_misc.x_lnsz.x_size) / (class != C_FIELD ? 8 : 1)) + +#define PUT_LNSZ_SIZE(abfd, in, ext) \ + H_PUT_16 (abfd, ((class != C_FIELD) ? (in) * 8 : (in)), \ + ext->x_sym.x_misc.x_lnsz.x_size) + +/* TI COFF stores offsets for MOS and MOU in bits; BFD expects bytes + Also put the load page flag of the section into the symbol value if it's an + address. */ +#ifndef NEEDS_PAGE +#define NEEDS_PAGE(X) 0 +#define PAGE_MASK 0 +#endif +#define COFF_ADJUST_SYM_IN_POST(ABFD, EXT, INT) \ + do \ + { \ + struct internal_syment *dst = (struct internal_syment *)(INT); \ + if (dst->n_sclass == C_MOS || dst->n_sclass == C_MOU) \ + dst->n_value /= 8; \ + else if (NEEDS_PAGE (dst->n_sclass)) { \ + asection *scn = coff_section_from_bfd_index (abfd, dst->n_scnum); \ + dst->n_value |= (scn->lma & PAGE_MASK); \ + } \ + } \ + while (0) + +#define COFF_ADJUST_SYM_OUT_POST(ABFD, INT, EXT) \ + do \ + { \ + struct internal_syment *src = (struct internal_syment *)(INT); \ + SYMENT *dst = (SYMENT *)(EXT); \ + if (src->n_sclass == C_MOU || src->n_sclass == C_MOS) \ + H_PUT_32 (abfd, src->n_value * 8, dst->e_value); \ + else if (NEEDS_PAGE (src->n_sclass)) { \ + H_PUT_32 (abfd, src->n_value &= ~PAGE_MASK, dst->e_value); \ + } \ + } \ + while (0) + +/* Detect section-relative absolute symbols so they get flagged with a sym + index of -1. +*/ +#define SECTION_RELATIVE_ABSOLUTE_SYMBOL_P(RELOC, SECT) \ + ((*(RELOC)->sym_ptr_ptr)->section->output_section == (SECT) \ + && (RELOC)->howto->name[0] == 'A') + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc_v0 +{ + char r_vaddr[4]; + char r_symndx[2]; + char r_reserved[2]; + char r_type[2]; +}; + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_reserved[2]; /* extended pmad byte for COFF2 */ + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ_V0 10 /* FIXME -- coffcode.h needs fixing */ +#define RELSZ 12 /* for COFF1/2 */ + +/* various relocation types. */ +#define R_ABS 0x0000 /* no relocation */ +#define R_REL13 0x002A /* 13-bit direct reference (???) */ +#define R_PARTLS7 0x0028 /* 7 LSBs of an address */ +#define R_PARTMS9 0x0029 /* 9MSBs of an address */ +#define R_EXTWORD 0x002B /* 23-bit direct reference */ +#define R_EXTWORD16 0x002C /* 16-bit direct reference to 23-bit addr*/ +#define R_EXTWORDMS7 0x002D /* upper 7 bits of 23-bit address */ + +#endif /* COFF_TI_H */ diff --git a/include/coff/tic30.h b/include/coff/tic30.h new file mode 100644 index 000000000..30bf9dca9 --- /dev/null +++ b/include/coff/tic30.h @@ -0,0 +1,50 @@ +/* coff information for Texas Instruments TMS320C3X + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define TIC30MAGIC 0xC000 + +#define TIC30BADMAG(x) (((x).f_magic != TIC30MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the z8k don't have room in the instruction for the entire + offset - eg with segments */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + +/* TMS320C30 relocation types. */ + +#define R_TIC30_ABS16 0x100 /* 16 bit absolute. */ +#define R_TIC30_ABS24 0x101 /* 24 bit absolute. */ +#define R_TIC30_ABS32 0x102 /* 32 bit absolute. */ +#define R_TIC30_LDP 0x103 /* LDP bits 23-16 to 7-0. */ +#define R_TIC30_PC16 0x104 /* 16 bit pc relative. */ diff --git a/include/coff/tic4x.h b/include/coff/tic4x.h new file mode 100644 index 000000000..0d224b253 --- /dev/null +++ b/include/coff/tic4x.h @@ -0,0 +1,46 @@ +/* TI COFF information for Texas Instruments TMS320C4X/C3X. + This file customizes the settings in coff/ti.h. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef COFF_TIC4X_H +#define COFF_TIC4X_H + +#define TIC4X_TARGET_ID 0x0093 +/* Octets per byte, as a power of two. */ +#define TI_TARGET_ID TIC4X_TARGET_ID +#define OCTETS_PER_BYTE_POWER 2 +/* Add to howto to get absolute/sect-relative version. */ +#define HOWTO_BANK 6 +#define TICOFF_TARGET_ARCH bfd_arch_tic4x +/* We use COFF2. */ +#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC + +#define TICOFF_TARGET_MACHINE_GET(FLAGS) \ + (((FLAGS) & F_VERS) ? bfd_mach_tic4x : bfd_mach_tic3x) + +#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) \ + do \ + { \ + if ((MACHINE) == bfd_mach_tic4x) \ + *(FLAGSP) |= F_VERS; \ + } \ + while (0) + +#include "coff/ti.h" + +#endif /* COFF_TIC4X_H */ diff --git a/include/coff/tic54x.h b/include/coff/tic54x.h new file mode 100644 index 000000000..a7b7003a9 --- /dev/null +++ b/include/coff/tic54x.h @@ -0,0 +1,59 @@ +/* TI COFF information for Texas Instruments TMS320C54X. + This file customizes the settings in coff/ti.h. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef COFF_TIC54X_H +#define COFF_TIC54X_H + +#define TIC54X_TARGET_ID 0x98 +#define TIC54XALGMAGIC 0x009B /* c54x algebraic assembler output */ +#define TIC5X_TARGET_ID 0x92 +#define TI_TARGET_ID TIC54X_TARGET_ID +#define OCTETS_PER_BYTE_POWER 1 /* octets per byte, as a power of two */ +#define HOWTO_BANK 6 /* add to howto to get absolute/sect-relative version */ +#define TICOFF_TARGET_ARCH bfd_arch_tic54x +#define TICOFF_DEFAULT_MAGIC TICOFF1MAGIC /* we use COFF1 for compatibility */ + +/* Page macros + + The first GDB port requires flags in its remote memory access commands to + distinguish between data/prog space. Hopefully we can make this go away + eventually. Stuff the page in the upper bits of a 32-bit address, since + the c5x family only uses 16 or 23 bits. + + c2x, c5x and most c54x devices have 16-bit addresses, but the c548 has + 23-bit program addresses. Make sure the page flags don't interfere. + These flags are used by GDB to identify the destination page for + addresses. +*/ + +/* Recognized load pages (by common convention). */ +#define PG_PROG 0x0 /* PROG page */ +#define PG_DATA 0x1 /* DATA page */ +#define PG_IO 0x2 /* I/O page */ + +/** Indicate whether the given storage class requires a page flag. */ +#define NEEDS_PAGE(X) ((X)==C_EXT) +#define PAGE_MASK 0xFF000000 +#define ADDR_MASK 0x00FFFFFF +#define PG_TO_FLAG(p) (((unsigned long)(p) & 0xFF) << 24) +#define FLAG_TO_PG(f) (((f) >> 24) & 0xFF) + +#include "coff/ti.h" + +#endif /* COFF_TIC54X_H */ diff --git a/include/coff/tic80.h b/include/coff/tic80.h new file mode 100644 index 000000000..c9347eb9e --- /dev/null +++ b/include/coff/tic80.h @@ -0,0 +1,122 @@ +/* coff information for TI TMS320C80 (MVP) + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DO_NOT_DEFINE_FILHDR +#define DO_NOT_DEFINE_SCNHDR +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/********************** FILE HEADER **********************/ + +struct external_filehdr + { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_target_id[2];/* target id (TIc80 specific) */ +}; + +#define TIC80_ARCH_MAGIC 0x0C1 /* Goes in the file header magic number field */ +#define TIC80_TARGET_ID 0x95 /* Goes in the target id field */ + +#define TIC80BADMAG(x) ((x).f_magic != TIC80_ARCH_MAGIC) + +#define FILHDR struct external_filehdr +#define FILHSZ 22 + +#define TIC80_AOUTHDR_MAGIC 0x108 /* Goes in the optional file header magic number field */ + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[2]; /* flags */ + char s_reserved[1]; /* reserved (TIc80 specific) */ + char s_mempage[1]; /* memory page number (TIc80) */ +}; + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _CINIT ".cinit" +#define _CONST ".const" +#define _SWITCH ".switch" +#define _STACK ".stack" +#define _SYSMEM ".sysmem" + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* FIXME - need to correlate external_auxent with + TIc80 Code Generation Tools User's Guide, CG:A-25 */ + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_reserved[2]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 12 + +/* TIc80 relocation types. */ + +#define R_ABS 0x00 /* Absolute address - no relocation */ +#define R_RELLONGX 0x11 /* PP: 32 bits, direct */ +#define R_PPBASE 0x34 /* PP: Global base address type */ +#define R_PPLBASE 0x35 /* PP: Local base address type */ +#define R_PP15 0x38 /* PP: Global 15 bit offset */ +#define R_PP15W 0x39 /* PP: Global 15 bit offset divided by 4 */ +#define R_PP15H 0x3A /* PP: Global 15 bit offset divided by 2 */ +#define R_PP16B 0x3B /* PP: Global 16 bit offset for bytes */ +#define R_PPL15 0x3C /* PP: Local 15 bit offset */ +#define R_PPL15W 0x3D /* PP: Local 15 bit offset divided by 4 */ +#define R_PPL15H 0x3E /* PP: Local 15 bit offset divided by 2 */ +#define R_PPL16B 0x3F /* PP: Local 16 bit offset for bytes */ +#define R_PPN15 0x40 /* PP: Global 15 bit negative offset */ +#define R_PPN15W 0x41 /* PP: Global 15 bit negative offset divided by 4 */ +#define R_PPN15H 0x42 /* PP: Global 15 bit negative offset divided by 2 */ +#define R_PPN16B 0x43 /* PP: Global 16 bit negative byte offset */ +#define R_PPLN15 0x44 /* PP: Local 15 bit negative offset */ +#define R_PPLN15W 0x45 /* PP: Local 15 bit negative offset divided by 4 */ +#define R_PPLN15H 0x46 /* PP: Local 15 bit negative offset divided by 2 */ +#define R_PPLN16B 0x47 /* PP: Local 16 bit negative byte offset */ +#define R_MPPCR15W 0x4E /* MP: 15 bit PC-relative divided by 4 */ +#define R_MPPCR 0x4F /* MP: 32 bit PC-relative divided by 4 */ diff --git a/include/coff/w65.h b/include/coff/w65.h new file mode 100644 index 000000000..0baa3d39b --- /dev/null +++ b/include/coff/w65.h @@ -0,0 +1,46 @@ +/* coff information for WDC 65816 + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define W65MAGIC 0x6500 + +#define W65BADMAG(x) (((x).f_magic != W65MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the w65 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/include/coff/we32k.h b/include/coff/we32k.h new file mode 100644 index 000000000..7e2791c27 --- /dev/null +++ b/include/coff/we32k.h @@ -0,0 +1,60 @@ +/* coff information for we32k + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) +#define F_BM32B (0020000) +#define F_BM32MAU (0040000) + +#define WE32KMAGIC 0x170 /* we32k sans transfer vector */ +#define FBOMAGIC 0x170 /* we32k sans transfer vector */ +#define MTVMAGIC 0x171 /* we32k with transfer vector */ +#define RBOMAGIC 0x172 /* reserved */ +#define WE32KBADMAG(x) ( ((x).f_magic != WE32KMAGIC) \ + && ((x).f_magic != FBOMAGIC) \ + && ((x).f_magic != RBOMAGIC) \ + && ((x).f_magic != MTVMAGIC)) + +/* More names of "special" sections. */ +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/include/coff/xcoff.h b/include/coff/xcoff.h new file mode 100644 index 000000000..64a9ee164 --- /dev/null +++ b/include/coff/xcoff.h @@ -0,0 +1,639 @@ +/* Internal format of XCOFF object file data structures for BFD. + + Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + Written by Ian Lance Taylor <ian@cygnus.com>, Cygnus Support. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _INTERNAL_XCOFF_H +#define _INTERNAL_XCOFF_H + +/* Linker */ + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _PAD ".pad" +#define _LOADER ".loader" +#define _EXCEPT ".except" +#define _TYPCHK ".typchk" + +/* XCOFF uses a special .loader section with type STYP_LOADER. */ +#define STYP_LOADER 0x1000 + +/* XCOFF uses a special .debug section with type STYP_DEBUG. */ +#define STYP_DEBUG 0x2000 + +/* XCOFF handles line number or relocation overflow by creating + another section header with STYP_OVRFLO set. */ +#define STYP_OVRFLO 0x8000 + +/* Specifies an exception section. A section of this type provides + information to identify the reason that a trap or ececptin occured within + and executable object program */ +#define STYP_EXCEPT 0x0100 + +/* Specifies a type check section. A section of this type contains parameter + argument type check strings used by the AIX binder. */ +#define STYP_TYPCHK 0x4000 + +#define RS6K_AOUTHDR_OMAGIC 0x0107 /* old: text & data writeable */ +#define RS6K_AOUTHDR_NMAGIC 0x0108 /* new: text r/o, data r/w */ +#define RS6K_AOUTHDR_ZMAGIC 0x010B /* paged: text r/o, both page-aligned */ + +/* XCOFF relocation types. + The relocations are described in the function + xcoff[64]_ppc_relocate_section in coff64-rs6000.c and coff-rs6000.c */ + +#define R_POS (0x00) +#define R_NEG (0x01) +#define R_REL (0x02) +#define R_TOC (0x03) +#define R_RTB (0x04) +#define R_GL (0x05) +#define R_TCL (0x06) +#define R_BA (0x08) +#define R_BR (0x0a) +#define R_RL (0x0c) +#define R_RLA (0x0d) +#define R_REF (0x0f) +#define R_TRL (0x12) +#define R_TRLA (0x13) +#define R_RRTBI (0x14) +#define R_RRTBA (0x15) +#define R_CAI (0x16) +#define R_CREL (0x17) +#define R_RBA (0x18) +#define R_RBAC (0x19) +#define R_RBR (0x1a) +#define R_RBRC (0x1b) + +/* Storage class #defines, from /usr/include/storclass.h that are not already + defined in internal.h */ + +/* Comment string in .info section */ +#define C_INFO 110 + +/* Auxillary Symbol Entries */ + +/* x_smtyp values: */ +#define SMTYP_ALIGN(x) ((x) >> 3) /* log2 of alignment */ +#define SMTYP_SMTYP(x) ((x) & 0x7) /* symbol type */ +/* Symbol type values: */ +#define XTY_ER 0 /* External reference */ +#define XTY_SD 1 /* Csect definition */ +#define XTY_LD 2 /* Label definition */ +#define XTY_CM 3 /* .BSS */ +#define XTY_EM 4 /* Error message */ +#define XTY_US 5 /* "Reserved for internal use" */ + +/* x_smclas values: */ +#define XMC_PR 0 /* Read-only program code */ +#define XMC_RO 1 /* Read-only constant */ +#define XMC_DB 2 /* Read-only debug dictionary table */ +#define XMC_TC 3 /* Read-write general TOC entry */ +#define XMC_UA 4 /* Read-write unclassified */ +#define XMC_RW 5 /* Read-write data */ +#define XMC_GL 6 /* Read-only global linkage */ +#define XMC_XO 7 /* Read-only extended operation */ +#define XMC_SV 8 /* Read-only supervisor call */ +#define XMC_BS 9 /* Read-write BSS */ +#define XMC_DS 10 /* Read-write descriptor csect */ +#define XMC_UC 11 /* Read-write unnamed Fortran common */ +#define XMC_TI 12 /* Read-only traceback index csect */ +#define XMC_TB 13 /* Read-only traceback table csect */ +/* 14 ??? */ +#define XMC_TC0 15 /* Read-write TOC anchor */ +#define XMC_TD 16 /* Read-write data in TOC */ +#define XMC_SV64 17 /* Read-only 64 bit supervisor call */ +#define XMC_SV3264 18 /* Read-only 32 or 64 bit supervisor call */ + +/* The ldhdr structure. This appears at the start of the .loader + section. */ + +struct internal_ldhdr +{ + /* The version number: + 1 : 32 bit + 2 : 64 bit */ + unsigned long l_version; + + /* The number of symbol table entries. */ + bfd_size_type l_nsyms; + + /* The number of relocation table entries. */ + bfd_size_type l_nreloc; + + /* The length of the import file string table. */ + bfd_size_type l_istlen; + + /* The number of import files. */ + bfd_size_type l_nimpid; + + /* The offset from the start of the .loader section to the first + entry in the import file table. */ + bfd_size_type l_impoff; + + /* The length of the string table. */ + bfd_size_type l_stlen; + + /* The offset from the start of the .loader section to the first + entry in the string table. */ + bfd_size_type l_stoff; + + /* The offset to start of the symbol table, only in XCOFF64 */ + bfd_vma l_symoff; + + /* The offset to the start of the relocation table, only in XCOFF64 */ + bfd_vma l_rldoff; +}; + +/* The ldsym structure. This is used to represent a symbol in the + .loader section. */ + +struct internal_ldsym +{ + union + { + /* The symbol name if <= SYMNMLEN characters. */ + char _l_name[SYMNMLEN]; + struct + { + /* Zero if the symbol name is more than SYMNMLEN characters. */ + long _l_zeroes; + + /* The offset in the string table if the symbol name is more + than SYMNMLEN characters. */ + long _l_offset; + } + _l_l; + } + _l; + + /* The symbol value. */ + bfd_vma l_value; + + /* The symbol section number. */ + short l_scnum; + + /* The symbol type and flags. */ + char l_smtype; + + /* The symbol storage class. */ + char l_smclas; + + /* The import file ID. */ + bfd_size_type l_ifile; + + /* Offset to the parameter type check string. */ + bfd_size_type l_parm; +}; + +/* These flags are for the l_smtype field (the lower three bits are an + XTY_* value). */ + +/* Imported symbol. */ +#define L_IMPORT (0x40) +/* Entry point. */ +#define L_ENTRY (0x20) +/* Exported symbol. */ +#define L_EXPORT (0x10) + +/* The ldrel structure. This is used to represent a reloc in the + .loader section. */ + +struct internal_ldrel +{ + /* The reloc address. */ + bfd_vma l_vaddr; + + /* The symbol table index in the .loader section symbol table. */ + bfd_size_type l_symndx; + + /* The relocation type and size. */ + short l_rtype; + + /* The section number this relocation applies to. */ + short l_rsecnm; +}; + +/* An entry in the XCOFF linker hash table. */ +struct xcoff_link_hash_entry +{ + struct bfd_link_hash_entry root; + + /* Symbol index in output file. Set to -1 initially. Set to -2 if + there is a reloc against this symbol. */ + long indx; + + /* If we have created a TOC entry for this symbol, this is the .tc + section which holds it. */ + asection *toc_section; + + union + { + /* If we have created a TOC entry (the XCOFF_SET_TOC flag is + set), this is the offset in toc_section. */ + bfd_vma toc_offset; + + /* If the TOC entry comes from an input file, this is set to the + symbol index of the C_HIDEXT XMC_TC or XMC_TD symbol. */ + long toc_indx; + } + u; + + /* If this symbol is a function entry point which is called, this + field holds a pointer to the function descriptor. If this symbol + is a function descriptor, this field holds a pointer to the + function entry point. */ + struct xcoff_link_hash_entry *descriptor; + + /* The .loader symbol table entry, if there is one. */ + struct internal_ldsym *ldsym; + + /* If XCOFF_BUILT_LDSYM is set, this is the .loader symbol table + index. If XCOFF_BUILD_LDSYM is clear, and XCOFF_IMPORT is set, + this is the l_ifile value. */ + long ldindx; + + /* Some linker flags. */ + unsigned long flags; + + /* The storage mapping class. */ + unsigned char smclas; +}; + +/* Flags for xcoff_link_hash_entry. */ + +/* Symbol is referenced by a regular object. */ +#define XCOFF_REF_REGULAR 0x00000001 +/* Symbol is defined by a regular object. */ +#define XCOFF_DEF_REGULAR 0x00000002 +/* Symbol is defined by a dynamic object. */ +#define XCOFF_DEF_DYNAMIC 0x00000004 +/* Symbol is used in a reloc being copied into the .loader section. */ +#define XCOFF_LDREL 0x00000008 +/* Symbol is the entry point. */ +#define XCOFF_ENTRY 0x00000010 +/* Symbol is called; this is, it appears in a R_BR reloc. */ +#define XCOFF_CALLED 0x00000020 +/* Symbol needs the TOC entry filled in. */ +#define XCOFF_SET_TOC 0x00000040 +/* Symbol is explicitly imported. */ +#define XCOFF_IMPORT 0x00000080 +/* Symbol is explicitly exported. */ +#define XCOFF_EXPORT 0x00000100 +/* Symbol has been processed by xcoff_build_ldsyms. */ +#define XCOFF_BUILT_LDSYM 0x00000200 +/* Symbol is mentioned by a section which was not garbage collected. */ +#define XCOFF_MARK 0x00000400 +/* Symbol size is recorded in size_list list from hash table. */ +#define XCOFF_HAS_SIZE 0x00000800 +/* Symbol is a function descriptor. */ +#define XCOFF_DESCRIPTOR 0x00001000 +/* Multiple definitions have been for the symbol. */ +#define XCOFF_MULTIPLY_DEFINED 0x00002000 +/* Symbol is the __rtinit symbol. */ +#define XCOFF_RTINIT 0x00004000 +/* Symbol is an imported 32 bit syscall. */ +#define XCOFF_SYSCALL32 0x00008000 +/* Symbol is an imported 64 bit syscall. */ +#define XCOFF_SYSCALL64 0x00010000 + +/* The XCOFF linker hash table. */ + +#define XCOFF_NUMBER_OF_SPECIAL_SECTIONS 6 +#define XCOFF_SPECIAL_SECTION_TEXT 0 +#define XCOFF_SPECIAL_SECTION_ETEXT 1 +#define XCOFF_SPECIAL_SECTION_DATA 2 +#define XCOFF_SPECIAL_SECTION_EDATA 3 +#define XCOFF_SPECIAL_SECTION_END 4 +#define XCOFF_SPECIAL_SECTION_END2 5 + +struct xcoff_link_hash_table +{ + struct bfd_link_hash_table root; + + /* The .debug string hash table. We need to compute this while + reading the input files, so that we know how large the .debug + section will be before we assign section positions. */ + struct bfd_strtab_hash *debug_strtab; + + /* The .debug section we will use for the final output. */ + asection *debug_section; + + /* The .loader section we will use for the final output. */ + asection *loader_section; + + /* A count of non TOC relative relocs which will need to be + allocated in the .loader section. */ + size_t ldrel_count; + + /* The .loader section header. */ + struct internal_ldhdr ldhdr; + + /* The .gl section we use to hold global linkage code. */ + asection *linkage_section; + + /* The .tc section we use to hold toc entries we build for global + linkage code. */ + asection *toc_section; + + /* The .ds section we use to hold function descriptors which we + create for exported symbols. */ + asection *descriptor_section; + + /* The list of import files. */ + struct xcoff_import_file *imports; + + /* Required alignment of sections within the output file. */ + unsigned long file_align; + + /* Whether the .text section must be read-only. */ + bfd_boolean textro; + + /* Whether garbage collection was done. */ + bfd_boolean gc; + + /* A linked list of symbols for which we have size information. */ + struct xcoff_link_size_list + { + struct xcoff_link_size_list *next; + struct xcoff_link_hash_entry *h; + bfd_size_type size; + } + *size_list; + + /* Magic sections: _text, _etext, _data, _edata, _end, end. */ + asection *special_sections[XCOFF_NUMBER_OF_SPECIAL_SECTIONS]; +}; + + +/* This structure is used to pass information through + xcoff_link_hash_traverse. */ + +struct xcoff_loader_info +{ + /* Set if a problem occurred. */ + bfd_boolean failed; + + /* Output BFD. */ + bfd *output_bfd; + + /* Link information structure. */ + struct bfd_link_info *info; + + /* Whether all defined symbols should be exported. */ + bfd_boolean export_defineds; + + /* Number of ldsym structures. */ + size_t ldsym_count; + + /* Size of string table. */ + size_t string_size; + + /* String table. */ + bfd_byte *strings; + + /* Allocated size of string table. */ + size_t string_alc; +}; + +/* In case we're on a 32-bit machine, construct a 64-bit "-1" value + from smaller values. Start with zero, widen, *then* decrement. */ +#define MINUS_ONE (((bfd_vma) 0) - 1) + +/* __rtinit, from /usr/include/rtinit.h. */ +struct __rtinit +{ + /* Pointer to runtime linker. + XXX: Is the parameter really void? */ + int (*rtl) (void); + + /* Offset to array of init functions, 0 if none. */ + int init_offset; + + /* Offset to array of fini functions, 0 if none. */ + int fini_offset; + + /* Size of __RTINIT_DESCRIPTOR. This value should be used instead of + sizeof(__RTINIT_DESCRIPTOR). */ + int __rtinit_descriptor_size; +}; + +#define RTINIT_DESCRIPTOR_SIZE (12) + +struct __rtinit_descriptor +{ + /* Init/fini function. */ + int f; + + /* Offset, relative to the start of the __rtinit symbol, to name of the + function. */ + + int name_offset; + + /* Flags */ + unsigned char flags; +}; + +/* Archive */ + +#define XCOFFARMAG "<aiaff>\012" +#define XCOFFARMAGBIG "<bigaf>\012" +#define SXCOFFARMAG 8 + +/* The size of the ascii archive elements */ +#define XCOFFARMAG_ELEMENT_SIZE 12 +#define XCOFFARMAGBIG_ELEMENT_SIZE 20 + +/* This terminates an XCOFF archive member name. */ + +#define XCOFFARFMAG "`\012" +#define SXCOFFARFMAG 2 + +/* XCOFF archives start with this (printable) structure. */ + +struct xcoff_ar_file_hdr +{ + /* Magic string. */ + char magic[SXCOFFARMAG]; + + /* Offset of the member table (decimal ASCII string). */ + char memoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* Offset of the global symbol table (decimal ASCII string). */ + char symoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* Offset of the first member in the archive (decimal ASCII string). */ + char firstmemoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* Offset of the last member in the archive (decimal ASCII string). */ + char lastmemoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* Offset of the first member on the free list (decimal ASCII + string). */ + char freeoff[XCOFFARMAG_ELEMENT_SIZE]; +}; + +#define SIZEOF_AR_FILE_HDR (SXCOFFARMAG + 5 * XCOFFARMAG_ELEMENT_SIZE) + +/* This is the equivalent data structure for the big archive format. */ + +struct xcoff_ar_file_hdr_big +{ + /* Magic string. */ + char magic[SXCOFFARMAG]; + + /* Offset of the member table (decimal ASCII string). */ + char memoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the global symbol table for 32-bit objects (decimal ASCII + string). */ + char symoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the global symbol table for 64-bit objects (decimal ASCII + string). */ + char symoff64[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the first member in the archive (decimal ASCII string). */ + char firstmemoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the last member in the archive (decimal ASCII string). */ + char lastmemoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the first member on the free list (decimal ASCII + string). */ + char freeoff[XCOFFARMAGBIG_ELEMENT_SIZE]; +}; + +#define SIZEOF_AR_FILE_HDR_BIG (SXCOFFARMAG + 6 * XCOFFARMAGBIG_ELEMENT_SIZE) + +/* Each XCOFF archive member starts with this (printable) structure. */ + +struct xcoff_ar_hdr +{ + /* File size not including the header (decimal ASCII string). */ + char size[XCOFFARMAG_ELEMENT_SIZE]; + + /* File offset of next archive member (decimal ASCII string). */ + char nextoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* File offset of previous archive member (decimal ASCII string). */ + char prevoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* File mtime (decimal ASCII string). */ + char date[12]; + + /* File UID (decimal ASCII string). */ + char uid[12]; + + /* File GID (decimal ASCII string). */ + char gid[12]; + + /* File mode (octal ASCII string). */ + char mode[12]; + + /* Length of file name (decimal ASCII string). */ + char namlen[4]; + + /* This structure is followed by the file name. The length of the + name is given in the namlen field. If the length of the name is + odd, the name is followed by a null byte. The name and optional + null byte are followed by XCOFFARFMAG, which is not included in + namlen. The contents of the archive member follow; the number of + bytes is given in the size field. */ +}; + +#define SIZEOF_AR_HDR (3 * XCOFFARMAG_ELEMENT_SIZE + 4 * 12 + 4) + +/* The equivalent for the big archive format. */ + +struct xcoff_ar_hdr_big +{ + /* File size not including the header (decimal ASCII string). */ + char size[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* File offset of next archive member (decimal ASCII string). */ + char nextoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* File offset of previous archive member (decimal ASCII string). */ + char prevoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* File mtime (decimal ASCII string). */ + char date[12]; + + /* File UID (decimal ASCII string). */ + char uid[12]; + + /* File GID (decimal ASCII string). */ + char gid[12]; + + /* File mode (octal ASCII string). */ + char mode[12]; + + /* Length of file name (decimal ASCII string). */ + char namlen[4]; + + /* This structure is followed by the file name. The length of the + name is given in the namlen field. If the length of the name is + odd, the name is followed by a null byte. The name and optional + null byte are followed by XCOFFARFMAG, which is not included in + namlen. The contents of the archive member follow; the number of + bytes is given in the size field. */ +}; + +#define SIZEOF_AR_HDR_BIG (3 * XCOFFARMAGBIG_ELEMENT_SIZE + 4 * 12 + 4) + +/* We often have to distinguish between the old and big file format. + Make it a bit cleaner. We can use `xcoff_ardata' here because the + `hdr' member has the same size and position in both formats. + <bigaf> is the default format, return TRUE even when xcoff_ardata is + NULL. */ +#ifndef SMALL_ARCHIVE +/* Creates big archives by default */ +#define xcoff_big_format_p(abfd) \ + ((NULL != bfd_ardata (abfd) && NULL == xcoff_ardata (abfd)) || \ + ((NULL != bfd_ardata (abfd)) && \ + (NULL != xcoff_ardata (abfd)) && \ + (xcoff_ardata (abfd)->magic[1] == 'b'))) +#else +/* Creates small archives by default. */ +#define xcoff_big_format_p(abfd) \ + (((NULL != bfd_ardata (abfd)) && \ + (NULL != xcoff_ardata (abfd)) && \ + (xcoff_ardata (abfd)->magic[1] == 'b'))) +#endif + +/* We store a copy of the xcoff_ar_file_hdr in the tdata field of the + artdata structure. Similar for the big archive. */ +#define xcoff_ardata(abfd) \ + ((struct xcoff_ar_file_hdr *) bfd_ardata (abfd)->tdata) +#define xcoff_ardata_big(abfd) \ + ((struct xcoff_ar_file_hdr_big *) bfd_ardata (abfd)->tdata) + +/* We store a copy of the xcoff_ar_hdr in the arelt_data field of an + archive element. Similar for the big archive. */ +#define arch_eltdata(bfd) ((struct areltdata *) ((bfd)->arelt_data)) +#define arch_xhdr(bfd) \ + ((struct xcoff_ar_hdr *) arch_eltdata (bfd)->arch_header) +#define arch_xhdr_big(bfd) \ + ((struct xcoff_ar_hdr_big *) arch_eltdata (bfd)->arch_header) + +#endif /* _INTERNAL_XCOFF_H */ diff --git a/include/coff/z8k.h b/include/coff/z8k.h new file mode 100644 index 000000000..50cbd6b3a --- /dev/null +++ b/include/coff/z8k.h @@ -0,0 +1,48 @@ +/* coff information for Zilog Z800N + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +/* Type of cpu is stored in flags */ +#define F_Z8001 0x1000 +#define F_Z8002 0x2000 +#define F_MACHMASK 0xf000 + +#define Z8KMAGIC 0x8000 + +#define Z8KBADMAG(x) (((x).f_magic != Z8KMAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the z8k don't have room in the instruction for the entire + offset - eg with segments. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + diff --git a/include/demangle.h b/include/demangle.h new file mode 100644 index 000000000..b3b8c58c5 --- /dev/null +++ b/include/demangle.h @@ -0,0 +1,533 @@ +/* Defs for interface to demanglers. + Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, + 2003, 2004 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + + +#if !defined (DEMANGLE_H) +#define DEMANGLE_H + +#include "libiberty.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Options passed to cplus_demangle (in 2nd parameter). */ + +#define DMGL_NO_OPTS 0 /* For readability... */ +#define DMGL_PARAMS (1 << 0) /* Include function args */ +#define DMGL_ANSI (1 << 1) /* Include const, volatile, etc */ +#define DMGL_JAVA (1 << 2) /* Demangle as Java rather than C++. */ +#define DMGL_VERBOSE (1 << 3) /* Include implementation details. */ +#define DMGL_TYPES (1 << 4) /* Also try to demangle type encodings. */ + +#define DMGL_AUTO (1 << 8) +#define DMGL_GNU (1 << 9) +#define DMGL_LUCID (1 << 10) +#define DMGL_ARM (1 << 11) +#define DMGL_HP (1 << 12) /* For the HP aCC compiler; + same as ARM except for + template arguments, etc. */ +#define DMGL_EDG (1 << 13) +#define DMGL_GNU_V3 (1 << 14) +#define DMGL_GNAT (1 << 15) + +/* If none of these are set, use 'current_demangling_style' as the default. */ +#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT) + +/* Enumeration of possible demangling styles. + + Lucid and ARM styles are still kept logically distinct, even though + they now both behave identically. The resulting style is actual the + union of both. I.E. either style recognizes both "__pt__" and "__rf__" + for operator "->", even though the first is lucid style and the second + is ARM style. (FIXME?) */ + +extern enum demangling_styles +{ + no_demangling = -1, + unknown_demangling = 0, + auto_demangling = DMGL_AUTO, + gnu_demangling = DMGL_GNU, + lucid_demangling = DMGL_LUCID, + arm_demangling = DMGL_ARM, + hp_demangling = DMGL_HP, + edg_demangling = DMGL_EDG, + gnu_v3_demangling = DMGL_GNU_V3, + java_demangling = DMGL_JAVA, + gnat_demangling = DMGL_GNAT +} current_demangling_style; + +/* Define string names for the various demangling styles. */ + +#define NO_DEMANGLING_STYLE_STRING "none" +#define AUTO_DEMANGLING_STYLE_STRING "auto" +#define GNU_DEMANGLING_STYLE_STRING "gnu" +#define LUCID_DEMANGLING_STYLE_STRING "lucid" +#define ARM_DEMANGLING_STYLE_STRING "arm" +#define HP_DEMANGLING_STYLE_STRING "hp" +#define EDG_DEMANGLING_STYLE_STRING "edg" +#define GNU_V3_DEMANGLING_STYLE_STRING "gnu-v3" +#define JAVA_DEMANGLING_STYLE_STRING "java" +#define GNAT_DEMANGLING_STYLE_STRING "gnat" + +/* Some macros to test what demangling style is active. */ + +#define CURRENT_DEMANGLING_STYLE current_demangling_style +#define AUTO_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_AUTO) +#define GNU_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU) +#define LUCID_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_LUCID) +#define ARM_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_ARM) +#define HP_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_HP) +#define EDG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_EDG) +#define GNU_V3_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU_V3) +#define JAVA_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_JAVA) +#define GNAT_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNAT) + +/* Provide information about the available demangle styles. This code is + pulled from gdb into libiberty because it is useful to binutils also. */ + +extern const struct demangler_engine +{ + const char *const demangling_style_name; + const enum demangling_styles demangling_style; + const char *const demangling_style_doc; +} libiberty_demanglers[]; + +extern char * +cplus_demangle PARAMS ((const char *mangled, int options)); + +extern int +cplus_demangle_opname PARAMS ((const char *opname, char *result, int options)); + +extern const char * +cplus_mangle_opname PARAMS ((const char *opname, int options)); + +/* Note: This sets global state. FIXME if you care about multi-threading. */ + +extern void +set_cplus_marker_for_demangling PARAMS ((int ch)); + +extern enum demangling_styles +cplus_demangle_set_style PARAMS ((enum demangling_styles style)); + +extern enum demangling_styles +cplus_demangle_name_to_style PARAMS ((const char *name)); + +/* V3 ABI demangling entry points, defined in cp-demangle.c. */ +extern char* +cplus_demangle_v3 PARAMS ((const char* mangled, int options)); + +extern char* +java_demangle_v3 PARAMS ((const char* mangled)); + + +enum gnu_v3_ctor_kinds { + gnu_v3_complete_object_ctor = 1, + gnu_v3_base_object_ctor, + gnu_v3_complete_object_allocating_ctor +}; + +/* Return non-zero iff NAME is the mangled form of a constructor name + in the G++ V3 ABI demangling style. Specifically, return an `enum + gnu_v3_ctor_kinds' value indicating what kind of constructor + it is. */ +extern enum gnu_v3_ctor_kinds + is_gnu_v3_mangled_ctor PARAMS ((const char *name)); + + +enum gnu_v3_dtor_kinds { + gnu_v3_deleting_dtor = 1, + gnu_v3_complete_object_dtor, + gnu_v3_base_object_dtor +}; + +/* Return non-zero iff NAME is the mangled form of a destructor name + in the G++ V3 ABI demangling style. Specifically, return an `enum + gnu_v3_dtor_kinds' value, indicating what kind of destructor + it is. */ +extern enum gnu_v3_dtor_kinds + is_gnu_v3_mangled_dtor PARAMS ((const char *name)); + +/* The V3 demangler works in two passes. The first pass builds a tree + representation of the mangled name, and the second pass turns the + tree representation into a demangled string. Here we define an + interface to permit a caller to build their own tree + representation, which they can pass to the demangler to get a + demangled string. This can be used to canonicalize user input into + something which the demangler might output. It could also be used + by other demanglers in the future. */ + +/* These are the component types which may be found in the tree. Many + component types have one or two subtrees, referred to as left and + right (a component type with only one subtree puts it in the left + subtree). */ + +enum demangle_component_type +{ + /* A name, with a length and a pointer to a string. */ + DEMANGLE_COMPONENT_NAME, + /* A qualified name. The left subtree is a class or namespace or + some such thing, and the right subtree is a name qualified by + that class. */ + DEMANGLE_COMPONENT_QUAL_NAME, + /* A local name. The left subtree describes a function, and the + right subtree is a name which is local to that function. */ + DEMANGLE_COMPONENT_LOCAL_NAME, + /* A typed name. The left subtree is a name, and the right subtree + describes that name as a function. */ + DEMANGLE_COMPONENT_TYPED_NAME, + /* A template. The left subtree is a template name, and the right + subtree is a template argument list. */ + DEMANGLE_COMPONENT_TEMPLATE, + /* A template parameter. This holds a number, which is the template + parameter index. */ + DEMANGLE_COMPONENT_TEMPLATE_PARAM, + /* A constructor. This holds a name and the kind of + constructor. */ + DEMANGLE_COMPONENT_CTOR, + /* A destructor. This holds a name and the kind of destructor. */ + DEMANGLE_COMPONENT_DTOR, + /* A vtable. This has one subtree, the type for which this is a + vtable. */ + DEMANGLE_COMPONENT_VTABLE, + /* A VTT structure. This has one subtree, the type for which this + is a VTT. */ + DEMANGLE_COMPONENT_VTT, + /* A construction vtable. The left subtree is the type for which + this is a vtable, and the right subtree is the derived type for + which this vtable is built. */ + DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE, + /* A typeinfo structure. This has one subtree, the type for which + this is the tpeinfo structure. */ + DEMANGLE_COMPONENT_TYPEINFO, + /* A typeinfo name. This has one subtree, the type for which this + is the typeinfo name. */ + DEMANGLE_COMPONENT_TYPEINFO_NAME, + /* A typeinfo function. This has one subtree, the type for which + this is the tpyeinfo function. */ + DEMANGLE_COMPONENT_TYPEINFO_FN, + /* A thunk. This has one subtree, the name for which this is a + thunk. */ + DEMANGLE_COMPONENT_THUNK, + /* A virtual thunk. This has one subtree, the name for which this + is a virtual thunk. */ + DEMANGLE_COMPONENT_VIRTUAL_THUNK, + /* A covariant thunk. This has one subtree, the name for which this + is a covariant thunk. */ + DEMANGLE_COMPONENT_COVARIANT_THUNK, + /* A Java class. This has one subtree, the type. */ + DEMANGLE_COMPONENT_JAVA_CLASS, + /* A guard variable. This has one subtree, the name for which this + is a guard variable. */ + DEMANGLE_COMPONENT_GUARD, + /* A reference temporary. This has one subtree, the name for which + this is a temporary. */ + DEMANGLE_COMPONENT_REFTEMP, + /* A standard substitution. This holds the name of the + substitution. */ + DEMANGLE_COMPONENT_SUB_STD, + /* The restrict qualifier. The one subtree is the type which is + being qualified. */ + DEMANGLE_COMPONENT_RESTRICT, + /* The volatile qualifier. The one subtree is the type which is + being qualified. */ + DEMANGLE_COMPONENT_VOLATILE, + /* The const qualifier. The one subtree is the type which is being + qualified. */ + DEMANGLE_COMPONENT_CONST, + /* The restrict qualifier modifying a member function. The one + subtree is the type which is being qualified. */ + DEMANGLE_COMPONENT_RESTRICT_THIS, + /* The volatile qualifier modifying a member function. The one + subtree is the type which is being qualified. */ + DEMANGLE_COMPONENT_VOLATILE_THIS, + /* The const qualifier modifying a member function. The one subtree + is the type which is being qualified. */ + DEMANGLE_COMPONENT_CONST_THIS, + /* A vendor qualifier. The left subtree is the type which is being + qualified, and the right subtree is the name of the + qualifier. */ + DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL, + /* A pointer. The one subtree is the type which is being pointed + to. */ + DEMANGLE_COMPONENT_POINTER, + /* A reference. The one subtree is the type which is being + referenced. */ + DEMANGLE_COMPONENT_REFERENCE, + /* A complex type. The one subtree is the base type. */ + DEMANGLE_COMPONENT_COMPLEX, + /* An imaginary type. The one subtree is the base type. */ + DEMANGLE_COMPONENT_IMAGINARY, + /* A builtin type. This holds the builtin type information. */ + DEMANGLE_COMPONENT_BUILTIN_TYPE, + /* A vendor's builtin type. This holds the name of the type. */ + DEMANGLE_COMPONENT_VENDOR_TYPE, + /* A function type. The left subtree is the return type. The right + subtree is a list of ARGLIST nodes. Either or both may be + NULL. */ + DEMANGLE_COMPONENT_FUNCTION_TYPE, + /* An array type. The left subtree is the dimension, which may be + NULL, or a string (represented as DEMANGLE_COMPONENT_NAME), or an + expression. The right subtree is the element type. */ + DEMANGLE_COMPONENT_ARRAY_TYPE, + /* A pointer to member type. The left subtree is the class type, + and the right subtree is the member type. CV-qualifiers appear + on the latter. */ + DEMANGLE_COMPONENT_PTRMEM_TYPE, + /* An argument list. The left subtree is the current argument, and + the right subtree is either NULL or another ARGLIST node. */ + DEMANGLE_COMPONENT_ARGLIST, + /* A template argument list. The left subtree is the current + template argument, and the right subtree is either NULL or + another TEMPLATE_ARGLIST node. */ + DEMANGLE_COMPONENT_TEMPLATE_ARGLIST, + /* An operator. This holds information about a standard + operator. */ + DEMANGLE_COMPONENT_OPERATOR, + /* An extended operator. This holds the number of arguments, and + the name of the extended operator. */ + DEMANGLE_COMPONENT_EXTENDED_OPERATOR, + /* A typecast, represented as a unary operator. The one subtree is + the type to which the argument should be cast. */ + DEMANGLE_COMPONENT_CAST, + /* A unary expression. The left subtree is the operator, and the + right subtree is the single argument. */ + DEMANGLE_COMPONENT_UNARY, + /* A binary expression. The left subtree is the operator, and the + right subtree is a BINARY_ARGS. */ + DEMANGLE_COMPONENT_BINARY, + /* Arguments to a binary expression. The left subtree is the first + argument, and the right subtree is the second argument. */ + DEMANGLE_COMPONENT_BINARY_ARGS, + /* A trinary expression. The left subtree is the operator, and the + right subtree is a TRINARY_ARG1. */ + DEMANGLE_COMPONENT_TRINARY, + /* Arguments to a trinary expression. The left subtree is the first + argument, and the right subtree is a TRINARY_ARG2. */ + DEMANGLE_COMPONENT_TRINARY_ARG1, + /* More arguments to a trinary expression. The left subtree is the + second argument, and the right subtree is the third argument. */ + DEMANGLE_COMPONENT_TRINARY_ARG2, + /* A literal. The left subtree is the type, and the right subtree + is the value, represented as a DEMANGLE_COMPONENT_NAME. */ + DEMANGLE_COMPONENT_LITERAL, + /* A negative literal. Like LITERAL, but the value is negated. + This is a minor hack: the NAME used for LITERAL points directly + to the mangled string, but since negative numbers are mangled + using 'n' instead of '-', we want a way to indicate a negative + number which involves neither modifying the mangled string nor + allocating a new copy of the literal in memory. */ + DEMANGLE_COMPONENT_LITERAL_NEG +}; + +/* Types which are only used internally. */ + +struct demangle_operator_info; +struct demangle_builtin_type_info; + +/* A node in the tree representation is an instance of a struct + demangle_component. Note that the field names of the struct are + not well protected against macros defined by the file including + this one. We can fix this if it ever becomes a problem. */ + +struct demangle_component +{ + /* The type of this component. */ + enum demangle_component_type type; + + union + { + /* For DEMANGLE_COMPONENT_NAME. */ + struct + { + /* A pointer to the name (which need not NULL terminated) and + its length. */ + const char *s; + int len; + } s_name; + + /* For DEMANGLE_COMPONENT_OPERATOR. */ + struct + { + /* Operator. */ + const struct demangle_operator_info *op; + } s_operator; + + /* For DEMANGLE_COMPONENT_EXTENDED_OPERATOR. */ + struct + { + /* Number of arguments. */ + int args; + /* Name. */ + struct demangle_component *name; + } s_extended_operator; + + /* For DEMANGLE_COMPONENT_CTOR. */ + struct + { + /* Kind of constructor. */ + enum gnu_v3_ctor_kinds kind; + /* Name. */ + struct demangle_component *name; + } s_ctor; + + /* For DEMANGLE_COMPONENT_DTOR. */ + struct + { + /* Kind of destructor. */ + enum gnu_v3_dtor_kinds kind; + /* Name. */ + struct demangle_component *name; + } s_dtor; + + /* For DEMANGLE_COMPONENT_BUILTIN_TYPE. */ + struct + { + /* Builtin type. */ + const struct demangle_builtin_type_info *type; + } s_builtin; + + /* For DEMANGLE_COMPONENT_SUB_STD. */ + struct + { + /* Standard substitution string. */ + const char* string; + /* Length of string. */ + int len; + } s_string; + + /* For DEMANGLE_COMPONENT_TEMPLATE_PARAM. */ + struct + { + /* Template parameter index. */ + long number; + } s_number; + + /* For other types. */ + struct + { + /* Left (or only) subtree. */ + struct demangle_component *left; + /* Right subtree. */ + struct demangle_component *right; + } s_binary; + + } u; +}; + +/* People building mangled trees are expected to allocate instances of + struct demangle_component themselves. They can then call one of + the following functions to fill them in. */ + +/* Fill in most component types with a left subtree and a right + subtree. Returns non-zero on success, zero on failure, such as an + unrecognized or inappropriate component type. */ + +extern int +cplus_demangle_fill_component PARAMS ((struct demangle_component *fill, + enum demangle_component_type, + struct demangle_component *left, + struct demangle_component *right)); + +/* Fill in a DEMANGLE_COMPONENT_NAME. Returns non-zero on success, + zero for bad arguments. */ + +extern int +cplus_demangle_fill_name PARAMS ((struct demangle_component *fill, + const char *, int)); + +/* Fill in a DEMANGLE_COMPONENT_BUILTIN_TYPE, using the name of the + builtin type (e.g., "int", etc.). Returns non-zero on success, + zero if the type is not recognized. */ + +extern int +cplus_demangle_fill_builtin_type PARAMS ((struct demangle_component *fill, + const char *type_name)); + +/* Fill in a DEMANGLE_COMPONENT_OPERATOR, using the name of the + operator and the number of arguments which it takes (the latter is + used to disambiguate operators which can be both binary and unary, + such as '-'). Returns non-zero on success, zero if the operator is + not recognized. */ + +extern int +cplus_demangle_fill_operator PARAMS ((struct demangle_component *fill, + const char *opname, int args)); + +/* Fill in a DEMANGLE_COMPONENT_EXTENDED_OPERATOR, providing the + number of arguments and the name. Returns non-zero on success, + zero for bad arguments. */ + +extern int +cplus_demangle_fill_extended_operator PARAMS ((struct demangle_component *fill, + int numargs, + struct demangle_component *nm)); + +/* Fill in a DEMANGLE_COMPONENT_CTOR. Returns non-zero on success, + zero for bad arguments. */ + +extern int +cplus_demangle_fill_ctor PARAMS ((struct demangle_component *fill, + enum gnu_v3_ctor_kinds kind, + struct demangle_component *name)); + +/* Fill in a DEMANGLE_COMPONENT_DTOR. Returns non-zero on success, + zero for bad arguments. */ + +extern int +cplus_demangle_fill_dtor PARAMS ((struct demangle_component *fill, + enum gnu_v3_dtor_kinds kind, + struct demangle_component *name)); + +/* This function translates a mangled name into a struct + demangle_component tree. The first argument is the mangled name. + The second argument is DMGL_* options. This returns a pointer to a + tree on success, or NULL on failure. On success, the third + argument is set to a block of memory allocated by malloc. This + block should be passed to free when the tree is no longer + needed. */ + +extern struct demangle_component * +cplus_demangle_v3_components PARAMS ((const char *mangled, + int options, + void **mem)); + +/* This function takes a struct demangle_component tree and returns + the corresponding demangled string. The first argument is DMGL_* + options. The second is the tree to demangle. The third is a guess + at the length of the demangled string, used to initially allocate + the return buffer. The fourth is a pointer to a size_t. On + success, this function returns a buffer allocated by malloc(), and + sets the size_t pointed to by the fourth argument to the size of + the allocated buffer (not the length of the returned string). On + failure, this function returns NULL, and sets the size_t pointed to + by the fourth argument to 0 for an invalid tree, or to 1 for a + memory allocation error. */ + +extern char * +cplus_demangle_print PARAMS ((int options, + const struct demangle_component *tree, + int estimated_length, + size_t *p_allocated_size)); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* DEMANGLE_H */ diff --git a/include/dis-asm.h b/include/dis-asm.h new file mode 100644 index 000000000..7171c847a --- /dev/null +++ b/include/dis-asm.h @@ -0,0 +1,318 @@ +/* Interface between the opcode library and its callers. + + Copyright 2001, 2002, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + Written by Cygnus Support, 1993. + + The opcode library (libopcodes.a) provides instruction decoders for + a large variety of instruction sets, callable with an identical + interface, for making instruction-processing programs more independent + of the instruction set being processed. */ + +#ifndef DIS_ASM_H +#define DIS_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdio.h> +#include "bfd.h" + +typedef int (*fprintf_ftype) (void *, const char*, ...); + +enum dis_insn_type { + dis_noninsn, /* Not a valid instruction */ + dis_nonbranch, /* Not a branch instruction */ + dis_branch, /* Unconditional branch */ + dis_condbranch, /* Conditional branch */ + dis_jsr, /* Jump to subroutine */ + dis_condjsr, /* Conditional jump to subroutine */ + dis_dref, /* Data reference instruction */ + dis_dref2 /* Two data references in instruction */ +}; + +/* This struct is passed into the instruction decoding routine, + and is passed back out into each callback. The various fields are used + for conveying information from your main routine into your callbacks, + for passing information into the instruction decoders (such as the + addresses of the callback functions), or for passing information + back from the instruction decoders to their callers. + + It must be initialized before it is first passed; this can be done + by hand, or using one of the initialization macros below. */ + +typedef struct disassemble_info { + fprintf_ftype fprintf_func; + void *stream; + void *application_data; + + /* Target description. We could replace this with a pointer to the bfd, + but that would require one. There currently isn't any such requirement + so to avoid introducing one we record these explicitly. */ + /* The bfd_flavour. This can be bfd_target_unknown_flavour. */ + enum bfd_flavour flavour; + /* The bfd_arch value. */ + enum bfd_architecture arch; + /* The bfd_mach value. */ + unsigned long mach; + /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ + enum bfd_endian endian; + /* An arch/mach-specific bitmask of selected instruction subsets, mainly + for processors with run-time-switchable instruction sets. The default, + zero, means that there is no constraint. CGEN-based opcodes ports + may use ISA_foo masks. */ + unsigned long insn_sets; + + /* Some targets need information about the current section to accurately + display insns. If this is NULL, the target disassembler function + will have to make its best guess. */ + asection *section; + + /* An array of pointers to symbols either at the location being disassembled + or at the start of the function being disassembled. The array is sorted + so that the first symbol is intended to be the one used. The others are + present for any misc. purposes. This is not set reliably, but if it is + not NULL, it is correct. */ + asymbol **symbols; + /* Number of symbols in array. */ + int num_symbols; + + /* For use by the disassembler. + The top 16 bits are reserved for public use (and are documented here). + The bottom 16 bits are for the internal use of the disassembler. */ + unsigned long flags; +#define INSN_HAS_RELOC 0x80000000 + void *private_data; + + /* Function used to get bytes to disassemble. MEMADDR is the + address of the stuff to be disassembled, MYADDR is the address to + put the bytes in, and LENGTH is the number of bytes to read. + INFO is a pointer to this struct. + Returns an errno value or 0 for success. */ + int (*read_memory_func) + (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, + struct disassemble_info *info); + + /* Function which should be called if we get an error that we can't + recover from. STATUS is the errno value from read_memory_func and + MEMADDR is the address that we were trying to read. INFO is a + pointer to this struct. */ + void (*memory_error_func) + (int status, bfd_vma memaddr, struct disassemble_info *info); + + /* Function called to print ADDR. */ + void (*print_address_func) + (bfd_vma addr, struct disassemble_info *info); + + /* Function called to determine if there is a symbol at the given ADDR. + If there is, the function returns 1, otherwise it returns 0. + This is used by ports which support an overlay manager where + the overlay number is held in the top part of an address. In + some circumstances we want to include the overlay number in the + address, (normally because there is a symbol associated with + that address), but sometimes we want to mask out the overlay bits. */ + int (* symbol_at_address_func) + (bfd_vma addr, struct disassemble_info * info); + + /* Function called to check if a SYMBOL is can be displayed to the user. + This is used by some ports that want to hide special symbols when + displaying debugging outout. */ + bfd_boolean (* symbol_is_valid) + (asymbol *, struct disassemble_info * info); + + /* These are for buffer_read_memory. */ + bfd_byte *buffer; + bfd_vma buffer_vma; + unsigned int buffer_length; + + /* This variable may be set by the instruction decoder. It suggests + the number of bytes objdump should display on a single line. If + the instruction decoder sets this, it should always set it to + the same value in order to get reasonable looking output. */ + int bytes_per_line; + + /* The next two variables control the way objdump displays the raw data. */ + /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */ + /* output will look like this: + 00: 00000000 00000000 + with the chunks displayed according to "display_endian". */ + int bytes_per_chunk; + enum bfd_endian display_endian; + + /* Number of octets per incremented target address + Normally one, but some DSPs have byte sizes of 16 or 32 bits. */ + unsigned int octets_per_byte; + + /* Results from instruction decoders. Not all decoders yet support + this information. This info is set each time an instruction is + decoded, and is only valid for the last such instruction. + + To determine whether this decoder supports this information, set + insn_info_valid to 0, decode an instruction, then check it. */ + + char insn_info_valid; /* Branch info has been set. */ + char branch_delay_insns; /* How many sequential insn's will run before + a branch takes effect. (0 = normal) */ + char data_size; /* Size of data reference in insn, in bytes */ + enum dis_insn_type insn_type; /* Type of instruction */ + bfd_vma target; /* Target address of branch or dref, if known; + zero if unknown. */ + bfd_vma target2; /* Second target address for dref2 */ + + /* Command line options specific to the target disassembler. */ + char * disassembler_options; + +} disassemble_info; + + +/* Standard disassemblers. Disassemble one instruction at the given + target address. Return number of octets processed. */ +typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); + +extern int print_insn_big_mips (bfd_vma, disassemble_info *); +extern int print_insn_little_mips (bfd_vma, disassemble_info *); +extern int print_insn_i386 (bfd_vma, disassemble_info *); +extern int print_insn_i386_att (bfd_vma, disassemble_info *); +extern int print_insn_i386_intel (bfd_vma, disassemble_info *); +extern int print_insn_ia64 (bfd_vma, disassemble_info *); +extern int print_insn_i370 (bfd_vma, disassemble_info *); +extern int print_insn_m68hc11 (bfd_vma, disassemble_info *); +extern int print_insn_m68hc12 (bfd_vma, disassemble_info *); +extern int print_insn_m68k (bfd_vma, disassemble_info *); +extern int print_insn_z8001 (bfd_vma, disassemble_info *); +extern int print_insn_z8002 (bfd_vma, disassemble_info *); +extern int print_insn_h8300 (bfd_vma, disassemble_info *); +extern int print_insn_h8300h (bfd_vma, disassemble_info *); +extern int print_insn_h8300s (bfd_vma, disassemble_info *); +extern int print_insn_h8500 (bfd_vma, disassemble_info *); +extern int print_insn_alpha (bfd_vma, disassemble_info *); +extern int print_insn_big_arm (bfd_vma, disassemble_info *); +extern int print_insn_little_arm (bfd_vma, disassemble_info *); +extern int print_insn_sparc (bfd_vma, disassemble_info *); +extern int print_insn_big_a29k (bfd_vma, disassemble_info *); +extern int print_insn_little_a29k (bfd_vma, disassemble_info *); +extern int print_insn_avr (bfd_vma, disassemble_info *); +extern int print_insn_d10v (bfd_vma, disassemble_info *); +extern int print_insn_d30v (bfd_vma, disassemble_info *); +extern int print_insn_dlx (bfd_vma, disassemble_info *); +extern int print_insn_fr30 (bfd_vma, disassemble_info *); +extern int print_insn_hppa (bfd_vma, disassemble_info *); +extern int print_insn_i860 (bfd_vma, disassemble_info *); +extern int print_insn_i960 (bfd_vma, disassemble_info *); +extern int print_insn_ip2k (bfd_vma, disassemble_info *); +extern int print_insn_m32r (bfd_vma, disassemble_info *); +extern int print_insn_m88k (bfd_vma, disassemble_info *); +extern int print_insn_mcore (bfd_vma, disassemble_info *); +extern int print_insn_mmix (bfd_vma, disassemble_info *); +extern int print_insn_mn10200 (bfd_vma, disassemble_info *); +extern int print_insn_mn10300 (bfd_vma, disassemble_info *); +extern int print_insn_msp430 (bfd_vma, disassemble_info *); +extern int print_insn_ns32k (bfd_vma, disassemble_info *); +extern int print_insn_crx (bfd_vma, disassemble_info *); +extern int print_insn_openrisc (bfd_vma, disassemble_info *); +extern int print_insn_big_or32 (bfd_vma, disassemble_info *); +extern int print_insn_little_or32 (bfd_vma, disassemble_info *); +extern int print_insn_pdp11 (bfd_vma, disassemble_info *); +extern int print_insn_pj (bfd_vma, disassemble_info *); +extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_rs6000 (bfd_vma, disassemble_info *); +extern int print_insn_s390 (bfd_vma, disassemble_info *); +extern int print_insn_sh (bfd_vma, disassemble_info *); +extern int print_insn_tic30 (bfd_vma, disassemble_info *); +extern int print_insn_tic4x (bfd_vma, disassemble_info *); +extern int print_insn_tic54x (bfd_vma, disassemble_info *); +extern int print_insn_tic80 (bfd_vma, disassemble_info *); +extern int print_insn_v850 (bfd_vma, disassemble_info *); +extern int print_insn_vax (bfd_vma, disassemble_info *); +extern int print_insn_w65 (bfd_vma, disassemble_info *); +extern int print_insn_xstormy16 (bfd_vma, disassemble_info *); +extern int print_insn_xtensa (bfd_vma, disassemble_info *); +extern int print_insn_sh64 (bfd_vma, disassemble_info *); +extern int print_insn_sh64x_media (bfd_vma, disassemble_info *); +extern int print_insn_frv (bfd_vma, disassemble_info *); +extern int print_insn_iq2000 (bfd_vma, disassemble_info *); + +extern disassembler_ftype arc_get_disassembler (void *); +extern disassembler_ftype cris_get_disassembler (bfd *); + +extern void print_mips_disassembler_options (FILE *); +extern void print_ppc_disassembler_options (FILE *); +extern void print_arm_disassembler_options (FILE *); +extern void parse_arm_disassembler_option (char *); +extern int get_arm_regname_num_options (void); +extern int set_arm_regname_option (int); +extern int get_arm_regnames (int, const char **, const char **, const char ***); +extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *); + +/* Fetch the disassembler for a given BFD, if that support is available. */ +extern disassembler_ftype disassembler (bfd *); + +/* Amend the disassemble_info structure as necessary for the target architecture. + Should only be called after initialising the info->arch field. */ +extern void disassemble_init_for_target (struct disassemble_info * info); + +/* Document any target specific options available from the disassembler. */ +extern void disassembler_usage (FILE *); + + +/* This block of definitions is for particular callers who read instructions + into a buffer before calling the instruction decoder. */ + +/* Here is a function which callers may wish to use for read_memory_func. + It gets bytes from a buffer. */ +extern int buffer_read_memory + (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *); + +/* This function goes with buffer_read_memory. + It prints a message using info->fprintf_func and info->stream. */ +extern void perror_memory (int, bfd_vma, struct disassemble_info *); + + +/* Just print the address in hex. This is included for completeness even + though both GDB and objdump provide their own (to print symbolic + addresses). */ +extern void generic_print_address + (bfd_vma, struct disassemble_info *); + +/* Always true. */ +extern int generic_symbol_at_address + (bfd_vma, struct disassemble_info *); + +/* Also always true. */ +extern bfd_boolean generic_symbol_is_valid + (asymbol *, struct disassemble_info *); + +/* Method to initialize a disassemble_info struct. This should be + called by all applications creating such a struct. */ +extern void init_disassemble_info (struct disassemble_info *info, void *stream, + fprintf_ftype fprintf_func); + +/* For compatibility with existing code. */ +#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \ + init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC)) +#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \ + init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC)) + + +#ifdef __cplusplus +} +#endif + +#endif /* ! defined (DIS_ASM_H) */ diff --git a/include/dyn-string.h b/include/dyn-string.h new file mode 100644 index 000000000..85f88b12c --- /dev/null +++ b/include/dyn-string.h @@ -0,0 +1,63 @@ +/* An abstract string datatype. + Copyright (C) 1998, 1999, 2000, 2002, 2004 Free Software Foundation, Inc. + Contributed by Mark Mitchell (mark@markmitchell.com). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +typedef struct dyn_string +{ + int allocated; /* The amount of space allocated for the string. */ + int length; /* The actual length of the string. */ + char *s; /* The string itself, NUL-terminated. */ +}* dyn_string_t; + +/* The length STR, in bytes, not including the terminating NUL. */ +#define dyn_string_length(STR) \ + ((STR)->length) + +/* The NTBS in which the contents of STR are stored. */ +#define dyn_string_buf(STR) \ + ((STR)->s) + +/* Compare DS1 to DS2 with strcmp. */ +#define dyn_string_compare(DS1, DS2) \ + (strcmp ((DS1)->s, (DS2)->s)) + + +extern int dyn_string_init PARAMS ((struct dyn_string *, int)); +extern dyn_string_t dyn_string_new PARAMS ((int)); +extern void dyn_string_delete PARAMS ((dyn_string_t)); +extern char *dyn_string_release PARAMS ((dyn_string_t)); +extern dyn_string_t dyn_string_resize PARAMS ((dyn_string_t, int)); +extern void dyn_string_clear PARAMS ((dyn_string_t)); +extern int dyn_string_copy PARAMS ((dyn_string_t, dyn_string_t)); +extern int dyn_string_copy_cstr PARAMS ((dyn_string_t, const char *)); +extern int dyn_string_prepend PARAMS ((dyn_string_t, dyn_string_t)); +extern int dyn_string_prepend_cstr PARAMS ((dyn_string_t, const char *)); +extern int dyn_string_insert PARAMS ((dyn_string_t, int, + dyn_string_t)); +extern int dyn_string_insert_cstr PARAMS ((dyn_string_t, int, + const char *)); +extern int dyn_string_insert_char PARAMS ((dyn_string_t, int, int)); +extern int dyn_string_append PARAMS ((dyn_string_t, dyn_string_t)); +extern int dyn_string_append_cstr PARAMS ((dyn_string_t, const char *)); +extern int dyn_string_append_char PARAMS ((dyn_string_t, int)); +extern int dyn_string_substring PARAMS ((dyn_string_t, + dyn_string_t, int, int)); +extern int dyn_string_eq PARAMS ((dyn_string_t, dyn_string_t)); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog new file mode 100644 index 000000000..6b0cf0d4e --- /dev/null +++ b/include/elf/ChangeLog @@ -0,0 +1,116 @@ +2004-08-25 Dmitry Diky <diwil@spec.ru> + + * msp430.h: Add new relocs. + +2004-08-12 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (R_386_USED_BY_INTEL_200): New. + +2004-07-29 Alexandre Oliva <aoliva@redhat.com> + + Introduce SH2a support. + 2004-02-18 Corinna Vinschen <vinschen@redhat.com> + * sh.h (EF_SH2A_NOFPU): New. + 2003-12-01 Michael Snyder <msnyder@redhat.com> + * sh.h (EF_SH2A): New. + +2004-07-27 Tomer Levi <Tomer.Levi@nsc.com> + + * crx.h: Add BFD_RELOC_CRX_SWITCH8, BFD_RELOC_CRX_SWITCH16, + BFD_RELOC_CRX_SWITCH32. + +2004-07-06 Tomer Levi <Tomer.Levi@nsc.com> + + * common.h (EM_CRX): Define. + * crx.h: New file. + +2004-06-25 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * m32r.h: Add defintions of R_M32R_GOTOFF_HI_ULO, + R_M32R_GOTOFF_HI_SLO and R_M32R_GOTOFF_LO. + +2004-06-19 Alan Modra <amodra@bigpond.net.au> + + * common.h (ELF64_R_INFO): Warning fix. + +2004-06-14 Chris Demetriou <cgd@broadcom.com> + + * mips.h (R_MIPS_PC32): Add back (undoing removal on 2004-04-24), + with an updated comment. + +2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com> + + * sh.h (EF_SH_HAS_DSP): Remove. + (EF_SH_HAS_FP): Remove. + (EF_SH_MERGE_MACH): Remove. + (EF_SH4_NOFPU): Convert to decimal. + (EF_SH4A_NOFPU): Likewise. + (EF_SH4_NOMMU_NOFPU): Likewise. + (EF_SH3_NOMMU): Add new macro. + (EF_SH_BFD_TABLE): Likewise. + (sh_find_elf_flags): Add prototype. + (sh_elf_get_flags_from_mach): Likewise. + +2004-04-24 Chris Demetriou <cgd@broadcom.com> + + * mips.h (R_MIPS_PC32, R_MIPS_PC64, R_MIPS_GNU_REL_LO16) + (R_MIPS_GNU_REL_HI16): Remove. + (R_MIPS_GNU_REL16_S2): Update comment. + +2004-30-30 Galit Heller <Galit.Heller@nsc.com> + Tomer Levi <Tomer.Levi@nsc.com> + + * common.h (EM_CR): Define. + * cr16c.h: New file. + +2004-03-23 Paul Brook <paul@codesourcery.com> + + * arm.h (EF_ERM_BE8, EF_ARM_LE8, EF_ARM_EABI_VER3): Add. + +2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com> + + * sh.h: Add EF_SH4_NOMMU_NOFPU. + +2004-03-01 Richard Sandiford <rsandifo@redhat.com> + + * frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define. + +2004-01-28 Roland McGrath <roland@redhat.com> + + * common.h (AT_SECURE): New macro. + +2004-01-21 Roland McGrath <roland@redhat.com> + + * common.h (AT_SUN_UID, AT_SUN_RUID, AT_SUN_GID): New macros. + (AT_SUN_RGID, AT_SUN_LDELF, AT_SUN_LDSHDR, AT_SUN_LDNAME, + AT_SUN_LPAGESZ, AT_SUN_PLATFORM, AT_SUN_HWCAP, AT_SUN_IFLUSH, + AT_SUN_CPU, AT_SUN_EMUL_ENTRY, AT_SUN_EMUL_EXECFD, + AT_SUN_EXECNAME) AT_SUN_MMU, AT_SUN_LDDATA): Likewise. + +2004-01-17 Mark Kettenis <kettenis@gnu.org> + + * common.h (NT_OPENBSD_IDENT): Define. + +2004-01-06 Alexandre Oliva <aoliva@redhat.com> + + 2003-09-18 Alexandre Oliva <aoliva@redhat.com> + * frv.h (EF_FRV_FDPIC): New macro. + (EF_FRV_PIC_FLAGS): Adjust. + 2003-08-08 Alexandre Oliva <aoliva@redhat.com> + * frv.h (R_FRV_FUNCDESC_VALUE, R_FRV_FUNCDESC_GOTOFF12, + R_FRV_FUNCDESC_GOTOFFLO, R_FRV_FUNCDESC_GOTOFFHI, R_FRV_GOTOFF12, + R_FRV_GOTOFFLO, R_FRV_GOTOFFHI): New. + 2003-08-04 Alexandre Oliva <aoliva@redhat.com> + * frv.h (R_FRV_GOT12, R_FRV_GOTHI, R_FRV_GOTLO, R_FRV_FUNCDESC, + R_FRV_FUNCDESC_GOT12, R_FRV_FUNCDESC_GOTHI, R_FRV_FUNCDESC_GOTLO): + New. + + +For older changes see ChangeLog-9103 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/include/elf/ChangeLog-9103 b/include/elf/ChangeLog-9103 new file mode 100644 index 000000000..713d80d14 --- /dev/null +++ b/include/elf/ChangeLog-9103 @@ -0,0 +1,1914 @@ +2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * elf/m32r.h : Added m32r-linux and PIC support. Add new ABI that + uses RELA. + (R_M32R_16_RELA, R_M32R_32_RELA, R_M32R_24_RELA, + R_M32R_10_PCREL_RELA, R_M32R_18_PCREL_RELA, + R_M32R_26_PCREL_RELA, R_M32R_HI16_ULO_RELA, + R_M32R_HI16_SLO_RELA, R_M32R_LO16_RELA, + R_M32R_SDA16_RELA, R_M32R_RELA_GNU_VTINHERIT, + R_M32R_RELA_GNU_VTENTRY, R_M32R_GOT24, + R_M32R_26_PLTREL, R_M32R_COPY, R_M32R_GLOB_DAT, + R_M32R_JMP_SLOT, R_M32R_RELATIVE, R_M32R_GOTOFF, + R_M32R_GOTPC24, R_M32R_GOT16_HI_ULO, + R_M32R_GOT16_HI_SLO, R_M32R_GOT16_LO, + R_M32R_GOTPC_HI_ULO, R_M32R_GOTPC_HI_SLO, + R_M32R_GOTPC_LO): New relocs. + +2003-12-06 Alan Modra <amodra@bigpond.net.au> + + From Jan Beulich <JBeulich@novell.com> + * common.h (DT_HIOS): Correct value. + +2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * elf/m32r.h: Add new machine type m32r2 and instruction modes. + +2003-11-06 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (R_PPC_RELAX32PC): Define. + +2003-10-22 Alexandre Oliva <aoliva@redhat.com>, + Michael Snyder <msnyder@redhat.com> + + * sh.h (EF_SH4A, EF_SH4AL_DSP, EF_SH4_NOFPU, EF_SH4A_NOFPU): New. + (EF_SH_MERGE_MACH): Combine them. + +2003-10-18 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix.h (R_MMIX_PUSHJ_STUBBABLE): New reloc number. + (_bfd_mmix_before_linker_allocation): Rename from + _bfd_mmix_prepare_linker_allocated_gregs. + (_bfd_mmix_after_linker_allocation): Rename from + _bfd_mmix_finalize_linker_allocated_gregs. + +2003-10-06 Dave Brolley <brolley@redhat.com> + + * frv.h (EF_FRV_CPU_FR550): New macro. + +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * mips.h (E_MIPS_ARCH_64R2): New define. + +2003-09-23 DJ Delorie <dj@redhat.com> + + * sh.h (R_SH_SWITCH8, R_SH_GNU_VTINHERIT, R_SH_GNU_VTENTRY, + R_SH_LOOP_START,R_SH_LOOP_END): Move to "reserved" spaces. + (R_SH_DIR16, R_SH_DIR8, R_SH_DIR8UL, R_SH_DIR8UW, R_SH_DIR8U, + R_SH_DIR8SW, R_SH_DIR8S, R_SH_DIR4UL, R_SH_DIR4UW, R_SH_DIR4U, + R_SH_PSHA, R_SH_PSHL): New. + +2003-09-11 James Cownie <jcownie@etnus.com> + + * dwarf2.h: Add HP dwarf extensions from their hacked gdb + header files (ftp://ftp.hp.com/pub/lang/tools/WDB/wdb-4.0.tar.gz). + +2003-09-04 Nick Clifton <nickc@redhat.com> + + * v850.h (E_V850E1_ARCH): Define. + +2003-08-21 James Cownie <jcownie@etnus.com> + + * dwarf2.h: Add PGI dwarf extensions. + +2003-08-08 Dmitry Diky <diwil@mail.ru> + + * msp430.h: Add xW42 and xE42 parts. Sort MPU list according to + gcc order. + +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * reloc-macros.h (START_RELOC_NUMBERS) : Remove PARAMS macro. Use + C90 function definition. Formatting. + (RELOC_NUMBER): Remove !__STDC__ code. + +2003-07-28 Eric Christopher <echristo@redhat.com> + + * ppc.h (R_PPC_RELAX32): New. Fake relocation. + +2003-07-25 H.J. Lu <hongjiu.lu@intel.com> + + * v850.h (SHF_V850_GPREL): New. + (SHF_V850_EPREL): Likewise. + (SHF_V850_R0REL): Likewise. + +2003-07-09 Alexandre Oliva <aoliva@redhat.com> + + 2001-05-16 Alexandre Oliva <aoliva@redhat.com> + * mn10300.h: Introduce GOTPC16, GOTOFF24, GOTOFF16 and + PLT16, and rename GOTPC to GOTPC32 and GOTOFF to GOTOFF32. + Renumbered all relocs. + 2001-04-12 Alexandre Oliva <aoliva@redhat.com> + * mn10300.h (R_MN10300_GOTPC, R_MN10300_GOTOFF, + R_MN10300_PLT32, R_MN10300_GOT32, R_MN10300_GOT24, + R_MN10300_GOT16, R_MN10300_COPY, R_MN10300_GLOB_DAT, + R_MN10300_JMP_SLOT, R_MN10300_RELATIVE): New relocs. + +2003-07-09 Alexandre Oliva <aoliva@redhat.com> + + 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> + * mn10300.h (E_MN10300_MACH_AM33_2): Renamed from + E_MN10300_MACH_AM332. + 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> + * mn10300.h (E_MN10300_MACH_AM332): Defined. + +2003-07-01 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h (elf_s390_reloc_type): Add long displacement relocations + R_390_20, R_390_GOT20, R_390_GOTPLT20 and R_390_TLS_GOTIE20. + +2003-06-29 Andreas Jaeger <aj@suse.de> + + * mmix.h: Convert to ISO C90 prototypes. + * mips.h: Likewise. + +2003-06-13 Robert Millan <zeratul2@wanadoo.es> + + * common.h (GNU_ABI_TAG_NETBSD): New tag. + (GNU_ABI_TAG_FREEBSD): New tag. + +2003-06-10 Richard Sandiford <rsandifo@redhat.com> + + * h8.h (E_H8_MACH_H8300SXN): New flag. + +2003-06-03 Nick Clifton <nickc@redhat.com> + + * v850.h (R_V850_32): Rename to R_V850_ABS32. + Add R_V850_REL32. + +2003-05-15 Roland McGrath <roland@redhat.com> + + * common.h (NT_AUXV, AT_*): New macros. + * external.h (Elf32_External_Auxv, Elf64_External_Auxv): New types. + * internal.h (Elf_Internal_Auxv): New type. + +2003-05-14 Michael Snyder <msnyder@redhat.com> + From Bernd Schmidt <bernds@redhat.com> + * h8.h (E_H8_MACH_H8300SX): New. + +2003-04-24 Dhananjay Deshpande <dhananjayd@kpitcummins.com> + + * elf/h8.h (E_H8_MACH_H8300HN, E_H8_MACH_H8300SN): New + +2003-04-23 J"orn Rennecke <joern.rennecke@superh.com> + + * common.h (EM_SH): Amend comment to refer to SuperH. + +2003-04-22 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * common.h: Replace references to Mitsubishi M32R with + references to Renesas M32R. + +2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com> + + * common.h: Replace occurrances of 'Hitachi' with 'Renesas'. + +2003-04-01 Bob Wilson <bob.wilson@acm.org> + + * elf/common.h (EM_XTENSA_OLD): Define. + * elf/xtensa.h: New file. + +2003-04-01 Nick Clifton <nickc@redhat.com> + + * arm.h (ARM_NOTE_SECTION): Include .gnu in the string. + +2003-03-25 Stan Cox <scox@redhat.com> + Nick Clifton <nickc@redhat.com> + + Contribute support for Intel's iWMMXt chip - an ARM variant: + + * arm.h (ARM_NOTE_SECTION): Define. + +2003-03-03 J"orn Rennecke <joern.rennecke@superh.com> + + * sh.h (EF_SH_MERGE_MACH): Make sure SH2E & SH3/SH3E merge to SH3E, + and SH2E & SH4 merge to SH4, not SH2E. + +2003-02-21 Ian Wienand <ianw@gelato.unsw.edu.au> + + * ia64.h (SHT_IA_64_LOPSREG, SHT_IA_64_HIPSREG, + SHT_IA_64_PRIORITY_INIT): Define. + +2003-02-18 Alan Modra <amodra@bigpond.net.au> + + * ppc64.h (IS_PPC64_TLS_RELOC): Rename from IS_TLS_RELOC. + + * ppc.h: Replace DTPMOD64, TPREL64, DTPREL64 with DTPMOD32 etc. + (IS_PPC_TLS_RELOC): Define. + +2003-02-10 Nick Clifton <nickc@redhat.com> + + * arm.h (EF_ARM_MAVERICK_FLOAT): Define. + +2003-02-05 Alan Modra <amodra@bigpond.net.au> + + * ppc.h: Add TLS relocs. Format. + * ppc64.h: Likewise. + +2003-01-27 Alexandre Oliva <aoliva@redhat.com> + + * mips.h (EF_MIPS_XGOT): Define. + +2003-01-24 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h: Add s390 TLS relocations. + +2003-01-23 Nick Clifton <nickc@redhat.com> + + * Add sh2e support: + + 2002-04-02 Alexandre Oliva <aoliva@redhat.com> + + * sh.h (EF_SH_MERGE_MACH): Handle SH2E. + + 2002-04-02 Elena Zannoni <ezannoni@redhat.com> + + * sh.h (EF_SH2E): New. + +2003-01-23 Alan Modra <amodra@bigpond.net.au> + + * sh.h: Split out various bits to bfd/elf32-sh64.h. + +2003-01-20 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h: Rename R_390_GOTOFF to R_390_GOTOFF32. Add new gotoff, + gotplt and pltoff relocations. + +2003-01-17 Alan Modra <amodra@bigpond.net.au> + + * common.h: Formatting, typo fixes. + (DT_ENCODING): Correct value. + +2003-01-17 Fabio Alemagna <falemagn@aros.org> + + * common.h (ELFOSABI_AROS): Define. + (ELFOSABI_OPENVMS): Likewise. + (ELFOSABI_NSK): Likewise. + +2003-01-16 Alan Modra <amodra@bigpond.net.au> + + * ppc.h: Split out ppc64 definitions to.. + * pcc64.h: ..here. New file. + (R_PPC64_REL30): Rename from R_PPC64_ADDR30. + +2003-01-13 Dmitry Diky <diwil@mail.ru> + + * elf/common.h (EM_MSP430): Change e_machine value to officially + assigned. + +2003-01-02 Ben Elliston <bje@redhat.com> + + * common.h (EM_IQ2000): Define. + * iq2000.h: New file. + +2002-12-30 Chris Demetriou <cgd@broadcom.com> + + * mips.h (E_MIPS_ARCH_32R2): New define. + +2002-12-24 Dmitry Diky <diwil@mail.ru> + + * common.h: Define msp430 machine numbers. + * msp430.h: New file. Define msp430 relocs. + +2002-12-20 DJ Delorie <dj@redhat.com> + + * xstormy16.h: Add XSTORMY16_12. + +2002-12-16 Andrew MacLeod <amacleod@redhat.com> + + * xstormy16.h (START_RELOC_NUMBERS) Add relocation numbers + for R_XSTORMY16_LO16 and R_XSTORMY16_HI16. + +2002-12-10 James Cownie <jcownie@etnus.com> + + * dwarf2.h (DW_TAG_upc_shared_type, DW_TAG_upc_strict_type, + DW_TAG_upc_relaxed_type, DW_AT_upc_threads_scaled, DW_LANG_Upc): + Define. + +2002-12-01 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11.h (EF_M68HC12_MACH, EF_M68HCS12_MACH): Define. + (EF_M68HC11_MACH_MASK, EF_M68HC11_MACH): Define. + (EF_M68HC11_MERGE_MACH, EF_M68HC11_CAN_MERGE_MACH): Define. + +2002-11-30 Alan Modra <amodra@bigpond.net.au> + + * mmix.h: Replace boolean with bfd_boolean. + * sh.h: Likewise. + +2002-11-28 Alan Modra <amodra@bigpond.net.au> + + * internal.h (elf32_internal_ehdr, Elf32_Internal_Ehdr, + elf64_internal_ehdr, Elf64_Internal_Ehdr, elf32_internal_phdr, + Elf32_Internal_Phdr, elf64_internal_phdr, Elf64_Internal_Phdr, + elf32_internal_shdr, Elf32_Internal_Shdr, elf64_internal_shdr, + Elf64_Internal_Shdr, elf32_internal_sym, elf64_internal_sym, + Elf32_Internal_Sym, Elf64_Internal_Sym, Elf32_Internal_Note, + elf32_internal_note, elf32_internal_rel, Elf32_Internal_Rel, + elf64_internal_rel, Elf64_Internal_Rel, elf32_internal_rela, + elf64_internal_rela, Elf32_Internal_Rela, Elf64_Internal_Rela, + elf32_internal_dyn, elf64_internal_dyn, Elf32_Internal_Dyn, + Elf64_Internal_Dyn, elf32_internal_verdef, elf64_internal_verdef, + elf32_internal_verdaux, elf64_internal_verdaux, elf32_internal_verneed, + elf64_internal_verneed, elf32_internal_vernaux, elf64_internal_vernaux, + elf32_internal_versym, elf64_internal_versym, Elf32_Internal_Verdef, + Elf64_Internal_Verdef, Elf32_Internal_Verdaux, Elf64_Internal_Verdaux, + Elf32_Internal_Verneed, Elf64_Internal_Verneed, Elf32_Internal_Vernaux, + Elf64_Internal_Vernaux, Elf32_Internal_Versym, Elf64_Internal_Versym, + Elf32_Internal_Syminfo, Elf64_Internal_Syminfo): Delete. + (Elf_Internal_Rel): Delete. + +2002-10-11 Kaz Kojima <kkojima@rr.iij4u.or.jp> + + * sh.h: Add SH TLS relocs. + +2002-09-30 Gavin Romig-Koch <gavin@redhat.com> + Ken Raeburn <raeburn@cygnus.com> + Aldy Hernandez <aldyh@redhat.com> + Eric Christopher <echristo@redhat.com> + Richard Sandiford <rsandifo@redhat.com> + + * mips.h (E_MIPS_MACH_4120, E_MIPS_MACH_5400, E_MIPS_MACH_5500): New. + +2002-09-12 Roland McGrath <roland@redhat.com> + + * dwarf2.h: Updates from GCC version of thie file: + (enum dwarf_location_atom): DW_OP_calli -> DW_OP_call_ref. + Add DW_OP_GNU_push_tls_address. + (DW_OP_lo_user): Change to 0xe0. + +2002-08-28 Catherine Moore <clm@redhat.com> + + * elf/v850.h (R_V850_LONGCALL, R_V850_ALIGN, + R_V850_LONGJUMP): New relocations. + +2002-08-15 Alan Modra <amodra@bigpond.net.au> + + * i370.h: Define relocs using reloc-macros.h. + +2002-08-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11.h (E_M68HC12_BANKS, E_M68HC11_I32, E_M68HC11_F64, + EF_M68HC11_ABI): Define for ABI specification. + (STO_M68HC12_FAR, STO_M68HC12_INTERRUPT): Symbol flags for + linker and debugger. + (R_M68HC11_24, R_M68HC11_LO16, R_M68HC11_PAGE): New relocs. + (R_M68HC11_RL_JUMP, R_M68HC11_RL_GROUP): New reloc for linker + relaxation. + +2002-07-15 Denis Chertykov <denisc@overta.ru> + Frank Ch. Eigler <fche@redhat.com> + Ben Elliston <bje@redhat.com> + Alan Lehotsky <alehotsky@cygnus.com> + John Healy <jhealy@redhat.com> + Graham Stott <grahams@redhat.com> + Jeff Johnston <jjohnstn@redhat.com> + + * common.h (EM_IP2K): New macro. + (EM_IP2K_OLD): New macro. + * ip2k.h: New file. + +2002-07-01 Matt Thomas <matt@3am-software.com> + + * vax.h: Rename EF_* to EF_VAX_*. + +2002-06-18 Dave Brolley <brolley@redhat.com> + + From Catherine Moore, Michael Meissner, Dave Brolley: + * common.h (EM_CYGNUS_FRV): New macro. + * frv.h: New file. + +2002-06-06 Lars Brinkhoff <lars@nocrew.org> + + * common.h: Change registry@sco.com to registry@caldera.com. + (EM_PDP10, EM_PDP11): Define. + +2002-06-04 Jason Thorpe <thorpej@wasabisystems.com> + + * sh.h (_bfd_sh64_crange_qsort_cmpb, _bfd_sh64_crange_qsort_cmpl) + (_bfd_sh64_crange_bsearch_cmpb, _bfd_sh64_crange_bsearch_cmpl): New + prototypes. + +2002-06-01 Richard Henderson <rth@redhat.com> + + * alpha.h (LITUSE_ALPHA_ADDR, LITUSE_ALPHA_BASE, LITUSE_ALPHA_BYTOFF, + LITUSE_ALPHA_JSR, LITUSE_ALPHA_TLSGD, LITUSE_ALPHA_TLSLDM): New. + +2002-05-30 Richard Henderson <rth@redhat.com> + + * alpha.h (R_ALPHA_TLSGD, R_ALPHA_TLSLDM, R_ALPHA_DTPMOD64, + R_ALPHA_GOTDTPREL, R_ALPHA_DTPREL64, R_ALPHA_DTPRELHI, + R_ALPHA_DTPRELLO, R_ALPHA_DTPREL16, R_ALPHA_GOTTPREL, R_ALPHA_TPREL64, + R_ALPHA_TPRELHI, R_ALPHA_TPRELLO, R_ALPHA_TPREL16): New. + +2002-05-29 Matt Thomas <matt@3am-software.com> + + * vax.h: New file + +2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> + + * common.h (EM_DLX): Define. + * dlx.h: New file. + +2002-05-08 Jason Thorpe <thorpej@wasabisystems.com> + + * common.h (NT_GNU_ABI_TAG): Define. + (GNU_ABI_TAG_LINUX): Define. + (GNU_ABI_TAG_HURD): Define. + (GNU_ABI_TAG_SOLARIS): Define. + (NT_NETBSD_IDENT): Define. + (NT_FREEBSD_ABI_TAG): Define. + +2002-04-24 Elena Zannoni <ezannoni@redhat.com> + + * dwarf2.h: Add DW_AT_GNU_vector. + +2002-02-13 Matt Fredette <fredette@netbsd.org> + + * m68k.h (EF_M68000): Define. + +2002-02-12 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (DT_PPC64_OPD, DT_PPC64_OPDSZ): Define. + +2002-02-09 Richard Henderson <rth@redhat.com> + + * alpha.h (R_ALPHA_BRSGP): New. + +2002-02-08 Alexandre Oliva <aoliva@redhat.com> + + Contribute sh64-elf. + 2002-01-23 Alexandre Oliva <aoliva@redhat.com> + * sh.h (R_SH_GOTPLT32, R_SH_GOT_LOW16, R_SH_GOT_MEDLOW16, + R_SH_GOT_MEDHI16, R_SH_GOT_HI16, R_SH_GOTPLT_LOW16, + R_SH_GOTPLT_MEDLOW16, R_SH_GOTPLT_MEDHI16, R_SH_GOTPLT_HI16, + R_SH_PLT_LOW16, R_SH_PLT_MEDLOW16, R_SH_PLT_MEDHI16, + R_SH_PLT_HI16, R_SH_GOTOFF_LOW16, R_SH_GOTOFF_MEDLOW16, + R_SH_GOTOFF_MEDHI16, R_SH_GOTOFF_HI16, R_SH_GOTPC_LOW16, + R_SH_GOTPC_MEDLOW16, R_SH_GOTPC_MEDHI16, R_SH_GOTPC_HI16, + R_SH_GOT10BY4, R_SH_GOTPLT10BY4, R_SH_GOT10BY8, + R_SH_GOTPLT10BY8, R_SH_COPY64, R_SH_GLOB_DAT64, R_SH_JMP_SLOT64, + R_SH_RELATIVE64): New relocs. + (R_SH_FIRST_INVALID_RELOC_4): Adjust. + 2001-05-16 Alexandre Oliva <aoliva@redhat.com> + * sh.h: Renumbered and renamed some SH5 relocations to match + official numbers and names; moved unmaching ones to the range + 0xf2-0xff. + 2001-01-06 Hans-Peter Nilsson <hpn@cygnus.com> + * sh.h (sh64_get_contents_type): Declare. + (sh64_address_is_shmedia): Likewise. + 2000-12-30 Hans-Peter Nilsson <hpn@cygnus.com> + * sh.h (sh64_elf_crange): New type. + (struct sh64_section_data): New. + (sh64_elf_section_data): New macro. + (EF_SH5): Rename back from EF_SH64. + 2000-12-18 Hans-Peter Nilsson <hpn@cygnus.com> + * sh.h (SHF_SH5_ISA32_MIXED, SHT_SH5_CR_SORTED, + SH64_CRANGES_SECTION_NAME, SH64_CRANGE_SIZE, + SH64_CRANGE_CR_ADDR_OFFSET, SH64_CRANGE_CR_SIZE_OFFSET, + SH64_CRANGE_CR_TYPE_OFFSET): New macros. + 2000-12-12 Hans-Peter Nilsson <hpn@cygnus.com> + * sh.h (EF_SH64): Don't define EF_SH64_ABI64. + 2000-11-27 Hans-Peter Nilsson <hpn@cygnus.com> + * sh.h (EF_SH64_32BIT_ABI, EF_SH64_64BIT_ABI): Delete. + (EF_SH64_ABI64): New. + 2000-11-23 Hans-Peter Nilsson <hpn@cygnus.com> + * sh.h (EF_SH64): Rename from EF_SH5. + (EF_SH64_32BIT_ABI): New. + (EF_SH64_64BIT_ABI): New. + (R_SH_PT_16, R_SH_SHMEDIA_CODE + R_SH_IMMU5, R_SH_IMMS6, R_SH_IMMU6, R_SH_IMMS10, R_SH_IMMS10BY2, + R_SH_IMMS10BY4, R_SH_IMMS10BY8, R_SH_IMMS16, R_SH_IMMU16, + R_SH_IMM_LOW16, R_SH_IMM_LOW16_PCREL, R_SH_IMM_MEDLOW16, + R_SH_IMM_MEDLOW16_PCREL, R_SH_IMM_MEDHI16, R_SH_IMM_MEDHI16_PCREL, + R_SH_IMM_HI16, R_SH_IMM_HI16_PCREL, R_SH_64, R_SH_64_PCREL): New + relocs. + 2000-09-01 Ben Elliston <bje@redhat.com> + * sh.h (EF_SH5): Define. + +2002-02-01 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix.h: Tweak comments. + (MMIX_LD_ALLOCATED_REG_CONTENTS_SECTION_NAME): New. + [BFD_ARCH_SIZE] (_bfd_mmix_prepare_linker_allocated_gregs, + _bfd_mmix_finalize_linker_allocated_gregs, + _bfd_mmix_check_all_relocs): Provide prototypes. + +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * or32.h: New file. + * common.h: Add support for or32 targets. + +2002-01-28 Jason Merrill <jason@redhat.com> + + * dwarf2.h: Sync with gcc version. + +2002-01-16 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (DT_PPC64_GLINK): Define. + +2002-01-15 Richard Earnshaw <rearnsha@arm.com> + + * arm.h (F_VFP_FLOAT, EF_ARM_VFP_FLOAT): Define. + +2002-01-09 Jason Thorpe <thorpej@wasabisystems.com> + + * common.h: Update copyright years. + (NT_NETBSDCORE_PROCINFO): Define. + (NT_NETBSDCORE_FIRSTMACH): Define. + +2002-01-06 Steve Ellcey <sje@cup.hp.com> + + * ia64.h (ELF_STRING_ia64_unwind_hdr): New Macro for HP-UX. + (SHT_IA_64_HP_OPT_ANOT): Ditto + (PT_IA_64_HP_OPT_ANOT): Ditto + (PT_IA_64_HP_HSL_ANOT): Ditto + (PT_IA_64_HP_STACK): Ditto + (SHN_IA_64_ANSI_COMMON): Ditto + +2001-12-17 Alan Modra <amodra@bigpond.net.au> + + * external.h (Elf_External_Sym_Shndx): Declare. + * internal.h (struct elf_internal_sym <st_shndx>): Make it an + unsigned int. + * common.h (SHN_BAD): Define. + +2001-12-13 Jakub Jelinek <jakub@redhat.com> + + * elf/common.h (PT_GNU_EH_FRAME): Define. + +2001-12-11 Alan Modra <amodra@bigpond.net.au> + + * common.h (SHN_XINDEX): Comment typo fix. + * internal.h (Elf_Internal_Ehdr): Change existing "unsigned short" + size, count and index fields to "unsigned int". + +2001-12-07 Geoffrey Keating <geoffk@redhat.com> + Richard Henderson <rth@redhat.com> + + * common.h (EM_XSTORMY16): Define. + * xstormy16.h: New file. + +2001-11-15 Alan Modra <amodra@bigpond.net.au> + + * common.h (NT_ARCH): Define. Remove incorrect comment. + +2001-11-11 Geoffrey Keating <geoffk@redhat.com> + + * dwarf2.h (dwarf_line_number_ops): Add DWARF 3 opcodes. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix.h: New file. + +2001-10-23 Alan Modra <amodra@bigpond.net.au> + + * internal.h: White space changes to keep lines under 80 chars. + +2001-10-16 Jeff Holcomb <jeffh@redhat.com> + + * internal.h (elf_internal_shdr): Make contents a unsigned char *. + +2001-09-18 Alan Modra <amodra@bigpond.net.au> + + * internal.h (elf_internal_rela): Make r_addend a bfd_vma. + +2001-09-13 Alexandre Oliva <aoliva@redhat.com> + + * common.h (EM_OPENRISC_OLD): Renamed the old EM_OPENRISC entry. + +2001-09-12 Alexandre Oliva <aoliva@redhat.com> + + * common.h (EM_AVR_OLD): Renamed from... + (EM_AVR): this, redefined as in the current ELF standard. + (EM_PJ_OLD): Renamed from... + (EM_PJ): this, redefined as in the current ELF standard. + (EM_R30, EM_D10V, EM_D30V, EM_V850, EM_M32R, EM_MN10300, + EM_MN10200, EM_OPENRISC, EM_ARC_A5, EM_XTENSA): Defined as in + the current ELF standard. + (EM_CYGNUS_ARC): Removed, unused for a long time. + +2001-09-04 Richard Henderson <rth@redhat.com> + + * alpha.h (R_ALPHA_OP*, R_ALPHA_IMMED*, R_ALPHA_GPVALUE): Remove. + (R_ALPHA_GPREL16): Rename from R_ALPHA_IMMED_GP_16. + +2001-08-30 Eric Christopher <echristo@redhat.com> + + * mips.h: Remove E_MIPS_MACH_MIPS32_4K. + +2001-08-29 Jeff Law <law@redhat.com> + + * h8.h (EF_H8_MACH): New mask for encoded machine type. + (E_H8_MACH_H8300, E_H8_MACH_H8300H, E_H8_MACH_H8300S): New + machine types. + +2001-08-26 J"orn Rennecke <amylaar@redhat.com> + + * h8.h: New file. + +2001-08-27 Staffan Ulfberg <staffanu@swox.se> + + * ppc.h: Add relocs from the 64-bit PowerPC ELF ABI revision 1.2. + +2001-06-30 Daniel Berlin <dan@cgsoftware.com> + + * dwarf2.h: Remerge with gcc version, + including all new DWARF 2.1 extensions. + +2001-06-29 James Cownie <jcownie@etnus.com> + + * dwarf2.h: Add DWARF 2.1 attribues. + +2001-06-15 Per Bothner <per@bothner.com> + + * dwarf2.h: Partial merge with gcc version. + (enum dwarf_descrim_list): Fix typo -> dwarf_discrim_list. + (DW_LANG_Java): Use value from dwarf 2.1 draft (also used in gcc). + +2001-05-15 Ralf Baechle <ralf@gnu.org> + + * common.h: Remove definition of EM_MIPS_RS4_BE. The constant was + never in active use and is used otherwise by the ABI. + +2001-05-11 Jakub Jelinek <jakub@redhat.com> + + * ia64.h (ELF_STRING_ia64_unwind_once): Define. + (ELF_STRING_ia64_unwind_info_once): Define. + +2001-05-07 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * external.h: Fix typo. + * mips.h: Add/Extend many comments with reference to the MIPS ELF64 + spec v. 2.4, available at e.g. + ftp://oss.sgi.com/pub/linux/mips/doc/ABI/ELF64.ps. + (EF_MIPS_UCODE): Define. + (EF_MIPS_OPTIONS_FIRST): Define. + (EF_MIPS_ARCH_ASE): Define. + (EF_MIPS_ARCH_ASE_MDMX): Define. + (EF_MIPS_ARCH_ASE_M16): Define. + (SHF_MIPS_ADDR): Renamed SHF_MIPS_ADDR32. + (SHF_MIPS_STRING): Renamed SHF_MIPS_ADDR64. + (SHF_MIPS_NODUPES): Define. + (ELF64_MIPS_R_SSYM): New MIPS ELF 64 relocation info access macro. + (ELF64_MIPS_R_TYPE3): Likewise. + (ELF64_MIPS_R_TYPE2): Likewise. + (ELF64_MIPS_R_TYPE): Likewise. + (OHW_R10KLDL): Define. + +2001-04-24 Todd Fries <todd@fries.net> + + * sparc.h: Fix typo. + +2001-04-20 Johan Rydberg <jrydberg@opencores.org> + + * openrisc.h: New file. + * common.h (EM_OPENRISC): New constant. + +2001-04-23 Bo Thorsen <bo@suse.de> + + * x86-64.h: Add vtable support. + +2001-03-23 Nick Clifton <nickc@redhat.com> + + * mips.h: Remove extraneous whitespace. + +2001-03-22 Hans-Peter Nilsson <hp@axis.com> + + * cris.h: Add leading comment about PC-relative location. + (R_CRIS_COPY, R_CRIS_GLOB_DAT, R_CRIS_JUMP_SLOT, R_CRIS_RELATIVE, + R_CRIS_16_GOT, R_CRIS_32_GOT, R_CRIS_16_GOTPLT, R_CRIS_32_GOTPLT, + R_CRIS_32_GOTREL, R_CRIS_32_PLT_GOTREL, R_CRIS_32_PLT_PCREL): + New relocs. + +2001-02-27 Philip Blundell <pb@futuretv.com> + + * arm.h: Add new definitions from ARM document SWS ESPC 0003 B-01. + (EF_PIC, et al.): Rename to EF_ARM_xx. + +2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * common.h: Add linux target for S/390. + * s390.h: New file. + +2001-01-11 Peter Targett <peter.targett@arccores.com> + + * arc.h (E_ARC_MACH_ARC5, E_ARC_MACH_ARC6, E_ARC_MACH_ARC7, + E_ARC_MACH_ARC8): New definitions for cpu types. + + * common.h (EM_ARC): Change comment. + +2000-12-12 Nick Clifton <nickc@redhat.com> + + * mips.h: Fix formatting. + +2000-12-11 Jeffrey A Law (law@cygnus.com) + + * hppa.h (DT_HP_*): Define relative to OLD_DT_LOOS for hpux + compatibility. + +2000-10-16 Chris Demetriou <cgd@sibyte.com> + + * mips.h (E_MIPS_ARCH_32): New constant. + (E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the + former with the latter. + + * mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions. + + * mips.h (E_MIPS_MACH_SB1): New constant. + +2000-11-30 Jan Hubicka <jh@suse.cz> + + * common.h (EM_X86_64): New macro. + * x86-64.h: New file. + +2000-11-27 Hans-Peter Nilsson <hp@axis.com> + + * common.h (e_machine numbers): Clarify comments to describe how + EM_* constants are assigned. Move EM_PJ from official section to + ad-hoc section. + (EM_CRIS): Correct comment to match official description. + (EM_MMIX): Ditto. + +2000-11-22 Nick Clifton <nickc@redhat.com> + + * common.h (EM_JAVELIN): New machine number. + (EM_FIREPATH): New machine number. + (EM_ZSP): New machine number. + (EM_MMIX): New machine number. + (EM_HUANY): New machine number. + (EM_PRISM): New machine number. + (SHT_GROUP): New section type. + (SHT_SYMTAB_SHNDX): New section type. + (SHF_GROUP): New section flag. + (SHN_XINDEX): New section index. + (GRP_COMDAT): New section group flag. + +2000-11-20 H.J. Lu <hjl@gnu.org> + + * common.h (ELFOSABI_MONTEREY): Renamed to ... + (ELFOSABI_AIX): This. + +2000-11-16 Richard Henderson <rth@redhat.com> + + Update relocations per August psABI docs. + * ia64.h (R_IA64_SEGBASE): Remove. + (R_IA64_LTV*): Renumber to 0x74 to 0x77. + (R_IA64_EPLTMSB, R_IA64_EPLTLSB): Remove. + (R_IA64_TPREL14, R_IA64_TPREL64I): New. + (R_IA64_DTPMOD*): New. + (R_IA64_DTPREL*): New. + +2000-09-29 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (EF_CRIS_UNDERSCORE): New. + +2000-09-27 Alan Modra <alan@linuxcare.com.au> + + * hppa.h (R_PARISC_DIR14F): Add. + +2000-09-14 Alexandre Oliva <aoliva@redhat.com> + + * sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT, + R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Change + numbers to the range from 160 to 167. + (R_SH_FIRST_INVALID_RELOC): Adjust. + (R_SH_FIRST_INVALID_RELOC_2, R_SH_LAST_INVALID_RELOC_2): + New relocs to fill in the gap. + +2000-09-13 Anders Norlander <anorland@acc.umu.se> + + * mips.h (E_MIPS_MACH_4K): New define. + +2000-09-05 Alan Modra <alan@linuxcare.com.au> + + * hppa.h: Fix a comment. + (R_PARISC_PCREL12F): Define. + (R_PARISC_GNU_VTENTRY): Define. + (R_PARISC_GNU_VTINHERIT): Define. + +2000-09-01 Alexandre Oliva <aoliva@redhat.com> + + * sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT, + R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): New relocs. + (R_SH_FIRST_INVALID_RELOC): Adjust. + +2000-08-14 Jim Wilson <wilson@cygnus.com> + + * ia64.h (EF_IA_64_REDUCEDFP, EF_IA_64_CONS_GP, + EF_IA_64_NOFUNCDESC_CONS_GP, EF_IA_64_ABSOLUTE): Define. + +2000-08-07 Nick Clifton <nickc@cygnus.com> + + * ppc.h: Remove spurious CYGNUS LOCAL comments. + * v850.h: Likewise. + +2000-07-22 Jason Eckhardt <jle@cygnus.com> + + * i860.h: New file. + (elf_i860_reloc_type): Defined ELF32 i860 relocations. + +2000-07-20 Hans-Peter Nilsson <hp@axis.com> + + common.h (EM_CRIS): New machine number. + cris.h: New file. + +2000-07-19 H.J. Lu <hjl@gnu.org> + + * common.h (DF_1_NODEFLIB): Renamed from DF_1_NODEPLIB. + +2000-07-19 H.J. Lu <hjl@gnu.org> + + * common.h (DT_CHECKSUM): Set to 0x6ffffdf8. + (DTF_1_CONFEXP): It is 0x00000002 as suspected. + +2000-07-19 H.J. Lu <hjl@gnu.org> + + * common.h (DT_FEATURE): Renamed from DT_FEATURE_1. + (DT_CONFIG): New. From Solaris 8. + (DT_DEPAUDIT): Likewise. + (DT_AUDIT): Likewise. + (DT_PLTPAD): Likewise. + (DT_MOVETAB): Likewise. + (DF_1_NODEPLIB): Likewise. + (DF_1_NODUMP): Likewise. + (DF_1_CONLFAT): Likewise. + (DT_CHECKSUM): Likewise. FIXME. Check the value on Solaris 8. + (DTF_1_CONFEXP): Likewise. + +2000-07-18 H.J. Lu <hjl@gnu.org> + + * common.h (DT_FLAGS_1): Renamed from DT_1_FLAGS. + +2000-07-12 Alan Modra <alan@linuxcare.com.au> + + * internal.h (struct elf_internal_sym): Update comment for st_other. + +2000-07-10 Alan Modra <alan@linuxcare.com.au> + + * hppa.h: Add comments to all the relocs. + +2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl> + + * avr.h (E_AVR_MACH_AVR5): Define. + +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * m68hc11.h: New file, definitions for the Motorola 68hc11. + +2000-06-06 Alan Modra <alan@linuxcare.com.au> + + * reloc-macros.h (START_RELOC_NUMBERS): Don't define initial dummy + -1 valued enum. + (RELOC_NUMBER, FAKE_RELOC, EMPTY_RELOC): Append rather than + prepend comma. + (END_RELOC_NUMBERS): Give macro an arg to define as last enum. + + * alpha.h (R_ALPHA_max): Define via END_RELOC_NUMBERS rather than + with EMPTY_RELOC. + * arc.h (R_ARC_max): Likewise. + * avr.h (R_AVR_max): Likewise. + * fr30.h (R_FR30_max): Likewise. + * hppa.h (R_PARISC_UNIMPLEMENTED): Likewise. + * i960.h (R_960_max): Likewise. + * m32r.h (R_M32R_max): Likewise. + * m68k.h (R_68K_max): Likewise. + * mcore.h (R_MCORE_max): Likewise. + * mn10300.h (R_MN10300_MAX): Likewise. + * pj.h (R_PJ_max): Likewise. + * ppc.h (R_PPC_max): Likewise. + * sh.h (R_SH_max): Likewise. + * sparc.h (R_SPARC_max): Likewise. + * v850.h (R_V850_max): Likewise. + + * arm.h (R_ARM_max): Define via END_RELOC_NUMBERS. + * d10v.h (R_D10V_max): Likewise. + * d30v.h (R_D30V_max): Likewise. + * ia64.h (R_IA64_max): Likewise. + * mips.h (R_MIPS_maxext): Likewise. + * mn10200.h (R_MN10200_max): Likewise. + + * i386.h (R_386_max): Remove old RELOC_NUMBER definition, and + define via END_RELOC_NUMBERS. + +2000-06-03 Alan Modra <alan@linuxcare.com.au> + + * reloc-macros.h (START_RELOC_NUMBERS): Fix name clash for + !__STDC__ case. + (RELOC_NUMBER): Use ansi stringify if ALMOST_STDC defined. + +2000-05-22 Richard Henderson <rth@cygnus.com> + + * ia64.h (R_IA64_PCREL60B, R_IA64_PCREL21BI): New. + (R_IA64_PCREL22, R_IA64_PCREL64I): New. + +2000-05-02 H.J. Lu <hjl@gnu.org> + + * common.h (ELFOSABI_NONE): Renamed from ELFOSABI_SYSV. + (ELFOSABI_MODESTO): Defined. + (ELFOSABI_OPENBSD): Likewise. + +2000-04-21 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + + * ia64.h: New file. + +2000-04-14 H.J. Lu <hjl@gnu.org> + + * common.h (ELFOSABI_TRUE64): Renamed to ELFOSABI_TRU64. + +2000-04-14 H.J. Lu <hjl@gnu.org> + + * common.h (ELFOSABI_NETBSD): Defined. + (ELFOSABI_HURD): Likewise. + (ELFOSABI_SOLARIS): Likewise. + (ELFOSABI_MONTEREY): Likewise. + (ELFOSABI_IRIX): Likewise. + (ELFOSABI_FREEBSD): Likewise. + (ELFOSABI_TRUE64): Likewise. + +2000-04-07 Nick Clifton <nickc@cygnus.com> + + * arm-oabi.h: Delete. + * arm.h: Merge in definitions of old reloc numbers from + arm-oabi.h. + +2000-04-06 Nick Clifton <nickc@cygnus.com> + + * arm.h (EF_ARM_SYMSARESORTED): Define. + (EF_ARM_EABIMASK): Define. + (EF_ARM_EABI_VERSION): Define. + (EF_ARM_EABI_UNKNOWN): Define. + (EF_ARM_EABI_VER1): Define. + (PF_ARM_PI): Define. + (PF_ARM_ABS): Define. + +2000-04-05 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): New RELOC_NUMBERs. + +2000-03-27 Denis Chertykov <denisc@overta.ru> + + * avr.h: New file. AVR ELF support for BFD. + * common.h: Add AVR magic number. + +2000-03-10 Geoffrey Keating <geoffk@cygnus.com> + + * mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16, + R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation + numbers. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * i370.h: New file. + +2000-02-22 Nick Clifton <nickc@cygnus.com> + + * common.h (ELF_ST_OTHER): Remove definition. + (ELF32_ST_OTHER): Remove definition. + (ELF64_ST_OTHER): Remove definition. + +2000-02-22 H.J. Lu <hjl@gnu.org> + + * common.h (ELFOSABI_LINUX): Define. + +2000-02-17 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros. + (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. + (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. + +2000-02-03 H.J. Lu <hjl@gnu.org> + + * arm-oabi.h: Duplicate changes made to arm.h on Jan. 27, + 2000 by Thomas de Lellis <tdel@windriver.com>. + +2000-01-27 Thomas de Lellis <tdel@windriver.com> + + * arm.h (STT_ARM_TFUNC): Define in terms of STT_LOPROC. + (STT_ARM_16BIT): New flag. Denotes a label that was defined in + Thumb block but was does not identify a function. + +2000-01-20 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_MCORE): Fix spelling of Motorola. + * mcore.h (EM_MCORE): Fix spelling of Motorola. + +2000-01-13 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_S370): Change comment - this is now the IBM + System/370. + (EM_IA_64): Change comment - this is now the IA-64. + +2000-01-11 Nick Clifton <nickc@cygnus.com> + + * common.h (DT_ENCODING): Fix definition of this value. + (DT_LOOS): Fix definition of this value. + (DT_HIOS): Fix definition of this value. + (OLD_DT_LOOS): Value of DT_LOOS before Oct 4, 1999 draft + of ELF spec changed it. + (OLD_DT_HIOS): Value of DT_HIOS before Oct 4, 1999 draft + of ELF spec changed it. + +2000-01-10 Egor Duda <deo@logos-m.ru> + + * common.h (NT_WIN32PSTATUS): Define. (cygwin elf core dumps). + +1999-12-28 Nick Clifton <nickc@cygnus.com> + + * mips.h (STO_*): Redefine in terms of STV_* values now in + common.h. + +1999-12-27 Nick Clifton <nickc@cygnus.com> + + * common.h: Upgrade to match Oct4, 1999 Draft ELF ABI Spec. + (EM_MIPS_RS3_LE): New machine number. + (EM_RCE): New machine number. + (EM_MMA): New machine number. + (EM_PCP): New machine number. + (EM_NCPU): New machine number. + (EM_NDR1): New machine number. + (EM_STARCORE): New machine number. + (EM_ME16): New machine number. + (EM_ST100): New machine number. + (EM_TINYJ): New machine number. + (EM_FX66): New machine number. + (EM_ST9PLUS): New machine number. + (EM_ST7): New machine number. + (EM_68HC16): New machine number. + (EM_68HC11): New machine number. + (EM_68HC08): New machine number. + (EM_68HC05): New machine number. + (EM_SVX): New machine number. + (EM_VAX): New machine number. + (PF_MASKOS): Change value. + (SHT_INIT_ARRAY): New value for sh_type field. + (SHT_FINI_ARRAY): New value for sh_type field. + (SHT_PREINIT_ARRAY): New value for sh_type field. + (SHT_HIUSER): Change value. + (SHF_MERGE): New valye for sh_flags field. + (SHF_STRINGS): New valye for sh_flags field. + (SHF_INFO_LINK): New valye for sh_flags field. + (SHF_OS_NONCONFORMING): New valye for sh_flags field. + (SHF_MASKOS): Change value. + (ELF_ST_VISIBILITY): New macro. + (ELF_ST_OTHER): New macro. + (STT_COMMON): New symbol type. + (STV_DEFAULT): Value for symbol visibility. + (STV_INTERNAL): Value for symbol visibility. + (STV_HIDDEN): Value for symbol visibility. + (STV_PROTECTED): Value for symbol visibility. + (DT_RUNPATH): New dynamic section tag. + (DT_FLAGS): New dynamic section tag. + (DT_ENCODING): New dynamic section tag. + (DT_PREINIT_ARRAY): New dynamic section tag. + (DT_PREINIT_ARRAYSZ): New dynamic section tag. + (DT_LOPROC): New dynamic section tag index. + (DT_HIPROC): New dynamic section tag index. + (DF_ORIGIN): Value for dynamic section flag. + (DF_SYMBOLIC): Value for dynamic section flag. + (DF_TEXTREL): Value for dynamic section flag. + (DF_BIND_NOW): Value for dynamic section flag. + +1999-12-09 Fred Fish <fnf@cygnus.com> + + * i960.h (reloc-macros.h): Include using relative dir elf/. + * i386.h (reloc-macros.h): Include using relative dir elf/. + * hppa.h (reloc-macros.h): Include using relative dir elf/. + +1999-12-07 Jim Blandy <jimb@cygnus.com> + + * common.h (NT_PRXFPREG): New definition. + +Wed Dec 1 03:02:15 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (E_MN10300_MACH_AM33): Define. + +Mon Oct 11 22:42:37 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (PF_HP_PAGE_SIZE): Define. + (PF_HP_FAR_SHARED, PF_HP_NEAR_SHARED, PF_HP_CODE): Likewise. + (PF_HP_MODIFY, PF_HP_LAZYSWAP, PF_HP_SBP): Likewise. + +Mon Oct 4 17:42:38 1999 Doug Evans <devans@canuck.cygnus.com> + + * m32r.h (E_M32RX_ARCH): Define. + +1999-09-15 Ulrich Drepper <drepper@cygnus.com> + + * hppa.h: Add DT_HP_GST_SIZE, DT_HP_GST_VERSION, and DT_HP_GST_HASHVAL. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * pj.h: New file. + * common.h (EM_PJ): Define. + +1999-09-02 Ulrich Drepper <drepper@cygnus.com> + + * hppa.h: Add HPUX specific symbol type definitions. + + * hppa.h: Add HPUX specific dynamic and program header table + specific definitions. + +1999-08-31 Scott Bambrough <scottb@netwinder.org> + + * common.h (NT_TASKSTRUCT): Define. + +1999-07-16 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (EF_SPARC_SUN_US3): Define in Cheetah extensions + flag (as per SCD2.4.1). + +1999-07-16 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (ELF64_R_TYPE_DATA): Only use ELF64_R_TYPE bits, not + ELF64_R_SYM bits. + +1999-06-21 Philip Blundell <pb@nexus.co.uk> + + * arm.h (EF_SOFT_FLOAT, F_SOFT_FLOAT): Define. + +1999-07-13 Andreas Schwab <schwab@suse.de> + + * m68k.h (EF_CPU32): Move definition inside multiple inclusion + guard. + +1999-07-08 Richard Henderson <rth@cygnus.com> + + * sparc.h (ELF64_R_TYPE_DATA): Sign extend the value. + (ELF64_R_TYPE_INFO): Mask out all but low 24 bits of data. + (DT_SPARC_PLTFMT): Delete. + Based on a patch from Jakub Jelinek. + +Mon Jun 21 16:36:02 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (elf_hppa_reloc_type): Renamed from elf32_hppa_reloc_type. + +1999-06-10 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (R_SPARC_max_std): Define. + +Wed Jun 9 15:16:34 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Update with various changes from newest PA ELF + specifications. + +1999-06-03 Ian Lance Taylor <ian@zembu.com> + + * common.h (EM_PPC64): Define. + +1999-06-02 Stu Grossman <grossman@babylon-5.cygnus.com> + + * dwarf.h: Add LANG_JAVA. + * dwarf2.h: Add DW_LANG_Java. + +1999-05-29 Nick Clifton <nickc@cygnus.com> + + * common.h (ELFOSABI_ARM): Define. + +1999-05-28 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h: Update comment. + +1999-05-28 Ian Lance Taylor <ian@zembu.com> + + * i960.h: New file. + +1999-05-16 Nick Clifton <nickc@cygnus.com> + + * mcore.h (R_MCORE_COPY): Define. + (R_MCORE_GLOB_DAT): Define. + (R_MCORE_JUMP_SLOT): Define. + +1999-05-15 Nick Clifton <nickc@cygnus.com> + + * mcore.h (R_MCORE_RELATIVE): Define. + +1999-05-05 Catherine Moore <clm@cygnus.com> + + * m68k.h (EF_CPU32): Define. + +1999-04-21 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h (START_RELOC_NUMBERS): Prepend an underscore to + fake reloc entry name (if possible), in order to avoid conflicts + with typedefs of the same name. + +1999-04-16 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (EF_MIPS_32BITMODE): New. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * mcore.h: New header file. Defines for Motorola's MCore + processor. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * common.h: Add new constants defined in: "System V Application + Binary Interface - DRAFT - April 29, 1998" found at the web site: + http://www.sco.com/developer/gabi/contents.html + + (EM_MMA): Removed. Replaced with EM_MCORE as Motorolla own this + value. + +1999-03-31 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h: Fixed to not generate an enum with a trailing + comma. + +1999-03-16 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (E_MIPS_MACH_5000): New. + +1999-03-10 Ulrich Drepper <drepper@cygnus.com> + + * common.h: Add definitions for a few more Solaris ELF extensions. + +Thu Feb 18 18:58:26 1999 Ian Lance Taylor <ian@cygnus.com> + + * external.h: Only use attribute if __GNUC__ is defined. + +1999-02-17 Nick Clifton <nickc@cygnus.com> + + Patch submitted by: Scott Bambrough <scottb@corelcomputer.com> + + * external.h: struct Elf_External_Versym must be packed on + ARM. Code uses sizeof(Elf_External_Versym) and assumes it is + equal to sizeof(char[2]). Reported by Jim Pick <jim@jimpick.com> + +1999-02-02 Nick Clifton <nickc@cygnus.com> + + * dwarf2.h (DWARF2_External_ARange): New structure. + (DWARF2_Internal_ARange): New structure. + +Mon Feb 1 11:33:56 1999 Catherine Moore <clm@cygnus.com> + + * arm.h: Renumber relocs to conform to standard. + (EF_NEW_ABI): Define. + (EF_OLD_ABI): Define. + * arm-oabi.h: New file. + +1999-01-28 Nick Clifton <nickc@cygnus.com> + + * fr30.h: Add R_FR30_GNU_VT{INHERIT,ENTRY} relocs. + +1999-01-27 Nick Clifton <nickc@cygnus.com> + + * dwarf2.h: Add typedefs for structures found in dwarf2 sections. + +1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (E_MIPS_MACH_4111): New. + +1998-12-15 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (EF_MIPS_ABI,E_MIPS_ABI_O32,E_MIPS_ABI_O64, + E_MIPS_ABI_EABI32,E_MIPS_ABI_EABI64): + +1998-12-03 Nick Clifton <nickc@cygnus.com> + + * fr30.h: Add R_FR30_48 reloc. + +1998-12-02 Ulrich Drepper <drepper@cygnus.com> + + * mips.h: Add external data type for conflict section. + + * mips.h: Add more LL_* options from Irix 6.5. + + * mips.h: Add R_MIPS_JALR and adjust R_MIPS_max appropriately. + +Mon Nov 30 15:25:58 1998 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h (elf_sh_reloc_type): Add R_SH_FIRST_INVALID_RELOC, + R_SH_LAST_INVALID_RELOC, R_SH_SWITCH8 and R_SH_max. + +Tue Nov 10 15:12:28 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_CYGNUS_FR30): Reduce to a 16 bit value. + +Tue Nov 10 15:17:28 1998 Catherine Moore <clm@cygnus.com> + + * d10v.h: Add vtable relocs. + +Wed Nov 4 15:56:50 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_CYGNUS_FR30): New machine number. + + * fr30.h: New file: Definitions for the FR30. + +Fri Oct 30 11:54:15 1998 Catherine Moore <clm@cygnus.com> + + From Philip Blundell <pb@nexus.co.uk>: + * arm.h (R_ARM_COPY, et al.): New relocs, used by Linux for PIC. + (EF_ALIGN8): New flag. + +Tue Oct 20 11:19:50 1998 Ian Lance Taylor <ian@cygnus.com> + + * common.h (NT_LWPSTATUS): Close comment accidentally left open. + +Mon Oct 19 20:24:11 1998 Catherine Moore <clm@cygnus.com> + + * sh.h: Add vtable relocs. + +Mon Oct 19 01:44:42 1998 Felix Lee <flee@cygnus.com> + + * common.h (NT_PSTATUS, NT_FPREGS, NT_PSINFO, + NT_LWPSTATUS,NT_LWPSINFO): added. + * internal.h (Elf_Internal_Note): new structure members. + +Fri Oct 16 14:11:25 1998 Catherine Moore <clm@cygnus.com> + + * m32r.h: Add vtable relocs. + +Tue Oct 6 09:22:22 1998 Catherine Moore <clm@cygnus.com> + + * sparc.h: Add vtable relocs. + +Mon Oct 5 09:39:22 1998 Catherine Moore <clm@cygnus.com> + + * v850.h: Add vtable relocs. + +Sun Oct 4 21:17:51 1998 Ian Lance Taylor <ian@cygnus.com> + + * i386.h (R_386_max): Change from 252 to 24. + +Mon Sep 21 12:24:44 1998 Catherine Moore <clm@cygnus.com> + + * i386.h: Change vtable reloc numbers. + +Sun Sep 20 00:54:22 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k.h: Add vtable relocs and R_68K_max. + +Tue Sep 15 09:56:49 CDT 1998 Catherine Moore <clm@cygnus.com> + + * arm.h: Add vtable relocs. + +Mon Aug 31 11:25:27 1998 Catherine Moore <clm@cygnus.com> + + * arm.h: Define STT_ARM_TFUNC. Remove ST_THUMB_xxxx + definitions. + +Sat Aug 29 22:25:51 1998 Richard Henderson <rth@cygnus.com> + + * i386.h: Add vtable relocs. + +1998-08-25 16:42 Ulrich Drepper <drepper@cygnus.com> + + * common.h: Add SYMINFO_* macros to access Elf*_Syminfo information. + + * external.h: Add Elf_External_Syminfo definition. + + * internal.h: Add Elf_Internal_Syminfo, Elf32_Internal_Syminfo, + and Elf64_Syminfo definitions. + +Sun Aug 9 20:26:49 CDT 1998 Catherine Moore <clm@cygnus.com> + + * arm.h: Add ST_THUMB definitions. + +Wed Aug 5 15:52:35 1998 Nick Clifton <nickc@cygnus.com> + + * arm.h: Add ELF header flags to specify compile time optins: + EF_INTERWORK: New flag. + EF_APCS_26: New flag. + EF_APCS_FLOAT: New flag. + EF_PIC: New flag. + +1998-07-31 21:28 Ulrich Drepper <drepper@cygnus.com> + + * mips.h: Add missing RHF_* constants. + +Fri Jul 31 10:01:40 1998 Catherine Moore <clm@cygnus.com> + + * arm.h: Add R_ARM_THM_PC9 relocation. + +1998-07-30 16:25 Ulrich Drepper <drepper@cygnus.com> + + * common.h: Add new DT_* entries and there flag macros from Solaris. + +Tue Jul 28 18:14:07 1998 Stan Cox <scox@equinox.cygnus.com> + + * sparc.h: (R_SPARC_REV32): Added for little endian data e.g. sparc 86x. + +Fri Jul 24 11:22:06 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add R_MN10300_24 relocation. + +1998-07-24 Ulrich Drepper <drepper@cygnus.com> + + * mips.h: Add MIPS64 relocation names and values. + +Wed Jul 22 19:29:00 Catherine Moore <clm@cygnus.com> + + * arm.h: Rename relocations. + +1998-07-22 Ulrich Drepper <drepper@cygnus.com> + + * ppc.h: Define enum as elf_ppc_reloc_type. + +Wed Jul 22 16:22:11 1998 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h: New file. Provides relocation macros: + START_RELOC_NUMBERS, RELOC_NUMBER, FAKE_RELOC, EMPTY_RELOC and + END_RELOC_NUMBERS used by other elf header files. + + * alpha.h: Use reloc-macros.h. + * arc.h: Use reloc-macros.h. + * arm.h: Use reloc-macros.h. + * d10v.h: Use reloc-macros.h. + * d30v.h: Use reloc-macros.h. + * hppa.h: Use reloc-macros.h. + * i386.h: Use reloc-macros.h. + * m32r.h: Use reloc-macros.h. + * m68k.h: Use reloc-macros.h. + * mips.h: Use reloc-macros.h. + * mn10200.h: Use reloc-macros.h. + * mn10300.h: Use reloc-macros.h. + * ppc.h: Use reloc-macros.h. + * sh.h: Use reloc-macros.h. + * sparc.h: Use reloc-macros.h. + * v850.h: Use reloc-macros.h. + +1998-07-22 13:07 Ulrich Drepper <drepper@cygnus.com> + + * mn10300.h: Rewrite relocation definition using macros. + * mips.h: Likewise. + * ppc.h: Likewise. + * alpha.h: Likewise. + * arm.h: Likewise. + * d10v.h: Likewise. + * d30v.h: Likewise. + * m32r.h: Likewise. + * m68k.h: Likewise. + * mn10200.h: Likewise. + * sh.h: Likewise. + * sparc.h: Likewise. + +1998-07-21 13:07 Ulrich Drepper <drepper@cygnus.com> + + * arm.h: New file. + * d10v.h: New file. + * d30v.h: New file. + * i386.h: New file. + * m68k.h: New file. + * mn10200.h: New file. + * sh.h: New file. + + * mips.h: Add R_MIPS_* and SHT_MIPS_* entries. + + * mn10300.h: Add R_MN10300_* entries. + + * ppc.h: Add R_PPC_* entries. + +1998-07-20 07:11 Ulrich Drepper <drepper@cygnus.com> + + * mips.h: Add ODK_*, OEX_*, OPAD_*, OHW_*, and OGP_* constants. + Define Elf32_External_Lib. + +1998-07-19 15:24 Ulrich Drepper <drepper@cygnus.com> + + * mips.h (PT_MIPS_OPTIONS): New symbol. + Add lots of DT_MIPS_* symbols. + +Fri Jun 26 10:46:35 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: New file. + +Thu Jun 18 19:27:56 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_960, EM_V800, EM_FR20, EM_RH32, EM_MMA, + EM_OLD_ALPHA): Add these constants. + +Thu Jun 11 17:59:01 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_486, EM_S370): Add these constants. + +Tue Jun 9 09:35:29 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_ARM): Add this constant. + +Wed May 6 09:45:30 1998 Gavin Koch <gavin@cygnus.com> + + * mips.h (EF_MIPS_MACH,E_MIPS_MACH_*): Added. + +Sat Apr 25 18:35:06 1998 Richard Henderson <rth@cygnus.com> + + * alpha.h (STO_ALPHA_NOPV, STO_ALPHA_STD_GPLOAD): New. + +Wed Apr 15 15:42:45 1998 Richard Henderson <rth@cygnus.com> + + * common.h (EM_SPARC64): Move and rename to EM_OLD_SPARCV9. + (EM_SPARCV9): New. This is the official ABI name and number. + +Sat Feb 28 17:04:41 1998 Richard Henderson <rth@cygnus.com> + + * alpha.h (EF_ALPHA_32BIT, EF_ALPHA_CANRELAX): New. + +Mon Dec 15 15:07:49 1997 Nick Clifton <nickc@cygnus.com> + + * m32r.h (EF_M32R_ARCH, E_M32R_ARCH): New flags to + specify machine architecture. + +Fri Dec 5 11:20:08 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h: New constants: SHN_V850_SCOMMON, SHN_V850_TCOMMON, + SHN_V850_ZCOMMON, SHT_V850_SCOMMON, SHT_V850_TCOMMON, + SHT_V850_ZCOMMON to handle v850 common sections. + enum reloc_type renamed to v850_reloc_type to avoid name + conflict. + +Thu Oct 23 13:55:24 1997 Richard Henderson <rth@cygnus.com> + + * sparc.h (enum elf_sparc_reloc_type): Add UA64 & UA16. + +Thu Oct 23 00:42:04 1997 Richard Henderson <rth@dot.cygnus.com> + + * sparc.h (DT_SPARC_REGISTER): New macro. + (DT_SPARC_PLTFMT): In support of old sparc64-linux .plts; will + go away soon. + +Tue Sep 30 13:26:58 1997 Doug Evans <dje@canuck.cygnus.com> + + * sparc.h (EF_SPARC_HAL_R1, EF_SPARC_EXT_MASK): New macros. + (EF_SPARCV9_{MM,TSO,PSO,RMO}): New macros. + (SHN_BEFORE,SHN_AFTER): New macros. + (SHF_EXCLUDE,SHF_ORDERED): New macros. + (STT_REGISTER): New macro. + (R_SPARC_GLOB_JMP): Deleted, but slot reserved. + (R_SPARC_{DISP64,PLT64,HIX22,LOX10}): New relocations. + (R_SPARC_{H44,M44,L44,REGISTER}): New relocations. + (ELF64_R_TYPE_{DATA,ID,INFO}): New macros. + +Wed Sep 17 16:41:42 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h: Add R_V850_CALLT_6_7_OFFSET and R_V850_CALLT_16_16_OFFSET. + +Tue Sep 16 14:16:17 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (reloc_type): Add R_V850_TDA_16_16_OFFSET. + +Wed Sep 3 15:11:14 1997 Richard Henderson <rth@cygnus.com> + + * mips.h: Correct typo in comment. + +Wed Sep 3 11:25:57 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (reloc_type): Remove R_V850_16_PCREL. + +Tue Sep 2 17:41:05 1997 Nick Clifton <nickc@cygnus.com> + + * common.h: Remove magic number for V850E. + * common.h: Remove magic number for V850EA. + * v850.h: Add new flags for e_flags field in elf header. + +Mon Aug 25 16:06:47 1997 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_CYGNUS_V850E): backend magic number for v850e. + * common.h (EM_CYGNUS_V850EA): backend magic number for v850ea. + +Mon Aug 18 11:05:23 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (reloc_type): Add 16 bit PC relative relocation. + +Fri Aug 15 05:10:09 1997 Doug Evans <dje@canuck.cygnus.com> + + * arc.h (enum reloc): Move here from elf32-arc.c. + +Fri Aug 8 17:05:29 1997 Doug Evans <dje@canuck.cygnus.com> + + * arc.h: New file. + * common.h (EM_CYGNUS_ARC): Define. + +Mon Jun 16 14:46:12 1997 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (Elf_Internal_Ehdr): Change e_phoff and e_shoff from + bfd_signed_vma to bfd_size_type, as they are not signed. + +Wed Mar 5 15:35:26 1997 Doug Evans <dje@seba.cygnus.com> + + * m32r.h (SHF_M32R_CAN_RELAX): Define. + +Mon Feb 24 17:49:01 1997 Ian Lance Taylor <ian@cygnus.com> + + * external.h: Dump the 32/64 bit specific forms of the version + structures, and just define them as size independent. + + * common.h (VERSYM_HIDDEN, VERSYM_VERSION): Define. + +Fri Feb 21 13:00:34 1997 Doug Evans <dje@canuck.cygnus.com> + + * m32r.h (enum reloc_type): Add R_M32R_SDA16. + (SHN_M32R_SCOMMON): Define. + +Wed Feb 19 15:35:31 1997 Ian Lance Taylor <ian@cygnus.com> + + From Eric Youngdale <eric@andante.jic.com>: + * external.h, internal.h, common.h: Added new structures and + definitions for ELF versions. + +Tue Feb 18 17:40:36 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * common.h (EM_CYGNUS_D30V): Define. + +Mon Jan 27 11:54:44 1997 Doug Evans <dje@seba.cygnus.com> + + * m32r.h (enum reloc_type): Add R_M32R_HI16_[SU]LO,R_M32R_LO16. + +Fri Jan 3 11:32:51 1997 Michael Meissner <meissner@tiktok.cygnus.com> + + * v850.h (V850_OTHER_{TDA_BYTE,ERROR}): New bits for the st_other + field. + (SHN_V850_*): Remove v850 specific section indexes, which are not + needed. + (enum reloc_type): Move the v850 relocations here from + elf32-v850.c + +Thu Jan 2 19:30:23 1997 Michael Meissner <meissner@tiktok.cygnus.com> + + * v850.h: New file, provide V850 specific definitions. + +Tue Dec 31 14:44:32 1996 Ian Lance Taylor <ian@cygnus.com> + + * common.h (DT_AUXILIARY): Define. + (DT_FILTER): Define. + +Wed Dec 4 05:03:37 1996 Jason Merrill <jason@yorick.cygnus.com> + + * dwarf2.h: Update. + +Tue Nov 26 10:44:47 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (STO_MIPS16): Define. + +Tue Nov 12 15:45:42 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v.h: Remove empty file. + +Tue Oct 8 11:31:24 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (EF_MIPS_ABI2): Define. + +Thu Oct 3 10:01:40 1996 Jeffrey A Law (law@cygnus.com) + + * common.h: Break mn10x00 support into mn10200 and mn10300. + +Wed Oct 2 21:26:43 1996 Jeffrey A Law (law@cygnus.com) + + * common.h (EM_CYGNUS_MN10x00): Define. + +Mon Sep 23 09:18:04 1996 Doug Evans <dje@seba.cygnus.com> + + * m32r.h: New file. + +Fri Aug 30 17:06:21 1996 Ian Lance Taylor <ian@cygnus.com> + + * common.h (EM_SH): Define. + +Tue Aug 20 14:47:54 1996 J.T. Conklin <jtc@hippo.cygnus.com> + + * common.h (EM_CYGNUS_V850): Define. + +Mon Aug 19 10:59:10 1996 Doug Evans <dje@canuck.cygnus.com> + + * common.h (EM_CYGNUS_M32R): Define. + +Mon Jul 22 18:59:55 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (SHT_MIPS_IFACE, SHT_MIPS_CONTENT): Define. + (SHT_MIPS_SYMBOL_LIB): Define. + (SHF_MIPS_MERGE, SHF_MIPS_ADDR32, SHF_MIPS_ADDR64): Define. + (SHF_MIPS_NOSTRIP, SHF_MIPS_LOCAL, SHF_MIPS_NAMES): Define. + +Thu Jul 18 19:12:15 1996 Stan Shebs <shebs@andros.cygnus.com> + + * dwarf2.h: New file. + +Jul 18 13:20:39 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * common.h (EM_CYGNUS_D10V): Define. + * d10v.h: New file. + +Fri Jun 21 12:33:24 1996 Richard Henderson <rth@tamu.edu> + + * alpha.h: New file. + * common.h (EM_ALPHA): Define. + +Fri May 31 17:28:05 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (Elf_External_Options, Elf_Internal_Options): Define. + (bfd_mips_elf_swap_options_in): Declare. + (bfd_mips_elf_swap_options_out): Declare. + (ODK_*): Define. + (Elf64_External_RegInfo, Elf64_Internal_RegInfo): Define. + (bfd_mips_elf64_swap_reginfo_in): Declare. + (bfd_mips_elf64_swap_reginfo_out): Declare. + +Thu May 30 12:35:57 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (E_MIPS_ARCH_4): Define. + +Wed May 29 15:35:33 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (Elf64_Mips_External_Rel): Define. + (Elf64_Mips_Internal_Rel): Define. + (Elf64_Mips_External_Rela, Elf64_Mips_Internal_Rela): Define. + (RSS_*): Define. + +Mon Apr 22 18:26:30 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc.h (R_SPARC_[56]): Always define. + +Mon Feb 19 01:55:56 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc.h (R_SPARC_{PLT32,HIPLT22,LOPLT10,PCPLT32,PCPLT22, + PCPLT10,5,6}): Don't define ifdef SPARC64_OLD_RELOCS. + +Tue Feb 6 11:33:58 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc.h (enum sparc_elf_reloc_type): Define. + +Wed Jan 17 09:09:16 1996 Doug Evans <dje@canuck.cygnus.com> + + * common.h: Define EM_SPARC32PLUS. + * sparc.h: New file. + +Thu Jan 11 16:27:34 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc.h (SHF_EXCLUDE, SHT_ORDERED): New fields from the abi. + +Thu Nov 30 16:47:18 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (struct elf_segment_map): Add includes_filehdr and + includes_phdrs fields. + +Tue Nov 28 16:58:10 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (struct elf_segment_map): Define. + +Tue Oct 31 15:19:36 1995 Fred Fish <fnf@cygnus.com> + + * common.h, dwarf.h, external.h, hppa.h, internal.h, + mips.h, ppc.h: Protect against multiple inclusions. + +Thu Sep 21 13:51:58 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc.h (EF_PPC_RELOCATABLE_LIB): Add new flag bit. + +Fri Sep 1 15:32:17 1995 Kazumoto Kojima <kkojima@info.kanagawa-u.ac.jp> + + * mips.h: Add some definitions used on Irix 5. + +Tue Jun 20 10:18:28 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa.h (CPU_PA_RISC1_0): Protect from redefinitions. + (CPU_PA_RISC1_1): Likewise. + +Wed Mar 8 18:14:37 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc.h: New file for PowerPC support. + +Tue Feb 14 13:59:13 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * common.h (EM_PPC): Use offical value of 20, not 17. + (EM_PPC_OLD): Define this to be the old value of EM_PPC. + +Tue Jan 24 09:40:59 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * common.h (EM_PPC): New macro, PowerPC machine id. + +Tue Jan 17 10:51:38 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * mips.h (SHT_MIPS_MSYM, SHT_MIPS_DWARF, SHT_MIPS_EVENTS): Define. + +Mon Oct 17 13:43:59 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * internal.h (Elf_Internal_Shdr): Remove rawdata and size fields. + Add bfd_section field. + +Tue May 24 16:11:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (Elf32_External_gptab): Define. + +Mon May 16 13:22:04 1994 Jeff Law (law@snake.cs.utah.edu) + + * common.h (EM_HPPA): Delete. + (EM_PARISC): Add. + * hppa.h: New file. + +Mon May 9 13:27:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * common.h (SHN_LORESERVE): Rename from SHN_LORESERV. + (ELF32_R_TYPE, ELF32_R_INFO): Don't rely on size of unsigned char. + (ELF64_R_TYPE): Don't rely on size of unsigned long. + +Mon Apr 25 15:53:09 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (Elf_Internal_Shdr): Use PTR, not void *. + +Fri Mar 11 00:34:59 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * mips.h (SHN_MIPS_TEXT, SHN_MIPS_DATA): Define. + +Sat Mar 5 14:08:54 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * internal.h: Remove Elf32_*, Elf64_* typedefs. These names + cause conflicts with system headers, e.g. link.h in gdb/solib.c. + Combine 32- and 64-bit versions of *_Internal_Dyn. + * common.h: Replace uses of Elf64_Word, Elf64_Xword typedefs + by their expansion. + * mips.h: Replace uses of Elf32_Word, Elf32_Sword, Elf32_Addr + typedefs by their expansion. Add DT_MIPS_RLD_MAP definition. + +Fri Feb 18 10:39:54 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * common.h (EM_CYGNUS_POWERPC): Define. This may be temporary, + depending upon how quickly I can find a real PowerPC ABI. + +Mon Feb 7 08:27:13 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * internal.h: Change HOST_64_BIT to BFD_HOST_64_BIT. + +Wed Feb 2 14:12:18 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * common.h: Add comments regarding value of EM_HPPA and how to + pick an unofficial value. + +Wed Nov 17 17:14:26 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (SHT_MIPS_OPTIONS): Define. + +Mon Nov 8 17:57:00 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h: Added some more MIPS ABI macro definitions. + +Wed Nov 3 22:07:17 1993 Ken Raeburn (raeburn@rtl.cygnus.com) + + * common.h (EM_MIPS_RS4_BE): New macro. + +Tue Oct 12 07:28:18 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h: New file. MIPS ABI specific information. + +Mon Jun 21 13:13:43 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) + + * internal.h: Combined 32- and 64-bit versions of all structures + except *_Internal_Dyn. This will simply the assembler interface, + and some bfd code. + +Tue May 25 02:00:16 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * external.h, internal.h, common.h: Added 64-bit versions of some + structures and macros. Renamed old versions to put "32" in the + name. Some are unchanged. + +Thu Apr 29 12:12:20 1993 Ken Raeburn (raeburn@deneb.cygnus.com) + + * common.h (EM_HPPA, NT_VERSION, STN_UNDEF, DT_*): New macros. + * external.h (Elf_External_Dyn): New type. + + * internal.h (Elf_Intenral_Shdr): New field `size'. + (Elf_Internal_Dyn): New type. + +Tue Apr 20 16:03:45 1993 Fred Fish (fnf@cygnus.com) + + * dwarf.h (LANG_CHILL): Change value to one randomly picked in + the user defined range, to reduce probability of collisions. + +Sun Nov 15 09:34:02 1992 Fred Fish (fnf@cygnus.com) + + * dwarf.h (AT_src_coords): Whitespace change only. + * dwarf.h (AT_body_begin, AT_body_end, LANG_MODULA2): + Add from latest gcc. + * dwarf.h (LANG_CHILL): Add as GNU extension. + +Sat Aug 1 13:46:53 1992 Fred Fish (fnf@cygnus.com) + + * dwarf.h: Replace with current version from gcc distribution. + +Fri Jun 19 19:05:09 1992 John Gilmore (gnu at cygnus.com) + + * internal.h: Add real struct tags to all the Type_Defs, so they + can be used in prototypes where the Type_Defs are not known. + +Fri Apr 3 20:58:58 1992 Mark Eichin (eichin at cygnus.com) + + * common.h: added ELF_R_{SYM,TYPE,INFO} for handling relocation + info + added EM_MIPS, and corrected value of EM_860 based on System V ABI + manual. + + * external.h: added Elf_External_{Rel,Rela}. + + * internal.h: added Elf_Internal_{Rel,Rela}. + added rawdata to Elf_Internal_Shdr. + +Sat Nov 30 20:43:59 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * common.h, dwarf.h, external.h, internal.h, ChangeLog; moved from + ../elf-<foo> + + +Local Variables: +version-control: never +End: diff --git a/include/elf/alpha.h b/include/elf/alpha.h new file mode 100644 index 000000000..0313b5be6 --- /dev/null +++ b/include/elf/alpha.h @@ -0,0 +1,126 @@ +/* ALPHA ELF support for BFD. + Copyright 1996, 1998, 2000 Free Software Foundation, Inc. + + By Eric Youngdale, <eric@aib.com>. No processor supplement available + for this platform. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the ALPHA ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_ALPHA_H +#define _ELF_ALPHA_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* All addresses must be below 2GB. */ +#define EF_ALPHA_32BIT 0x00000001 + +/* All relocations needed for relaxation with code movement are present. */ +#define EF_ALPHA_CANRELAX 0x00000002 + +/* Processor specific section flags. */ + +/* This section must be in the global data area. */ +#define SHF_ALPHA_GPREL 0x10000000 + +/* Section contains some sort of debugging information. The exact + format is unspecified. It's probably ECOFF symbols. */ +#define SHT_ALPHA_DEBUG 0x70000001 + +/* Section contains register usage information. */ +#define SHT_ALPHA_REGINFO 0x70000002 + +/* A section of type SHT_MIPS_REGINFO contains the following + structure. */ +typedef struct +{ + /* Mask of general purpose registers used. */ + unsigned long ri_gprmask; + /* Mask of co-processor registers used. */ + unsigned long ri_cprmask[4]; + /* GP register value for this object file. */ + long ri_gp_value; +} Elf64_RegInfo; + +/* Special values for the st_other field in the symbol table. */ + +#define STO_ALPHA_NOPV 0x80 +#define STO_ALPHA_STD_GPLOAD 0x88 + +#include "elf/reloc-macros.h" + +/* Alpha relocs. */ +START_RELOC_NUMBERS (elf_alpha_reloc_type) + RELOC_NUMBER (R_ALPHA_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_ALPHA_REFLONG, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_ALPHA_REFQUAD, 2) /* Direct 64 bit */ + RELOC_NUMBER (R_ALPHA_GPREL32, 3) /* GP relative 32 bit */ + RELOC_NUMBER (R_ALPHA_LITERAL, 4) /* GP relative 16 bit w/optimization */ + RELOC_NUMBER (R_ALPHA_LITUSE, 5) /* Optimization hint for LITERAL */ + RELOC_NUMBER (R_ALPHA_GPDISP, 6) /* Add displacement to GP */ + RELOC_NUMBER (R_ALPHA_BRADDR, 7) /* PC+4 relative 23 bit shifted */ + RELOC_NUMBER (R_ALPHA_HINT, 8) /* PC+4 relative 16 bit shifted */ + RELOC_NUMBER (R_ALPHA_SREL16, 9) /* PC relative 16 bit */ + RELOC_NUMBER (R_ALPHA_SREL32, 10) /* PC relative 32 bit */ + RELOC_NUMBER (R_ALPHA_SREL64, 11) /* PC relative 64 bit */ + + /* Skip 12 - 16; deprecated ECOFF relocs. */ + + RELOC_NUMBER (R_ALPHA_GPRELHIGH, 17) /* GP relative 32 bit, high 16 bits */ + RELOC_NUMBER (R_ALPHA_GPRELLOW, 18) /* GP relative 32 bit, low 16 bits */ + RELOC_NUMBER (R_ALPHA_GPREL16, 19) /* GP relative 16 bit */ + + /* Skip 20 - 23; deprecated ECOFF relocs. */ + + /* These relocations are specific to shared libraries. */ + RELOC_NUMBER (R_ALPHA_COPY, 24) /* Copy symbol at runtime */ + RELOC_NUMBER (R_ALPHA_GLOB_DAT, 25) /* Create GOT entry */ + RELOC_NUMBER (R_ALPHA_JMP_SLOT, 26) /* Create PLT entry */ + RELOC_NUMBER (R_ALPHA_RELATIVE, 27) /* Adjust by program base */ + + /* Like BRADDR, but assert that the source and target object file + share the same GP value, and adjust the target address for + STO_ALPHA_STD_GPLOAD. */ + RELOC_NUMBER (R_ALPHA_BRSGP, 28) + + /* Thread-Local Storage. */ + RELOC_NUMBER (R_ALPHA_TLSGD, 29) + RELOC_NUMBER (R_ALPHA_TLSLDM, 30) + RELOC_NUMBER (R_ALPHA_DTPMOD64, 31) + RELOC_NUMBER (R_ALPHA_GOTDTPREL, 32) + RELOC_NUMBER (R_ALPHA_DTPREL64, 33) + RELOC_NUMBER (R_ALPHA_DTPRELHI, 34) + RELOC_NUMBER (R_ALPHA_DTPRELLO, 35) + RELOC_NUMBER (R_ALPHA_DTPREL16, 36) + RELOC_NUMBER (R_ALPHA_GOTTPREL, 37) + RELOC_NUMBER (R_ALPHA_TPREL64, 38) + RELOC_NUMBER (R_ALPHA_TPRELHI, 39) + RELOC_NUMBER (R_ALPHA_TPRELLO, 40) + RELOC_NUMBER (R_ALPHA_TPREL16, 41) + +END_RELOC_NUMBERS (R_ALPHA_max) + +#define LITUSE_ALPHA_ADDR 0 +#define LITUSE_ALPHA_BASE 1 +#define LITUSE_ALPHA_BYTOFF 2 +#define LITUSE_ALPHA_JSR 3 +#define LITUSE_ALPHA_TLSGD 4 +#define LITUSE_ALPHA_TLSLDM 5 + +#endif /* _ELF_ALPHA_H */ diff --git a/include/elf/arc.h b/include/elf/arc.h new file mode 100644 index 000000000..6e94c29db --- /dev/null +++ b/include/elf/arc.h @@ -0,0 +1,56 @@ +/* ARC ELF support for BFD. + Copyright 1995, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + Contributed by Doug Evans, (dje@cygnus.com) + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the ARC ELF ABI. */ + +#ifndef _ELF_ARC_H +#define _ELF_ARC_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ + +START_RELOC_NUMBERS (elf_arc_reloc_type) + RELOC_NUMBER (R_ARC_NONE, 0) + RELOC_NUMBER (R_ARC_32, 1) + RELOC_NUMBER (R_ARC_B26, 2) + RELOC_NUMBER (R_ARC_B22_PCREL, 3) +END_RELOC_NUMBERS (R_ARC_max) + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Four bit ARC machine type field. */ + +#define EF_ARC_MACH 0x0000000f + +/* Various CPU types. */ + +#define E_ARC_MACH_ARC5 0 +#define E_ARC_MACH_ARC6 1 +#define E_ARC_MACH_ARC7 2 +#define E_ARC_MACH_ARC8 3 + +/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. */ + +/* File contains position independent code. */ + +#define EF_ARC_PIC 0x00000100 + +#endif /* _ELF_ARC_H */ diff --git a/include/elf/arm.h b/include/elf/arm.h new file mode 100644 index 000000000..05ba3464f --- /dev/null +++ b/include/elf/arm.h @@ -0,0 +1,161 @@ +/* ARM ELF support for BFD. + Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_ARM_H +#define _ELF_ARM_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_ARM_INTERWORK 0x04 +#define EF_ARM_APCS_26 0x08 +#define EF_ARM_APCS_FLOAT 0x10 +#define EF_ARM_PIC 0x20 +#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ +#define EF_ARM_NEW_ABI 0x80 +#define EF_ARM_OLD_ABI 0x100 +#define EF_ARM_SOFT_FLOAT 0x200 +#define EF_ARM_VFP_FLOAT 0x400 +#define EF_ARM_MAVERICK_FLOAT 0x800 + +/* Other constants defined in the ARM ELF spec. version B-01. */ +#define EF_ARM_SYMSARESORTED 0x04 /* NB conflicts with EF_INTERWORK */ +#define EF_ARM_DYNSYMSUSESEGIDX 0x08 /* NB conflicts with EF_APCS26 */ +#define EF_ARM_MAPSYMSFIRST 0x10 /* NB conflicts with EF_APCS_FLOAT */ +#define EF_ARM_EABIMASK 0xFF000000 + +/* Constants defined in AAELF. */ +#define EF_ARM_BE8 0x00800000 +#define EF_ARM_LE8 0x00400000 + +#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) +#define EF_ARM_EABI_UNKNOWN 0x00000000 +#define EF_ARM_EABI_VER1 0x01000000 +#define EF_ARM_EABI_VER2 0x02000000 +#define EF_ARM_EABI_VER3 0x03000000 + +/* Local aliases for some flags to match names used by COFF port. */ +#define F_INTERWORK EF_ARM_INTERWORK +#define F_APCS26 EF_ARM_APCS_26 +#define F_APCS_FLOAT EF_ARM_APCS_FLOAT +#define F_PIC EF_ARM_PIC +#define F_SOFT_FLOAT EF_ARM_SOFT_FLOAT +#define F_VFP_FLOAT EF_ARM_VFP_FLOAT + +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ + +/* ARM-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ + +/* ARM-specific program header flags. */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ +#define PF_ARM_PI 0x20000000 /* Segment is position-independent. */ +#define PF_ARM_ABS 0x40000000 /* Segment must be loaded at its base address. */ + +/* Relocation types. */ + +START_RELOC_NUMBERS (elf_arm_reloc_type) + RELOC_NUMBER (R_ARM_NONE, 0) + RELOC_NUMBER (R_ARM_PC24, 1) + RELOC_NUMBER (R_ARM_ABS32, 2) + RELOC_NUMBER (R_ARM_REL32, 3) +#ifdef OLD_ARM_ABI + RELOC_NUMBER (R_ARM_ABS8, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_THM_PC22, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_AMP_VCALL9, 10) + RELOC_NUMBER (R_ARM_THM_PC11, 11) /* Cygnus extension to abi: Thumb unconditional branch. */ + RELOC_NUMBER (R_ARM_THM_PC9, 12) /* Cygnus extension to abi: Thumb conditional branch. */ + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14) +#else /* not OLD_ARM_ABI */ + RELOC_NUMBER (R_ARM_PC13, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_ABS8, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_THM_PC22, 10) + RELOC_NUMBER (R_ARM_THM_PC8, 11) + RELOC_NUMBER (R_ARM_AMP_VCALL9, 12) + RELOC_NUMBER (R_ARM_SWI24, 13) + RELOC_NUMBER (R_ARM_THM_SWI8, 14) + RELOC_NUMBER (R_ARM_XPC25, 15) + RELOC_NUMBER (R_ARM_THM_XPC22, 16) +#endif /* not OLD_ARM_ABI */ + RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ + RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry. */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address. */ +#ifdef OLD_ARM_ABI + FAKE_RELOC (FIRST_INVALID_RELOC, 28) + FAKE_RELOC (LAST_INVALID_RELOC, 249) +#else /* not OLD_ARM_ABI */ + FAKE_RELOC (FIRST_INVALID_RELOC1, 28) + FAKE_RELOC (LAST_INVALID_RELOC1, 31) + RELOC_NUMBER (R_ARM_ALU_PCREL7_0, 32) + RELOC_NUMBER (R_ARM_ALU_PCREL15_8, 33) + RELOC_NUMBER (R_ARM_ALU_PCREL23_15, 34) + RELOC_NUMBER (R_ARM_LDR_SBREL_11_0, 35) + RELOC_NUMBER (R_ARM_ALU_SBREL_19_12, 36) + RELOC_NUMBER (R_ARM_ALU_SBREL_27_20, 37) + RELOC_NUMBER (R_ARM_TARGET1, 38) + RELOC_NUMBER (R_ARM_ROSEGREL32, 39) + RELOC_NUMBER (R_ARM_V4BX, 40) + RELOC_NUMBER (R_ARM_TARGET2, 41) + RELOC_NUMBER (R_ARM_PREL31, 42) + FAKE_RELOC (FIRST_INVALID_RELOC2, 43) + FAKE_RELOC (LAST_INVALID_RELOC2, 94) + RELOC_NUMBER (R_ARM_GOT_ABS, 95) + RELOC_NUMBER (R_ARM_GOT_PREL, 96) + RELOC_NUMBER (R_ARM_GOT_BREL12, 97) + RELOC_NUMBER (R_ARM_GOTOFF12, 98) + RELOC_NUMBER (R_ARM_GOTRELAX, 99) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) + RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch. */ + RELOC_NUMBER (R_ARM_THM_PC9, 103) /* Cygnus extension to abi: Thumb conditional branch. */ + FAKE_RELOC (FIRST_INVALID_RELOC3, 104) + FAKE_RELOC (LAST_INVALID_RELOC3, 248) + RELOC_NUMBER (R_ARM_RXPC25, 249) +#endif /* not OLD_ARM_ABI */ + RELOC_NUMBER (R_ARM_RSBREL32, 250) + RELOC_NUMBER (R_ARM_THM_RPC22, 251) + RELOC_NUMBER (R_ARM_RREL32, 252) + RELOC_NUMBER (R_ARM_RABS32, 253) + RELOC_NUMBER (R_ARM_RPC24, 254) + RELOC_NUMBER (R_ARM_RBASE, 255) +END_RELOC_NUMBERS (R_ARM_max) + +/* The name of the note section used to identify arm variants. */ +#define ARM_NOTE_SECTION ".note.gnu.arm.ident" + +#endif /* _ELF_ARM_H */ diff --git a/include/elf/avr.h b/include/elf/avr.h new file mode 100644 index 000000000..59cf07347 --- /dev/null +++ b/include/elf/avr.h @@ -0,0 +1,58 @@ +/* AVR ELF support for BFD. + Copyright 1999, 2000 Free Software Foundation, Inc. + Contributed by Denis Chertykov <denisc@overta.ru> + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_AVR_H +#define _ELF_AVR_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_AVR_MACH 0xf + +#define E_AVR_MACH_AVR1 1 +#define E_AVR_MACH_AVR2 2 +#define E_AVR_MACH_AVR3 3 +#define E_AVR_MACH_AVR4 4 +#define E_AVR_MACH_AVR5 5 + +/* Relocations. */ +START_RELOC_NUMBERS (elf_avr_reloc_type) + RELOC_NUMBER (R_AVR_NONE, 0) + RELOC_NUMBER (R_AVR_32, 1) + RELOC_NUMBER (R_AVR_7_PCREL, 2) + RELOC_NUMBER (R_AVR_13_PCREL, 3) + RELOC_NUMBER (R_AVR_16, 4) + RELOC_NUMBER (R_AVR_16_PM, 5) + RELOC_NUMBER (R_AVR_LO8_LDI, 6) + RELOC_NUMBER (R_AVR_HI8_LDI, 7) + RELOC_NUMBER (R_AVR_HH8_LDI, 8) + RELOC_NUMBER (R_AVR_LO8_LDI_NEG, 9) + RELOC_NUMBER (R_AVR_HI8_LDI_NEG, 10) + RELOC_NUMBER (R_AVR_HH8_LDI_NEG, 11) + RELOC_NUMBER (R_AVR_LO8_LDI_PM, 12) + RELOC_NUMBER (R_AVR_HI8_LDI_PM, 13) + RELOC_NUMBER (R_AVR_HH8_LDI_PM, 14) + RELOC_NUMBER (R_AVR_LO8_LDI_PM_NEG, 15) + RELOC_NUMBER (R_AVR_HI8_LDI_PM_NEG, 16) + RELOC_NUMBER (R_AVR_HH8_LDI_PM_NEG, 17) + RELOC_NUMBER (R_AVR_CALL, 18) +END_RELOC_NUMBERS (R_AVR_max) + +#endif /* _ELF_AVR_H */ diff --git a/include/elf/common.h b/include/elf/common.h new file mode 100644 index 000000000..5573fca76 --- /dev/null +++ b/include/elf/common.h @@ -0,0 +1,753 @@ +/* ELF support for BFD. + Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, + 2001, 2002, 2003, 2004 + Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support, from information published + in "UNIX System V Release 4, Programmers Guide: ANSI C and + Programming Support Tools". + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of ELF support for BFD, and contains the portions + that are common to both the internal and external representations. + For example, ELFMAG0 is the byte 0x7F in both the internal (in-memory) + and external (in-file) representations. */ + +#ifndef _ELF_COMMON_H +#define _ELF_COMMON_H + +/* Fields in e_ident[]. */ + +#define EI_MAG0 0 /* File identification byte 0 index */ +#define ELFMAG0 0x7F /* Magic number byte 0 */ + +#define EI_MAG1 1 /* File identification byte 1 index */ +#define ELFMAG1 'E' /* Magic number byte 1 */ + +#define EI_MAG2 2 /* File identification byte 2 index */ +#define ELFMAG2 'L' /* Magic number byte 2 */ + +#define EI_MAG3 3 /* File identification byte 3 index */ +#define ELFMAG3 'F' /* Magic number byte 3 */ + +#define EI_CLASS 4 /* File class */ +#define ELFCLASSNONE 0 /* Invalid class */ +#define ELFCLASS32 1 /* 32-bit objects */ +#define ELFCLASS64 2 /* 64-bit objects */ + +#define EI_DATA 5 /* Data encoding */ +#define ELFDATANONE 0 /* Invalid data encoding */ +#define ELFDATA2LSB 1 /* 2's complement, little endian */ +#define ELFDATA2MSB 2 /* 2's complement, big endian */ + +#define EI_VERSION 6 /* File version */ + +#define EI_OSABI 7 /* Operating System/ABI indication */ +#define ELFOSABI_NONE 0 /* UNIX System V ABI */ +#define ELFOSABI_HPUX 1 /* HP-UX operating system */ +#define ELFOSABI_NETBSD 2 /* NetBSD */ +#define ELFOSABI_LINUX 3 /* GNU/Linux */ +#define ELFOSABI_HURD 4 /* GNU/Hurd */ +#define ELFOSABI_SOLARIS 6 /* Solaris */ +#define ELFOSABI_AIX 7 /* AIX */ +#define ELFOSABI_IRIX 8 /* IRIX */ +#define ELFOSABI_FREEBSD 9 /* FreeBSD */ +#define ELFOSABI_TRU64 10 /* TRU64 UNIX */ +#define ELFOSABI_MODESTO 11 /* Novell Modesto */ +#define ELFOSABI_OPENBSD 12 /* OpenBSD */ +#define ELFOSABI_OPENVMS 13 /* OpenVMS */ +#define ELFOSABI_NSK 14 /* Hewlett-Packard Non-Stop Kernel */ +#define ELFOSABI_AROS 15 /* Amiga Research OS */ +#define ELFOSABI_ARM 97 /* ARM */ +#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ + +#define EI_ABIVERSION 8 /* ABI version */ + +#define EI_PAD 9 /* Start of padding bytes */ + + +/* Values for e_type, which identifies the object file type. */ + +#define ET_NONE 0 /* No file type */ +#define ET_REL 1 /* Relocatable file */ +#define ET_EXEC 2 /* Executable file */ +#define ET_DYN 3 /* Shared object file */ +#define ET_CORE 4 /* Core file */ +#define ET_LOOS 0xFE00 /* Operating system-specific */ +#define ET_HIOS 0xFEFF /* Operating system-specific */ +#define ET_LOPROC 0xFF00 /* Processor-specific */ +#define ET_HIPROC 0xFFFF /* Processor-specific */ + +/* Values for e_machine, which identifies the architecture. These numbers + are officially assigned by registry@caldera.com. See below for a list of + ad-hoc numbers used during initial development. */ + +#define EM_NONE 0 /* No machine */ +#define EM_M32 1 /* AT&T WE 32100 */ +#define EM_SPARC 2 /* SUN SPARC */ +#define EM_386 3 /* Intel 80386 */ +#define EM_68K 4 /* Motorola m68k family */ +#define EM_88K 5 /* Motorola m88k family */ +#define EM_486 6 /* Intel 80486 *//* Reserved for future use */ +#define EM_860 7 /* Intel 80860 */ +#define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */ +#define EM_S370 9 /* IBM System/370 */ +#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian (Oct 4 1999 Draft) Deprecated */ + +#define EM_PARISC 15 /* HPPA */ + +#define EM_VPP550 17 /* Fujitsu VPP500 */ +#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ +#define EM_960 19 /* Intel 80960 */ +#define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* 64-bit PowerPC */ +#define EM_S390 22 /* IBM S/390 */ + +#define EM_V800 36 /* NEC V800 series */ +#define EM_FR20 37 /* Fujitsu FR20 */ +#define EM_RH32 38 /* TRW RH32 */ +#define EM_MCORE 39 /* Motorola M*Core */ /* May also be taken by Fujitsu MMA */ +#define EM_RCE 39 /* Old name for MCore */ +#define EM_ARM 40 /* ARM */ +#define EM_OLD_ALPHA 41 /* Digital Alpha */ +#define EM_SH 42 /* Renesas (formerly Hitachi) / SuperH SH */ +#define EM_SPARCV9 43 /* SPARC v9 64-bit */ +#define EM_TRICORE 44 /* Siemens Tricore embedded processor */ +#define EM_ARC 45 /* ARC Cores */ +#define EM_H8_300 46 /* Renesas (formerly Hitachi) H8/300 */ +#define EM_H8_300H 47 /* Renesas (formerly Hitachi) H8/300H */ +#define EM_H8S 48 /* Renesas (formerly Hitachi) H8S */ +#define EM_H8_500 49 /* Renesas (formerly Hitachi) H8/500 */ +#define EM_IA_64 50 /* Intel IA-64 Processor */ +#define EM_MIPS_X 51 /* Stanford MIPS-X */ +#define EM_COLDFIRE 52 /* Motorola Coldfire */ +#define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu Multimedia Accelerator */ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embedded RISC processor */ +#define EM_NDR1 57 /* Denso NDR1 microprocesspr */ +#define EM_STARCORE 58 /* Motorola Star*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronics ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ embedded processor */ +#define EM_X86_64 62 /* Advanced Micro Devices X86-64 processor */ + +#define EM_PDP10 64 /* Digital Equipment Corp. PDP-10 */ +#define EM_PDP11 65 /* Digital Equipment Corp. PDP-11 */ +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 bit microcontroller */ +#define EM_ST7 68 /* STMicroelectronics ST7 8-bit microcontroller */ +#define EM_68HC16 69 /* Motorola MC68HC16 Microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 Microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 Microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 Microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8-bit cpu */ +#define EM_VAX 75 /* Digital VAX */ +#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ +#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded cpu */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP processor */ +#define EM_ZSP 79 /* LSI Logic's 16-bit DSP processor */ +#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ +#define EM_HUANY 81 /* Harvard's machine-independent format */ +#define EM_PRISM 82 /* SiTera Prism */ +#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ +#define EM_FR30 84 /* Fujitsu FR30 */ +#define EM_D10V 85 /* Mitsubishi D10V */ +#define EM_D30V 86 /* Mitsubishi D30V */ +#define EM_V850 87 /* NEC v850 */ +#define EM_M32R 88 /* Renesas M32R (formerly Mitsubishi M32R) */ +#define EM_MN10300 89 /* Matsushita MN10300 */ +#define EM_MN10200 90 /* Matsushita MN10200 */ +#define EM_PJ 91 /* picoJava */ +#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ +#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ +#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ +#define EM_IP2K 101 /* Ubicom IP2022 micro controller */ +#define EM_CR 103 /* National Semiconductor CompactRISC */ +#define EM_MSP430 105 /* TI msp430 micro controller */ +#define EM_CRX 114 /* National Semiconductor CRX */ + +/* If it is necessary to assign new unofficial EM_* values, please pick large + random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision + with official or non-GNU unofficial values. + + NOTE: Do not just increment the most recent number by one. + Somebody else somewhere will do exactly the same thing, and you + will have a collision. Instead, pick a random number. + + Normally, each entity or maintainer responsible for a machine with an + unofficial e_machine number should eventually ask registry@caldera.com for + an officially blessed number to be added to the list above. */ + +#define EM_PJ_OLD 99 /* picoJava */ + +/* Cygnus PowerPC ELF backend. Written in the absence of an ABI. */ +#define EM_CYGNUS_POWERPC 0x9025 + +/* Old version of Sparc v9, from before the ABI; this should be + removed shortly. */ +#define EM_OLD_SPARCV9 11 + +/* Old version of PowerPC, this should be removed shortly. */ +#define EM_PPC_OLD 17 + +/* (Deprecated) Temporary number for the OpenRISC processor. */ +#define EM_OR32 0x8472 + +/* Cygnus M32R ELF backend. Written in the absence of an ABI. */ +#define EM_CYGNUS_M32R 0x9041 + +/* Alpha backend magic number. Written in the absence of an ABI. */ +#define EM_ALPHA 0x9026 + +/* old S/390 backend magic number. Written in the absence of an ABI. */ +#define EM_S390_OLD 0xa390 + +/* D10V backend magic number. Written in the absence of an ABI. */ +#define EM_CYGNUS_D10V 0x7650 + +/* D30V backend magic number. Written in the absence of an ABI. */ +#define EM_CYGNUS_D30V 0x7676 + +/* V850 backend magic number. Written in the absense of an ABI. */ +#define EM_CYGNUS_V850 0x9080 + +/* mn10200 and mn10300 backend magic numbers. + Written in the absense of an ABI. */ +#define EM_CYGNUS_MN10200 0xdead +#define EM_CYGNUS_MN10300 0xbeef + +/* FR30 magic number - no EABI available. */ +#define EM_CYGNUS_FR30 0x3330 + +/* AVR magic number + Written in the absense of an ABI. */ +#define EM_AVR_OLD 0x1057 + +/* OpenRISC magic number + Written in the absense of an ABI. */ +#define EM_OPENRISC_OLD 0x3426 + +/* DLX magic number + Written in the absense of an ABI. */ +#define EM_DLX 0x5aa5 + +#define EM_XSTORMY16 0xad45 + +/* FRV magic number - no EABI available??. */ +#define EM_CYGNUS_FRV 0x5441 + +/* Ubicom IP2xxx; no ABI */ +#define EM_IP2K_OLD 0x8217 + +/* MSP430 magic number + Written in the absense everything. */ +#define EM_MSP430_OLD 0x1059 + +/* Vitesse IQ2000. */ +#define EM_IQ2000 0xFEBA + +/* Old, unofficial value for Xtensa. */ +#define EM_XTENSA_OLD 0xabc7 + +/* See the above comment before you add a new EM_* value here. */ + +/* Values for e_version. */ + +#define EV_NONE 0 /* Invalid ELF version */ +#define EV_CURRENT 1 /* Current version */ + +/* Values for program header, p_type field. */ + +#define PT_NULL 0 /* Program header table entry unused */ +#define PT_LOAD 1 /* Loadable program segment */ +#define PT_DYNAMIC 2 /* Dynamic linking information */ +#define PT_INTERP 3 /* Program interpreter */ +#define PT_NOTE 4 /* Auxiliary information */ +#define PT_SHLIB 5 /* Reserved, unspecified semantics */ +#define PT_PHDR 6 /* Entry for header table itself */ +#define PT_TLS 7 /* Thread local storage segment */ +#define PT_LOOS 0x60000000 /* OS-specific */ +#define PT_HIOS 0x6fffffff /* OS-specific */ +#define PT_LOPROC 0x70000000 /* Processor-specific */ +#define PT_HIPROC 0x7FFFFFFF /* Processor-specific */ + +#define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550) /* Frame unwind information */ +#define PT_GNU_STACK (PT_LOOS + 0x474e551) /* Stack flags */ +#define PT_GNU_RELRO (PT_LOOS + 0x474e552) /* Read-only after relocation */ + +/* Program segment permissions, in program header p_flags field. */ + +#define PF_X (1 << 0) /* Segment is executable */ +#define PF_W (1 << 1) /* Segment is writable */ +#define PF_R (1 << 2) /* Segment is readable */ +/* #define PF_MASKOS 0x0F000000 *//* OS-specific reserved bits */ +#define PF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ +#define PF_MASKPROC 0xF0000000 /* Processor-specific reserved bits */ + +/* Values for section header, sh_type field. */ + +#define SHT_NULL 0 /* Section header table entry unused */ +#define SHT_PROGBITS 1 /* Program specific (private) data */ +#define SHT_SYMTAB 2 /* Link editing symbol table */ +#define SHT_STRTAB 3 /* A string table */ +#define SHT_RELA 4 /* Relocation entries with addends */ +#define SHT_HASH 5 /* A symbol hash table */ +#define SHT_DYNAMIC 6 /* Information for dynamic linking */ +#define SHT_NOTE 7 /* Information that marks file */ +#define SHT_NOBITS 8 /* Section occupies no space in file */ +#define SHT_REL 9 /* Relocation entries, no addends */ +#define SHT_SHLIB 10 /* Reserved, unspecified semantics */ +#define SHT_DYNSYM 11 /* Dynamic linking symbol table */ + +#define SHT_INIT_ARRAY 14 /* Array of ptrs to init functions */ +#define SHT_FINI_ARRAY 15 /* Array of ptrs to finish functions */ +#define SHT_PREINIT_ARRAY 16 /* Array of ptrs to pre-init funcs */ +#define SHT_GROUP 17 /* Section contains a section group */ +#define SHT_SYMTAB_SHNDX 18 /* Indicies for SHN_XINDEX entries */ + +#define SHT_LOOS 0x60000000 /* First of OS specific semantics */ +#define SHT_HIOS 0x6fffffff /* Last of OS specific semantics */ + +#define SHT_GNU_LIBLIST 0x6ffffff7 /* List of prelink dependencies */ + +/* The next three section types are defined by Solaris, and are named + SHT_SUNW*. We use them in GNU code, so we also define SHT_GNU* + versions. */ +#define SHT_SUNW_verdef 0x6ffffffd /* Versions defined by file */ +#define SHT_SUNW_verneed 0x6ffffffe /* Versions needed by file */ +#define SHT_SUNW_versym 0x6fffffff /* Symbol versions */ + +#define SHT_GNU_verdef SHT_SUNW_verdef +#define SHT_GNU_verneed SHT_SUNW_verneed +#define SHT_GNU_versym SHT_SUNW_versym + +#define SHT_LOPROC 0x70000000 /* Processor-specific semantics, lo */ +#define SHT_HIPROC 0x7FFFFFFF /* Processor-specific semantics, hi */ +#define SHT_LOUSER 0x80000000 /* Application-specific semantics */ +/* #define SHT_HIUSER 0x8FFFFFFF *//* Application-specific semantics */ +#define SHT_HIUSER 0xFFFFFFFF /* New value, defined in Oct 4, 1999 Draft */ + +/* Values for section header, sh_flags field. */ + +#define SHF_WRITE (1 << 0) /* Writable data during execution */ +#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ +#define SHF_EXECINSTR (1 << 2) /* Executable machine instructions */ +#define SHF_MERGE (1 << 4) /* Data in this section can be merged */ +#define SHF_STRINGS (1 << 5) /* Contains null terminated character strings */ +#define SHF_INFO_LINK (1 << 6) /* sh_info holds section header table index */ +#define SHF_LINK_ORDER (1 << 7) /* Preserve section ordering when linking */ +#define SHF_OS_NONCONFORMING (1 << 8) /* OS specific processing required */ +#define SHF_GROUP (1 << 9) /* Member of a section group */ +#define SHF_TLS (1 << 10) /* Thread local storage section */ + +/* #define SHF_MASKOS 0x0F000000 *//* OS-specific semantics */ +#define SHF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ +#define SHF_MASKPROC 0xF0000000 /* Processor-specific semantics */ + +/* Values of note segment descriptor types for core files. */ + +#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ +#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ +#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ +#define NT_TASKSTRUCT 4 /* Contains copy of task struct */ +#define NT_AUXV 6 /* Contains copy of Elfxx_auxv_t */ +#define NT_PRXFPREG 0x46e62b7f /* Contains a user_xfpregs_struct; */ + /* note name must be "LINUX". */ + +/* Note segments for core files on dir-style procfs systems. */ + +#define NT_PSTATUS 10 /* Has a struct pstatus */ +#define NT_FPREGS 12 /* Has a struct fpregset */ +#define NT_PSINFO 13 /* Has a struct psinfo */ +#define NT_LWPSTATUS 16 /* Has a struct lwpstatus_t */ +#define NT_LWPSINFO 17 /* Has a struct lwpsinfo_t */ +#define NT_WIN32PSTATUS 18 /* Has a struct win32_pstatus */ + + +/* Note segments for core files on NetBSD systems. Note name + must start with "NetBSD-CORE". */ + +#define NT_NETBSDCORE_PROCINFO 1 /* Has a struct procinfo */ +#define NT_NETBSDCORE_FIRSTMACH 32 /* start of machdep note types */ + + +/* Values of note segment descriptor types for object files. */ + +#define NT_VERSION 1 /* Contains a version string. */ +#define NT_ARCH 2 /* Contains an architecture string. */ + +/* Values for GNU .note.ABI-tag notes. Note name is "GNU". */ + +#define NT_GNU_ABI_TAG 1 +#define GNU_ABI_TAG_LINUX 0 +#define GNU_ABI_TAG_HURD 1 +#define GNU_ABI_TAG_SOLARIS 2 +#define GNU_ABI_TAG_FREEBSD 3 +#define GNU_ABI_TAG_NETBSD 4 + +/* Values for NetBSD .note.netbsd.ident notes. Note name is "NetBSD". */ + +#define NT_NETBSD_IDENT 1 + +/* Values for OpenBSD .note.openbsd.ident notes. Note name is "OpenBSD". */ + +#define NT_OPENBSD_IDENT 1 + +/* Values for FreeBSD .note.ABI-tag notes. Note name is "FreeBSD". */ + +#define NT_FREEBSD_ABI_TAG 1 + +/* These three macros disassemble and assemble a symbol table st_info field, + which contains the symbol binding and symbol type. The STB_ and STT_ + defines identify the binding and type. */ + +#define ELF_ST_BIND(val) (((unsigned int)(val)) >> 4) +#define ELF_ST_TYPE(val) ((val) & 0xF) +#define ELF_ST_INFO(bind,type) (((bind) << 4) + ((type) & 0xF)) + +/* The 64bit and 32bit versions of these macros are identical, but + the ELF spec defines them, so here they are. */ +#define ELF32_ST_BIND ELF_ST_BIND +#define ELF32_ST_TYPE ELF_ST_TYPE +#define ELF32_ST_INFO ELF_ST_INFO +#define ELF64_ST_BIND ELF_ST_BIND +#define ELF64_ST_TYPE ELF_ST_TYPE +#define ELF64_ST_INFO ELF_ST_INFO + +/* This macro disassembles and assembles a symbol's visibility into + the st_other field. The STV_ defines specificy the actual visibility. */ + +#define ELF_ST_VISIBILITY(v) ((v) & 0x3) +/* The remaining bits in the st_other field are not currently used. + They should be set to zero. */ + +#define ELF32_ST_VISIBILITY ELF_ST_VISIBILITY +#define ELF64_ST_VISIBILITY ELF_ST_VISIBILITY + + +#define STN_UNDEF 0 /* Undefined symbol index */ + +#define STB_LOCAL 0 /* Symbol not visible outside obj */ +#define STB_GLOBAL 1 /* Symbol visible outside obj */ +#define STB_WEAK 2 /* Like globals, lower precedence */ +#define STB_LOOS 10 /* OS-specific semantics */ +#define STB_HIOS 12 /* OS-specific semantics */ +#define STB_LOPROC 13 /* Application-specific semantics */ +#define STB_HIPROC 15 /* Application-specific semantics */ + +#define STT_NOTYPE 0 /* Symbol type is unspecified */ +#define STT_OBJECT 1 /* Symbol is a data object */ +#define STT_FUNC 2 /* Symbol is a code object */ +#define STT_SECTION 3 /* Symbol associated with a section */ +#define STT_FILE 4 /* Symbol gives a file name */ +#define STT_COMMON 5 /* An uninitialised common block */ +#define STT_TLS 6 /* Thread local data object */ +#define STT_LOOS 10 /* OS-specific semantics */ +#define STT_HIOS 12 /* OS-specific semantics */ +#define STT_LOPROC 13 /* Application-specific semantics */ +#define STT_HIPROC 15 /* Application-specific semantics */ + +/* Special section indices, which may show up in st_shndx fields, among + other places. */ + +#define SHN_UNDEF 0 /* Undefined section reference */ +#define SHN_LORESERVE 0xFF00 /* Begin range of reserved indices */ +#define SHN_LOPROC 0xFF00 /* Begin range of appl-specific */ +#define SHN_HIPROC 0xFF1F /* End range of appl-specific */ +#define SHN_LOOS 0xFF20 /* OS specific semantics, lo */ +#define SHN_HIOS 0xFF3F /* OS specific semantics, hi */ +#define SHN_ABS 0xFFF1 /* Associated symbol is absolute */ +#define SHN_COMMON 0xFFF2 /* Associated symbol is in common */ +#define SHN_XINDEX 0xFFFF /* Section index is held elsewhere */ +#define SHN_HIRESERVE 0xFFFF /* End range of reserved indices */ +#define SHN_BAD ((unsigned) -1) /* Used internally by bfd */ + +/* The following constants control how a symbol may be accessed once it has + become part of an executable or shared library. */ + +#define STV_DEFAULT 0 /* Visibility is specified by binding type */ +#define STV_INTERNAL 1 /* OS specific version of STV_HIDDEN */ +#define STV_HIDDEN 2 /* Can only be seen inside currect component */ +#define STV_PROTECTED 3 /* Treat as STB_LOCAL inside current component */ + +/* Relocation info handling macros. */ + +#define ELF32_R_SYM(i) ((i) >> 8) +#define ELF32_R_TYPE(i) ((i) & 0xff) +#define ELF32_R_INFO(s,t) (((s) << 8) + ((t) & 0xff)) + +#define ELF64_R_SYM(i) ((i) >> 32) +#define ELF64_R_TYPE(i) ((i) & 0xffffffff) +#define ELF64_R_INFO(s,t) (((bfd_vma) (s) << 31 << 1) + (bfd_vma) (t)) + +/* Dynamic section tags. */ + +#define DT_NULL 0 +#define DT_NEEDED 1 +#define DT_PLTRELSZ 2 +#define DT_PLTGOT 3 +#define DT_HASH 4 +#define DT_STRTAB 5 +#define DT_SYMTAB 6 +#define DT_RELA 7 +#define DT_RELASZ 8 +#define DT_RELAENT 9 +#define DT_STRSZ 10 +#define DT_SYMENT 11 +#define DT_INIT 12 +#define DT_FINI 13 +#define DT_SONAME 14 +#define DT_RPATH 15 +#define DT_SYMBOLIC 16 +#define DT_REL 17 +#define DT_RELSZ 18 +#define DT_RELENT 19 +#define DT_PLTREL 20 +#define DT_DEBUG 21 +#define DT_TEXTREL 22 +#define DT_JMPREL 23 +#define DT_BIND_NOW 24 +#define DT_INIT_ARRAY 25 +#define DT_FINI_ARRAY 26 +#define DT_INIT_ARRAYSZ 27 +#define DT_FINI_ARRAYSZ 28 +#define DT_RUNPATH 29 +#define DT_FLAGS 30 +#define DT_ENCODING 31 +#define DT_PREINIT_ARRAY 32 +#define DT_PREINIT_ARRAYSZ 33 + +/* Note, the Oct 4, 1999 draft of the ELF ABI changed the values + for DT_LOOS and DT_HIOS. Some implementations however, use + values outside of the new range (see below). */ +#define OLD_DT_LOOS 0x60000000 +#define DT_LOOS 0x6000000d +#define DT_HIOS 0x6ffff000 +#define OLD_DT_HIOS 0x6fffffff + +#define DT_LOPROC 0x70000000 +#define DT_HIPROC 0x7fffffff + +/* The next four dynamic tags are used on Solaris. We support them + everywhere. Note these values lie outside of the (new) range for + OS specific values. This is a deliberate special case and we + maintain it for backwards compatability. */ +#define DT_VALRNGLO 0x6ffffd00 +#define DT_GNU_PRELINKED 0x6ffffdf5 +#define DT_GNU_CONFLICTSZ 0x6ffffdf6 +#define DT_GNU_LIBLISTSZ 0x6ffffdf7 +#define DT_CHECKSUM 0x6ffffdf8 +#define DT_PLTPADSZ 0x6ffffdf9 +#define DT_MOVEENT 0x6ffffdfa +#define DT_MOVESZ 0x6ffffdfb +#define DT_FEATURE 0x6ffffdfc +#define DT_POSFLAG_1 0x6ffffdfd +#define DT_SYMINSZ 0x6ffffdfe +#define DT_SYMINENT 0x6ffffdff +#define DT_VALRNGHI 0x6ffffdff + +#define DT_ADDRRNGLO 0x6ffffe00 +#define DT_GNU_CONFLICT 0x6ffffef8 +#define DT_GNU_LIBLIST 0x6ffffef9 +#define DT_CONFIG 0x6ffffefa +#define DT_DEPAUDIT 0x6ffffefb +#define DT_AUDIT 0x6ffffefc +#define DT_PLTPAD 0x6ffffefd +#define DT_MOVETAB 0x6ffffefe +#define DT_SYMINFO 0x6ffffeff +#define DT_ADDRRNGHI 0x6ffffeff + +#define DT_RELACOUNT 0x6ffffff9 +#define DT_RELCOUNT 0x6ffffffa +#define DT_FLAGS_1 0x6ffffffb +#define DT_VERDEF 0x6ffffffc +#define DT_VERDEFNUM 0x6ffffffd +#define DT_VERNEED 0x6ffffffe +#define DT_VERNEEDNUM 0x6fffffff + +/* This tag is a GNU extension to the Solaris version scheme. */ +#define DT_VERSYM 0x6ffffff0 + +#define DT_LOPROC 0x70000000 +#define DT_HIPROC 0x7fffffff + +/* These section tags are used on Solaris. We support them + everywhere, and hope they do not conflict. */ + +#define DT_AUXILIARY 0x7ffffffd +#define DT_USED 0x7ffffffe +#define DT_FILTER 0x7fffffff + + +/* Values used in DT_FEATURE .dynamic entry. */ +#define DTF_1_PARINIT 0x00000001 +/* From + + http://docs.sun.com:80/ab2/coll.45.13/LLM/@Ab2PageView/21165?Ab2Lang=C&Ab2Enc=iso-8859-1 + + DTF_1_CONFEXP is the same as DTF_1_PARINIT. It is a typo. The value + defined here is the same as the one in <sys/link.h> on Solaris 8. */ +#define DTF_1_CONFEXP 0x00000002 + +/* Flag values used in the DT_POSFLAG_1 .dynamic entry. */ +#define DF_P1_LAZYLOAD 0x00000001 +#define DF_P1_GROUPPERM 0x00000002 + +/* Flag value in in the DT_FLAGS_1 .dynamic entry. */ +#define DF_1_NOW 0x00000001 +#define DF_1_GLOBAL 0x00000002 +#define DF_1_GROUP 0x00000004 +#define DF_1_NODELETE 0x00000008 +#define DF_1_LOADFLTR 0x00000010 +#define DF_1_INITFIRST 0x00000020 +#define DF_1_NOOPEN 0x00000040 +#define DF_1_ORIGIN 0x00000080 +#define DF_1_DIRECT 0x00000100 +#define DF_1_TRANS 0x00000200 +#define DF_1_INTERPOSE 0x00000400 +#define DF_1_NODEFLIB 0x00000800 +#define DF_1_NODUMP 0x00001000 +#define DF_1_CONLFAT 0x00002000 + +/* Flag values for the DT_FLAGS entry. */ +#define DF_ORIGIN (1 << 0) +#define DF_SYMBOLIC (1 << 1) +#define DF_TEXTREL (1 << 2) +#define DF_BIND_NOW (1 << 3) +#define DF_STATIC_TLS (1 << 4) + +/* These constants are used for the version number of a Elf32_Verdef + structure. */ + +#define VER_DEF_NONE 0 +#define VER_DEF_CURRENT 1 + +/* These constants appear in the vd_flags field of a Elf32_Verdef + structure. */ + +#define VER_FLG_BASE 0x1 +#define VER_FLG_WEAK 0x2 + +/* These special constants can be found in an Elf32_Versym field. */ + +#define VER_NDX_LOCAL 0 +#define VER_NDX_GLOBAL 1 + +/* These constants are used for the version number of a Elf32_Verneed + structure. */ + +#define VER_NEED_NONE 0 +#define VER_NEED_CURRENT 1 + +/* This flag appears in a Versym structure. It means that the symbol + is hidden, and is only visible with an explicit version number. + This is a GNU extension. */ + +#define VERSYM_HIDDEN 0x8000 + +/* This is the mask for the rest of the Versym information. */ + +#define VERSYM_VERSION 0x7fff + +/* This is a special token which appears as part of a symbol name. It + indictes that the rest of the name is actually the name of a + version node, and is not part of the actual name. This is a GNU + extension. For example, the symbol name `stat@ver2' is taken to + mean the symbol `stat' in version `ver2'. */ + +#define ELF_VER_CHR '@' + +/* Possible values for si_boundto. */ + +#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ +#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ +#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ + +/* Possible bitmasks for si_flags. */ + +#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ +#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ +#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ +#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy loaded */ + +/* Syminfo version values. */ + +#define SYMINFO_NONE 0 +#define SYMINFO_CURRENT 1 +#define SYMINFO_NUM 2 + +/* Section Group Flags. */ + +#define GRP_COMDAT 0x1 /* A COMDAT group */ + +/* Auxv a_type values. */ + +#define AT_NULL 0 /* End of vector */ +#define AT_IGNORE 1 /* Entry should be ignored */ +#define AT_EXECFD 2 /* File descriptor of program */ +#define AT_PHDR 3 /* Program headers for program */ +#define AT_PHENT 4 /* Size of program header entry */ +#define AT_PHNUM 5 /* Number of program headers */ +#define AT_PAGESZ 6 /* System page size */ +#define AT_BASE 7 /* Base address of interpreter */ +#define AT_FLAGS 8 /* Flags */ +#define AT_ENTRY 9 /* Entry point of program */ +#define AT_NOTELF 10 /* Program is not ELF */ +#define AT_UID 11 /* Real uid */ +#define AT_EUID 12 /* Effective uid */ +#define AT_GID 13 /* Real gid */ +#define AT_EGID 14 /* Effective gid */ +#define AT_CLKTCK 17 /* Frequency of times() */ +#define AT_PLATFORM 15 /* String identifying platform. */ +#define AT_HWCAP 16 /* Machine dependent hints about + processor capabilities. */ +#define AT_FPUCW 18 /* Used FPU control word. */ +#define AT_DCACHEBSIZE 19 /* Data cache block size. */ +#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ +#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ +#define AT_IGNOREPPC 22 /* Entry should be ignored */ +#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ +/* Pointer to the global system page used for system calls and other + nice things. */ +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 /* Pointer to ELF header of system-supplied DSO. */ + +#define AT_SUN_UID 2000 /* Effective user ID. */ +#define AT_SUN_RUID 2001 /* Real user ID. */ +#define AT_SUN_GID 2002 /* Effective group ID. */ +#define AT_SUN_RGID 2003 /* Real group ID. */ +#define AT_SUN_LDELF 2004 /* Dynamic linker's ELF header. */ +#define AT_SUN_LDSHDR 2005 /* Dynamic linker's section headers. */ +#define AT_SUN_LDNAME 2006 /* String giving name of dynamic linker. */ +#define AT_SUN_LPAGESZ 2007 /* Large pagesize. */ +#define AT_SUN_PLATFORM 2008 /* Platform name string. */ +#define AT_SUN_HWCAP 2009 /* Machine dependent hints about + processor capabilities. */ +#define AT_SUN_IFLUSH 2010 /* Should flush icache? */ +#define AT_SUN_CPU 2011 /* CPU name string. */ +#define AT_SUN_EMUL_ENTRY 2012 /* COFF entry point address. */ +#define AT_SUN_EMUL_EXECFD 2013 /* COFF executable file descriptor. */ +#define AT_SUN_EXECNAME 2014 /* Canonicalized file name given to execve. */ +#define AT_SUN_MMU 2015 /* String for name of MMU module. */ +#define AT_SUN_LDDATA 2016 /* Dynamic linker's data segment address. */ + + +#endif /* _ELF_COMMON_H */ diff --git a/include/elf/cr16c.h b/include/elf/cr16c.h new file mode 100644 index 000000000..1a91afe0f --- /dev/null +++ b/include/elf/cr16c.h @@ -0,0 +1,258 @@ +/* CR16C ELF support for BFD. + Copyright 2004 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_CR16C_H +#define _ELF_CR16C_H + +#include "bfd.h" +#include "elf/reloc-macros.h" + +/* Creating indices for reloc_map_index array. */ +START_RELOC_NUMBERS (elf_cr16c_reloc_type) + RELOC_NUMBER (RINDEX_16C_NUM08, 0) + RELOC_NUMBER (RINDEX_16C_NUM08_C, 1) + RELOC_NUMBER (RINDEX_16C_NUM16, 2) + RELOC_NUMBER (RINDEX_16C_NUM16_C, 3) + RELOC_NUMBER (RINDEX_16C_NUM32, 4) + RELOC_NUMBER (RINDEX_16C_NUM32_C, 5) + RELOC_NUMBER (RINDEX_16C_DISP04, 6) + RELOC_NUMBER (RINDEX_16C_DISP04_C, 7) + RELOC_NUMBER (RINDEX_16C_DISP08, 8) + RELOC_NUMBER (RINDEX_16C_DISP08_C, 9) + RELOC_NUMBER (RINDEX_16C_DISP16, 10) + RELOC_NUMBER (RINDEX_16C_DISP16_C, 11) + RELOC_NUMBER (RINDEX_16C_DISP24, 12) + RELOC_NUMBER (RINDEX_16C_DISP24_C, 13) + RELOC_NUMBER (RINDEX_16C_DISP24a, 14) + RELOC_NUMBER (RINDEX_16C_DISP24a_C, 15) + RELOC_NUMBER (RINDEX_16C_REG04, 16) + RELOC_NUMBER (RINDEX_16C_REG04_C, 17) + RELOC_NUMBER (RINDEX_16C_REG04a, 18) + RELOC_NUMBER (RINDEX_16C_REG04a_C, 19) + RELOC_NUMBER (RINDEX_16C_REG14, 20) + RELOC_NUMBER (RINDEX_16C_REG14_C, 21) + RELOC_NUMBER (RINDEX_16C_REG16, 22) + RELOC_NUMBER (RINDEX_16C_REG16_C, 23) + RELOC_NUMBER (RINDEX_16C_REG20, 24) + RELOC_NUMBER (RINDEX_16C_REG20_C, 25) + RELOC_NUMBER (RINDEX_16C_ABS20, 26) + RELOC_NUMBER (RINDEX_16C_ABS20_C, 27) + RELOC_NUMBER (RINDEX_16C_ABS24, 28) + RELOC_NUMBER (RINDEX_16C_ABS24_C, 29) + RELOC_NUMBER (RINDEX_16C_IMM04, 30) + RELOC_NUMBER (RINDEX_16C_IMM04_C, 31) + RELOC_NUMBER (RINDEX_16C_IMM16, 32) + RELOC_NUMBER (RINDEX_16C_IMM16_C, 33) + RELOC_NUMBER (RINDEX_16C_IMM20, 34) + RELOC_NUMBER (RINDEX_16C_IMM20_C, 35) + RELOC_NUMBER (RINDEX_16C_IMM24, 36) + RELOC_NUMBER (RINDEX_16C_IMM24_C, 37) + RELOC_NUMBER (RINDEX_16C_IMM32, 38) + RELOC_NUMBER (RINDEX_16C_IMM32_C, 39) +END_RELOC_NUMBERS (RINDEX_16C_MAX) + +/* CR16C Relocation Types ('cr_reloc_type' entry in the reloc_map structure). + The relocation constant name is determined as follows : + + R_16C_<format><size>[_C] + + Where : + + <format> is one of the following: + NUM - R_NUMBER mnemonic, + DISP - R_16C_DISPL mnemonic, + REG - R_16C_REGREL mnemonic, + ABS - R_16C_ABS mnemonic, + IMM - R_16C_IMMED mnemonic, + <size> stands for R_S_16C_<size> + _C means 'code label' and is only added when R_ADDRTYPE subfield + is of type R_CODE_ADDR. */ + +/* The table below shows what the hex digits in the definition of the + relocation type constants correspond to. + ------------------------------------------------------------------ + R_SIZESP R_FORMAT R_RELTO R_ADDRTYPE + ------------------------------------------------------------------ */ +/* R_S_16C_08 R_NUMBER R_ABS R_ADDRESS */ +#define R_16C_NUM08 0X0001 + +/* R_S_16C_08 R_NUMBER R_ABS R_CODE_ADDR */ +#define R_16C_NUM08_C 0X0006 + +/* R_S_16C_16 R_NUMBER R_ABS R_ADDRESS */ +#define R_16C_NUM16 0X1001 + +/* R_S_16C_16 R_NUMBER R_ABS R_CODE_ADDR */ +#define R_16C_NUM16_C 0X1006 + +/* R_S_16C_32 R_NUMBER R_ABS R_ADDRESS */ +#define R_16C_NUM32 0X2001 + +/* R_S_16C_32 R_NUMBER R_ABS R_CODE_ADDR */ +#define R_16C_NUM32_C 0X2006 + +/* R_S_16C_04 R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP04 0X5411 + +/* R_S_16C_04 R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP04_C 0X5416 + +/* R_S_16C_08 R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP08 0X0411 + +/* R_S_16C_08 R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP08_C 0X0416 + +/* R_S_16C_16 R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP16 0X1411 + +/* R_S_16C_16 R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP16_C 0X1416 + +/* R_S_16C_24 R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP24 0X7411 + +/* R_S_16C_24 R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP24_C 0X7416 + +/* R_S_16C_24a R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP24a 0X6411 + +/* R_S_16C_24a R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP24a_C 0X6416 + +/* R_S_16C_04 R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG04 0X5201 + +/* R_S_16C_04 R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG04_C 0X5206 + +/* R_S_16C_04_a R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG04a 0X4201 + +/* R_S_16C_04_a R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG04a_C 0X4206 + +/* R_S_16C_14 R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG14 0X3201 + +/* R_S_16C_14 R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG14_C 0X3206 + +/* R_S_16C_16 R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG16 0X1201 + +/* R_S_16C_16 R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG16_C 0X1206 + +/* R_S_16C_20 R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG20 0X8201 + +/* R_S_16C_20 R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG20_C 0X8206 + +/* R_S_16C_20 R_16C_ABS R_ABS R_ADDRESS */ +#define R_16C_ABS20 0X8101 + +/* R_S_16C_20 R_16C_ABS R_ABS R_CODE_ADDR */ +#define R_16C_ABS20_C 0X8106 + +/* R_S_16C_24 R_16C_ABS R_ABS R_ADDRESS */ +#define R_16C_ABS24 0X7101 + +/* R_S_16C_24 R_16C_ABS R_ABS R_CODE_ADDR */ +#define R_16C_ABS24_C 0X7106 + +/* R_S_16C_04 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM04 0X5301 + +/* R_S_16C_04 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM04_C 0X5306 + +/* R_S_16C_16 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM16 0X1301 + +/* R_S_16C_16 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM16_C 0X1306 + +/* R_S_16C_20 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM20 0X8301 + +/* R_S_16C_20 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM20_C 0X8306 + +/* R_S_16C_24 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM24 0X7301 + +/* R_S_16C_24 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM24_C 0X7306 + +/* R_S_16C_32 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM32 0X2301 + +/* R_S_16C_32 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM32_C 0X2306 + + +/* Relocation item type. */ +#define R_ADDRTYPE 0x000f +#define R_ADDRESS 0x0001 /* Take address of symbol. */ +#define R_CODE_ADDR 0x0006 /* Take address of symbol divided by 2. */ + +/* Relocation action. */ +#define R_RELTO 0x00f0 +#define R_ABS 0x0000 /* Keep symbol's address as such. */ +#define R_PCREL 0x0010 /* Subtract the pc address of hole. */ + +/* Relocation item data format. */ +#define R_FORMAT 0x0f00 +#define R_NUMBER 0x0000 /* Retain as two's complement value. */ +#define R_16C_DISPL 0x0400 /* CR16C displacement type. */ +#define R_16C_ABS 0x0100 /* CR16C absolute type. */ +#define R_16C_REGREL 0x0200 /* CR16C register-relative type. */ +#define R_16C_IMMED 0x0300 /* CR16C immediate type. */ + +/* Relocation item size. */ +#define R_SIZESP 0xf000 +#define R_S_16C_04 0x5000 +#define R_S_16C_04_a 0x4000 +#define R_S_16C_08 0x0000 +#define R_S_16C_14 0x3000 +#define R_S_16C_16 0x1000 +#define R_S_16C_20 0x8000 +#define R_S_16C_24_a 0x6000 +#define R_S_16C_24 0x7000 +#define R_S_16C_32 0x2000 + + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Far common symbol. */ +#define SHN_CR16C_FCOMMON 0xff00 +#define SHN_CR16C_NCOMMON 0xff01 + +typedef struct reloc_map +{ + unsigned short cr_reloc_type; /* CR relocation type. */ + bfd_reloc_code_real_type bfd_reloc_enum; /* BFD relocation enum. */ +} RELOC_MAP; + +#endif /* _ELF_CR16C_H */ diff --git a/include/elf/cris.h b/include/elf/cris.h new file mode 100644 index 000000000..3bd03e8aa --- /dev/null +++ b/include/elf/cris.h @@ -0,0 +1,101 @@ +/* CRIS ELF support for BFD. + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Written by Hans-Peter Nilsson. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_CRIS_H +#define _ELF_CRIS_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_cris_reloc_type) + RELOC_NUMBER (R_CRIS_NONE, 0) + RELOC_NUMBER (R_CRIS_8, 1) + RELOC_NUMBER (R_CRIS_16, 2) + RELOC_NUMBER (R_CRIS_32, 3) + + /* The "PC" position is the location right after the relocation. */ + RELOC_NUMBER (R_CRIS_8_PCREL, 4) + RELOC_NUMBER (R_CRIS_16_PCREL, 5) + RELOC_NUMBER (R_CRIS_32_PCREL, 6) + + RELOC_NUMBER (R_CRIS_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_CRIS_GNU_VTENTRY, 8) + + /* Copy contents at dynlinking. Generated by the linker. + The BFD equivalent is BFD_RELOC_CRIS_COPY. */ + RELOC_NUMBER (R_CRIS_COPY, 9) + + /* Create GOT entry. Generated by the linker. + The BFD equivalent is BFD_RELOC_CRIS_GLOB_DAT. */ + RELOC_NUMBER (R_CRIS_GLOB_DAT, 10) + + /* Create PLT entry. Generated by the linker. + The BFD equivalent is BFD_RELOC_CRIS_JUMP_SLOT. */ + RELOC_NUMBER (R_CRIS_JUMP_SLOT, 11) + + /* Adjust by program base. Generated by the linker. + The BFD equivalent is BFD_RELOC_CRIS_RELATIVE. */ + RELOC_NUMBER (R_CRIS_RELATIVE, 12) + + /* A 16-bit offset to entry in GOT and request to create GOT entry for + that symbol. + The BFD equivalent is BFD_RELOC_CRIS_16_GOT. */ + RELOC_NUMBER (R_CRIS_16_GOT, 13) + + /* A 32-bit offset to entry in GOT and request to create GOT entry for + that symbol. + The BFD equivalent is BFD_RELOC_CRIS_32_GOT. */ + RELOC_NUMBER (R_CRIS_32_GOT, 14) + + /* A 16-bit offset to entry in PLT part of GOT and request to create PLT + entry for that symbol. + The BFD equivalent is BFD_RELOC_CRIS_16_GOTPLT. */ + RELOC_NUMBER (R_CRIS_16_GOTPLT, 15) + + /* A 32-bit offset to entry in PLT part of GOT and request to create PLT + entry for that symbol. + The BFD equivalent is BFD_RELOC_CRIS_32_GOTPLT. */ + RELOC_NUMBER (R_CRIS_32_GOTPLT, 16) + + /* A 32-bit offset from GOT to (local) symbol: no GOT entry should be + necessary. + The BFD equivalent is BFD_RELOC_CRIS_32_GOTREL. */ + RELOC_NUMBER (R_CRIS_32_GOTREL, 17) + + /* A 32-bit offset from GOT to entry for this symbol in PLT and request + to create PLT entry for symbol. + The BFD equivalent is BFD_RELOC_CRIS_32_GOTREL. */ + RELOC_NUMBER (R_CRIS_32_PLT_GOTREL, 18) + + /* A 32-bit offset from location after this relocation (addend specifies + offset) to entry for this symbol in PLT and request to create PLT + entry for symbol. + The BFD equivalent is BFD_RELOC_CRIS_32_PLT_PCREL. */ + RELOC_NUMBER (R_CRIS_32_PLT_PCREL, 19) + + /* No other relocs must be visible outside the assembler. */ + +END_RELOC_NUMBERS (R_CRIS_max) + +/* User symbols in this file have a leading underscore. */ +#define EF_CRIS_UNDERSCORE 0x00000001 + +#endif /* _ELF_CRIS_H */ diff --git a/include/elf/crx.h b/include/elf/crx.h new file mode 100644 index 000000000..33ba00514 --- /dev/null +++ b/include/elf/crx.h @@ -0,0 +1,53 @@ +/* CRX ELF support for BFD. + Copyright 2004 Free Software Foundation, Inc. + Contributed by Tomer Levi, NSC, Israel. + Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. + Updates, BFDizing, GNUifying and ELF support by Tomer Levi. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_CRX_H +#define _ELF_CRX_H + +#include "elf/reloc-macros.h" + +/* Creating indices for reloc_map_index array. */ +START_RELOC_NUMBERS(elf_crx_reloc_type) + RELOC_NUMBER (R_CRX_NONE, 0) + RELOC_NUMBER (R_CRX_REL4, 1) + RELOC_NUMBER (R_CRX_REL8, 2) + RELOC_NUMBER (R_CRX_REL8_CMP, 3) + RELOC_NUMBER (R_CRX_REL16, 4) + RELOC_NUMBER (R_CRX_REL24, 5) + RELOC_NUMBER (R_CRX_REL32, 6) + RELOC_NUMBER (R_CRX_REGREL12, 7) + RELOC_NUMBER (R_CRX_REGREL22, 8) + RELOC_NUMBER (R_CRX_REGREL28, 9) + RELOC_NUMBER (R_CRX_REGREL32, 10) + RELOC_NUMBER (R_CRX_ABS16, 11) + RELOC_NUMBER (R_CRX_ABS32, 12) + RELOC_NUMBER (R_CRX_NUM8, 13) + RELOC_NUMBER (R_CRX_NUM16, 14) + RELOC_NUMBER (R_CRX_NUM32, 15) + RELOC_NUMBER (R_CRX_IMM16, 16) + RELOC_NUMBER (R_CRX_IMM32, 17) + RELOC_NUMBER (R_CRX_SWITCH8, 18) + RELOC_NUMBER (R_CRX_SWITCH16, 19) + RELOC_NUMBER (R_CRX_SWITCH32, 20) +END_RELOC_NUMBERS(R_CRX_MAX) + +#endif /* _ELF_CRX_H */ diff --git a/include/elf/d10v.h b/include/elf/d10v.h new file mode 100644 index 000000000..5bc613bc3 --- /dev/null +++ b/include/elf/d10v.h @@ -0,0 +1,38 @@ +/* d10v ELF support for BFD. + Copyright 1998, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_D10V_H +#define _ELF_D10V_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_d10v_reloc_type) + RELOC_NUMBER (R_D10V_NONE, 0) + RELOC_NUMBER (R_D10V_10_PCREL_R, 1) + RELOC_NUMBER (R_D10V_10_PCREL_L, 2) + RELOC_NUMBER (R_D10V_16, 3) + RELOC_NUMBER (R_D10V_18, 4) + RELOC_NUMBER (R_D10V_18_PCREL, 5) + RELOC_NUMBER (R_D10V_32, 6) + RELOC_NUMBER (R_D10V_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_D10V_GNU_VTENTRY, 8) +END_RELOC_NUMBERS (R_D10V_max) + +#endif diff --git a/include/elf/d30v.h b/include/elf/d30v.h new file mode 100644 index 000000000..5abb06a55 --- /dev/null +++ b/include/elf/d30v.h @@ -0,0 +1,42 @@ +/* d30v ELF support for BFD. + Copyright 1998, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_D30V_H +#define _ELF_D30V_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_d30v_reloc_type) + RELOC_NUMBER (R_D30V_NONE, 0) + RELOC_NUMBER (R_D30V_6, 1) + RELOC_NUMBER (R_D30V_9_PCREL, 2) + RELOC_NUMBER (R_D30V_9_PCREL_R, 3) + RELOC_NUMBER (R_D30V_15, 4) + RELOC_NUMBER (R_D30V_15_PCREL, 5) + RELOC_NUMBER (R_D30V_15_PCREL_R, 6) + RELOC_NUMBER (R_D30V_21, 7) + RELOC_NUMBER (R_D30V_21_PCREL, 8) + RELOC_NUMBER (R_D30V_21_PCREL_R, 9) + RELOC_NUMBER (R_D30V_32, 10) + RELOC_NUMBER (R_D30V_32_PCREL, 11) + RELOC_NUMBER (R_D30V_32_NORMAL, 12) +END_RELOC_NUMBERS (R_D30V_max) + +#endif diff --git a/include/elf/dlx.h b/include/elf/dlx.h new file mode 100644 index 000000000..562f600f3 --- /dev/null +++ b/include/elf/dlx.h @@ -0,0 +1,53 @@ +/* DLX support for BFD. + Copyright 2002 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_DLX_H +#define _ELF_DLX_H + +#include "elf/reloc-macros.h" + +#if 0 +START_RELOC_NUMBERS (elf_dlx_reloc_type) + RELOC_NUMBER (R_DLX_NONE, 0) + RELOC_NUMBER (R_DLX_RELOC_16, 1) + RELOC_NUMBER (R_DLX_RELOC_26, 2) + RELOC_NUMBER (R_DLX_RELOC_32, 3) + RELOC_NUMBER (R_DLX_GNU_VTINHERIT, 4) + RELOC_NUMBER (R_DLX_GNU_VTENTRY, 5) + RELOC_NUMBER (R_DLX_RELOC_16_HI, 6) + RELOC_NUMBER (R_DLX_RELOC_16_LO, 7) + RELOC_NUMBER (R_DLX_RELOC_16_PCREL, 8) + RELOC_NUMBER (R_DLX_RELOC_26_PCREL, 9) +END_RELOC_NUMBERS (R_DLX_max) +#else +START_RELOC_NUMBERS (elf_dlx_reloc_type) + RELOC_NUMBER (R_DLX_NONE, 0) + RELOC_NUMBER (R_DLX_RELOC_8, 1) + RELOC_NUMBER (R_DLX_RELOC_16, 2) + RELOC_NUMBER (R_DLX_RELOC_32, 3) + RELOC_NUMBER (R_DLX_GNU_VTINHERIT, 4) + RELOC_NUMBER (R_DLX_GNU_VTENTRY, 5) + RELOC_NUMBER (R_DLX_RELOC_16_HI, 6) + RELOC_NUMBER (R_DLX_RELOC_16_LO, 7) + RELOC_NUMBER (R_DLX_RELOC_16_PCREL, 8) + RELOC_NUMBER (R_DLX_RELOC_26_PCREL, 9) +END_RELOC_NUMBERS (R_DLX_max) +#endif /* 0 */ + +#endif /* _ELF_DLX_H */ diff --git a/include/elf/dwarf.h b/include/elf/dwarf.h new file mode 100644 index 000000000..f79397253 --- /dev/null +++ b/include/elf/dwarf.h @@ -0,0 +1,320 @@ +/* Declarations and definitions of codes relating to the DWARF symbolic + debugging information format. + + Written by Ron Guilmette (rfg@ncd.com) + +Copyright 1992, 1993, 1995, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file is derived from the DWARF specification (a public document) + Revision 1.0.1 (April 8, 1992) developed by the UNIX International + Programming Languages Special Interest Group (UI/PLSIG) and distributed + by UNIX International. Copies of this specification are available from + UNIX International, 20 Waterview Boulevard, Parsippany, NJ, 07054. +*/ + +#ifndef _ELF_DWARF_H +#define _ELF_DWARF_H + +/* Tag names and codes. */ + +enum dwarf_tag { + TAG_padding = 0x0000, + TAG_array_type = 0x0001, + TAG_class_type = 0x0002, + TAG_entry_point = 0x0003, + TAG_enumeration_type = 0x0004, + TAG_formal_parameter = 0x0005, + TAG_global_subroutine = 0x0006, + TAG_global_variable = 0x0007, + /* 0x0008 -- reserved */ + /* 0x0009 -- reserved */ + TAG_label = 0x000a, + TAG_lexical_block = 0x000b, + TAG_local_variable = 0x000c, + TAG_member = 0x000d, + /* 0x000e -- reserved */ + TAG_pointer_type = 0x000f, + TAG_reference_type = 0x0010, + TAG_compile_unit = 0x0011, + TAG_string_type = 0x0012, + TAG_structure_type = 0x0013, + TAG_subroutine = 0x0014, + TAG_subroutine_type = 0x0015, + TAG_typedef = 0x0016, + TAG_union_type = 0x0017, + TAG_unspecified_parameters = 0x0018, + TAG_variant = 0x0019, + TAG_common_block = 0x001a, + TAG_common_inclusion = 0x001b, + TAG_inheritance = 0x001c, + TAG_inlined_subroutine = 0x001d, + TAG_module = 0x001e, + TAG_ptr_to_member_type = 0x001f, + TAG_set_type = 0x0020, + TAG_subrange_type = 0x0021, + TAG_with_stmt = 0x0022, + + /* GNU extensions */ + + TAG_format_label = 0x8000, /* for FORTRAN 77 and Fortran 90 */ + TAG_namelist = 0x8001, /* For Fortran 90 */ + TAG_function_template = 0x8002, /* for C++ */ + TAG_class_template = 0x8003 /* for C++ */ +}; + +#define TAG_lo_user 0x8000 /* implementation-defined range start */ +#define TAG_hi_user 0xffff /* implementation-defined range end */ +#define TAG_source_file TAG_compile_unit /* for backward compatibility */ + +/* Form names and codes. */ + +enum dwarf_form { + FORM_ADDR = 0x1, + FORM_REF = 0x2, + FORM_BLOCK2 = 0x3, + FORM_BLOCK4 = 0x4, + FORM_DATA2 = 0x5, + FORM_DATA4 = 0x6, + FORM_DATA8 = 0x7, + FORM_STRING = 0x8 +}; + +/* Attribute names and codes. */ + +enum dwarf_attribute { + AT_sibling = (0x0010|FORM_REF), + AT_location = (0x0020|FORM_BLOCK2), + AT_name = (0x0030|FORM_STRING), + AT_fund_type = (0x0050|FORM_DATA2), + AT_mod_fund_type = (0x0060|FORM_BLOCK2), + AT_user_def_type = (0x0070|FORM_REF), + AT_mod_u_d_type = (0x0080|FORM_BLOCK2), + AT_ordering = (0x0090|FORM_DATA2), + AT_subscr_data = (0x00a0|FORM_BLOCK2), + AT_byte_size = (0x00b0|FORM_DATA4), + AT_bit_offset = (0x00c0|FORM_DATA2), + AT_bit_size = (0x00d0|FORM_DATA4), + /* (0x00e0|FORM_xxxx) -- reserved */ + AT_element_list = (0x00f0|FORM_BLOCK4), + AT_stmt_list = (0x0100|FORM_DATA4), + AT_low_pc = (0x0110|FORM_ADDR), + AT_high_pc = (0x0120|FORM_ADDR), + AT_language = (0x0130|FORM_DATA4), + AT_member = (0x0140|FORM_REF), + AT_discr = (0x0150|FORM_REF), + AT_discr_value = (0x0160|FORM_BLOCK2), + /* (0x0170|FORM_xxxx) -- reserved */ + /* (0x0180|FORM_xxxx) -- reserved */ + AT_string_length = (0x0190|FORM_BLOCK2), + AT_common_reference = (0x01a0|FORM_REF), + AT_comp_dir = (0x01b0|FORM_STRING), + AT_const_value_string = (0x01c0|FORM_STRING), + AT_const_value_data2 = (0x01c0|FORM_DATA2), + AT_const_value_data4 = (0x01c0|FORM_DATA4), + AT_const_value_data8 = (0x01c0|FORM_DATA8), + AT_const_value_block2 = (0x01c0|FORM_BLOCK2), + AT_const_value_block4 = (0x01c0|FORM_BLOCK4), + AT_containing_type = (0x01d0|FORM_REF), + AT_default_value_addr = (0x01e0|FORM_ADDR), + AT_default_value_data2 = (0x01e0|FORM_DATA2), + AT_default_value_data4 = (0x01e0|FORM_DATA4), + AT_default_value_data8 = (0x01e0|FORM_DATA8), + AT_default_value_string = (0x01e0|FORM_STRING), + AT_friends = (0x01f0|FORM_BLOCK2), + AT_inline = (0x0200|FORM_STRING), + AT_is_optional = (0x0210|FORM_STRING), + AT_lower_bound_ref = (0x0220|FORM_REF), + AT_lower_bound_data2 = (0x0220|FORM_DATA2), + AT_lower_bound_data4 = (0x0220|FORM_DATA4), + AT_lower_bound_data8 = (0x0220|FORM_DATA8), + AT_private = (0x0240|FORM_STRING), + AT_producer = (0x0250|FORM_STRING), + AT_program = (0x0230|FORM_STRING), + AT_protected = (0x0260|FORM_STRING), + AT_prototyped = (0x0270|FORM_STRING), + AT_public = (0x0280|FORM_STRING), + AT_pure_virtual = (0x0290|FORM_STRING), + AT_return_addr = (0x02a0|FORM_BLOCK2), + AT_abstract_origin = (0x02b0|FORM_REF), + AT_start_scope = (0x02c0|FORM_DATA4), + AT_stride_size = (0x02e0|FORM_DATA4), + AT_upper_bound_ref = (0x02f0|FORM_REF), + AT_upper_bound_data2 = (0x02f0|FORM_DATA2), + AT_upper_bound_data4 = (0x02f0|FORM_DATA4), + AT_upper_bound_data8 = (0x02f0|FORM_DATA8), + AT_virtual = (0x0300|FORM_STRING), + + /* GNU extensions. */ + + AT_sf_names = (0x8000|FORM_DATA4), + AT_src_info = (0x8010|FORM_DATA4), + AT_mac_info = (0x8020|FORM_DATA4), + AT_src_coords = (0x8030|FORM_DATA4), + AT_body_begin = (0x8040|FORM_ADDR), + AT_body_end = (0x8050|FORM_ADDR) +}; + +#define AT_lo_user 0x8000 /* implementation-defined range start */ +#define AT_hi_user 0xffff /* implementation-defined range end */ + +/* Location atom names and codes. */ + +enum dwarf_location_atom { + OP_REG = 0x01, + OP_BASEREG = 0x02, + OP_ADDR = 0x03, + OP_CONST = 0x04, + OP_DEREF2 = 0x05, + OP_DEREF4 = 0x06, + OP_ADD = 0x07 +}; + +#define OP_LO_USER 0x80 /* implementation-defined range start */ +#define OP_HI_USER 0xff /* implementation-defined range end */ + +/* Fundamental type names and codes. */ + +enum dwarf_fundamental_type { + FT_char = 0x0001, + FT_signed_char = 0x0002, + FT_unsigned_char = 0x0003, + FT_short = 0x0004, + FT_signed_short = 0x0005, + FT_unsigned_short = 0x0006, + FT_integer = 0x0007, + FT_signed_integer = 0x0008, + FT_unsigned_integer = 0x0009, + FT_long = 0x000a, + FT_signed_long = 0x000b, + FT_unsigned_long = 0x000c, + FT_pointer = 0x000d, /* an alias for (void *) */ + FT_float = 0x000e, + FT_dbl_prec_float = 0x000f, + FT_ext_prec_float = 0x0010, /* breaks "classic" svr4 SDB */ + FT_complex = 0x0011, /* breaks "classic" svr4 SDB */ + FT_dbl_prec_complex = 0x0012, /* breaks "classic" svr4 SDB */ + /* 0x0013 -- reserved */ + FT_void = 0x0014, + FT_boolean = 0x0015, /* breaks "classic" svr4 SDB */ + FT_ext_prec_complex = 0x0016, /* breaks "classic" svr4 SDB */ + FT_label = 0x0017, + + /* GNU extensions + The low order byte must indicate the size (in bytes) for the type. + All of these types will probably break "classic" svr4 SDB */ + + FT_long_long = 0x8008, + FT_signed_long_long = 0x8108, + FT_unsigned_long_long = 0x8208, + + FT_int8 = 0x9001, + FT_signed_int8 = 0x9101, + FT_unsigned_int8 = 0x9201, + FT_int16 = 0x9302, + FT_signed_int16 = 0x9402, + FT_unsigned_int16 = 0x9502, + FT_int32 = 0x9604, + FT_signed_int32 = 0x9704, + FT_unsigned_int32 = 0x9804, + FT_int64 = 0x9908, + FT_signed_int64 = 0x9a08, + FT_unsigned_int64 = 0x9b08, + + FT_real32 = 0xa004, + FT_real64 = 0xa108, + FT_real96 = 0xa20c, + FT_real128 = 0xa310 +}; + +#define FT_lo_user 0x8000 /* implementation-defined range start */ +#define FT_hi_user 0xffff /* implementation defined range end */ + +/* Type modifier names and codes. */ + +enum dwarf_type_modifier { + MOD_pointer_to = 0x01, + MOD_reference_to = 0x02, + MOD_const = 0x03, + MOD_volatile = 0x04 +}; + +#define MOD_lo_user 0x80 /* implementation-defined range start */ +#define MOD_hi_user 0xff /* implementation-defined range end */ + +/* Array ordering names and codes. */ + +enum dwarf_array_dim_ordering { + ORD_row_major = 0, + ORD_col_major = 1 +}; + +/* Array subscript format names and codes. */ + +enum dwarf_subscr_data_formats { + FMT_FT_C_C = 0x0, + FMT_FT_C_X = 0x1, + FMT_FT_X_C = 0x2, + FMT_FT_X_X = 0x3, + FMT_UT_C_C = 0x4, + FMT_UT_C_X = 0x5, + FMT_UT_X_C = 0x6, + FMT_UT_X_X = 0x7, + FMT_ET = 0x8 +}; + +/* Derived from above for ease of use. */ + +#define FMT_CODE(_FUNDAMENTAL_TYPE_P, _UB_CONST_P, _LB_CONST_P) \ + (((_FUNDAMENTAL_TYPE_P) ? 0 : 4) \ + | ((_UB_CONST_P) ? 0 : 2) \ + | ((_LB_CONST_P) ? 0 : 1)) + +/* Source language names and codes. */ + +enum dwarf_source_language { + LANG_C89 = 0x00000001, + LANG_C = 0x00000002, + LANG_ADA83 = 0x00000003, + LANG_C_PLUS_PLUS = 0x00000004, + LANG_COBOL74 = 0x00000005, + LANG_COBOL85 = 0x00000006, + LANG_FORTRAN77 = 0x00000007, + LANG_FORTRAN90 = 0x00000008, + LANG_PASCAL83 = 0x00000009, + LANG_MODULA2 = 0x0000000a, + + /* GNU extensions */ + + LANG_CHILL = 0x00009af3, /* random value for GNU Chill */ + LANG_JAVA = 0x00009af4 /* random value + 1 for GNU Java */ +}; + +#define LANG_lo_user 0x00008000 /* implementation-defined range start */ +#define LANG_hi_user 0x0000ffff /* implementation-defined range end */ + +/* Names and codes for GNU "macinfo" extension. */ + +enum dwarf_macinfo_record_type { + MACINFO_start = 's', + MACINFO_resume = 'r', + MACINFO_define = 'd', + MACINFO_undef = 'u' +}; + +#endif /* _ELF_DWARF_H */ diff --git a/include/elf/dwarf2.h b/include/elf/dwarf2.h new file mode 100644 index 000000000..bede7e297 --- /dev/null +++ b/include/elf/dwarf2.h @@ -0,0 +1,775 @@ +/* Declarations and definitions of codes relating to the DWARF2 symbolic + debugging information format. + Copyright (C) 1992, 1993, 1995, 1996, 1997, 1999, 2000, 2001, 2002, + 2003 Free Software Foundation, Inc. + + Written by Gary Funck (gary@intrepid.com) The Ada Joint Program + Office (AJPO), Florida State Unviversity and Silicon Graphics Inc. + provided support for this effort -- June 21, 1995. + + Derived from the DWARF 1 implementation written by Ron Guilmette + (rfg@netcom.com), November 1990. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2, or (at your option) any later + version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* This file is derived from the DWARF specification (a public document) + Revision 2.0.0 (July 27, 1993) developed by the UNIX International + Programming Languages Special Interest Group (UI/PLSIG) and distributed + by UNIX International. Copies of this specification are available from + UNIX International, 20 Waterview Boulevard, Parsippany, NJ, 07054. + + This file also now contains definitions from the DWARF 3 specification. */ + +/* This file is shared between GCC and GDB, and should not contain + prototypes. */ + +#ifndef _ELF_DWARF2_H +#define _ELF_DWARF2_H + +/* Structure found in the .debug_line section. */ +typedef struct +{ + unsigned char li_length [4]; + unsigned char li_version [2]; + unsigned char li_prologue_length [4]; + unsigned char li_min_insn_length [1]; + unsigned char li_default_is_stmt [1]; + unsigned char li_line_base [1]; + unsigned char li_line_range [1]; + unsigned char li_opcode_base [1]; +} +DWARF2_External_LineInfo; + +typedef struct +{ + unsigned long li_length; + unsigned short li_version; + unsigned int li_prologue_length; + unsigned char li_min_insn_length; + unsigned char li_default_is_stmt; + int li_line_base; + unsigned char li_line_range; + unsigned char li_opcode_base; +} +DWARF2_Internal_LineInfo; + +/* Structure found in .debug_pubnames section. */ +typedef struct +{ + unsigned char pn_length [4]; + unsigned char pn_version [2]; + unsigned char pn_offset [4]; + unsigned char pn_size [4]; +} +DWARF2_External_PubNames; + +typedef struct +{ + unsigned long pn_length; + unsigned short pn_version; + unsigned long pn_offset; + unsigned long pn_size; +} +DWARF2_Internal_PubNames; + +/* Structure found in .debug_info section. */ +typedef struct +{ + unsigned char cu_length [4]; + unsigned char cu_version [2]; + unsigned char cu_abbrev_offset [4]; + unsigned char cu_pointer_size [1]; +} +DWARF2_External_CompUnit; + +typedef struct +{ + unsigned long cu_length; + unsigned short cu_version; + unsigned long cu_abbrev_offset; + unsigned char cu_pointer_size; +} +DWARF2_Internal_CompUnit; + +typedef struct +{ + unsigned char ar_length [4]; + unsigned char ar_version [2]; + unsigned char ar_info_offset [4]; + unsigned char ar_pointer_size [1]; + unsigned char ar_segment_size [1]; +} +DWARF2_External_ARange; + +typedef struct +{ + unsigned long ar_length; + unsigned short ar_version; + unsigned long ar_info_offset; + unsigned char ar_pointer_size; + unsigned char ar_segment_size; +} +DWARF2_Internal_ARange; + + +/* Tag names and codes. */ +enum dwarf_tag + { + DW_TAG_padding = 0x00, + DW_TAG_array_type = 0x01, + DW_TAG_class_type = 0x02, + DW_TAG_entry_point = 0x03, + DW_TAG_enumeration_type = 0x04, + DW_TAG_formal_parameter = 0x05, + DW_TAG_imported_declaration = 0x08, + DW_TAG_label = 0x0a, + DW_TAG_lexical_block = 0x0b, + DW_TAG_member = 0x0d, + DW_TAG_pointer_type = 0x0f, + DW_TAG_reference_type = 0x10, + DW_TAG_compile_unit = 0x11, + DW_TAG_string_type = 0x12, + DW_TAG_structure_type = 0x13, + DW_TAG_subroutine_type = 0x15, + DW_TAG_typedef = 0x16, + DW_TAG_union_type = 0x17, + DW_TAG_unspecified_parameters = 0x18, + DW_TAG_variant = 0x19, + DW_TAG_common_block = 0x1a, + DW_TAG_common_inclusion = 0x1b, + DW_TAG_inheritance = 0x1c, + DW_TAG_inlined_subroutine = 0x1d, + DW_TAG_module = 0x1e, + DW_TAG_ptr_to_member_type = 0x1f, + DW_TAG_set_type = 0x20, + DW_TAG_subrange_type = 0x21, + DW_TAG_with_stmt = 0x22, + DW_TAG_access_declaration = 0x23, + DW_TAG_base_type = 0x24, + DW_TAG_catch_block = 0x25, + DW_TAG_const_type = 0x26, + DW_TAG_constant = 0x27, + DW_TAG_enumerator = 0x28, + DW_TAG_file_type = 0x29, + DW_TAG_friend = 0x2a, + DW_TAG_namelist = 0x2b, + DW_TAG_namelist_item = 0x2c, + DW_TAG_packed_type = 0x2d, + DW_TAG_subprogram = 0x2e, + DW_TAG_template_type_param = 0x2f, + DW_TAG_template_value_param = 0x30, + DW_TAG_thrown_type = 0x31, + DW_TAG_try_block = 0x32, + DW_TAG_variant_part = 0x33, + DW_TAG_variable = 0x34, + DW_TAG_volatile_type = 0x35, + /* DWARF 3. */ + DW_TAG_dwarf_procedure = 0x36, + DW_TAG_restrict_type = 0x37, + DW_TAG_interface_type = 0x38, + DW_TAG_namespace = 0x39, + DW_TAG_imported_module = 0x3a, + DW_TAG_unspecified_type = 0x3b, + DW_TAG_partial_unit = 0x3c, + DW_TAG_imported_unit = 0x3d, + /* SGI/MIPS Extensions. */ + DW_TAG_MIPS_loop = 0x4081, + /* HP extensions. See: ftp://ftp.hp.com/pub/lang/tools/WDB/wdb-4.0.tar.gz . */ + DW_TAG_HP_array_descriptor = 0x4090, + /* GNU extensions. */ + DW_TAG_format_label = 0x4101, /* For FORTRAN 77 and Fortran 90. */ + DW_TAG_function_template = 0x4102, /* For C++. */ + DW_TAG_class_template = 0x4103, /* For C++. */ + DW_TAG_GNU_BINCL = 0x4104, + DW_TAG_GNU_EINCL = 0x4105, + /* Extensions for UPC. See: http://upc.gwu.edu/~upc. */ + DW_TAG_upc_shared_type = 0x8765, + DW_TAG_upc_strict_type = 0x8766, + DW_TAG_upc_relaxed_type = 0x8767, + /* PGI (STMicroelectronics) extensions. No documentation available. */ + DW_TAG_PGI_kanji_type = 0xA000, + DW_TAG_PGI_interface_block = 0xA020 + }; + +#define DW_TAG_lo_user 0x4080 +#define DW_TAG_hi_user 0xffff + +/* Flag that tells whether entry has a child or not. */ +#define DW_children_no 0 +#define DW_children_yes 1 + +/* Form names and codes. */ +enum dwarf_form + { + DW_FORM_addr = 0x01, + DW_FORM_block2 = 0x03, + DW_FORM_block4 = 0x04, + DW_FORM_data2 = 0x05, + DW_FORM_data4 = 0x06, + DW_FORM_data8 = 0x07, + DW_FORM_string = 0x08, + DW_FORM_block = 0x09, + DW_FORM_block1 = 0x0a, + DW_FORM_data1 = 0x0b, + DW_FORM_flag = 0x0c, + DW_FORM_sdata = 0x0d, + DW_FORM_strp = 0x0e, + DW_FORM_udata = 0x0f, + DW_FORM_ref_addr = 0x10, + DW_FORM_ref1 = 0x11, + DW_FORM_ref2 = 0x12, + DW_FORM_ref4 = 0x13, + DW_FORM_ref8 = 0x14, + DW_FORM_ref_udata = 0x15, + DW_FORM_indirect = 0x16 + }; + +/* Attribute names and codes. */ +enum dwarf_attribute + { + DW_AT_sibling = 0x01, + DW_AT_location = 0x02, + DW_AT_name = 0x03, + DW_AT_ordering = 0x09, + DW_AT_subscr_data = 0x0a, + DW_AT_byte_size = 0x0b, + DW_AT_bit_offset = 0x0c, + DW_AT_bit_size = 0x0d, + DW_AT_element_list = 0x0f, + DW_AT_stmt_list = 0x10, + DW_AT_low_pc = 0x11, + DW_AT_high_pc = 0x12, + DW_AT_language = 0x13, + DW_AT_member = 0x14, + DW_AT_discr = 0x15, + DW_AT_discr_value = 0x16, + DW_AT_visibility = 0x17, + DW_AT_import = 0x18, + DW_AT_string_length = 0x19, + DW_AT_common_reference = 0x1a, + DW_AT_comp_dir = 0x1b, + DW_AT_const_value = 0x1c, + DW_AT_containing_type = 0x1d, + DW_AT_default_value = 0x1e, + DW_AT_inline = 0x20, + DW_AT_is_optional = 0x21, + DW_AT_lower_bound = 0x22, + DW_AT_producer = 0x25, + DW_AT_prototyped = 0x27, + DW_AT_return_addr = 0x2a, + DW_AT_start_scope = 0x2c, + DW_AT_stride_size = 0x2e, + DW_AT_upper_bound = 0x2f, + DW_AT_abstract_origin = 0x31, + DW_AT_accessibility = 0x32, + DW_AT_address_class = 0x33, + DW_AT_artificial = 0x34, + DW_AT_base_types = 0x35, + DW_AT_calling_convention = 0x36, + DW_AT_count = 0x37, + DW_AT_data_member_location = 0x38, + DW_AT_decl_column = 0x39, + DW_AT_decl_file = 0x3a, + DW_AT_decl_line = 0x3b, + DW_AT_declaration = 0x3c, + DW_AT_discr_list = 0x3d, + DW_AT_encoding = 0x3e, + DW_AT_external = 0x3f, + DW_AT_frame_base = 0x40, + DW_AT_friend = 0x41, + DW_AT_identifier_case = 0x42, + DW_AT_macro_info = 0x43, + DW_AT_namelist_items = 0x44, + DW_AT_priority = 0x45, + DW_AT_segment = 0x46, + DW_AT_specification = 0x47, + DW_AT_static_link = 0x48, + DW_AT_type = 0x49, + DW_AT_use_location = 0x4a, + DW_AT_variable_parameter = 0x4b, + DW_AT_virtuality = 0x4c, + DW_AT_vtable_elem_location = 0x4d, + /* DWARF 3 values. */ + DW_AT_allocated = 0x4e, + DW_AT_associated = 0x4f, + DW_AT_data_location = 0x50, + DW_AT_stride = 0x51, + DW_AT_entry_pc = 0x52, + DW_AT_use_UTF8 = 0x53, + DW_AT_extension = 0x54, + DW_AT_ranges = 0x55, + DW_AT_trampoline = 0x56, + DW_AT_call_column = 0x57, + DW_AT_call_file = 0x58, + DW_AT_call_line = 0x59, + /* SGI/MIPS extensions. */ + DW_AT_MIPS_fde = 0x2001, + DW_AT_MIPS_loop_begin = 0x2002, + DW_AT_MIPS_tail_loop_begin = 0x2003, + DW_AT_MIPS_epilog_begin = 0x2004, + DW_AT_MIPS_loop_unroll_factor = 0x2005, + DW_AT_MIPS_software_pipeline_depth = 0x2006, + DW_AT_MIPS_linkage_name = 0x2007, + DW_AT_MIPS_stride = 0x2008, + DW_AT_MIPS_abstract_name = 0x2009, + DW_AT_MIPS_clone_origin = 0x200a, + DW_AT_MIPS_has_inlines = 0x200b, + /* HP extensions. */ + DW_AT_HP_block_index = 0x2000, + DW_AT_HP_unmodifiable = 0x2001, /* Same as DW_AT_MIPS_fde. */ + DW_AT_HP_actuals_stmt_list = 0x2010, + DW_AT_HP_proc_per_section = 0x2011, + DW_AT_HP_raw_data_ptr = 0x2012, + DW_AT_HP_pass_by_reference = 0x2013, + DW_AT_HP_opt_level = 0x2014, + DW_AT_HP_prof_version_id = 0x2015, + DW_AT_HP_opt_flags = 0x2016, + DW_AT_HP_cold_region_low_pc = 0x2017, + DW_AT_HP_cold_region_high_pc = 0x2018, + DW_AT_HP_all_variables_modifiable = 0x2019, + DW_AT_HP_linkage_name = 0x201a, + DW_AT_HP_prof_flags = 0x201b, /* In comp unit of procs_info for -g. */ + /* GNU extensions. */ + DW_AT_sf_names = 0x2101, + DW_AT_src_info = 0x2102, + DW_AT_mac_info = 0x2103, + DW_AT_src_coords = 0x2104, + DW_AT_body_begin = 0x2105, + DW_AT_body_end = 0x2106, + DW_AT_GNU_vector = 0x2107, + /* VMS extensions. */ + DW_AT_VMS_rtnbeg_pd_address = 0x2201, + /* UPC extension. */ + DW_AT_upc_threads_scaled = 0x3210, + /* PGI (STMicroelectronics) extensions. */ + DW_AT_PGI_lbase = 0x3a00, + DW_AT_PGI_soffset = 0x3a01, + DW_AT_PGI_lstride = 0x3a02 + }; + +#define DW_AT_lo_user 0x2000 /* Implementation-defined range start. */ +#define DW_AT_hi_user 0x3ff0 /* Implementation-defined range end. */ + +/* Location atom names and codes. */ +enum dwarf_location_atom + { + DW_OP_addr = 0x03, + DW_OP_deref = 0x06, + DW_OP_const1u = 0x08, + DW_OP_const1s = 0x09, + DW_OP_const2u = 0x0a, + DW_OP_const2s = 0x0b, + DW_OP_const4u = 0x0c, + DW_OP_const4s = 0x0d, + DW_OP_const8u = 0x0e, + DW_OP_const8s = 0x0f, + DW_OP_constu = 0x10, + DW_OP_consts = 0x11, + DW_OP_dup = 0x12, + DW_OP_drop = 0x13, + DW_OP_over = 0x14, + DW_OP_pick = 0x15, + DW_OP_swap = 0x16, + DW_OP_rot = 0x17, + DW_OP_xderef = 0x18, + DW_OP_abs = 0x19, + DW_OP_and = 0x1a, + DW_OP_div = 0x1b, + DW_OP_minus = 0x1c, + DW_OP_mod = 0x1d, + DW_OP_mul = 0x1e, + DW_OP_neg = 0x1f, + DW_OP_not = 0x20, + DW_OP_or = 0x21, + DW_OP_plus = 0x22, + DW_OP_plus_uconst = 0x23, + DW_OP_shl = 0x24, + DW_OP_shr = 0x25, + DW_OP_shra = 0x26, + DW_OP_xor = 0x27, + DW_OP_bra = 0x28, + DW_OP_eq = 0x29, + DW_OP_ge = 0x2a, + DW_OP_gt = 0x2b, + DW_OP_le = 0x2c, + DW_OP_lt = 0x2d, + DW_OP_ne = 0x2e, + DW_OP_skip = 0x2f, + DW_OP_lit0 = 0x30, + DW_OP_lit1 = 0x31, + DW_OP_lit2 = 0x32, + DW_OP_lit3 = 0x33, + DW_OP_lit4 = 0x34, + DW_OP_lit5 = 0x35, + DW_OP_lit6 = 0x36, + DW_OP_lit7 = 0x37, + DW_OP_lit8 = 0x38, + DW_OP_lit9 = 0x39, + DW_OP_lit10 = 0x3a, + DW_OP_lit11 = 0x3b, + DW_OP_lit12 = 0x3c, + DW_OP_lit13 = 0x3d, + DW_OP_lit14 = 0x3e, + DW_OP_lit15 = 0x3f, + DW_OP_lit16 = 0x40, + DW_OP_lit17 = 0x41, + DW_OP_lit18 = 0x42, + DW_OP_lit19 = 0x43, + DW_OP_lit20 = 0x44, + DW_OP_lit21 = 0x45, + DW_OP_lit22 = 0x46, + DW_OP_lit23 = 0x47, + DW_OP_lit24 = 0x48, + DW_OP_lit25 = 0x49, + DW_OP_lit26 = 0x4a, + DW_OP_lit27 = 0x4b, + DW_OP_lit28 = 0x4c, + DW_OP_lit29 = 0x4d, + DW_OP_lit30 = 0x4e, + DW_OP_lit31 = 0x4f, + DW_OP_reg0 = 0x50, + DW_OP_reg1 = 0x51, + DW_OP_reg2 = 0x52, + DW_OP_reg3 = 0x53, + DW_OP_reg4 = 0x54, + DW_OP_reg5 = 0x55, + DW_OP_reg6 = 0x56, + DW_OP_reg7 = 0x57, + DW_OP_reg8 = 0x58, + DW_OP_reg9 = 0x59, + DW_OP_reg10 = 0x5a, + DW_OP_reg11 = 0x5b, + DW_OP_reg12 = 0x5c, + DW_OP_reg13 = 0x5d, + DW_OP_reg14 = 0x5e, + DW_OP_reg15 = 0x5f, + DW_OP_reg16 = 0x60, + DW_OP_reg17 = 0x61, + DW_OP_reg18 = 0x62, + DW_OP_reg19 = 0x63, + DW_OP_reg20 = 0x64, + DW_OP_reg21 = 0x65, + DW_OP_reg22 = 0x66, + DW_OP_reg23 = 0x67, + DW_OP_reg24 = 0x68, + DW_OP_reg25 = 0x69, + DW_OP_reg26 = 0x6a, + DW_OP_reg27 = 0x6b, + DW_OP_reg28 = 0x6c, + DW_OP_reg29 = 0x6d, + DW_OP_reg30 = 0x6e, + DW_OP_reg31 = 0x6f, + DW_OP_breg0 = 0x70, + DW_OP_breg1 = 0x71, + DW_OP_breg2 = 0x72, + DW_OP_breg3 = 0x73, + DW_OP_breg4 = 0x74, + DW_OP_breg5 = 0x75, + DW_OP_breg6 = 0x76, + DW_OP_breg7 = 0x77, + DW_OP_breg8 = 0x78, + DW_OP_breg9 = 0x79, + DW_OP_breg10 = 0x7a, + DW_OP_breg11 = 0x7b, + DW_OP_breg12 = 0x7c, + DW_OP_breg13 = 0x7d, + DW_OP_breg14 = 0x7e, + DW_OP_breg15 = 0x7f, + DW_OP_breg16 = 0x80, + DW_OP_breg17 = 0x81, + DW_OP_breg18 = 0x82, + DW_OP_breg19 = 0x83, + DW_OP_breg20 = 0x84, + DW_OP_breg21 = 0x85, + DW_OP_breg22 = 0x86, + DW_OP_breg23 = 0x87, + DW_OP_breg24 = 0x88, + DW_OP_breg25 = 0x89, + DW_OP_breg26 = 0x8a, + DW_OP_breg27 = 0x8b, + DW_OP_breg28 = 0x8c, + DW_OP_breg29 = 0x8d, + DW_OP_breg30 = 0x8e, + DW_OP_breg31 = 0x8f, + DW_OP_regx = 0x90, + DW_OP_fbreg = 0x91, + DW_OP_bregx = 0x92, + DW_OP_piece = 0x93, + DW_OP_deref_size = 0x94, + DW_OP_xderef_size = 0x95, + DW_OP_nop = 0x96, + /* DWARF 3 extensions. */ + DW_OP_push_object_address = 0x97, + DW_OP_call2 = 0x98, + DW_OP_call4 = 0x99, + DW_OP_call_ref = 0x9a, + /* GNU extensions. */ + DW_OP_GNU_push_tls_address = 0xe0, + /* HP extensions. */ + DW_OP_HP_unknown = 0xe0, /* Ouch, the same as GNU_push_tls_address. */ + DW_OP_HP_is_value = 0xe1, + DW_OP_HP_fltconst4 = 0xe2, + DW_OP_HP_fltconst8 = 0xe3, + DW_OP_HP_mod_range = 0xe4, + DW_OP_HP_unmod_range = 0xe5, + DW_OP_HP_tls = 0xe6 + }; + +#define DW_OP_lo_user 0xe0 /* Implementation-defined range start. */ +#define DW_OP_hi_user 0xff /* Implementation-defined range end. */ + +/* Type encodings. */ +enum dwarf_type + { + DW_ATE_void = 0x0, + DW_ATE_address = 0x1, + DW_ATE_boolean = 0x2, + DW_ATE_complex_float = 0x3, + DW_ATE_float = 0x4, + DW_ATE_signed = 0x5, + DW_ATE_signed_char = 0x6, + DW_ATE_unsigned = 0x7, + DW_ATE_unsigned_char = 0x8, + /* DWARF 3. */ + DW_ATE_imaginary_float = 0x9, + /* HP extensions. */ + DW_ATE_HP_float80 = 0x80, /* Floating-point (80 bit). */ + DW_ATE_HP_complex_float80 = 0x81, /* Complex floating-point (80 bit). */ + DW_ATE_HP_float128 = 0x82, /* Floating-point (128 bit). */ + DW_ATE_HP_complex_float128 = 0x83, /* Complex floating-point (128 bit). */ + DW_ATE_HP_floathpintel = 0x84, /* Floating-point (82 bit IA64). */ + DW_ATE_HP_imaginary_float80 = 0x85, + DW_ATE_HP_imaginary_float128 = 0x86 + }; + +#define DW_ATE_lo_user 0x80 +#define DW_ATE_hi_user 0xff + +/* Array ordering names and codes. */ +enum dwarf_array_dim_ordering + { + DW_ORD_row_major = 0, + DW_ORD_col_major = 1 + }; + +/* Access attribute. */ +enum dwarf_access_attribute + { + DW_ACCESS_public = 1, + DW_ACCESS_protected = 2, + DW_ACCESS_private = 3 + }; + +/* Visibility. */ +enum dwarf_visibility_attribute + { + DW_VIS_local = 1, + DW_VIS_exported = 2, + DW_VIS_qualified = 3 + }; + +/* Virtuality. */ +enum dwarf_virtuality_attribute + { + DW_VIRTUALITY_none = 0, + DW_VIRTUALITY_virtual = 1, + DW_VIRTUALITY_pure_virtual = 2 + }; + +/* Case sensitivity. */ +enum dwarf_id_case + { + DW_ID_case_sensitive = 0, + DW_ID_up_case = 1, + DW_ID_down_case = 2, + DW_ID_case_insensitive = 3 + }; + +/* Calling convention. */ +enum dwarf_calling_convention + { + DW_CC_normal = 0x1, + DW_CC_program = 0x2, + DW_CC_nocall = 0x3 + }; + +#define DW_CC_lo_user 0x40 +#define DW_CC_hi_user 0xff + +/* Inline attribute. */ +enum dwarf_inline_attribute + { + DW_INL_not_inlined = 0, + DW_INL_inlined = 1, + DW_INL_declared_not_inlined = 2, + DW_INL_declared_inlined = 3 + }; + +/* Discriminant lists. */ +enum dwarf_discrim_list + { + DW_DSC_label = 0, + DW_DSC_range = 1 + }; + +/* Line number opcodes. */ +enum dwarf_line_number_ops + { + DW_LNS_extended_op = 0, + DW_LNS_copy = 1, + DW_LNS_advance_pc = 2, + DW_LNS_advance_line = 3, + DW_LNS_set_file = 4, + DW_LNS_set_column = 5, + DW_LNS_negate_stmt = 6, + DW_LNS_set_basic_block = 7, + DW_LNS_const_add_pc = 8, + DW_LNS_fixed_advance_pc = 9, + /* DWARF 3. */ + DW_LNS_set_prologue_end = 10, + DW_LNS_set_epilogue_begin = 11, + DW_LNS_set_isa = 12 + }; + +/* Line number extended opcodes. */ +enum dwarf_line_number_x_ops + { + DW_LNE_end_sequence = 1, + DW_LNE_set_address = 2, + DW_LNE_define_file = 3, + /* HP extensions. */ + DW_LNE_HP_negate_is_UV_update = 0x11, + DW_LNE_HP_push_context = 0x12, + DW_LNE_HP_pop_context = 0x13, + DW_LNE_HP_set_file_line_column = 0x14, + DW_LNE_HP_set_routine_name = 0x15, + DW_LNE_HP_set_sequence = 0x16, + DW_LNE_HP_negate_post_semantics = 0x17, + DW_LNE_HP_negate_function_exit = 0x18, + DW_LNE_HP_negate_front_end_logical = 0x19, + DW_LNE_HP_define_proc = 0x20 + }; + +/* Call frame information. */ +enum dwarf_call_frame_info + { + DW_CFA_advance_loc = 0x40, + DW_CFA_offset = 0x80, + DW_CFA_restore = 0xc0, + DW_CFA_nop = 0x00, + DW_CFA_set_loc = 0x01, + DW_CFA_advance_loc1 = 0x02, + DW_CFA_advance_loc2 = 0x03, + DW_CFA_advance_loc4 = 0x04, + DW_CFA_offset_extended = 0x05, + DW_CFA_restore_extended = 0x06, + DW_CFA_undefined = 0x07, + DW_CFA_same_value = 0x08, + DW_CFA_register = 0x09, + DW_CFA_remember_state = 0x0a, + DW_CFA_restore_state = 0x0b, + DW_CFA_def_cfa = 0x0c, + DW_CFA_def_cfa_register = 0x0d, + DW_CFA_def_cfa_offset = 0x0e, + /* DWARF 3. */ + DW_CFA_def_cfa_expression = 0x0f, + DW_CFA_expression = 0x10, + DW_CFA_offset_extended_sf = 0x11, + DW_CFA_def_cfa_sf = 0x12, + DW_CFA_def_cfa_offset_sf = 0x13, + /* SGI/MIPS specific. */ + DW_CFA_MIPS_advance_loc8 = 0x1d, + /* GNU extensions. */ + DW_CFA_GNU_window_save = 0x2d, + DW_CFA_GNU_args_size = 0x2e, + DW_CFA_GNU_negative_offset_extended = 0x2f + }; + +#define DW_CIE_ID 0xffffffff +#define DW_CIE_VERSION 1 + +#define DW_CFA_extended 0 +#define DW_CFA_lo_user 0x1c +#define DW_CFA_hi_user 0x3f + +#define DW_CHILDREN_no 0x00 +#define DW_CHILDREN_yes 0x01 + +#define DW_ADDR_none 0 + +/* Source language names and codes. */ +enum dwarf_source_language + { + DW_LANG_C89 = 0x0001, + DW_LANG_C = 0x0002, + DW_LANG_Ada83 = 0x0003, + DW_LANG_C_plus_plus = 0x0004, + DW_LANG_Cobol74 = 0x0005, + DW_LANG_Cobol85 = 0x0006, + DW_LANG_Fortran77 = 0x0007, + DW_LANG_Fortran90 = 0x0008, + DW_LANG_Pascal83 = 0x0009, + DW_LANG_Modula2 = 0x000a, + DW_LANG_Java = 0x000b, + /* DWARF 3. */ + DW_LANG_C99 = 0x000c, + DW_LANG_Ada95 = 0x000d, + DW_LANG_Fortran95 = 0x000e, + /* MIPS. */ + DW_LANG_Mips_Assembler = 0x8001, + /* UPC. */ + DW_LANG_Upc = 0x8765 + }; + +#define DW_LANG_lo_user 0x8000 /* Implementation-defined range start. */ +#define DW_LANG_hi_user 0xffff /* Implementation-defined range start. */ + +/* Names and codes for macro information. */ +enum dwarf_macinfo_record_type + { + DW_MACINFO_define = 1, + DW_MACINFO_undef = 2, + DW_MACINFO_start_file = 3, + DW_MACINFO_end_file = 4, + DW_MACINFO_vendor_ext = 255 + }; + +/* @@@ For use with GNU frame unwind information. */ + +#define DW_EH_PE_absptr 0x00 +#define DW_EH_PE_omit 0xff + +#define DW_EH_PE_uleb128 0x01 +#define DW_EH_PE_udata2 0x02 +#define DW_EH_PE_udata4 0x03 +#define DW_EH_PE_udata8 0x04 +#define DW_EH_PE_sleb128 0x09 +#define DW_EH_PE_sdata2 0x0A +#define DW_EH_PE_sdata4 0x0B +#define DW_EH_PE_sdata8 0x0C +#define DW_EH_PE_signed 0x08 + +#define DW_EH_PE_pcrel 0x10 +#define DW_EH_PE_textrel 0x20 +#define DW_EH_PE_datarel 0x30 +#define DW_EH_PE_funcrel 0x40 +#define DW_EH_PE_aligned 0x50 + +#define DW_EH_PE_indirect 0x80 + +#endif /* _ELF_DWARF2_H */ diff --git a/include/elf/external.h b/include/elf/external.h new file mode 100644 index 000000000..a17143917 --- /dev/null +++ b/include/elf/external.h @@ -0,0 +1,276 @@ +/* ELF support for BFD. + Copyright 1991, 1992, 1993, 1995, 1997, 1998, 1999, 2001 + Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support, from information published + in "UNIX System V Release 4, Programmers Guide: ANSI C and + Programming Support Tools". + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of ELF support for BFD, and contains the portions + that describe how ELF is represented externally by the BFD library. + I.E. it describes the in-file representation of ELF. It requires + the elf/common.h file which contains the portions that are common to + both the internal and external representations. */ + +/* The 64-bit stuff is kind of random. Perhaps someone will publish a + spec someday. */ + +#ifndef _ELF_EXTERNAL_H +#define _ELF_EXTERNAL_H + +/* ELF Header (32-bit implementations) */ + +typedef struct { + unsigned char e_ident[16]; /* ELF "magic number" */ + unsigned char e_type[2]; /* Identifies object file type */ + unsigned char e_machine[2]; /* Specifies required architecture */ + unsigned char e_version[4]; /* Identifies object file version */ + unsigned char e_entry[4]; /* Entry point virtual address */ + unsigned char e_phoff[4]; /* Program header table file offset */ + unsigned char e_shoff[4]; /* Section header table file offset */ + unsigned char e_flags[4]; /* Processor-specific flags */ + unsigned char e_ehsize[2]; /* ELF header size in bytes */ + unsigned char e_phentsize[2]; /* Program header table entry size */ + unsigned char e_phnum[2]; /* Program header table entry count */ + unsigned char e_shentsize[2]; /* Section header table entry size */ + unsigned char e_shnum[2]; /* Section header table entry count */ + unsigned char e_shstrndx[2]; /* Section header string table index */ +} Elf32_External_Ehdr; + +typedef struct { + unsigned char e_ident[16]; /* ELF "magic number" */ + unsigned char e_type[2]; /* Identifies object file type */ + unsigned char e_machine[2]; /* Specifies required architecture */ + unsigned char e_version[4]; /* Identifies object file version */ + unsigned char e_entry[8]; /* Entry point virtual address */ + unsigned char e_phoff[8]; /* Program header table file offset */ + unsigned char e_shoff[8]; /* Section header table file offset */ + unsigned char e_flags[4]; /* Processor-specific flags */ + unsigned char e_ehsize[2]; /* ELF header size in bytes */ + unsigned char e_phentsize[2]; /* Program header table entry size */ + unsigned char e_phnum[2]; /* Program header table entry count */ + unsigned char e_shentsize[2]; /* Section header table entry size */ + unsigned char e_shnum[2]; /* Section header table entry count */ + unsigned char e_shstrndx[2]; /* Section header string table index */ +} Elf64_External_Ehdr; + +/* Program header */ + +typedef struct { + unsigned char p_type[4]; /* Identifies program segment type */ + unsigned char p_offset[4]; /* Segment file offset */ + unsigned char p_vaddr[4]; /* Segment virtual address */ + unsigned char p_paddr[4]; /* Segment physical address */ + unsigned char p_filesz[4]; /* Segment size in file */ + unsigned char p_memsz[4]; /* Segment size in memory */ + unsigned char p_flags[4]; /* Segment flags */ + unsigned char p_align[4]; /* Segment alignment, file & memory */ +} Elf32_External_Phdr; + +typedef struct { + unsigned char p_type[4]; /* Identifies program segment type */ + unsigned char p_flags[4]; /* Segment flags */ + unsigned char p_offset[8]; /* Segment file offset */ + unsigned char p_vaddr[8]; /* Segment virtual address */ + unsigned char p_paddr[8]; /* Segment physical address */ + unsigned char p_filesz[8]; /* Segment size in file */ + unsigned char p_memsz[8]; /* Segment size in memory */ + unsigned char p_align[8]; /* Segment alignment, file & memory */ +} Elf64_External_Phdr; + +/* Section header */ + +typedef struct { + unsigned char sh_name[4]; /* Section name, index in string tbl */ + unsigned char sh_type[4]; /* Type of section */ + unsigned char sh_flags[4]; /* Miscellaneous section attributes */ + unsigned char sh_addr[4]; /* Section virtual addr at execution */ + unsigned char sh_offset[4]; /* Section file offset */ + unsigned char sh_size[4]; /* Size of section in bytes */ + unsigned char sh_link[4]; /* Index of another section */ + unsigned char sh_info[4]; /* Additional section information */ + unsigned char sh_addralign[4]; /* Section alignment */ + unsigned char sh_entsize[4]; /* Entry size if section holds table */ +} Elf32_External_Shdr; + +typedef struct { + unsigned char sh_name[4]; /* Section name, index in string tbl */ + unsigned char sh_type[4]; /* Type of section */ + unsigned char sh_flags[8]; /* Miscellaneous section attributes */ + unsigned char sh_addr[8]; /* Section virtual addr at execution */ + unsigned char sh_offset[8]; /* Section file offset */ + unsigned char sh_size[8]; /* Size of section in bytes */ + unsigned char sh_link[4]; /* Index of another section */ + unsigned char sh_info[4]; /* Additional section information */ + unsigned char sh_addralign[8]; /* Section alignment */ + unsigned char sh_entsize[8]; /* Entry size if section holds table */ +} Elf64_External_Shdr; + +/* Symbol table entry */ + +typedef struct { + unsigned char st_name[4]; /* Symbol name, index in string tbl */ + unsigned char st_value[4]; /* Value of the symbol */ + unsigned char st_size[4]; /* Associated symbol size */ + unsigned char st_info[1]; /* Type and binding attributes */ + unsigned char st_other[1]; /* No defined meaning, 0 */ + unsigned char st_shndx[2]; /* Associated section index */ +} Elf32_External_Sym; + +typedef struct { + unsigned char st_name[4]; /* Symbol name, index in string tbl */ + unsigned char st_info[1]; /* Type and binding attributes */ + unsigned char st_other[1]; /* No defined meaning, 0 */ + unsigned char st_shndx[2]; /* Associated section index */ + unsigned char st_value[8]; /* Value of the symbol */ + unsigned char st_size[8]; /* Associated symbol size */ +} Elf64_External_Sym; + +typedef struct { + unsigned char est_shndx[4]; /* Section index */ +} Elf_External_Sym_Shndx; + +/* Note segments */ + +typedef struct { + unsigned char namesz[4]; /* Size of entry's owner string */ + unsigned char descsz[4]; /* Size of the note descriptor */ + unsigned char type[4]; /* Interpretation of the descriptor */ + char name[1]; /* Start of the name+desc data */ +} Elf_External_Note; + +/* Relocation Entries */ +typedef struct { + unsigned char r_offset[4]; /* Location at which to apply the action */ + unsigned char r_info[4]; /* index and type of relocation */ +} Elf32_External_Rel; + +typedef struct { + unsigned char r_offset[4]; /* Location at which to apply the action */ + unsigned char r_info[4]; /* index and type of relocation */ + unsigned char r_addend[4]; /* Constant addend used to compute value */ +} Elf32_External_Rela; + +typedef struct { + unsigned char r_offset[8]; /* Location at which to apply the action */ + unsigned char r_info[8]; /* index and type of relocation */ +} Elf64_External_Rel; + +typedef struct { + unsigned char r_offset[8]; /* Location at which to apply the action */ + unsigned char r_info[8]; /* index and type of relocation */ + unsigned char r_addend[8]; /* Constant addend used to compute value */ +} Elf64_External_Rela; + +/* dynamic section structure */ + +typedef struct { + unsigned char d_tag[4]; /* entry tag value */ + union { + unsigned char d_val[4]; + unsigned char d_ptr[4]; + } d_un; +} Elf32_External_Dyn; + +typedef struct { + unsigned char d_tag[8]; /* entry tag value */ + union { + unsigned char d_val[8]; + unsigned char d_ptr[8]; + } d_un; +} Elf64_External_Dyn; + +/* The version structures are currently size independent. They are + named without a 32 or 64. If that ever changes, these structures + will need to be renamed. */ + +/* This structure appears in a SHT_GNU_verdef section. */ + +typedef struct { + unsigned char vd_version[2]; + unsigned char vd_flags[2]; + unsigned char vd_ndx[2]; + unsigned char vd_cnt[2]; + unsigned char vd_hash[4]; + unsigned char vd_aux[4]; + unsigned char vd_next[4]; +} Elf_External_Verdef; + +/* This structure appears in a SHT_GNU_verdef section. */ + +typedef struct { + unsigned char vda_name[4]; + unsigned char vda_next[4]; +} Elf_External_Verdaux; + +/* This structure appears in a SHT_GNU_verneed section. */ + +typedef struct { + unsigned char vn_version[2]; + unsigned char vn_cnt[2]; + unsigned char vn_file[4]; + unsigned char vn_aux[4]; + unsigned char vn_next[4]; +} Elf_External_Verneed; + +/* This structure appears in a SHT_GNU_verneed section. */ + +typedef struct { + unsigned char vna_hash[4]; + unsigned char vna_flags[2]; + unsigned char vna_other[2]; + unsigned char vna_name[4]; + unsigned char vna_next[4]; +} Elf_External_Vernaux; + +/* This structure appears in a SHT_GNU_versym section. This is not a + standard ELF structure; ELF just uses Elf32_Half. */ + +typedef struct { + unsigned char vs_vers[2]; +} +#ifdef __GNUC__ + __attribute__ ((packed)) +#endif + Elf_External_Versym; + +/* Structure for syminfo section. */ +typedef struct +{ + unsigned char si_boundto[2]; + unsigned char si_flags[2]; +} Elf_External_Syminfo; + + +/* This structure appears on the stack and in NT_AUXV core file notes. */ +typedef struct +{ + unsigned char a_type[4]; + unsigned char a_val[4]; +} Elf32_External_Auxv; + +typedef struct +{ + unsigned char a_type[8]; + unsigned char a_val[8]; +} Elf64_External_Auxv; + + +#endif /* _ELF_EXTERNAL_H */ diff --git a/include/elf/fr30.h b/include/elf/fr30.h new file mode 100644 index 000000000..12a450dff --- /dev/null +++ b/include/elf/fr30.h @@ -0,0 +1,42 @@ +/* FR30 ELF support for BFD. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_FR30_H +#define _ELF_FR30_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_fr30_reloc_type) + RELOC_NUMBER (R_FR30_NONE, 0) + RELOC_NUMBER (R_FR30_8, 1) + RELOC_NUMBER (R_FR30_20, 2) + RELOC_NUMBER (R_FR30_32, 3) + RELOC_NUMBER (R_FR30_48, 4) + RELOC_NUMBER (R_FR30_6_IN_4, 5) + RELOC_NUMBER (R_FR30_8_IN_8, 6) + RELOC_NUMBER (R_FR30_9_IN_8, 7) + RELOC_NUMBER (R_FR30_10_IN_8, 8) + RELOC_NUMBER (R_FR30_9_PCREL, 9) + RELOC_NUMBER (R_FR30_12_PCREL, 10) + RELOC_NUMBER (R_FR30_GNU_VTINHERIT, 11) + RELOC_NUMBER (R_FR30_GNU_VTENTRY, 12) +END_RELOC_NUMBERS (R_FR30_max) + +#endif /* _ELF_FR30_H */ diff --git a/include/elf/frv.h b/include/elf/frv.h new file mode 100644 index 000000000..a6b8a7d14 --- /dev/null +++ b/include/elf/frv.h @@ -0,0 +1,114 @@ +/* FRV ELF support for BFD. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_FRV_H +#define _ELF_FRV_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_frv_reloc_type) + RELOC_NUMBER (R_FRV_NONE, 0) + RELOC_NUMBER (R_FRV_32, 1) + RELOC_NUMBER (R_FRV_LABEL16, 2) + RELOC_NUMBER (R_FRV_LABEL24, 3) + RELOC_NUMBER (R_FRV_LO16, 4) + RELOC_NUMBER (R_FRV_HI16, 5) + RELOC_NUMBER (R_FRV_GPREL12, 6) + RELOC_NUMBER (R_FRV_GPRELU12, 7) + RELOC_NUMBER (R_FRV_GPREL32, 8) + RELOC_NUMBER (R_FRV_GPRELHI, 9) + RELOC_NUMBER (R_FRV_GPRELLO, 10) + RELOC_NUMBER (R_FRV_GOT12, 11) + RELOC_NUMBER (R_FRV_GOTHI, 12) + RELOC_NUMBER (R_FRV_GOTLO, 13) + RELOC_NUMBER (R_FRV_FUNCDESC, 14) + RELOC_NUMBER (R_FRV_FUNCDESC_GOT12, 15) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTHI, 16) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTLO, 17) + RELOC_NUMBER (R_FRV_FUNCDESC_VALUE, 18) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFF12, 19) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFFHI, 20) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFFLO, 21) + RELOC_NUMBER (R_FRV_GOTOFF12, 22) + RELOC_NUMBER (R_FRV_GOTOFFHI, 23) + RELOC_NUMBER (R_FRV_GOTOFFLO, 24) + RELOC_NUMBER (R_FRV_GNU_VTINHERIT, 200) + RELOC_NUMBER (R_FRV_GNU_VTENTRY, 201) +END_RELOC_NUMBERS(R_FRV_max) + +/* Processor specific flags for the ELF header e_flags field. */ + /* gpr support */ +#define EF_FRV_GPR_MASK 0x00000003 /* mask for # of gprs */ +#define EF_FRV_GPR_32 0x00000001 /* -mgpr-32 */ +#define EF_FRV_GPR_64 0x00000002 /* -mgpr-64 */ + + /* fpr support */ +#define EF_FRV_FPR_MASK 0x0000000c /* mask for # of fprs */ +#define EF_FRV_FPR_32 0x00000004 /* -mfpr-32 */ +#define EF_FRV_FPR_64 0x00000008 /* -mfpr-64 */ +#define EF_FRV_FPR_NONE 0x0000000c /* -msoft-float */ + + /* double word support */ +#define EF_FRV_DWORD_MASK 0x00000030 /* mask for dword support */ +#define EF_FRV_DWORD_YES 0x00000010 /* use double word insns */ +#define EF_FRV_DWORD_NO 0x00000020 /* don't use double word insn*/ + +#define EF_FRV_DOUBLE 0x00000040 /* -mdouble */ +#define EF_FRV_MEDIA 0x00000080 /* -mmedia */ + +#define EF_FRV_PIC 0x00000100 /* -fpic */ +#define EF_FRV_NON_PIC_RELOCS 0x00000200 /* used non pic safe relocs */ + +#define EF_FRV_MULADD 0x00000400 /* -mmuladd */ +#define EF_FRV_BIGPIC 0x00000800 /* -fPIC */ +#define EF_FRV_LIBPIC 0x00001000 /* -mlibrary-pic */ +#define EF_FRV_G0 0x00002000 /* -G 0, no small data ptr */ +#define EF_FRV_NOPACK 0x00004000 /* -mnopack */ +#define EF_FRV_FDPIC 0x00008000 /* -mfdpic */ + +#define EF_FRV_CPU_MASK 0xff000000 /* specific cpu bits */ +#define EF_FRV_CPU_GENERIC 0x00000000 /* generic FRV */ +#define EF_FRV_CPU_FR500 0x01000000 /* FRV500 */ +#define EF_FRV_CPU_FR300 0x02000000 /* FRV300 */ +#define EF_FRV_CPU_SIMPLE 0x03000000 /* SIMPLE */ +#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */ +#define EF_FRV_CPU_FR400 0x05000000 /* FRV400 */ +#define EF_FRV_CPU_FR550 0x06000000 /* FRV550 */ +#define EF_FRV_CPU_FR405 0x07000000 +#define EF_FRV_CPU_FR450 0x08000000 + + /* Mask of PIC related bits */ +#define EF_FRV_PIC_FLAGS (EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC \ + | EF_FRV_FDPIC) + + /* Mask of all flags */ +#define EF_FRV_ALL_FLAGS (EF_FRV_GPR_MASK | \ + EF_FRV_FPR_MASK | \ + EF_FRV_DWORD_MASK | \ + EF_FRV_DOUBLE | \ + EF_FRV_MEDIA | \ + EF_FRV_PIC_FLAGS | \ + EF_FRV_NON_PIC_RELOCS | \ + EF_FRV_MULADD | \ + EF_FRV_G0 | \ + EF_FRV_NOPACK | \ + EF_FRV_CPU_MASK) + +#endif /* _ELF_FRV_H */ diff --git a/include/elf/h8.h b/include/elf/h8.h new file mode 100644 index 000000000..1aad7a4ed --- /dev/null +++ b/include/elf/h8.h @@ -0,0 +1,100 @@ +/* H8300/h8500 ELF support for BFD. + Copyright 2001, 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_H8_H +#define _ELF_H8_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +/* Relocations 59..63 are GNU extensions. */ +START_RELOC_NUMBERS (elf_h8_reloc_type) + RELOC_NUMBER (R_H8_NONE, 0) + RELOC_NUMBER (R_H8_DIR32, 1) + RELOC_NUMBER (R_H8_DIR32_28, 2) + RELOC_NUMBER (R_H8_DIR32_24, 3) + RELOC_NUMBER (R_H8_DIR32_16, 4) + RELOC_NUMBER (R_H8_DIR32U, 6) + RELOC_NUMBER (R_H8_DIR32U_28, 7) + RELOC_NUMBER (R_H8_DIR32U_24, 8) + RELOC_NUMBER (R_H8_DIR32U_20, 9) + RELOC_NUMBER (R_H8_DIR32U_16, 10) + RELOC_NUMBER (R_H8_DIR24, 11) + RELOC_NUMBER (R_H8_DIR24_20, 12) + RELOC_NUMBER (R_H8_DIR24_16, 13) + RELOC_NUMBER (R_H8_DIR24U, 14) + RELOC_NUMBER (R_H8_DIR24U_20, 15) + RELOC_NUMBER (R_H8_DIR24U_16, 16) + RELOC_NUMBER (R_H8_DIR16, 17) + RELOC_NUMBER (R_H8_DIR16U, 18) + RELOC_NUMBER (R_H8_DIR16S_32, 19) + RELOC_NUMBER (R_H8_DIR16S_28, 20) + RELOC_NUMBER (R_H8_DIR16S_24, 21) + RELOC_NUMBER (R_H8_DIR16S_20, 22) + RELOC_NUMBER (R_H8_DIR16S, 23) + RELOC_NUMBER (R_H8_DIR8, 24) + RELOC_NUMBER (R_H8_DIR8U, 25) + RELOC_NUMBER (R_H8_DIR8Z_32, 26) + RELOC_NUMBER (R_H8_DIR8Z_28, 27) + RELOC_NUMBER (R_H8_DIR8Z_24, 28) + RELOC_NUMBER (R_H8_DIR8Z_20, 29) + RELOC_NUMBER (R_H8_DIR8Z_16, 30) + RELOC_NUMBER (R_H8_PCREL16, 31) + RELOC_NUMBER (R_H8_PCREL8, 32) + RELOC_NUMBER (R_H8_BPOS, 33) + FAKE_RELOC (R_H8_FIRST_INVALID_DIR_RELOC, 34) + FAKE_RELOC (R_H8_LAST_INVALID_DIR_RELOC, 58) + RELOC_NUMBER (R_H8_DIR16A8, 59) + RELOC_NUMBER (R_H8_DIR16R8, 60) + RELOC_NUMBER (R_H8_DIR24A8, 61) + RELOC_NUMBER (R_H8_DIR24R8, 62) + RELOC_NUMBER (R_H8_DIR32A16, 63) + RELOC_NUMBER (R_H8_ABS32, 65) + RELOC_NUMBER (R_H8_ABS32A16, 127) + RELOC_NUMBER (R_H8_SYM, 128) + RELOC_NUMBER (R_H8_OPneg, 129) + RELOC_NUMBER (R_H8_OPadd, 130) + RELOC_NUMBER (R_H8_OPsub, 131) + RELOC_NUMBER (R_H8_OPmul, 132) + RELOC_NUMBER (R_H8_OPdiv, 133) + RELOC_NUMBER (R_H8_OPshla, 134) + RELOC_NUMBER (R_H8_OPshra, 135) + RELOC_NUMBER (R_H8_OPsctsize, 136) + RELOC_NUMBER (R_H8_OPhword, 137) + RELOC_NUMBER (R_H8_OPlword, 138) + RELOC_NUMBER (R_H8_OPhigh, 139) + RELOC_NUMBER (R_H8_OPlow, 140) + RELOC_NUMBER (R_H8_OPscttop, 141) +END_RELOC_NUMBERS (R_H8_max) + +/* Machine variant if we know it. This field was invented at Cygnus, + but it is hoped that other vendors will adopt it. If some standard + is developed, this code should be changed to follow it. */ + +#define EF_H8_MACH 0x00FF0000 + +#define E_H8_MACH_H8300 0x00800000 +#define E_H8_MACH_H8300H 0x00810000 +#define E_H8_MACH_H8300S 0x00820000 +#define E_H8_MACH_H8300HN 0x00830000 +#define E_H8_MACH_H8300SN 0x00840000 +#define E_H8_MACH_H8300SX 0x00850000 +#define E_H8_MACH_H8300SXN 0x00860000 + +#endif diff --git a/include/elf/hppa.h b/include/elf/hppa.h new file mode 100644 index 000000000..45e0b9f0f --- /dev/null +++ b/include/elf/hppa.h @@ -0,0 +1,552 @@ +/* HPPA ELF support for BFD. + Copyright 1993, 1994, 1995, 1998, 1999, 2000 + Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the HPPA ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_HPPA_H +#define _ELF_HPPA_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Trap null address dereferences. */ +#define EF_PARISC_TRAPNIL 0x00010000 + +/* .PARISC.archext section is present. */ +#define EF_PARISC_EXT 0x00020000 + +/* Program expects little-endian mode. */ +#define EF_PARISC_LSB 0x00040000 + +/* Program expects wide mode. */ +#define EF_PARISC_WIDE 0x00080000 + +/* Do not allow kernel-assisted branch prediction. */ +#define EF_PARISC_NO_KABP 0x00100000 + +/* Allow lazy swap for dynamically allocated program segments. */ +#define EF_PARISC_LAZYSWAP 0x00400000 + +/* Architecture version */ +#define EF_PARISC_ARCH 0x0000ffff + +#define EFA_PARISC_1_0 0x020b +#define EFA_PARISC_1_1 0x0210 +#define EFA_PARISC_2_0 0x0214 + +/* Special section indices. */ +/* A symbol that has been declared as a tentative definition in an ANSI C + compilation. */ +#define SHN_PARISC_ANSI_COMMON 0xff00 + +/* A symbol that has been declared as a common block using the + huge memory model. */ +#define SHN_PARISC_HUGE_COMMON 0xff01 + +/* Processor specific section types. */ + +/* Section contains product specific extension bits. */ +#define SHT_PARISC_EXT 0x70000000 + +/* Section contains unwind table entries. */ +#define SHT_PARISC_UNWIND 0x70000001 + +/* Section contains debug information for optimized code. */ +#define SHT_PARISC_DOC 0x70000002 + +/* Section contains code annotations. */ +#define SHT_PARISC_ANNOT 0x70000003 + +/* These are strictly for compatibility with the older elf32-hppa + implementation. Hopefully we can eliminate them in the future. */ +/* Optional section holding argument location/relocation info. */ +#define SHT_PARISC_SYMEXTN SHT_LOPROC+8 + +/* Option section for linker stubs. */ +#define SHT_PARISC_STUBS SHT_LOPROC+9 + +/* Processor specific section flags. */ + +/* Section contains code compiled for static branch prediction. */ +#define SHF_PARISC_SBP 0x80000000 + +/* Section should be allocated from from GP. */ +#define SHF_PARISC_HUGE 0x40000000 + +/* Section should go near GP. */ +#define SHF_PARISC_SHORT 0x20000000 + + +/* Identifies the entry point of a millicode routine. */ +#define STT_PARISC_MILLI 13 + +/* ELF/HPPA relocation types */ + +/* Note: PA-ELF is defined to use only RELA relocations. */ +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_hppa_reloc_type) +RELOC_NUMBER (R_PARISC_NONE, 0) /* No reloc */ + +/* Data / Inst. Format Relocation Expression */ + +RELOC_NUMBER (R_PARISC_DIR32, 1) +/* 32-bit word symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR21L, 2) +/* long immediate (7) LR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR17R, 3) +/* branch external (19) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR17F, 4) +/* branch external (19) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR14R, 6) +/* load/store (1) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR14F, 7) +/* load/store (1) symbol, addend */ + +/* PC-relative relocation types + Typically used for calls. + Note PCREL17C and PCREL17F differ only in overflow handling. + PCREL17C never reports a relocation error. + + When supporting argument relocations, function calls must be + accompanied by parameter relocation information. This information is + carried in the ten high-order bits of the addend field. The remaining + 22 bits of of the addend field are sign-extended to form the Addend. + + Note the code to build argument relocations depends on the + addend being zero. A consequence of this limitation is GAS + can not perform relocation reductions for function symbols. */ + +RELOC_NUMBER (R_PARISC_PCREL12F, 8) +/* op & branch (17) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL32, 9) +/* 32-bit word symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL21L, 10) +/* long immediate (7) L(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL17R, 11) +/* branch external (19) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL17F, 12) +/* branch (20) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL17C, 13) +/* branch (20) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL14R, 14) +/* load/store (1) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL14F, 15) +/* load/store (1) symbol - PC - 8 + addend */ + + +/* DP-relative relocation types. */ +RELOC_NUMBER (R_PARISC_DPREL21L, 18) +/* long immediate (7) LR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14WR, 19) +/* load/store mod. comp. (2) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14DR, 20) +/* load/store doubleword (3) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14R, 22) +/* load/store (1) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14F, 23) +/* load/store (1) symbol - GP + addend */ + + +/* Data linkage table (DLT) relocation types + + SOM DLT_REL fixup requests are used to for static data references + from position-independent code within shared libraries. They are + similar to the GOT relocation types in some SVR4 implementations. */ + +RELOC_NUMBER (R_PARISC_DLTREL21L, 26) +/* long immediate (7) LR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14R, 30) +/* load/store (1) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14F, 31) +/* load/store (1) symbol - GP + addend */ + + +/* DLT indirect relocation types */ +RELOC_NUMBER (R_PARISC_DLTIND21L, 34) +/* long immediate (7) L(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14R, 38) +/* load/store (1) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14F, 39) +/* load/store (1) ltoff(symbol + addend) */ + + +/* Base relative relocation types. Ugh. These imply lots of state */ +RELOC_NUMBER (R_PARISC_SETBASE, 40) +/* none no reloc; base := sym */ + +RELOC_NUMBER (R_PARISC_SECREL32, 41) +/* 32-bit word symbol - SECT + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL21L, 42) +/* long immediate (7) LR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL17R, 43) +/* branch external (19) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL17F, 44) +/* branch external (19) symbol - base + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL14R, 46) +/* load/store (1) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL14F, 47) +/* load/store (1) symbol - base, addend */ + + +/* Segment relative relocation types. */ +RELOC_NUMBER (R_PARISC_SEGBASE, 48) +/* none no relocation; SB := sym */ + +RELOC_NUMBER (R_PARISC_SEGREL32, 49) +/* 32-bit word symbol - SB + addend */ + + +/* Offsets from the PLT. */ +RELOC_NUMBER (R_PARISC_PLTOFF21L, 50) +/* long immediate (7) LR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14R, 54) +/* load/store (1) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14F, 55) +/* load/store (1) pltoff(symbol) + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR32, 57) +/* 32-bit word ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR21L, 58) +/* long immediate (7) L(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14R, 62) +/* load/store (1) R(ltoff(fptr(symbol+addend))) */ + + +RELOC_NUMBER (R_PARISC_FPTR64, 64) +/* 64-bit doubleword fptr(symbol+addend) */ + + +/* Plabel relocation types. */ +RELOC_NUMBER (R_PARISC_PLABEL32, 65) +/* 32-bit word fptr(symbol) */ + +RELOC_NUMBER (R_PARISC_PLABEL21L, 66) +/* long immediate (7) L(fptr(symbol)) */ + +RELOC_NUMBER (R_PARISC_PLABEL14R, 70) +/* load/store (1) R(fptr(symbol)) */ + + +/* PCREL relocations. */ +RELOC_NUMBER (R_PARISC_PCREL64, 72) +/* 64-bit doubleword symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL22C, 73) +/* branch & link (21) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL22F, 74) +/* branch & link (21) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL14WR, 75) +/* load/store mod. comp. (2) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL14DR, 76) +/* load/store doubleword (3) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL16F, 77) +/* load/store (1) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL16WF, 78) +/* load/store mod. comp. (2) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL16DF, 79) +/* load/store doubleword (3) symbol - PC - 8 + addend */ + + +RELOC_NUMBER (R_PARISC_DIR64, 80) +/* 64-bit doubleword symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR64WR, 81) +/* 64-bit doubleword RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR64DR, 82) +/* 64-bit doubleword RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR14WR, 83) +/* load/store mod. comp. (2) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR14DR, 84) +/* load/store doubleword (3) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR16F, 85) +/* load/store (1) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR16WF, 86) +/* load/store mod. comp. (2) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR16DF, 87) +/* load/store doubleword (3) symbol + addend */ + +RELOC_NUMBER (R_PARISC_GPREL64, 88) +/* 64-bit doubleword symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_DLTREL14WR, 91) +/* load/store mod. comp. (2) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14DR, 92) +/* load/store doubleword (3) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_GPREL16F, 93) +/* load/store (1) symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_GPREL16WF, 94) +/* load/store mod. comp. (2) symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_GPREL16DF, 95) +/* load/store doubleword (3) symbol - GP + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF64, 96) +/* 64-bit doubleword ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_DLTIND14WR, 99) +/* load/store mod. comp. (2) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14DR, 100) +/* load/store doubleword (3) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF16F, 101) +/* load/store (1) ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF16WF, 102) +/* load/store mod. comp. (2) ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF16DF, 103) +/* load/store doubleword (3) ltoff(symbol + addend) */ + + +RELOC_NUMBER (R_PARISC_SECREL64, 104) +/* 64-bit doubleword symbol - SECT + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL14WR, 107) +/* load/store mod. comp. (2) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL14DR, 108) +/* load/store doubleword (3) RR(symbol - base, addend) */ + + +RELOC_NUMBER (R_PARISC_SEGREL64, 112) +/* 64-bit doubleword symbol - SB + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF14WR, 115) +/* load/store mod. comp. (2) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14DR, 116) +/* load/store doubleword (3) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF16F, 117) +/* load/store (1) pltoff(symbol) + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF16WF, 118) +/* load/store mod. comp. (2) pltoff(symbol) + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF16DF, 119) +/* load/store doubleword (3) pltoff(symbol) + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR64, 120) +/* 64-bit doubleword ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14WR, 123) +/* load/store mod. comp. (2) R(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14DR, 124) +/* load/store doubleword (3) R(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16F, 125) +/* load/store (1) ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16WF, 126) +/* load/store mod. comp. (2) ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16DF, 127) +/* load/store doubleword (3) ltoff(fptr(symbol+addend)) */ + + +RELOC_NUMBER (R_PARISC_COPY, 128) +/* data Dynamic relocations only */ + +RELOC_NUMBER (R_PARISC_IPLT, 129) +/* plt */ + +RELOC_NUMBER (R_PARISC_EPLT, 130) +/* plt */ + + +RELOC_NUMBER (R_PARISC_TPREL32, 153) +/* 32-bit word symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL21L, 154) +/* long immediate (7) LR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL14R, 158) +/* load/store (1) RR(symbol - TP, addend) */ + + +RELOC_NUMBER (R_PARISC_LTOFF_TP21L, 162) +/* long immediate (7) L(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14R, 166) +/* load/store (1) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14F, 167) +/* load/store (1) ltoff(symbol - TP + addend) */ + + +RELOC_NUMBER (R_PARISC_TPREL64, 216) +/* 64-bit word symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL14WR, 219) +/* load/store mod. comp. (2) RR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL14DR, 220) +/* load/store doubleword (3) RR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL16F, 221) +/* load/store (1) symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL16WF, 222) +/* load/store mod. comp. (2) symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL16DF, 223) +/* load/store doubleword (3) symbol - TP + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_TP64, 224) +/* 64-bit doubleword ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14WR, 227) +/* load/store mod. comp. (2) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14DR, 228) +/* load/store doubleword (3) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16F, 229) +/* load/store (1) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16WF, 230) +/* load/store mod. comp. (2) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16DF, 231) +/* load/store doubleword (3) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_GNU_VTENTRY, 232) +RELOC_NUMBER (R_PARISC_GNU_VTINHERIT, 233) + +END_RELOC_NUMBERS (R_PARISC_UNIMPLEMENTED) + +#ifndef RELOC_MACROS_GEN_FUNC +typedef enum elf_hppa_reloc_type elf_hppa_reloc_type; +#endif + +#define PT_PARISC_ARCHEXT 0x70000000 +#define PT_PARISC_UNWIND 0x70000001 +#define PF_PARISC_SBP 0x08000000 +#define PF_HP_PAGE_SIZE 0x00100000 +#define PF_HP_FAR_SHARED 0x00200000 +#define PF_HP_NEAR_SHARED 0x00400000 +#define PF_HP_CODE 0x01000000 +#define PF_HP_MODIFY 0x02000000 +#define PF_HP_LAZYSWAP 0x04000000 +#define PF_HP_SBP 0x08000000 + + +/* Processor specific dynamic array tags. */ + +/* Arggh. HP's tools define these symbols based on the + old value of DT_LOOS. So we must do the same to be + compatible. */ +#define DT_HP_LOAD_MAP (OLD_DT_LOOS + 0x0) +#define DT_HP_DLD_FLAGS (OLD_DT_LOOS + 0x1) +#define DT_HP_DLD_HOOK (OLD_DT_LOOS + 0x2) +#define DT_HP_UX10_INIT (OLD_DT_LOOS + 0x3) +#define DT_HP_UX10_INITSZ (OLD_DT_LOOS + 0x4) +#define DT_HP_PREINIT (OLD_DT_LOOS + 0x5) +#define DT_HP_PREINITSZ (OLD_DT_LOOS + 0x6) +#define DT_HP_NEEDED (OLD_DT_LOOS + 0x7) +#define DT_HP_TIME_STAMP (OLD_DT_LOOS + 0x8) +#define DT_HP_CHECKSUM (OLD_DT_LOOS + 0x9) +#define DT_HP_GST_SIZE (OLD_DT_LOOS + 0xa) +#define DT_HP_GST_VERSION (OLD_DT_LOOS + 0xb) +#define DT_HP_GST_HASHVAL (OLD_DT_LOOS + 0xc) + +/* Values for DT_HP_DLD_FLAGS. */ +#define DT_HP_DEBUG_PRIVATE 0x0001 /* Map text private */ +#define DT_HP_DEBUG_CALLBACK 0x0002 /* Callback */ +#define DT_HP_DEBUG_CALLBACK_BOR 0x0004 /* BOR callback */ +#define DT_HP_NO_ENVVAR 0x0008 /* No env var */ +#define DT_HP_BIND_NOW 0x0010 /* Bind now */ +#define DT_HP_BIND_NONFATAL 0x0020 /* Bind non-fatal */ +#define DT_HP_BIND_VERBOSE 0x0040 /* Bind verbose */ +#define DT_HP_BIND_RESTRICTED 0x0080 /* Bind restricted */ +#define DT_HP_BIND_SYMBOLIC 0x0100 /* Bind symbolic */ +#define DT_HP_RPATH_FIRST 0x0200 /* RPATH first */ +#define DT_HP_BIND_DEPTH_FIRST 0x0400 /* Bind depth-first */ + +/* Program header extensions. */ +#define PT_HP_TLS (PT_LOOS + 0x0) +#define PT_HP_CORE_NONE (PT_LOOS + 0x1) +#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) +#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) +#define PT_HP_CORE_COMM (PT_LOOS + 0x4) +#define PT_HP_CORE_PROC (PT_LOOS + 0x5) +#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) +#define PT_HP_CORE_STACK (PT_LOOS + 0x7) +#define PT_HP_CORE_SHM (PT_LOOS + 0x8) +#define PT_HP_CORE_MMF (PT_LOOS + 0x9) +#define PT_HP_PARALLEL (PT_LOOS + 0x10) +#define PT_HP_FASTBIND (PT_LOOS + 0x11) + +/* Additional symbol types. */ +#define STT_HP_OPAQUE (STT_LOOS + 0x1) +#define STT_HP_STUB (STT_LOOS + 0x2) + +#endif /* _ELF_HPPA_H */ diff --git a/include/elf/i370.h b/include/elf/i370.h new file mode 100644 index 000000000..fd5ec4739 --- /dev/null +++ b/include/elf/i370.h @@ -0,0 +1,68 @@ +/* i370 ELF support for BFD. + Copyright 2000, 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the i370 ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_I370_H +#define _ELF_I370_H + +#include "elf/reloc-macros.h" + +/* Processor specific section headers, sh_type field */ + +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +#define EF_I370_RELOCATABLE 0x00010000 /* i370 -mrelocatable flag */ +#define EF_I370_RELOCATABLE_LIB 0x00008000 /* i370 -mrelocatable-lib flag */ +/* Processor specific section flags, sh_flags field */ + +#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \ + this section from executable \ + and shared objects that it \ + builds when those objects \ + are not to be furhter \ + relocated. */ + +/* i370 relocations + Note that there is really just one relocation that we currently + support (and only one that we seem to need, at the moment), and + that is the 31-bit address relocation. Note that the 370/390 + only supports a 31-bit (2GB) address space. */ + +START_RELOC_NUMBERS (i370_reloc_type) + RELOC_NUMBER (R_I370_NONE, 0) + RELOC_NUMBER (R_I370_ADDR31, 1) + RELOC_NUMBER (R_I370_ADDR32, 2) + RELOC_NUMBER (R_I370_ADDR16, 3) + RELOC_NUMBER (R_I370_REL31, 4) + RELOC_NUMBER (R_I370_REL32, 5) + RELOC_NUMBER (R_I370_ADDR12, 6) + RELOC_NUMBER (R_I370_REL12, 7) + RELOC_NUMBER (R_I370_ADDR8, 8) + RELOC_NUMBER (R_I370_REL8, 9) + RELOC_NUMBER (R_I370_COPY, 10) + RELOC_NUMBER (R_I370_RELATIVE, 11) +END_RELOC_NUMBERS (R_I370_max) + +#endif /* _ELF_I370_H */ diff --git a/include/elf/i386.h b/include/elf/i386.h new file mode 100644 index 000000000..bd54e8ead --- /dev/null +++ b/include/elf/i386.h @@ -0,0 +1,73 @@ +/* ix86 ELF support for BFD. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_I386_H +#define _ELF_I386_H + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_i386_reloc_type) + RELOC_NUMBER (R_386_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_386_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_386_PC32, 2) /* PC relative 32 bit */ + RELOC_NUMBER (R_386_GOT32, 3) /* 32 bit GOT entry */ + RELOC_NUMBER (R_386_PLT32, 4) /* 32 bit PLT address */ + RELOC_NUMBER (R_386_COPY, 5) /* Copy symbol at runtime */ + RELOC_NUMBER (R_386_GLOB_DAT, 6) /* Create GOT entry */ + RELOC_NUMBER (R_386_JUMP_SLOT, 7) /* Create PLT entry */ + RELOC_NUMBER (R_386_RELATIVE, 8) /* Adjust by program base */ + RELOC_NUMBER (R_386_GOTOFF, 9) /* 32 bit offset to GOT */ + RELOC_NUMBER (R_386_GOTPC, 10) /* 32 bit PC relative offset to GOT */ + RELOC_NUMBER (R_386_32PLT, 11) /* Used by Sun */ + FAKE_RELOC (FIRST_INVALID_RELOC, 12) + FAKE_RELOC (LAST_INVALID_RELOC, 13) + RELOC_NUMBER (R_386_TLS_TPOFF,14) + RELOC_NUMBER (R_386_TLS_IE, 15) + RELOC_NUMBER (R_386_TLS_GOTIE,16) + RELOC_NUMBER (R_386_TLS_LE, 17) + RELOC_NUMBER (R_386_TLS_GD, 18) + RELOC_NUMBER (R_386_TLS_LDM, 19) + RELOC_NUMBER (R_386_16, 20) + RELOC_NUMBER (R_386_PC16, 21) + RELOC_NUMBER (R_386_8, 22) + RELOC_NUMBER (R_386_PC8, 23) + RELOC_NUMBER (R_386_TLS_GD_32, 24) + RELOC_NUMBER (R_386_TLS_GD_PUSH, 25) + RELOC_NUMBER (R_386_TLS_GD_CALL, 26) + RELOC_NUMBER (R_386_TLS_GD_POP, 27) + RELOC_NUMBER (R_386_TLS_LDM_32, 28) + RELOC_NUMBER (R_386_TLS_LDM_PUSH, 29) + RELOC_NUMBER (R_386_TLS_LDM_CALL, 30) + RELOC_NUMBER (R_386_TLS_LDM_POP, 31) + RELOC_NUMBER (R_386_TLS_LDO_32, 32) + RELOC_NUMBER (R_386_TLS_IE_32, 33) + RELOC_NUMBER (R_386_TLS_LE_32, 34) + RELOC_NUMBER (R_386_TLS_DTPMOD32, 35) + RELOC_NUMBER (R_386_TLS_DTPOFF32, 36) + RELOC_NUMBER (R_386_TLS_TPOFF32, 37) + + /* Used by Intel. */ + RELOC_NUMBER (R_386_USED_BY_INTEL_200, 200) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_386_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_386_GNU_VTENTRY, 251) +END_RELOC_NUMBERS (R_386_max) + +#endif diff --git a/include/elf/i860.h b/include/elf/i860.h new file mode 100644 index 000000000..de34aeb01 --- /dev/null +++ b/include/elf/i860.h @@ -0,0 +1,66 @@ +/* i860 ELF support for BFD. + Copyright 2000 Free Software Foundation, Inc. + + Contributed by Jason Eckhardt <jle@cygnus.com>. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_I860_H +#define _ELF_I860_H + +/* Note: i860 ELF is defined to use only RELA relocations. */ + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_i860_reloc_type) + RELOC_NUMBER (R_860_NONE, 0x00) /* No reloc */ + RELOC_NUMBER (R_860_32, 0x01) /* S+A */ + RELOC_NUMBER (R_860_COPY, 0x02) /* No calculation */ + RELOC_NUMBER (R_860_GLOB_DAT, 0x03) /* S, Create GOT entry */ + RELOC_NUMBER (R_860_JUMP_SLOT, 0x04) /* S+A, Create PLT entry */ + RELOC_NUMBER (R_860_RELATIVE, 0x05) /* B+A, Adj by program base */ + RELOC_NUMBER (R_860_PC26, 0x30) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_PLT26, 0x31) /* (L+A-P) >> 2 */ + RELOC_NUMBER (R_860_PC16, 0x32) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_LOW0, 0x40) /* S+A */ + RELOC_NUMBER (R_860_SPLIT0, 0x42) /* S+A */ + RELOC_NUMBER (R_860_LOW1, 0x44) /* S+A */ + RELOC_NUMBER (R_860_SPLIT1, 0x46) /* S+A */ + RELOC_NUMBER (R_860_LOW2, 0x48) /* S+A */ + RELOC_NUMBER (R_860_SPLIT2, 0x4A) /* S+A */ + RELOC_NUMBER (R_860_LOW3, 0x4C) /* S+A */ + RELOC_NUMBER (R_860_LOGOT0, 0x50) /* G */ + RELOC_NUMBER (R_860_SPGOT0, 0x52) /* G */ + RELOC_NUMBER (R_860_LOGOT1, 0x54) /* G */ + RELOC_NUMBER (R_860_SPGOT1, 0x56) /* G */ + RELOC_NUMBER (R_860_LOGOTOFF0, 0x60) /* O */ + RELOC_NUMBER (R_860_SPGOTOFF0, 0x62) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF1, 0x64) /* O */ + RELOC_NUMBER (R_860_SPGOTOFF1, 0x66) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF2, 0x68) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF3, 0x6C) /* O */ + RELOC_NUMBER (R_860_LOPC, 0x70) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_HIGHADJ, 0x80) /* hiadj(S+A) */ + RELOC_NUMBER (R_860_HAGOT, 0x90) /* hiadj(G) */ + RELOC_NUMBER (R_860_HAGOTOFF, 0xA0) /* hiadj(O) */ + RELOC_NUMBER (R_860_HAPC, 0xB0) /* hiadj((S+A-P) >> 2) */ + RELOC_NUMBER (R_860_HIGH, 0xC0) /* (S+A) >> 16 */ + RELOC_NUMBER (R_860_HIGOT, 0xD0) /* G >> 16 */ + RELOC_NUMBER (R_860_HIGOTOFF, 0xE0) /* O */ +END_RELOC_NUMBERS (R_860_max) + +#endif diff --git a/include/elf/i960.h b/include/elf/i960.h new file mode 100644 index 000000000..253e43852 --- /dev/null +++ b/include/elf/i960.h @@ -0,0 +1,37 @@ +/* Intel 960 ELF support for BFD. + Copyright 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_I960_H +#define _ELF_I960_H + +#include "elf/reloc-macros.h" + + +START_RELOC_NUMBERS (elf_i960_reloc_type) + RELOC_NUMBER (R_960_NONE, 0) + RELOC_NUMBER (R_960_12, 1) + RELOC_NUMBER (R_960_32, 2) + RELOC_NUMBER (R_960_IP24, 3) + RELOC_NUMBER (R_960_SUB, 4) + RELOC_NUMBER (R_960_OPTCALL, 5) + RELOC_NUMBER (R_960_OPTCALLX, 6) + RELOC_NUMBER (R_960_OPTCALLXA, 7) +END_RELOC_NUMBERS (R_960_max) + +#endif /* _ELF_I960_H */ diff --git a/include/elf/ia64.h b/include/elf/ia64.h new file mode 100644 index 000000000..06dfa606d --- /dev/null +++ b/include/elf/ia64.h @@ -0,0 +1,216 @@ +/* IA-64 ELF support for BFD. + Copyright 1998, 1999, 2000, 2003 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_IA64_H +#define _ELF_IA64_H + +/* Bits in the e_flags field of the Elf64_Ehdr: */ + +#define EF_IA_64_MASKOS 0x0000000f /* OS-specific flags. */ +#define EF_IA_64_ARCH 0xff000000 /* Arch. version mask. */ + +/* ??? These four definitions are not part of the SVR4 ABI. + They were present in David's initial code drop, so it is probable + that they are used by HP/UX. */ +#define EF_IA_64_TRAPNIL (1 << 0) /* Trap NIL pointer dereferences. */ +#define EF_IA_64_EXT (1 << 2) /* Program uses arch. extensions. */ +#define EF_IA_64_BE (1 << 3) /* PSR BE bit set (big-endian). */ +#define EFA_IA_64_EAS2_3 0x23000000 /* IA64 EAS 2.3. */ + +#define EF_IA_64_ABI64 (1 << 4) /* 64-bit ABI. */ +/* Not used yet. */ +#define EF_IA_64_REDUCEDFP (1 << 5) /* Only FP6-FP11 used. */ +#define EF_IA_64_CONS_GP (1 << 6) /* gp as program wide constant. */ +#define EF_IA_64_NOFUNCDESC_CONS_GP (1 << 7) /* And no function descriptors. */ +/* Not used yet. */ +#define EF_IA_64_ABSOLUTE (1 << 8) /* Load at absolute addresses. */ + +#define ELF_STRING_ia64_archext ".IA_64.archext" +#define ELF_STRING_ia64_pltoff ".IA_64.pltoff" +#define ELF_STRING_ia64_unwind ".IA_64.unwind" +#define ELF_STRING_ia64_unwind_info ".IA_64.unwind_info" +#define ELF_STRING_ia64_unwind_once ".gnu.linkonce.ia64unw." +#define ELF_STRING_ia64_unwind_info_once ".gnu.linkonce.ia64unwi." +/* .IA_64.unwind_hdr is only used by HP-UX. */ +#define ELF_STRING_ia64_unwind_hdr ".IA_64.unwind_hdr" + +/* Bits in the sh_flags field of Elf64_Shdr: */ + +#define SHF_IA_64_SHORT 0x10000000 /* Section near gp. */ +#define SHF_IA_64_NORECOV 0x20000000 /* Spec insns w/o recovery. */ + +/* Possible values for sh_type in Elf64_Shdr: */ + +#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* Extension bits. */ +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* Unwind bits. */ +#define SHT_IA_64_LOPSREG (SHT_LOPROC + 0x8000000) +/* ABI says (SHT_LOPROC + 0xfffffff) but I think it's a typo -- this makes sense. */ +#define SHT_IA_64_HIPSREG (SHT_LOPROC + 0x8ffffff) +#define SHT_IA_64_PRIORITY_INIT (SHT_LOPROC + 0x9000000) + +/* SHT_IA_64_HP_OPT_ANOT is only generated by HPUX compilers for its + optimization annotation section. GCC does not generate it but we + want readelf to know what they are. Do not use two capital Ns in + annotate or sed will turn it into 32 or 64 during the build. */ +#define SHT_IA_64_HP_OPT_ANOT 0x60000004 + +/* Bits in the p_flags field of Elf64_Phdr: */ + +#define PF_IA_64_NORECOV 0x80000000 + +/* Possible values for p_type in Elf64_Phdr: */ + +#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* Arch extension bits, */ +#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* IA64 unwind bits. */ + +/* HP-UX specific values for p_type in Elf64_Phdr. + These values are currently just used to make + readelf more usable on HP-UX. */ + +#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) +#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) +#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) + +/* Possible values for d_tag in Elf64_Dyn: */ + +#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) + +/* This section only used by HP-UX, The HP linker gives weak symbols + precedence over regular common symbols. We want common to override + weak. Using this common instead of SHN_COMMON does that. */ +#define SHN_IA_64_ANSI_COMMON 0xFF00 + +/* IA64-specific relocation types: */ + +/* Relocs apply to specific instructions within a bundle. The least + significant 2 bits of the address indicate which instruction in the + bundle the reloc refers to (0=first slot, 1=second slow, 2=third + slot, 3=undefined) and the remaining bits give the address of the + bundle (16 byte aligned). + + The top 5 bits of the reloc code specifies the expression type, the + low 3 bits the format of the data word being relocated. */ + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_ia64_reloc_type) + RELOC_NUMBER (R_IA64_NONE, 0x00) /* none */ + + RELOC_NUMBER (R_IA64_IMM14, 0x21) /* symbol + addend, add imm14 */ + RELOC_NUMBER (R_IA64_IMM22, 0x22) /* symbol + addend, add imm22 */ + RELOC_NUMBER (R_IA64_IMM64, 0x23) /* symbol + addend, mov imm64 */ + RELOC_NUMBER (R_IA64_DIR32MSB, 0x24) /* symbol + addend, data4 MSB */ + RELOC_NUMBER (R_IA64_DIR32LSB, 0x25) /* symbol + addend, data4 LSB */ + RELOC_NUMBER (R_IA64_DIR64MSB, 0x26) /* symbol + addend, data8 MSB */ + RELOC_NUMBER (R_IA64_DIR64LSB, 0x27) /* symbol + addend, data8 LSB */ + + RELOC_NUMBER (R_IA64_GPREL22, 0x2a) /* @gprel(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_GPREL64I, 0x2b) /* @gprel(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF22, 0x32) /* @ltoff(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_LTOFF64I, 0x33) /* @ltoff(sym+add), mov imm64 */ + + RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a) /* @pltoff(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b) /* @pltoff(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_FPTR64I, 0x43) /* @fptr(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44) /* @fptr(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45) /* @fptr(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46) /* @fptr(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47) /* @fptr(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_PCREL60B, 0x48) /* @pcrel(sym+add), brl */ + RELOC_NUMBER (R_IA64_PCREL21B, 0x49) /* @pcrel(sym+add), ptb, call */ + RELOC_NUMBER (R_IA64_PCREL21M, 0x4a) /* @pcrel(sym+add), chk.s */ + RELOC_NUMBER (R_IA64_PCREL21F, 0x4b) /* @pcrel(sym+add), fchkf */ + RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR32MSB, 0x54) /* @ltoff(@fptr(s+a)), 4 MSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR32LSB, 0x55) /* @ltoff(@fptr(s+a)), 4 LSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB */ + + RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_REL32MSB, 0x6c) /* data 4 + REL */ + RELOC_NUMBER (R_IA64_REL32LSB, 0x6d) /* data 4 + REL */ + RELOC_NUMBER (R_IA64_REL64MSB, 0x6e) /* data 8 + REL */ + RELOC_NUMBER (R_IA64_REL64LSB, 0x6f) /* data 8 + REL */ + + RELOC_NUMBER (R_IA64_LTV32MSB, 0x74) /* symbol + addend, data4 MSB */ + RELOC_NUMBER (R_IA64_LTV32LSB, 0x75) /* symbol + addend, data4 LSB */ + RELOC_NUMBER (R_IA64_LTV64MSB, 0x76) /* symbol + addend, data8 MSB */ + RELOC_NUMBER (R_IA64_LTV64LSB, 0x77) /* symbol + addend, data8 LSB */ + + RELOC_NUMBER (R_IA64_PCREL21BI, 0x79) /* @pcrel(sym+add), ptb, call */ + RELOC_NUMBER (R_IA64_PCREL22, 0x7a) /* @pcrel(sym+add), imm22 */ + RELOC_NUMBER (R_IA64_PCREL64I, 0x7b) /* @pcrel(sym+add), imm64 */ + + RELOC_NUMBER (R_IA64_IPLTMSB, 0x80) /* dynamic reloc, imported PLT, MSB */ + RELOC_NUMBER (R_IA64_IPLTLSB, 0x81) /* dynamic reloc, imported PLT, LSB */ + RELOC_NUMBER (R_IA64_COPY, 0x84) /* dynamic reloc, data copy */ + RELOC_NUMBER (R_IA64_LTOFF22X, 0x86) /* LTOFF22, relaxable. */ + RELOC_NUMBER (R_IA64_LDXMOV, 0x87) /* Use of LTOFF22X. */ + + RELOC_NUMBER (R_IA64_TPREL14, 0x91) /* @tprel(sym+add), add imm14 */ + RELOC_NUMBER (R_IA64_TPREL22, 0x92) /* @tprel(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_TPREL64I, 0x93) /* @tprel(sym+add), add imm64 */ + RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* @tprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* @tprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_TPREL22, 0x9a) /* @ltoff(@tprel(s+a)), add imm22 */ + + RELOC_NUMBER (R_IA64_DTPMOD64MSB, 0xa6) /* @dtpmod(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_DTPMOD64LSB, 0xa7) /* @dtpmod(sym+add), data8 LSB */ + RELOC_NUMBER (R_IA64_LTOFF_DTPMOD22, 0xaa) /* @ltoff(@dtpmod(s+a)), imm22 */ + + RELOC_NUMBER (R_IA64_DTPREL14, 0xb1) /* @dtprel(sym+add), imm14 */ + RELOC_NUMBER (R_IA64_DTPREL22, 0xb2) /* @dtprel(sym+add), imm22 */ + RELOC_NUMBER (R_IA64_DTPREL64I, 0xb3) /* @dtprel(sym+add), imm64 */ + RELOC_NUMBER (R_IA64_DTPREL32MSB, 0xb4) /* @dtprel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_DTPREL32LSB, 0xb5) /* @dtprel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_DTPREL64MSB, 0xb6) /* @dtprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_DTPREL64LSB, 0xb7) /* @dtprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_DTPREL22, 0xba) /* @ltoff(@dtprel(s+a)), imm22 */ + + FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0xba) +END_RELOC_NUMBERS (R_IA64_max) + +#endif /* _ELF_IA64_H */ diff --git a/include/elf/internal.h b/include/elf/internal.h new file mode 100644 index 000000000..a7299d905 --- /dev/null +++ b/include/elf/internal.h @@ -0,0 +1,254 @@ +/* ELF support for BFD. + Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002 + Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support, from information published + in "UNIX System V Release 4, Programmers Guide: ANSI C and + Programming Support Tools". + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of ELF support for BFD, and contains the portions + that describe how ELF is represented internally in the BFD library. + I.E. it describes the in-memory representation of ELF. It requires + the elf-common.h file which contains the portions that are common to + both the internal and external representations. */ + + +/* NOTE that these structures are not kept in the same order as they appear + in the object file. In some cases they've been reordered for more optimal + packing under various circumstances. */ + +#ifndef _ELF_INTERNAL_H +#define _ELF_INTERNAL_H + +/* ELF Header */ + +#define EI_NIDENT 16 /* Size of e_ident[] */ + +typedef struct elf_internal_ehdr { + unsigned char e_ident[EI_NIDENT]; /* ELF "magic number" */ + bfd_vma e_entry; /* Entry point virtual address */ + bfd_size_type e_phoff; /* Program header table file offset */ + bfd_size_type e_shoff; /* Section header table file offset */ + unsigned long e_version; /* Identifies object file version */ + unsigned long e_flags; /* Processor-specific flags */ + unsigned short e_type; /* Identifies object file type */ + unsigned short e_machine; /* Specifies required architecture */ + unsigned int e_ehsize; /* ELF header size in bytes */ + unsigned int e_phentsize; /* Program header table entry size */ + unsigned int e_phnum; /* Program header table entry count */ + unsigned int e_shentsize; /* Section header table entry size */ + unsigned int e_shnum; /* Section header table entry count */ + unsigned int e_shstrndx; /* Section header string table index */ +} Elf_Internal_Ehdr; + +/* Program header */ + +struct elf_internal_phdr { + unsigned long p_type; /* Identifies program segment type */ + unsigned long p_flags; /* Segment flags */ + bfd_vma p_offset; /* Segment file offset */ + bfd_vma p_vaddr; /* Segment virtual address */ + bfd_vma p_paddr; /* Segment physical address */ + bfd_vma p_filesz; /* Segment size in file */ + bfd_vma p_memsz; /* Segment size in memory */ + bfd_vma p_align; /* Segment alignment, file & memory */ +}; + +typedef struct elf_internal_phdr Elf_Internal_Phdr; + +/* Section header */ + +typedef struct elf_internal_shdr { + unsigned int sh_name; /* Section name, index in string tbl */ + unsigned int sh_type; /* Type of section */ + bfd_vma sh_flags; /* Miscellaneous section attributes */ + bfd_vma sh_addr; /* Section virtual addr at execution */ + bfd_size_type sh_size; /* Size of section in bytes */ + bfd_size_type sh_entsize; /* Entry size if section holds table */ + unsigned long sh_link; /* Index of another section */ + unsigned long sh_info; /* Additional section information */ + file_ptr sh_offset; /* Section file offset */ + unsigned int sh_addralign; /* Section alignment */ + + /* The internal rep also has some cached info associated with it. */ + asection * bfd_section; /* Associated BFD section. */ + unsigned char *contents; /* Section contents. */ +} Elf_Internal_Shdr; + +/* Symbol table entry */ + +struct elf_internal_sym { + bfd_vma st_value; /* Value of the symbol */ + bfd_vma st_size; /* Associated symbol size */ + unsigned long st_name; /* Symbol name, index in string tbl */ + unsigned char st_info; /* Type and binding attributes */ + unsigned char st_other; /* Visibilty, and target specific */ + unsigned int st_shndx; /* Associated section index */ +}; + +typedef struct elf_internal_sym Elf_Internal_Sym; + +/* Note segments */ + +typedef struct elf_internal_note { + unsigned long namesz; /* Size of entry's owner string */ + unsigned long descsz; /* Size of the note descriptor */ + unsigned long type; /* Interpretation of the descriptor */ + char * namedata; /* Start of the name+desc data */ + char * descdata; /* Start of the desc data */ + bfd_vma descpos; /* File offset of the descdata */ +} Elf_Internal_Note; + +/* Relocation Entries */ + +typedef struct elf_internal_rela { + bfd_vma r_offset; /* Location at which to apply the action */ + bfd_vma r_info; /* Index and Type of relocation */ + bfd_vma r_addend; /* Constant addend used to compute value */ +} Elf_Internal_Rela; + +/* dynamic section structure */ + +typedef struct elf_internal_dyn { + /* This needs to support 64-bit values in elf64. */ + bfd_vma d_tag; /* entry tag value */ + union { + /* This needs to support 64-bit values in elf64. */ + bfd_vma d_val; + bfd_vma d_ptr; + } d_un; +} Elf_Internal_Dyn; + +/* This structure appears in a SHT_GNU_verdef section. */ + +typedef struct elf_internal_verdef { + unsigned short vd_version; /* Version number of structure. */ + unsigned short vd_flags; /* Flags (VER_FLG_*). */ + unsigned short vd_ndx; /* Version index. */ + unsigned short vd_cnt; /* Number of verdaux entries. */ + unsigned long vd_hash; /* Hash of name. */ + unsigned long vd_aux; /* Offset to verdaux entries. */ + unsigned long vd_next; /* Offset to next verdef. */ + + /* These fields are set up when BFD reads in the structure. FIXME: + It would be cleaner to store these in a different structure. */ + bfd *vd_bfd; /* BFD. */ + const char *vd_nodename; /* Version name. */ + struct elf_internal_verdef *vd_nextdef; /* vd_next as pointer. */ + struct elf_internal_verdaux *vd_auxptr; /* vd_aux as pointer. */ + unsigned int vd_exp_refno; /* Used by the linker. */ +} Elf_Internal_Verdef; + +/* This structure appears in a SHT_GNU_verdef section. */ + +typedef struct elf_internal_verdaux { + unsigned long vda_name; /* String table offset of name. */ + unsigned long vda_next; /* Offset to next verdaux. */ + + /* These fields are set up when BFD reads in the structure. FIXME: + It would be cleaner to store these in a different structure. */ + const char *vda_nodename; /* vda_name as pointer. */ + struct elf_internal_verdaux *vda_nextptr; /* vda_next as pointer. */ +} Elf_Internal_Verdaux; + +/* This structure appears in a SHT_GNU_verneed section. */ + +typedef struct elf_internal_verneed { + unsigned short vn_version; /* Version number of structure. */ + unsigned short vn_cnt; /* Number of vernaux entries. */ + unsigned long vn_file; /* String table offset of library name. */ + unsigned long vn_aux; /* Offset to vernaux entries. */ + unsigned long vn_next; /* Offset to next verneed. */ + + /* These fields are set up when BFD reads in the structure. FIXME: + It would be cleaner to store these in a different structure. */ + bfd *vn_bfd; /* BFD. */ + const char *vn_filename; /* vn_file as pointer. */ + struct elf_internal_vernaux *vn_auxptr; /* vn_aux as pointer. */ + struct elf_internal_verneed *vn_nextref; /* vn_nextref as pointer. */ +} Elf_Internal_Verneed; + +/* This structure appears in a SHT_GNU_verneed section. */ + +typedef struct elf_internal_vernaux { + unsigned long vna_hash; /* Hash of dependency name. */ + unsigned short vna_flags; /* Flags (VER_FLG_*). */ + unsigned short vna_other; /* Unused. */ + unsigned long vna_name; /* String table offset to version name. */ + unsigned long vna_next; /* Offset to next vernaux. */ + + /* These fields are set up when BFD reads in the structure. FIXME: + It would be cleaner to store these in a different structure. */ + const char *vna_nodename; /* vna_name as pointer. */ + struct elf_internal_vernaux *vna_nextptr; /* vna_next as pointer. */ +} Elf_Internal_Vernaux; + +/* This structure appears in a SHT_GNU_versym section. This is not a + standard ELF structure; ELF just uses Elf32_Half. */ + +typedef struct elf_internal_versym { + unsigned short vs_vers; +} Elf_Internal_Versym; + +/* Structure for syminfo section. */ +typedef struct +{ + unsigned short int si_boundto; + unsigned short int si_flags; +} Elf_Internal_Syminfo; + +/* This structure appears on the stack and in NT_AUXV core file notes. */ +typedef struct +{ + bfd_vma a_type; + bfd_vma a_val; +} Elf_Internal_Auxv; + + +/* This structure is used to describe how sections should be assigned + to program segments. */ + +struct elf_segment_map +{ + /* Next program segment. */ + struct elf_segment_map *next; + /* Program segment type. */ + unsigned long p_type; + /* Program segment flags. */ + unsigned long p_flags; + /* Program segment physical address. */ + bfd_vma p_paddr; + /* Whether the p_flags field is valid; if not, the flags are based + on the section flags. */ + unsigned int p_flags_valid : 1; + /* Whether the p_paddr field is valid; if not, the physical address + is based on the section lma values. */ + unsigned int p_paddr_valid : 1; + /* Whether this segment includes the file header. */ + unsigned int includes_filehdr : 1; + /* Whether this segment includes the program headers. */ + unsigned int includes_phdrs : 1; + /* Number of sections (may be 0). */ + unsigned int count; + /* Sections. Actual number of elements is in count field. */ + asection *sections[1]; +}; + +#endif /* _ELF_INTERNAL_H */ diff --git a/include/elf/ip2k.h b/include/elf/ip2k.h new file mode 100644 index 000000000..c331b720f --- /dev/null +++ b/include/elf/ip2k.h @@ -0,0 +1,62 @@ +/* IP2xxx ELF support for BFD. + Copyright (C) 2000, 2002 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_IP2K_H +#define _ELF_IP2K_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_ip2k_reloc_type) + RELOC_NUMBER (R_IP2K_NONE, 0) + RELOC_NUMBER (R_IP2K_16, 1) + RELOC_NUMBER (R_IP2K_32, 2) + RELOC_NUMBER (R_IP2K_FR9, 3) + RELOC_NUMBER (R_IP2K_BANK, 4) + RELOC_NUMBER (R_IP2K_ADDR16CJP, 5) + RELOC_NUMBER (R_IP2K_PAGE3, 6) + RELOC_NUMBER (R_IP2K_LO8DATA, 7) + RELOC_NUMBER (R_IP2K_HI8DATA, 8) + RELOC_NUMBER (R_IP2K_LO8INSN, 9) + RELOC_NUMBER (R_IP2K_HI8INSN, 10) + RELOC_NUMBER (R_IP2K_PC_SKIP, 11) + RELOC_NUMBER (R_IP2K_TEXT, 12) + RELOC_NUMBER (R_IP2K_FR_OFFSET, 13) + RELOC_NUMBER (R_IP2K_EX8DATA, 14) +END_RELOC_NUMBERS(R_IP2K_max) + + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & IP2K_INSN_MASK) == IP2K_INSN_VALUE), and similarly + for the data space. See also `ld/emulparams/elf32ip2k.sh'. */ +/* ??? Consider extending the _MASK values to include all the + intermediate bits that must be zero due to the limited physical + memory size on the IP2K. */ + +#define IP2K_DATA_MASK 0xff000000 +#define IP2K_DATA_VALUE 0x01000000 +#define IP2K_INSN_MASK 0xff000000 +#define IP2K_INSN_VALUE 0x02000000 + +/* The location of the memory mapped hardware stack. */ +#define IP2K_STACK_VALUE 0x0f000000 +#define IP2K_STACK_SIZE 0x20 + +#endif /* _ELF_IP2K_H */ diff --git a/include/elf/iq2000.h b/include/elf/iq2000.h new file mode 100644 index 000000000..83c690c70 --- /dev/null +++ b/include/elf/iq2000.h @@ -0,0 +1,58 @@ +/* IQ2000 ELF support for BFD. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_IQ2000_H +#define _ELF_IQ2000_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_iq2000_reloc_type) + RELOC_NUMBER (R_IQ2000_NONE, 0) + RELOC_NUMBER (R_IQ2000_16, 1) + RELOC_NUMBER (R_IQ2000_32, 2) + RELOC_NUMBER (R_IQ2000_26, 3) + RELOC_NUMBER (R_IQ2000_PC16, 4) + RELOC_NUMBER (R_IQ2000_HI16, 5) + RELOC_NUMBER (R_IQ2000_LO16, 6) + RELOC_NUMBER (R_IQ2000_OFFSET_16, 7) + RELOC_NUMBER (R_IQ2000_OFFSET_21, 8) + RELOC_NUMBER (R_IQ2000_UHI16, 9) + RELOC_NUMBER (R_IQ2000_32_DEBUG, 10) + RELOC_NUMBER (R_IQ2000_GNU_VTINHERIT, 200) + RELOC_NUMBER (R_IQ2000_GNU_VTENTRY, 201) +END_RELOC_NUMBERS(R_IQ2000_max) + +#define EF_IQ2000_CPU_IQ2000 0x00000001 /* default */ +#define EF_IQ2000_CPU_IQ10 0x00000002 /* IQ10 */ +#define EF_IQ2000_CPU_MASK 0x00000003 /* specific cpu bits */ +#define EF_IQ2000_ALL_FLAGS (EF_IQ2000_CPU_MASK) + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & IQ2000_INSN_MASK) == IQ2000_INSN_VALUE), and similarly + for the data space. */ + +#define IQ2000_DATA_MASK 0x80000000 +#define IQ2000_DATA_VALUE 0x00000000 +#define IQ2000_INSN_MASK 0x80000000 +#define IQ2000_INSN_VALUE 0x80000000 + + +#endif /* _ELF_IQ2000_H */ diff --git a/include/elf/m32r.h b/include/elf/m32r.h new file mode 100644 index 000000000..6441efe27 --- /dev/null +++ b/include/elf/m32r.h @@ -0,0 +1,119 @@ +/* M32R ELF support for BFD. + Copyright 1996, 1997, 1998, 1999, 2000, 2003, 2004 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_M32R_H +#define _ELF_M32R_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_m32r_reloc_type) + RELOC_NUMBER (R_M32R_NONE, 0) + /* REL relocations */ + RELOC_NUMBER (R_M32R_16, 1) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_32, 2) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_24, 3) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_10_PCREL, 4) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_18_PCREL, 5) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_26_PCREL, 6) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_HI16_ULO, 7) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_HI16_SLO, 8) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_LO16, 9) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_SDA16, 10) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11)/* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12) /* For backwards compatibility. */ + + /* RELA relocations */ + RELOC_NUMBER (R_M32R_16_RELA, 33) + RELOC_NUMBER (R_M32R_32_RELA, 34) + RELOC_NUMBER (R_M32R_24_RELA, 35) + RELOC_NUMBER (R_M32R_10_PCREL_RELA, 36) + RELOC_NUMBER (R_M32R_18_PCREL_RELA, 37) + RELOC_NUMBER (R_M32R_26_PCREL_RELA, 38) + RELOC_NUMBER (R_M32R_HI16_ULO_RELA, 39) + RELOC_NUMBER (R_M32R_HI16_SLO_RELA, 40) + RELOC_NUMBER (R_M32R_LO16_RELA, 41) + RELOC_NUMBER (R_M32R_SDA16_RELA, 42) + RELOC_NUMBER (R_M32R_RELA_GNU_VTINHERIT, 43) + RELOC_NUMBER (R_M32R_RELA_GNU_VTENTRY, 44) + + RELOC_NUMBER (R_M32R_GOT24, 48) + RELOC_NUMBER (R_M32R_26_PLTREL, 49) + RELOC_NUMBER (R_M32R_COPY, 50) + RELOC_NUMBER (R_M32R_GLOB_DAT, 51) + RELOC_NUMBER (R_M32R_JMP_SLOT, 52) + RELOC_NUMBER (R_M32R_RELATIVE, 53) + RELOC_NUMBER (R_M32R_GOTOFF, 54) + RELOC_NUMBER (R_M32R_GOTPC24, 55) + RELOC_NUMBER (R_M32R_GOT16_HI_ULO, 56) + RELOC_NUMBER (R_M32R_GOT16_HI_SLO, 57) + RELOC_NUMBER (R_M32R_GOT16_LO, 58) + RELOC_NUMBER (R_M32R_GOTPC_HI_ULO, 59) + RELOC_NUMBER (R_M32R_GOTPC_HI_SLO, 60) + RELOC_NUMBER (R_M32R_GOTPC_LO, 61) + RELOC_NUMBER (R_M32R_GOTOFF_HI_ULO, 62) + RELOC_NUMBER (R_M32R_GOTOFF_HI_SLO, 63) + RELOC_NUMBER (R_M32R_GOTOFF_LO, 64) +END_RELOC_NUMBERS (R_M32R_max) + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Small common symbol. */ +#define SHN_M32R_SCOMMON 0xff00 + +/* Processor specific section flags. */ + +/* This section contains sufficient relocs to be relaxed. + When relaxing, even relocs of branch instructions the assembler could + complete must be present because relaxing may cause the branch target to + move. */ +#define SHF_M32R_CAN_RELAX 0x10000000 + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Two bit m32r architecture field. */ +#define EF_M32R_ARCH 0x30000000 + +/* m32r code. */ +#define E_M32R_ARCH 0x00000000 +/* m32rx code. */ +#define E_M32RX_ARCH 0x10000000 +/* m32r2 code. */ +#define E_M32R2_ARCH 0x20000000 + +/* 12 bit m32r new instructions field. */ +#define EF_M32R_INST 0x0FFF0000 +/* Parallel instructions. */ +#define E_M32R_HAS_PARALLEL 0x00010000 +/* Hidden instructions for m32rx: + jc, jnc, macwhi-a, macwlo-a, mulwhi-a, mulwlo-a, sth+, shb+, sat, pcmpbz, + sc, snc. */ +#define E_M32R_HAS_HIDDEN_INST 0x00020000 +/* New bit instructions: + clrpsw, setpsw, bset, bclr, btst. */ +#define E_M32R_HAS_BIT_INST 0x00040000 +/* Floating point instructions. */ +#define E_M32R_HAS_FLOAT_INST 0x00080000 + +/* 4 bit m32r ignore to check field. */ +#define EF_M32R_IGNORE 0x0000000F + +#endif diff --git a/include/elf/m68hc11.h b/include/elf/m68hc11.h new file mode 100644 index 000000000..1902f7fa6 --- /dev/null +++ b/include/elf/m68hc11.h @@ -0,0 +1,95 @@ +/* m68hc11 & m68hc12 ELF support for BFD. + Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_M68HC11_H +#define _ELF_M68HC11_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_m68hc11_reloc_type) + RELOC_NUMBER (R_M68HC11_NONE, 0) + RELOC_NUMBER (R_M68HC11_8, 1) + RELOC_NUMBER (R_M68HC11_HI8, 2) + RELOC_NUMBER (R_M68HC11_LO8, 3) + RELOC_NUMBER (R_M68HC11_PCREL_8, 4) + RELOC_NUMBER (R_M68HC11_16, 5) + RELOC_NUMBER (R_M68HC11_32, 6) + RELOC_NUMBER (R_M68HC11_3B, 7) + RELOC_NUMBER (R_M68HC11_PCREL_16, 8) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_M68HC11_GNU_VTINHERIT, 9) + RELOC_NUMBER (R_M68HC11_GNU_VTENTRY, 10) + + RELOC_NUMBER (R_M68HC11_24, 11) + RELOC_NUMBER (R_M68HC11_LO16, 12) + RELOC_NUMBER (R_M68HC11_PAGE, 13) + + /* GNU extension for linker relaxation. + Mark beginning of a jump instruction (any form). */ + RELOC_NUMBER (R_M68HC11_RL_JUMP, 20) + + /* Mark beginning of Gcc relaxation group instruction. */ + RELOC_NUMBER (R_M68HC11_RL_GROUP, 21) +END_RELOC_NUMBERS (R_M68HC11_max) + +/* Processor specific flags for the ELF header e_flags field. */ + +/* ABI identification. */ +#define EF_M68HC11_ABI 0x00000000F + +/* Integers are 32-bit long. */ +#define E_M68HC11_I32 0x000000001 + +/* Doubles are 64-bit long. */ +#define E_M68HC11_F64 0x000000002 + +/* Uses 68HC12 memory banks. */ +#define E_M68HC12_BANKS 0x000000004 + +#define EF_M68HC11_MACH_MASK 0xF0 +#define EF_M68HC11_GENERIC 0x00 /* Generic 68HC12/backward compatibility. */ +#define EF_M68HC12_MACH 0x10 /* 68HC12 microcontroller. */ +#define EF_M68HCS12_MACH 0x20 /* 68HCS12 microcontroller. */ +#define EF_M68HC11_MACH(mach) ((mach) & EF_M68HC11_MACH_MASK) + +/* True if we can merge machines. A generic HC12 can work on any proc + but once we have specific code, merge is not possible. */ +#define EF_M68HC11_CAN_MERGE_MACH(mach1, mach2) \ + ((EF_M68HC11_MACH (mach1) == EF_M68HC11_MACH (mach2)) \ + || (EF_M68HC11_MACH (mach1) == EF_M68HC11_GENERIC) \ + || (EF_M68HC11_MACH (mach2) == EF_M68HC11_GENERIC)) + +#define EF_M68HC11_MERGE_MACH(mach1, mach2) \ + (((EF_M68HC11_MACH (mach1) == EF_M68HC11_MACH (mach2)) \ + || (EF_M68HC11_MACH (mach1) == EF_M68HC11_GENERIC)) ? \ + EF_M68HC11_MACH (mach2) : EF_M68HC11_MACH (mach1)) + + +/* Special values for the st_other field in the symbol table. These + are used for 68HC12 to identify far functions (must be called with + 'call' and returns with 'rtc'). */ +#define STO_M68HC12_FAR 0x80 + +/* Identify interrupt handlers. This is used by the debugger to + correctly compute the stack frame. */ +#define STO_M68HC12_INTERRUPT 0x40 + +#endif diff --git a/include/elf/m68k.h b/include/elf/m68k.h new file mode 100644 index 000000000..7769c59eb --- /dev/null +++ b/include/elf/m68k.h @@ -0,0 +1,58 @@ +/* MC68k ELF support for BFD. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_M68K_H +#define _ELF_M68K_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_m68k_reloc_type) + RELOC_NUMBER (R_68K_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_68K_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_68K_16, 2) /* Direct 16 bit */ + RELOC_NUMBER (R_68K_8, 3) /* Direct 8 bit */ + RELOC_NUMBER (R_68K_PC32, 4) /* PC relative 32 bit */ + RELOC_NUMBER (R_68K_PC16, 5) /* PC relative 16 bit */ + RELOC_NUMBER (R_68K_PC8, 6) /* PC relative 8 bit */ + RELOC_NUMBER (R_68K_GOT32, 7) /* 32 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT16, 8) /* 16 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT8, 9) /* 8 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT32O, 10) /* 32 bit GOT offset */ + RELOC_NUMBER (R_68K_GOT16O, 11) /* 16 bit GOT offset */ + RELOC_NUMBER (R_68K_GOT8O, 12) /* 8 bit GOT offset */ + RELOC_NUMBER (R_68K_PLT32, 13) /* 32 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT16, 14) /* 16 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT8, 15) /* 8 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT32O, 16) /* 32 bit PLT offset */ + RELOC_NUMBER (R_68K_PLT16O, 17) /* 16 bit PLT offset */ + RELOC_NUMBER (R_68K_PLT8O, 18) /* 8 bit PLT offset */ + RELOC_NUMBER (R_68K_COPY, 19) /* Copy symbol at runtime */ + RELOC_NUMBER (R_68K_GLOB_DAT, 20) /* Create GOT entry */ + RELOC_NUMBER (R_68K_JMP_SLOT, 21) /* Create PLT entry */ + RELOC_NUMBER (R_68K_RELATIVE, 22) /* Adjust by program base */ + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_68K_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_68K_GNU_VTENTRY, 24) +END_RELOC_NUMBERS (R_68K_max) + +#define EF_CPU32 0x00810000 +#define EF_M68000 0x01000000 + +#endif diff --git a/include/elf/mcore.h b/include/elf/mcore.h new file mode 100644 index 000000000..387a57d45 --- /dev/null +++ b/include/elf/mcore.h @@ -0,0 +1,46 @@ +/* Motorola MCore support for BFD. + Copyright 1995, 1999, 2000 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MCore ELF ABI. */ +#ifndef _ELF_MORE_H +#define _ELF_MORE_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mcore_reloc_type) + RELOC_NUMBER (R_MCORE_NONE, 0) + RELOC_NUMBER (R_MCORE_ADDR32, 1) + RELOC_NUMBER (R_MCORE_PCRELIMM8BY4, 2) + RELOC_NUMBER (R_MCORE_PCRELIMM11BY2, 3) + RELOC_NUMBER (R_MCORE_PCRELIMM4BY2, 4) + RELOC_NUMBER (R_MCORE_PCREL32, 5) + RELOC_NUMBER (R_MCORE_PCRELJSR_IMM11BY2, 6) + RELOC_NUMBER (R_MCORE_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_MCORE_GNU_VTENTRY, 8) + RELOC_NUMBER (R_MCORE_RELATIVE, 9) + RELOC_NUMBER (R_MCORE_COPY, 10) + RELOC_NUMBER (R_MCORE_GLOB_DAT, 11) + RELOC_NUMBER (R_MCORE_JUMP_SLOT, 12) +END_RELOC_NUMBERS (R_MCORE_max) + +/* Section Attributes. */ +#define SHF_MCORE_NOREAD 0x80000000 + +#endif /* _ELF_MCORE_H */ diff --git a/include/elf/mips.h b/include/elf/mips.h new file mode 100644 index 000000000..b7d800a70 --- /dev/null +++ b/include/elf/mips.h @@ -0,0 +1,976 @@ +/* MIPS ELF support for BFD. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + + By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from + information in the System V Application Binary Interface, MIPS + Processor Supplement. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MIPS ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_MIPS_H +#define _ELF_MIPS_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_mips_reloc_type) + RELOC_NUMBER (R_MIPS_NONE, 0) + RELOC_NUMBER (R_MIPS_16, 1) + RELOC_NUMBER (R_MIPS_32, 2) /* In Elf 64: alias R_MIPS_ADD */ + RELOC_NUMBER (R_MIPS_REL32, 3) /* In Elf 64: alias R_MIPS_REL */ + RELOC_NUMBER (R_MIPS_26, 4) + RELOC_NUMBER (R_MIPS_HI16, 5) + RELOC_NUMBER (R_MIPS_LO16, 6) + RELOC_NUMBER (R_MIPS_GPREL16, 7) /* In Elf 64: alias R_MIPS_GPREL */ + RELOC_NUMBER (R_MIPS_LITERAL, 8) + RELOC_NUMBER (R_MIPS_GOT16, 9) /* In Elf 64: alias R_MIPS_GOT */ + RELOC_NUMBER (R_MIPS_PC16, 10) + RELOC_NUMBER (R_MIPS_CALL16, 11) /* In Elf 64: alias R_MIPS_CALL */ + RELOC_NUMBER (R_MIPS_GPREL32, 12) + /* The remaining relocs are defined on Irix, although they are not + in the MIPS ELF ABI. */ + RELOC_NUMBER (R_MIPS_UNUSED1, 13) + RELOC_NUMBER (R_MIPS_UNUSED2, 14) + RELOC_NUMBER (R_MIPS_UNUSED3, 15) + RELOC_NUMBER (R_MIPS_SHIFT5, 16) + RELOC_NUMBER (R_MIPS_SHIFT6, 17) + RELOC_NUMBER (R_MIPS_64, 18) + RELOC_NUMBER (R_MIPS_GOT_DISP, 19) + RELOC_NUMBER (R_MIPS_GOT_PAGE, 20) + RELOC_NUMBER (R_MIPS_GOT_OFST, 21) + RELOC_NUMBER (R_MIPS_GOT_HI16, 22) + RELOC_NUMBER (R_MIPS_GOT_LO16, 23) + RELOC_NUMBER (R_MIPS_SUB, 24) + RELOC_NUMBER (R_MIPS_INSERT_A, 25) + RELOC_NUMBER (R_MIPS_INSERT_B, 26) + RELOC_NUMBER (R_MIPS_DELETE, 27) + RELOC_NUMBER (R_MIPS_HIGHER, 28) + RELOC_NUMBER (R_MIPS_HIGHEST, 29) + RELOC_NUMBER (R_MIPS_CALL_HI16, 30) + RELOC_NUMBER (R_MIPS_CALL_LO16, 31) + RELOC_NUMBER (R_MIPS_SCN_DISP, 32) + RELOC_NUMBER (R_MIPS_REL16, 33) + RELOC_NUMBER (R_MIPS_ADD_IMMEDIATE, 34) + RELOC_NUMBER (R_MIPS_PJUMP, 35) + RELOC_NUMBER (R_MIPS_RELGOT, 36) + RELOC_NUMBER (R_MIPS_JALR, 37) + RELOC_NUMBER (R_MIPS_max, 38) + /* These relocs are used for the mips16. */ + RELOC_NUMBER (R_MIPS16_26, 100) + RELOC_NUMBER (R_MIPS16_GPREL, 101) + /* This was a GNU extension used by embedded-PIC. It was co-opted by + mips-linux for exception-handling data. It is no longer used, but + should continue to be supported by the linker for backward + compatibility. (GCC stopped using it in May, 2004.) */ + RELOC_NUMBER (R_MIPS_PC32, 248) + /* FIXME: this relocation is used internally by gas. */ + RELOC_NUMBER (R_MIPS_GNU_REL16_S2, 250) + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_MIPS_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_MIPS_GNU_VTENTRY, 254) +END_RELOC_NUMBERS (R_MIPS_maxext) + +/* Processor specific flags for the ELF header e_flags field. */ + +/* At least one .noreorder directive appears in the source. */ +#define EF_MIPS_NOREORDER 0x00000001 + +/* File contains position independent code. */ +#define EF_MIPS_PIC 0x00000002 + +/* Code in file uses the standard calling sequence for calling + position independent code. */ +#define EF_MIPS_CPIC 0x00000004 + +/* ??? Unknown flag, set in IRIX 6's BSDdup2.o in libbsd.a. */ +#define EF_MIPS_XGOT 0x00000008 + +/* Code in file uses UCODE (obsolete) */ +#define EF_MIPS_UCODE 0x00000010 + +/* Code in file uses new ABI (-n32 on Irix 6). */ +#define EF_MIPS_ABI2 0x00000020 + +/* Process the .MIPS.options section first by ld */ +#define EF_MIPS_OPTIONS_FIRST 0x00000080 + +/* Architectural Extensions used by this file */ +#define EF_MIPS_ARCH_ASE 0x0f000000 + +/* Use MDMX multimedia extensions */ +#define EF_MIPS_ARCH_ASE_MDMX 0x08000000 + +/* Use MIPS-16 ISA extensions */ +#define EF_MIPS_ARCH_ASE_M16 0x04000000 + +/* Indicates code compiled for a 64-bit machine in 32-bit mode. + (regs are 32-bits wide.) */ +#define EF_MIPS_32BITMODE 0x00000100 + +/* Four bit MIPS architecture field. */ +#define EF_MIPS_ARCH 0xf0000000 + +/* -mips1 code. */ +#define E_MIPS_ARCH_1 0x00000000 + +/* -mips2 code. */ +#define E_MIPS_ARCH_2 0x10000000 + +/* -mips3 code. */ +#define E_MIPS_ARCH_3 0x20000000 + +/* -mips4 code. */ +#define E_MIPS_ARCH_4 0x30000000 + +/* -mips5 code. */ +#define E_MIPS_ARCH_5 0x40000000 + +/* -mips32 code. */ +#define E_MIPS_ARCH_32 0x50000000 + +/* -mips64 code. */ +#define E_MIPS_ARCH_64 0x60000000 + +/* -mips32r2 code. */ +#define E_MIPS_ARCH_32R2 0x70000000 + +/* -mips64r2 code. */ +#define E_MIPS_ARCH_64R2 0x80000000 + +/* The ABI of the file. Also see EF_MIPS_ABI2 above. */ +#define EF_MIPS_ABI 0x0000F000 + +/* The original o32 abi. */ +#define E_MIPS_ABI_O32 0x00001000 + +/* O32 extended to work on 64 bit architectures */ +#define E_MIPS_ABI_O64 0x00002000 + +/* EABI in 32 bit mode */ +#define E_MIPS_ABI_EABI32 0x00003000 + +/* EABI in 64 bit mode */ +#define E_MIPS_ABI_EABI64 0x00004000 + + +/* Machine variant if we know it. This field was invented at Cygnus, + but it is hoped that other vendors will adopt it. If some standard + is developed, this code should be changed to follow it. */ + +#define EF_MIPS_MACH 0x00FF0000 + +/* Cygnus is choosing values between 80 and 9F; + 00 - 7F should be left for a future standard; + the rest are open. */ + +#define E_MIPS_MACH_3900 0x00810000 +#define E_MIPS_MACH_4010 0x00820000 +#define E_MIPS_MACH_4100 0x00830000 +#define E_MIPS_MACH_4650 0x00850000 +#define E_MIPS_MACH_4120 0x00870000 +#define E_MIPS_MACH_4111 0x00880000 +#define E_MIPS_MACH_SB1 0x008a0000 +#define E_MIPS_MACH_5400 0x00910000 +#define E_MIPS_MACH_5500 0x00980000 + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Defined and allocated common symbol. Value is virtual address. If + relocated, alignment must be preserved. */ +#define SHN_MIPS_ACOMMON 0xff00 + +/* Defined and allocated text symbol. Value is virtual address. + Occur in the dynamic symbol table of Alpha OSF/1 and Irix 5 executables. */ +#define SHN_MIPS_TEXT 0xff01 + +/* Defined and allocated data symbol. Value is virtual address. + Occur in the dynamic symbol table of Alpha OSF/1 and Irix 5 executables. */ +#define SHN_MIPS_DATA 0xff02 + +/* Small common symbol. */ +#define SHN_MIPS_SCOMMON 0xff03 + +/* Small undefined symbol. */ +#define SHN_MIPS_SUNDEFINED 0xff04 + +/* Processor specific section types. */ + +/* Section contains the set of dynamic shared objects used when + statically linking. */ +#define SHT_MIPS_LIBLIST 0x70000000 + +/* I'm not sure what this is, but it's used on Irix 5. */ +#define SHT_MIPS_MSYM 0x70000001 + +/* Section contains list of symbols whose definitions conflict with + symbols defined in shared objects. */ +#define SHT_MIPS_CONFLICT 0x70000002 + +/* Section contains the global pointer table. */ +#define SHT_MIPS_GPTAB 0x70000003 + +/* Section contains microcode information. The exact format is + unspecified. */ +#define SHT_MIPS_UCODE 0x70000004 + +/* Section contains some sort of debugging information. The exact + format is unspecified. It's probably ECOFF symbols. */ +#define SHT_MIPS_DEBUG 0x70000005 + +/* Section contains register usage information. */ +#define SHT_MIPS_REGINFO 0x70000006 + +/* ??? */ +#define SHT_MIPS_PACKAGE 0x70000007 + +/* ??? */ +#define SHT_MIPS_PACKSYM 0x70000008 + +/* ??? */ +#define SHT_MIPS_RELD 0x70000009 + +/* Section contains interface information. */ +#define SHT_MIPS_IFACE 0x7000000b + +/* Section contains description of contents of another section. */ +#define SHT_MIPS_CONTENT 0x7000000c + +/* Section contains miscellaneous options. */ +#define SHT_MIPS_OPTIONS 0x7000000d + +/* ??? */ +#define SHT_MIPS_SHDR 0x70000010 + +/* ??? */ +#define SHT_MIPS_FDESC 0x70000011 + +/* ??? */ +#define SHT_MIPS_EXTSYM 0x70000012 + +/* ??? */ +#define SHT_MIPS_DENSE 0x70000013 + +/* ??? */ +#define SHT_MIPS_PDESC 0x70000014 + +/* ??? */ +#define SHT_MIPS_LOCSYM 0x70000015 + +/* ??? */ +#define SHT_MIPS_AUXSYM 0x70000016 + +/* ??? */ +#define SHT_MIPS_OPTSYM 0x70000017 + +/* ??? */ +#define SHT_MIPS_LOCSTR 0x70000018 + +/* ??? */ +#define SHT_MIPS_LINE 0x70000019 + +/* ??? */ +#define SHT_MIPS_RFDESC 0x7000001a + +/* Delta C++: symbol table */ +#define SHT_MIPS_DELTASYM 0x7000001b + +/* Delta C++: instance table */ +#define SHT_MIPS_DELTAINST 0x7000001c + +/* Delta C++: class table */ +#define SHT_MIPS_DELTACLASS 0x7000001d + +/* DWARF debugging section. */ +#define SHT_MIPS_DWARF 0x7000001e + +/* Delta C++: declarations */ +#define SHT_MIPS_DELTADECL 0x7000001f + +/* List of libraries the binary depends on. Includes a time stamp, version + number. */ +#define SHT_MIPS_SYMBOL_LIB 0x70000020 + +/* Events section. */ +#define SHT_MIPS_EVENTS 0x70000021 + +/* ??? */ +#define SHT_MIPS_TRANSLATE 0x70000022 + +/* Special pixie sections */ +#define SHT_MIPS_PIXIE 0x70000023 + +/* Address translation table (for debug info) */ +#define SHT_MIPS_XLATE 0x70000024 + +/* SGI internal address translation table (for debug info) */ +#define SHT_MIPS_XLATE_DEBUG 0x70000025 + +/* Intermediate code */ +#define SHT_MIPS_WHIRL 0x70000026 + +/* C++ exception handling region info */ +#define SHT_MIPS_EH_REGION 0x70000027 + +/* Obsolete address translation table (for debug info) */ +#define SHT_MIPS_XLATE_OLD 0x70000028 + +/* Runtime procedure descriptor table exception information (ucode) ??? */ +#define SHT_MIPS_PDR_EXCEPTION 0x70000029 + + +/* A section of type SHT_MIPS_LIBLIST contains an array of the + following structure. The sh_link field is the section index of the + string table. The sh_info field is the number of entries in the + section. */ +typedef struct +{ + /* String table index for name of shared object. */ + unsigned long l_name; + /* Time stamp. */ + unsigned long l_time_stamp; + /* Checksum of symbol names and common sizes. */ + unsigned long l_checksum; + /* String table index for version. */ + unsigned long l_version; + /* Flags. */ + unsigned long l_flags; +} Elf32_Lib; + +/* The external version of Elf32_Lib. */ +typedef struct +{ + unsigned char l_name[4]; + unsigned char l_time_stamp[4]; + unsigned char l_checksum[4]; + unsigned char l_version[4]; + unsigned char l_flags[4]; +} Elf32_External_Lib; + +/* The l_flags field of an Elf32_Lib structure may contain the + following flags. */ + +/* Require an exact match at runtime. */ +#define LL_EXACT_MATCH 0x00000001 + +/* Ignore version incompatibilities at runtime. */ +#define LL_IGNORE_INT_VER 0x00000002 + +/* Require matching minor version number. */ +#define LL_REQUIRE_MINOR 0x00000004 + +/* ??? */ +#define LL_EXPORTS 0x00000008 + +/* Delay loading of this library until really needed. */ +#define LL_DELAY_LOAD 0x00000010 + +/* ??? Delta C++ stuff ??? */ +#define LL_DELTA 0x00000020 + + +/* A section of type SHT_MIPS_CONFLICT is an array of indices into the + .dynsym section. Each element has the following type. */ +typedef unsigned long Elf32_Conflict; +typedef unsigned char Elf32_External_Conflict[4]; + +typedef unsigned long Elf64_Conflict; +typedef unsigned char Elf64_External_Conflict[8]; + +/* A section of type SHT_MIPS_GPTAB contains information about how + much GP space would be required for different -G arguments. This + information is only used so that the linker can provide informative + suggestions as to the best -G value to use. The sh_info field is + the index of the section for which this information applies. The + contents of the section are an array of the following union. The + first element uses the gt_header field. The remaining elements use + the gt_entry field. */ +typedef union +{ + struct + { + /* -G value actually used for this object file. */ + unsigned long gt_current_g_value; + /* Unused. */ + unsigned long gt_unused; + } gt_header; + struct + { + /* If this -G argument has been used... */ + unsigned long gt_g_value; + /* ...this many GP section bytes would be required. */ + unsigned long gt_bytes; + } gt_entry; +} Elf32_gptab; + +/* The external version of Elf32_gptab. */ + +typedef union +{ + struct + { + unsigned char gt_current_g_value[4]; + unsigned char gt_unused[4]; + } gt_header; + struct + { + unsigned char gt_g_value[4]; + unsigned char gt_bytes[4]; + } gt_entry; +} Elf32_External_gptab; + +/* A section of type SHT_MIPS_REGINFO contains the following + structure. */ +typedef struct +{ + /* Mask of general purpose registers used. */ + unsigned long ri_gprmask; + /* Mask of co-processor registers used. */ + unsigned long ri_cprmask[4]; + /* GP register value for this object file. */ + long ri_gp_value; +} Elf32_RegInfo; + +/* The external version of the Elf_RegInfo structure. */ +typedef struct +{ + unsigned char ri_gprmask[4]; + unsigned char ri_cprmask[4][4]; + unsigned char ri_gp_value[4]; +} Elf32_External_RegInfo; + +/* MIPS ELF .reginfo swapping routines. */ +extern void bfd_mips_elf32_swap_reginfo_in + (bfd *, const Elf32_External_RegInfo *, Elf32_RegInfo *); +extern void bfd_mips_elf32_swap_reginfo_out + (bfd *, const Elf32_RegInfo *, Elf32_External_RegInfo *); + +/* Processor specific section flags. */ + +/* This section must be in the global data area. */ +#define SHF_MIPS_GPREL 0x10000000 + +/* This section should be merged. */ +#define SHF_MIPS_MERGE 0x20000000 + +/* This section contains address data of size implied by section + element size. */ +#define SHF_MIPS_ADDR 0x40000000 + +/* This section contains string data. */ +#define SHF_MIPS_STRING 0x80000000 + +/* This section may not be stripped. */ +#define SHF_MIPS_NOSTRIP 0x08000000 + +/* This section is local to threads. */ +#define SHF_MIPS_LOCAL 0x04000000 + +/* Linker should generate implicit weak names for this section. */ +#define SHF_MIPS_NAMES 0x02000000 + +/* Section contais text/data which may be replicated in other sections. + Linker should retain only one copy. */ +#define SHF_MIPS_NODUPES 0x01000000 + +/* Processor specific program header types. */ + +/* Register usage information. Identifies one .reginfo section. */ +#define PT_MIPS_REGINFO 0x70000000 + +/* Runtime procedure table. */ +#define PT_MIPS_RTPROC 0x70000001 + +/* .MIPS.options section. */ +#define PT_MIPS_OPTIONS 0x70000002 + +/* Processor specific dynamic array tags. */ + +/* 32 bit version number for runtime linker interface. */ +#define DT_MIPS_RLD_VERSION 0x70000001 + +/* Time stamp. */ +#define DT_MIPS_TIME_STAMP 0x70000002 + +/* Checksum of external strings and common sizes. */ +#define DT_MIPS_ICHECKSUM 0x70000003 + +/* Index of version string in string table. */ +#define DT_MIPS_IVERSION 0x70000004 + +/* 32 bits of flags. */ +#define DT_MIPS_FLAGS 0x70000005 + +/* Base address of the segment. */ +#define DT_MIPS_BASE_ADDRESS 0x70000006 + +/* ??? */ +#define DT_MIPS_MSYM 0x70000007 + +/* Address of .conflict section. */ +#define DT_MIPS_CONFLICT 0x70000008 + +/* Address of .liblist section. */ +#define DT_MIPS_LIBLIST 0x70000009 + +/* Number of local global offset table entries. */ +#define DT_MIPS_LOCAL_GOTNO 0x7000000a + +/* Number of entries in the .conflict section. */ +#define DT_MIPS_CONFLICTNO 0x7000000b + +/* Number of entries in the .liblist section. */ +#define DT_MIPS_LIBLISTNO 0x70000010 + +/* Number of entries in the .dynsym section. */ +#define DT_MIPS_SYMTABNO 0x70000011 + +/* Index of first external dynamic symbol not referenced locally. */ +#define DT_MIPS_UNREFEXTNO 0x70000012 + +/* Index of first dynamic symbol in global offset table. */ +#define DT_MIPS_GOTSYM 0x70000013 + +/* Number of page table entries in global offset table. */ +#define DT_MIPS_HIPAGENO 0x70000014 + +/* Address of run time loader map, used for debugging. */ +#define DT_MIPS_RLD_MAP 0x70000016 + +/* Delta C++ class definition. */ +#define DT_MIPS_DELTA_CLASS 0x70000017 + +/* Number of entries in DT_MIPS_DELTA_CLASS. */ +#define DT_MIPS_DELTA_CLASS_NO 0x70000018 + +/* Delta C++ class instances. */ +#define DT_MIPS_DELTA_INSTANCE 0x70000019 + +/* Number of entries in DT_MIPS_DELTA_INSTANCE. */ +#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a + +/* Delta relocations. */ +#define DT_MIPS_DELTA_RELOC 0x7000001b + +/* Number of entries in DT_MIPS_DELTA_RELOC. */ +#define DT_MIPS_DELTA_RELOC_NO 0x7000001c + +/* Delta symbols that Delta relocations refer to. */ +#define DT_MIPS_DELTA_SYM 0x7000001d + +/* Number of entries in DT_MIPS_DELTA_SYM. */ +#define DT_MIPS_DELTA_SYM_NO 0x7000001e + +/* Delta symbols that hold class declarations. */ +#define DT_MIPS_DELTA_CLASSSYM 0x70000020 + +/* Number of entries in DT_MIPS_DELTA_CLASSSYM. */ +#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 + +/* Flags indicating information about C++ flavor. */ +#define DT_MIPS_CXX_FLAGS 0x70000022 + +/* Pixie information (???). */ +#define DT_MIPS_PIXIE_INIT 0x70000023 + +/* Address of .MIPS.symlib */ +#define DT_MIPS_SYMBOL_LIB 0x70000024 + +/* The GOT index of the first PTE for a segment */ +#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 + +/* The GOT index of the first PTE for a local symbol */ +#define DT_MIPS_LOCAL_GOTIDX 0x70000026 + +/* The GOT index of the first PTE for a hidden symbol */ +#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 + +/* The GOT index of the first PTE for a protected symbol */ +#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 + +/* Address of `.MIPS.options'. */ +#define DT_MIPS_OPTIONS 0x70000029 + +/* Address of `.interface'. */ +#define DT_MIPS_INTERFACE 0x7000002a + +/* ??? */ +#define DT_MIPS_DYNSTR_ALIGN 0x7000002b + +/* Size of the .interface section. */ +#define DT_MIPS_INTERFACE_SIZE 0x7000002c + +/* Size of rld_text_resolve function stored in the GOT. */ +#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d + +/* Default suffix of DSO to be added by rld on dlopen() calls. */ +#define DT_MIPS_PERF_SUFFIX 0x7000002e + +/* Size of compact relocation section (O32). */ +#define DT_MIPS_COMPACT_SIZE 0x7000002f + +/* GP value for auxiliary GOTs. */ +#define DT_MIPS_GP_VALUE 0x70000030 + +/* Address of auxiliary .dynamic. */ +#define DT_MIPS_AUX_DYNAMIC 0x70000031 + +/* Flags which may appear in a DT_MIPS_FLAGS entry. */ + +/* No flags. */ +#define RHF_NONE 0x00000000 + +/* Uses shortcut pointers. */ +#define RHF_QUICKSTART 0x00000001 + +/* Hash size is not a power of two. */ +#define RHF_NOTPOT 0x00000002 + +/* Ignore LD_LIBRARY_PATH. */ +#define RHS_NO_LIBRARY_REPLACEMENT 0x00000004 + +/* DSO address may not be relocated. */ +#define RHF_NO_MOVE 0x00000008 + +/* SGI specific features. */ +#define RHF_SGI_ONLY 0x00000010 + +/* Guarantee that .init will finish executing before any non-init + code in DSO is called. */ +#define RHF_GUARANTEE_INIT 0x00000020 + +/* Contains Delta C++ code. */ +#define RHF_DELTA_C_PLUS_PLUS 0x00000040 + +/* Guarantee that .init will start executing before any non-init + code in DSO is called. */ +#define RHF_GUARANTEE_START_INIT 0x00000080 + +/* Generated by pixie. */ +#define RHF_PIXIE 0x00000100 + +/* Delay-load DSO by default. */ +#define RHF_DEFAULT_DELAY_LOAD 0x00000200 + +/* Object may be requickstarted */ +#define RHF_REQUICKSTART 0x00000400 + +/* Object has been requickstarted */ +#define RHF_REQUICKSTARTED 0x00000800 + +/* Generated by cord. */ +#define RHF_CORD 0x00001000 + +/* Object contains no unresolved undef symbols. */ +#define RHF_NO_UNRES_UNDEF 0x00002000 + +/* Symbol table is in a safe order. */ +#define RHF_RLD_ORDER_SAFE 0x00004000 + +/* Special values for the st_other field in the symbol table. These + are used in an Irix 5 dynamic symbol table. */ + +#define STO_DEFAULT STV_DEFAULT +#define STO_INTERNAL STV_INTERNAL +#define STO_HIDDEN STV_HIDDEN +#define STO_PROTECTED STV_PROTECTED + +/* This value is used for a mips16 .text symbol. */ +#define STO_MIPS16 0xf0 + +/* The 64-bit MIPS ELF ABI uses an unusual reloc format. Each + relocation entry specifies up to three actual relocations, all at + the same address. The first relocation which required a symbol + uses the symbol in the r_sym field. The second relocation which + requires a symbol uses the symbol in the r_ssym field. If all + three relocations require a symbol, the third one uses a zero + value. */ + +/* An entry in a 64 bit SHT_REL section. */ + +typedef struct +{ + /* Address of relocation. */ + unsigned char r_offset[8]; + /* Symbol index. */ + unsigned char r_sym[4]; + /* Special symbol. */ + unsigned char r_ssym[1]; + /* Third relocation. */ + unsigned char r_type3[1]; + /* Second relocation. */ + unsigned char r_type2[1]; + /* First relocation. */ + unsigned char r_type[1]; +} Elf64_Mips_External_Rel; + +typedef struct +{ + /* Address of relocation. */ + bfd_vma r_offset; + /* Symbol index. */ + unsigned long r_sym; + /* Special symbol. */ + unsigned char r_ssym; + /* Third relocation. */ + unsigned char r_type3; + /* Second relocation. */ + unsigned char r_type2; + /* First relocation. */ + unsigned char r_type; +} Elf64_Mips_Internal_Rel; + +/* An entry in a 64 bit SHT_RELA section. */ + +typedef struct +{ + /* Address of relocation. */ + unsigned char r_offset[8]; + /* Symbol index. */ + unsigned char r_sym[4]; + /* Special symbol. */ + unsigned char r_ssym[1]; + /* Third relocation. */ + unsigned char r_type3[1]; + /* Second relocation. */ + unsigned char r_type2[1]; + /* First relocation. */ + unsigned char r_type[1]; + /* Addend. */ + unsigned char r_addend[8]; +} Elf64_Mips_External_Rela; + +typedef struct +{ + /* Address of relocation. */ + bfd_vma r_offset; + /* Symbol index. */ + unsigned long r_sym; + /* Special symbol. */ + unsigned char r_ssym; + /* Third relocation. */ + unsigned char r_type3; + /* Second relocation. */ + unsigned char r_type2; + /* First relocation. */ + unsigned char r_type; + /* Addend. */ + bfd_signed_vma r_addend; +} Elf64_Mips_Internal_Rela; + +/* MIPS ELF 64 relocation info access macros. */ +#define ELF64_MIPS_R_SSYM(i) (((i) >> 24) & 0xff) +#define ELF64_MIPS_R_TYPE3(i) (((i) >> 16) & 0xff) +#define ELF64_MIPS_R_TYPE2(i) (((i) >> 8) & 0xff) +#define ELF64_MIPS_R_TYPE(i) ((i) & 0xff) + +/* Values found in the r_ssym field of a relocation entry. */ + +/* No relocation. */ +#define RSS_UNDEF 0 + +/* Value of GP. */ +#define RSS_GP 1 + +/* Value of GP in object being relocated. */ +#define RSS_GP0 2 + +/* Address of location being relocated. */ +#define RSS_LOC 3 + +/* A SHT_MIPS_OPTIONS section contains a series of options, each of + which starts with this header. */ + +typedef struct +{ + /* Type of option. */ + unsigned char kind[1]; + /* Size of option descriptor, including header. */ + unsigned char size[1]; + /* Section index of affected section, or 0 for global option. */ + unsigned char section[2]; + /* Information specific to this kind of option. */ + unsigned char info[4]; +} Elf_External_Options; + +typedef struct +{ + /* Type of option. */ + unsigned char kind; + /* Size of option descriptor, including header. */ + unsigned char size; + /* Section index of affected section, or 0 for global option. */ + unsigned short section; + /* Information specific to this kind of option. */ + unsigned long info; +} Elf_Internal_Options; + +/* MIPS ELF option header swapping routines. */ +extern void bfd_mips_elf_swap_options_in + (bfd *, const Elf_External_Options *, Elf_Internal_Options *); +extern void bfd_mips_elf_swap_options_out + (bfd *, const Elf_Internal_Options *, Elf_External_Options *); + +/* Values which may appear in the kind field of an Elf_Options + structure. */ + +/* Undefined. */ +#define ODK_NULL 0 + +/* Register usage and GP value. */ +#define ODK_REGINFO 1 + +/* Exception processing information. */ +#define ODK_EXCEPTIONS 2 + +/* Section padding information. */ +#define ODK_PAD 3 + +/* Hardware workarounds performed. */ +#define ODK_HWPATCH 4 + +/* Fill value used by the linker. */ +#define ODK_FILL 5 + +/* Reserved space for desktop tools. */ +#define ODK_TAGS 6 + +/* Hardware workarounds, AND bits when merging. */ +#define ODK_HWAND 7 + +/* Hardware workarounds, OR bits when merging. */ +#define ODK_HWOR 8 + +/* GP group to use for text/data sections. */ +#define ODK_GP_GROUP 9 + +/* ID information. */ +#define ODK_IDENT 10 + +/* In the 32 bit ABI, an ODK_REGINFO option is just a Elf32_RegInfo + structure. In the 64 bit ABI, it is the following structure. The + info field of the options header is not used. */ + +typedef struct +{ + /* Mask of general purpose registers used. */ + unsigned char ri_gprmask[4]; + /* Padding. */ + unsigned char ri_pad[4]; + /* Mask of co-processor registers used. */ + unsigned char ri_cprmask[4][4]; + /* GP register value for this object file. */ + unsigned char ri_gp_value[8]; +} Elf64_External_RegInfo; + +typedef struct +{ + /* Mask of general purpose registers used. */ + unsigned long ri_gprmask; + /* Padding. */ + unsigned long ri_pad; + /* Mask of co-processor registers used. */ + unsigned long ri_cprmask[4]; + /* GP register value for this object file. */ + bfd_vma ri_gp_value; +} Elf64_Internal_RegInfo; + +typedef struct +{ + /* The hash value computed from the name of the corresponding + dynamic symbol. */ + unsigned char ms_hash_value[4]; + /* Contains both the dynamic relocation index and the symbol flags + field. The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used + to access the individual values. The dynamic relocation index + identifies the first entry in the .rel.dyn section that + references the dynamic symbol corresponding to this msym entry. + If the index is 0, no dynamic relocations are associated with the + symbol. The symbol flags field is reserved for future use. */ + unsigned char ms_info[4]; +} Elf32_External_Msym; + +typedef struct +{ + /* The hash value computed from the name of the corresponding + dynamic symbol. */ + unsigned long ms_hash_value; + /* Contains both the dynamic relocation index and the symbol flags + field. The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used + to access the individual values. The dynamic relocation index + identifies the first entry in the .rel.dyn section that + references the dynamic symbol corresponding to this msym entry. + If the index is 0, no dynamic relocations are associated with the + symbol. The symbol flags field is reserved for future use. */ + unsigned long ms_info; +} Elf32_Internal_Msym; + +#define ELF32_MS_REL_INDEX(i) ((i) >> 8) +#define ELF32_MS_FLAGS(i) (i) & 0xff) +#define ELF32_MS_INFO(r, f) (((r) << 8) + ((f) & 0xff)) + +/* MIPS ELF reginfo swapping routines. */ +extern void bfd_mips_elf64_swap_reginfo_in + (bfd *, const Elf64_External_RegInfo *, Elf64_Internal_RegInfo *); +extern void bfd_mips_elf64_swap_reginfo_out + (bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *); + +/* Masks for the info work of an ODK_EXCEPTIONS descriptor. */ +#define OEX_FPU_MIN 0x1f /* FPEs which must be enabled. */ +#define OEX_FPU_MAX 0x1f00 /* FPEs which may be enabled. */ +#define OEX_PAGE0 0x10000 /* Page zero must be mapped. */ +#define OEX_SMM 0x20000 /* Force sequential memory mode. */ +#define OEX_FPDBUG 0x40000 /* Force precise floating-point + exceptions (debug mode). */ +#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults. */ + +/* Masks of the FP exceptions for OEX_FPU_MIN and OEX_FPU_MAX. */ +#define OEX_FPU_INVAL 0x10 /* Invalid operation exception. */ +#define OEX_FPU_DIV0 0x08 /* Division by zero exception. */ +#define OEX_FPU_OFLO 0x04 /* Overflow exception. */ +#define OEX_FPU_UFLO 0x02 /* Underflow exception. */ +#define OEX_FPU_INEX 0x01 /* Inexact exception. */ + +/* Masks for the info word of an ODK_PAD descriptor. */ +#define OPAD_PREFIX 0x01 +#define OPAD_POSTFIX 0x02 +#define OPAD_SYMBOL 0x04 + +/* Masks for the info word of an ODK_HWPATCH descriptor. */ +#define OHW_R4KEOP 0x00000001 /* R4000 end-of-page patch. */ +#define OHW_R8KPFETCH 0x00000002 /* May need R8000 prefetch patch. */ +#define OHW_R5KEOP 0x00000004 /* R5000 end-of-page patch. */ +#define OHW_R5KCVTL 0x00000008 /* R5000 cvt.[ds].l bug + (clean == 1). */ +#define OHW_R10KLDL 0x00000010 /* Needs R10K misaligned + load patch. */ + +/* Masks for the info word of an ODK_IDENT/ODK_GP_GROUP descriptor. */ +#define OGP_GROUP 0x0000ffff /* GP group number. */ +#define OGP_SELF 0xffff0000 /* Self-contained GP groups. */ + +/* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor. */ +#define OHWA0_R4KEOP_CHECKED 0x00000001 +#define OHWA0_R4KEOP_CLEAN 0x00000002 + + +#endif /* _ELF_MIPS_H */ diff --git a/include/elf/mmix.h b/include/elf/mmix.h new file mode 100644 index 000000000..89778e447 --- /dev/null +++ b/include/elf/mmix.h @@ -0,0 +1,171 @@ +/* MMIX support for BFD. + Copyright 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MMIX ELF ABI. */ +#ifndef ELF_MMIX_H +#define ELF_MMIX_H + +#include "elf/reloc-macros.h" + +/* Relocations. See the reloc table in bfd/elf64-mmix.c for details. */ +START_RELOC_NUMBERS (elf_mmix_reloc_type) + RELOC_NUMBER (R_MMIX_NONE, 0) + + /* Standard absolute relocations. */ + RELOC_NUMBER (R_MMIX_8, 1) + RELOC_NUMBER (R_MMIX_16, 2) + RELOC_NUMBER (R_MMIX_24, 3) + RELOC_NUMBER (R_MMIX_32, 4) + RELOC_NUMBER (R_MMIX_64, 5) + + /* Standard relative relocations. */ + RELOC_NUMBER (R_MMIX_PC_8, 6) + RELOC_NUMBER (R_MMIX_PC_16, 7) + RELOC_NUMBER (R_MMIX_PC_24, 8) + RELOC_NUMBER (R_MMIX_PC_32, 9) + RELOC_NUMBER (R_MMIX_PC_64, 10) + + /* GNU extensions for C++ vtables. */ + RELOC_NUMBER (R_MMIX_GNU_VTINHERIT, 11) + RELOC_NUMBER (R_MMIX_GNU_VTENTRY, 12) + + /* A GETA instruction. */ + RELOC_NUMBER (R_MMIX_GETA, 13) + RELOC_NUMBER (R_MMIX_GETA_1, 14) + RELOC_NUMBER (R_MMIX_GETA_2, 15) + RELOC_NUMBER (R_MMIX_GETA_3, 16) + + /* A conditional branch instruction. */ + RELOC_NUMBER (R_MMIX_CBRANCH, 17) + RELOC_NUMBER (R_MMIX_CBRANCH_J, 18) + RELOC_NUMBER (R_MMIX_CBRANCH_1, 19) + RELOC_NUMBER (R_MMIX_CBRANCH_2, 20) + RELOC_NUMBER (R_MMIX_CBRANCH_3, 21) + + /* A PUSHJ instruction. */ + RELOC_NUMBER (R_MMIX_PUSHJ, 22) + RELOC_NUMBER (R_MMIX_PUSHJ_1, 23) + RELOC_NUMBER (R_MMIX_PUSHJ_2, 24) + RELOC_NUMBER (R_MMIX_PUSHJ_3, 25) + + /* A JMP instruction. */ + RELOC_NUMBER (R_MMIX_JMP, 26) + RELOC_NUMBER (R_MMIX_JMP_1, 27) + RELOC_NUMBER (R_MMIX_JMP_2, 28) + RELOC_NUMBER (R_MMIX_JMP_3, 29) + + /* A relative address such as in a GETA or a branch. */ + RELOC_NUMBER (R_MMIX_ADDR19, 30) + + /* A relative address such as in a JMP (only). */ + RELOC_NUMBER (R_MMIX_ADDR27, 31) + + /* A general register or a number 0..255. */ + RELOC_NUMBER (R_MMIX_REG_OR_BYTE, 32) + + /* A general register. */ + RELOC_NUMBER (R_MMIX_REG, 33) + + /* A global register and an offset, the global register (allocated at + link time) contents plus the offset made equivalent to the relocation + expression at link time. The relocation must point at the Y field of + an instruction. */ + RELOC_NUMBER (R_MMIX_BASE_PLUS_OFFSET, 34) + + /* A LOCAL assertion. */ + RELOC_NUMBER (R_MMIX_LOCAL, 35) + + /* A PUSHJ instruction, generating a stub if it does not reach. */ + RELOC_NUMBER (R_MMIX_PUSHJ_STUBBABLE, 36) +END_RELOC_NUMBERS (R_MMIX_max) + + +/* Section Attributes. */ +/* A section containing necessary information for relaxation. */ +#define SHF_MMIX_CANRELAX 0x80000000 + +/* Symbol attributes. */ +/* A symbol with this section-index is a register. */ +#define SHN_REGISTER SHN_LOPROC + +/* This section holds contents for each initialized register, at VMA + regno*8. A symbol relative to this section will be transformed to an + absolute symbol with the value corresponding to the register number at + final link time. A symbol with a value outside the inclusive range + 32*8 .. 254*8 is an error. It is highly recommended to only use an + upper bound of 253*8 or lower as specified in the (currently + unspecified) ABI. */ +#define MMIX_REG_CONTENTS_SECTION_NAME ".MMIX.reg_contents" + +/* At link time, a section by this name is created, expected to be + included in MMIX_REG_CONTENTS_SECTION_NAME in the output. */ +#define MMIX_LD_ALLOCATED_REG_CONTENTS_SECTION_NAME \ + ".MMIX.reg_contents.linker_allocated" + +/* This is a faked section holding symbols with SHN_REGISTER. Don't + confuse it with MMIX_REG_CONTENTS_SECTION_NAME; this one has no + contents, just values. It is an error for a value in this section to + be outside the range 32..255 and it must never become an actual section + in an object file. */ +#define MMIX_REG_SECTION_NAME "*REG*" + +/* Appended with a number N=0..65535, this is a representation of the + mmixal "BSPEC N" ... "ESPEC" directive pair; the contents go into an + ELF section by name ".MMIX.spec_data.N". */ +#define MMIX_OTHER_SPEC_SECTION_PREFIX ".MMIX.spec_data." + +/* A section SECNAME is noted to start at "__.MMIX.start.SECNAME" by the + presence of this symbol. Currently only implemented for ".text" + through the symbol "__.MMIX.start..text". */ +#define MMIX_LOC_SECTION_START_SYMBOL_PREFIX "__.MMIX.start." + +/* This symbol is always a function. */ +#define MMIX_START_SYMBOL_NAME "Main" + + +/* We smuggle in a few MMO specifics here. We don't make a specific MMO + file, since we can't reasonably support MMO without ELF; we have to + include this file anyway. */ + +#define MMO_TEXT_SECTION_NAME ".text" +#define MMO_DATA_SECTION_NAME ".data" + +/* A definition for the flags we put in spec data in files. A copy of our + own of some flags to keep immune to BFD flag changes. See section.c of + 2001-07-18 for flag documentation. */ +#define MMO_SEC_ALLOC 0x001 +#define MMO_SEC_LOAD 0x002 +#define MMO_SEC_RELOC 0x004 +#define MMO_SEC_READONLY 0x010 +#define MMO_SEC_CODE 0x020 +#define MMO_SEC_DATA 0x040 +#define MMO_SEC_NEVER_LOAD 0x400 +#define MMO_SEC_IS_COMMON 0x8000 +#define MMO_SEC_DEBUGGING 0x10000 + +#ifdef BFD_ARCH_SIZE +extern bfd_boolean _bfd_mmix_before_linker_allocation + (bfd *, struct bfd_link_info *); +extern bfd_boolean _bfd_mmix_after_linker_allocation + (bfd *, struct bfd_link_info *); +extern bfd_boolean _bfd_mmix_check_all_relocs + (bfd *, struct bfd_link_info *); +#endif + +#endif /* ELF_MMIX_H */ diff --git a/include/elf/mn10200.h b/include/elf/mn10200.h new file mode 100644 index 000000000..1dfade5cc --- /dev/null +++ b/include/elf/mn10200.h @@ -0,0 +1,39 @@ +/* MN10200 ELF support for BFD. + Copyright 1998, 2000 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MN10200 ELF ABI. */ + +#ifndef _ELF_MN10200_H +#define _ELF_MN10200_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mn10200_reloc_type) + RELOC_NUMBER (R_MN10200_NONE, 0) + RELOC_NUMBER (R_MN10200_32, 1) + RELOC_NUMBER (R_MN10200_16, 2) + RELOC_NUMBER (R_MN10200_8, 3) + RELOC_NUMBER (R_MN10200_24, 4) + RELOC_NUMBER (R_MN10200_PCREL8, 5) + RELOC_NUMBER (R_MN10200_PCREL16, 6) + RELOC_NUMBER (R_MN10200_PCREL24, 7) +END_RELOC_NUMBERS (R_MN10200_max) + +#endif /* _ELF_MN10200_H */ diff --git a/include/elf/mn10300.h b/include/elf/mn10300.h new file mode 100644 index 000000000..e640096a2 --- /dev/null +++ b/include/elf/mn10300.h @@ -0,0 +1,68 @@ +/* MN10300 ELF support for BFD. + Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MN10300 ELF ABI. */ + +#ifndef _ELF_MN10300_H +#define _ELF_MN10300_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mn10300_reloc_type) + RELOC_NUMBER (R_MN10300_NONE, 0) + RELOC_NUMBER (R_MN10300_32, 1) + RELOC_NUMBER (R_MN10300_16, 2) + RELOC_NUMBER (R_MN10300_8, 3) + RELOC_NUMBER (R_MN10300_PCREL32, 4) + RELOC_NUMBER (R_MN10300_PCREL16, 5) + RELOC_NUMBER (R_MN10300_PCREL8, 6) + RELOC_NUMBER (R_MN10300_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_MN10300_GNU_VTENTRY, 8) + RELOC_NUMBER (R_MN10300_24, 9) + RELOC_NUMBER (R_MN10300_GOTPC32, 10) + RELOC_NUMBER (R_MN10300_GOTPC16, 11) + RELOC_NUMBER (R_MN10300_GOTOFF32, 12) + RELOC_NUMBER (R_MN10300_GOTOFF24, 13) + RELOC_NUMBER (R_MN10300_GOTOFF16, 14) + RELOC_NUMBER (R_MN10300_PLT32, 15) + RELOC_NUMBER (R_MN10300_PLT16, 16) + RELOC_NUMBER (R_MN10300_GOT32, 17) + RELOC_NUMBER (R_MN10300_GOT24, 18) + RELOC_NUMBER (R_MN10300_GOT16, 19) + RELOC_NUMBER (R_MN10300_COPY, 20) + RELOC_NUMBER (R_MN10300_GLOB_DAT, 21) + RELOC_NUMBER (R_MN10300_JMP_SLOT, 22) + RELOC_NUMBER (R_MN10300_RELATIVE, 23) +END_RELOC_NUMBERS (R_MN10300_MAX) + +/* Machine variant if we know it. This field was invented at Cygnus, + but it is hoped that other vendors will adopt it. If some standard + is developed, this code should be changed to follow it. */ + +#define EF_MN10300_MACH 0x00FF0000 + +/* Cygnus is choosing values between 80 and 9F; + 00 - 7F should be left for a future standard; + the rest are open. */ + +#define E_MN10300_MACH_MN10300 0x00810000 +#define E_MN10300_MACH_AM33 0x00820000 +#define E_MN10300_MACH_AM33_2 0x00830000 +#endif /* _ELF_MN10300_H */ diff --git a/include/elf/msp430.h b/include/elf/msp430.h new file mode 100644 index 000000000..2bf95a629 --- /dev/null +++ b/include/elf/msp430.h @@ -0,0 +1,58 @@ +/* MSP430 ELF support for BFD. + Copyright (C) 2002, 2004 Free Software Foundation, Inc. + Contributed by Dmitry Diky <diwil@mail.ru> + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_MSP430_H +#define _ELF_MSP430_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_MSP430_MACH 0xff + +#define E_MSP430_MACH_MSP430x11 11 +#define E_MSP430_MACH_MSP430x11x1 110 +#define E_MSP430_MACH_MSP430x12 12 +#define E_MSP430_MACH_MSP430x13 13 +#define E_MSP430_MACH_MSP430x14 14 +#define E_MSP430_MACH_MSP430x15 15 +#define E_MSP430_MACH_MSP430x16 16 +#define E_MSP430_MACH_MSP430x31 31 +#define E_MSP430_MACH_MSP430x32 32 +#define E_MSP430_MACH_MSP430x33 33 +#define E_MSP430_MACH_MSP430x41 41 +#define E_MSP430_MACH_MSP430x42 42 +#define E_MSP430_MACH_MSP430x43 43 +#define E_MSP430_MACH_MSP430x44 44 + +/* Relocations. */ +START_RELOC_NUMBERS (elf_msp430_reloc_type) + RELOC_NUMBER (R_MSP430_NONE, 0) + RELOC_NUMBER (R_MSP430_32, 1) + RELOC_NUMBER (R_MSP430_10_PCREL, 2) + RELOC_NUMBER (R_MSP430_16, 3) + RELOC_NUMBER (R_MSP430_16_PCREL, 4) + RELOC_NUMBER (R_MSP430_16_BYTE, 5) + RELOC_NUMBER (R_MSP430_16_PCREL_BYTE, 6) + RELOC_NUMBER (R_MSP430_2X_PCREL, 7) + RELOC_NUMBER (R_MSP430_RL_PCREL, 8) + +END_RELOC_NUMBERS (R_MSP430_max) + +#endif /* _ELF_MSP430_H */ diff --git a/include/elf/openrisc.h b/include/elf/openrisc.h new file mode 100644 index 000000000..c60990624 --- /dev/null +++ b/include/elf/openrisc.h @@ -0,0 +1,39 @@ +/* OpenRISC ELF support for BFD. + Copyright 2001 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_OPENRISC_H +#define _ELF_OPENRISC_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_openrisc_reloc_type) + RELOC_NUMBER (R_OPENRISC_NONE, 0) + RELOC_NUMBER (R_OPENRISC_INSN_REL_26, 1) + RELOC_NUMBER (R_OPENRISC_INSN_ABS_26, 2) + RELOC_NUMBER (R_OPENRISC_LO_16_IN_INSN, 3) + RELOC_NUMBER (R_OPENRISC_HI_16_IN_INSN, 4) + RELOC_NUMBER (R_OPENRISC_8, 5) + RELOC_NUMBER (R_OPENRISC_16, 6) + RELOC_NUMBER (R_OPENRISC_32, 7) + RELOC_NUMBER (R_OPENRISC_GNU_VTINHERIT, 8) + RELOC_NUMBER (R_OPENRISC_GNU_VTENTRY, 9) +END_RELOC_NUMBERS (R_OPENRISC_max) + +#endif /* _ELF_OPENRISC_H */ diff --git a/include/elf/or32.h b/include/elf/or32.h new file mode 100644 index 000000000..14884f330 --- /dev/null +++ b/include/elf/or32.h @@ -0,0 +1,62 @@ +/* OR1K ELF support for BFD. Derived from ppc.h. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by Ivan Guzvinec <ivang@opencores.org> + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_OR1K_H +#define _ELF_OR1K_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_or32_reloc_type) + RELOC_NUMBER (R_OR32_NONE, 0) + RELOC_NUMBER (R_OR32_32, 1) + RELOC_NUMBER (R_OR32_16, 2) + RELOC_NUMBER (R_OR32_8, 3) + RELOC_NUMBER (R_OR32_CONST, 4) + RELOC_NUMBER (R_OR32_CONSTH, 5) + RELOC_NUMBER (R_OR32_JUMPTARG, 6) + RELOC_NUMBER (R_OR32_GNU_VTENTRY, 7) + RELOC_NUMBER (R_OR32_GNU_VTINHERIT, 8) +END_RELOC_NUMBERS (R_OR32_max) + +/* Four bit OR32 machine type field. */ +#define EF_OR32_MACH 0x0000000f + +/* Various CPU types. */ +#define E_OR32_MACH_BASE 0x00000000 +#define E_OR32_MACH_UNUSED1 0x00000001 +#define E_OR32_MACH_UNUSED2 0x00000002 +#define E_OR32_MACH_UNUSED4 0x00000003 + +/* Processor specific section headers, sh_type field */ +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +/* Processor specific section flags, sh_flags field */ +#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \ + this section from executable \ + and shared objects that it \ + builds when those objects \ + are not to be furhter \ + relocated. */ +#endif /* _ELF_OR1K_H */ diff --git a/include/elf/pj.h b/include/elf/pj.h new file mode 100644 index 000000000..586fd3a36 --- /dev/null +++ b/include/elf/pj.h @@ -0,0 +1,44 @@ +/* picoJava ELF support for BFD. + Copyright 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_PJ_H +#define _ELF_PJ_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ + +START_RELOC_NUMBERS (elf_pj_reloc_type) + RELOC_NUMBER (R_PJ_NONE, 0) + RELOC_NUMBER (R_PJ_DATA_DIR32, 1) + RELOC_NUMBER (R_PJ_CODE_REL32, 2) + RELOC_NUMBER (R_PJ_CODE_REL16, 3) + RELOC_NUMBER (R_PJ_CODE_DIR32, 6) + RELOC_NUMBER (R_PJ_CODE_DIR16, 7) + RELOC_NUMBER (R_PJ_CODE_LO16, 13) + RELOC_NUMBER (R_PJ_CODE_HI16, 14) + RELOC_NUMBER (R_PJ_GNU_VTINHERIT, 15) + RELOC_NUMBER (R_PJ_GNU_VTENTRY, 16) +END_RELOC_NUMBERS (R_PJ_max) + +#define EF_PICOJAVA_ARCH 0x0000000f +#define EF_PICOJAVA_NEWCALLS 0x00000010 +#define EF_PICOJAVA_GNUCALLS 0x00000020 /* The (currently) non standard GNU calling convention */ + +#endif diff --git a/include/elf/ppc.h b/include/elf/ppc.h new file mode 100644 index 000000000..b510f441c --- /dev/null +++ b/include/elf/ppc.h @@ -0,0 +1,164 @@ +/* PPC ELF support for BFD. + Copyright 1995, 1996, 1998, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + + By Michael Meissner, Cygnus Support, <meissner@cygnus.com>, from information + in the System V Application Binary Interface, PowerPC Processor Supplement + and the PowerPC Embedded Application Binary Interface (eabi). + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the PPC ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_PPC_H +#define _ELF_PPC_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_ppc_reloc_type) + RELOC_NUMBER (R_PPC_NONE, 0) + RELOC_NUMBER (R_PPC_ADDR32, 1) + RELOC_NUMBER (R_PPC_ADDR24, 2) + RELOC_NUMBER (R_PPC_ADDR16, 3) + RELOC_NUMBER (R_PPC_ADDR16_LO, 4) + RELOC_NUMBER (R_PPC_ADDR16_HI, 5) + RELOC_NUMBER (R_PPC_ADDR16_HA, 6) + RELOC_NUMBER (R_PPC_ADDR14, 7) + RELOC_NUMBER (R_PPC_ADDR14_BRTAKEN, 8) + RELOC_NUMBER (R_PPC_ADDR14_BRNTAKEN, 9) + RELOC_NUMBER (R_PPC_REL24, 10) + RELOC_NUMBER (R_PPC_REL14, 11) + RELOC_NUMBER (R_PPC_REL14_BRTAKEN, 12) + RELOC_NUMBER (R_PPC_REL14_BRNTAKEN, 13) + RELOC_NUMBER (R_PPC_GOT16, 14) + RELOC_NUMBER (R_PPC_GOT16_LO, 15) + RELOC_NUMBER (R_PPC_GOT16_HI, 16) + RELOC_NUMBER (R_PPC_GOT16_HA, 17) + RELOC_NUMBER (R_PPC_PLTREL24, 18) + RELOC_NUMBER (R_PPC_COPY, 19) + RELOC_NUMBER (R_PPC_GLOB_DAT, 20) + RELOC_NUMBER (R_PPC_JMP_SLOT, 21) + RELOC_NUMBER (R_PPC_RELATIVE, 22) + RELOC_NUMBER (R_PPC_LOCAL24PC, 23) + RELOC_NUMBER (R_PPC_UADDR32, 24) + RELOC_NUMBER (R_PPC_UADDR16, 25) + RELOC_NUMBER (R_PPC_REL32, 26) + RELOC_NUMBER (R_PPC_PLT32, 27) + RELOC_NUMBER (R_PPC_PLTREL32, 28) + RELOC_NUMBER (R_PPC_PLT16_LO, 29) + RELOC_NUMBER (R_PPC_PLT16_HI, 30) + RELOC_NUMBER (R_PPC_PLT16_HA, 31) + RELOC_NUMBER (R_PPC_SDAREL16, 32) + RELOC_NUMBER (R_PPC_SECTOFF, 33) + RELOC_NUMBER (R_PPC_SECTOFF_LO, 34) + RELOC_NUMBER (R_PPC_SECTOFF_HI, 35) + RELOC_NUMBER (R_PPC_SECTOFF_HA, 36) + RELOC_NUMBER (R_PPC_ADDR30, 37) + + /* Relocs added to support TLS. */ + RELOC_NUMBER (R_PPC_TLS, 67) + RELOC_NUMBER (R_PPC_DTPMOD32, 68) + RELOC_NUMBER (R_PPC_TPREL16, 69) + RELOC_NUMBER (R_PPC_TPREL16_LO, 70) + RELOC_NUMBER (R_PPC_TPREL16_HI, 71) + RELOC_NUMBER (R_PPC_TPREL16_HA, 72) + RELOC_NUMBER (R_PPC_TPREL32, 73) + RELOC_NUMBER (R_PPC_DTPREL16, 74) + RELOC_NUMBER (R_PPC_DTPREL16_LO, 75) + RELOC_NUMBER (R_PPC_DTPREL16_HI, 76) + RELOC_NUMBER (R_PPC_DTPREL16_HA, 77) + RELOC_NUMBER (R_PPC_DTPREL32, 78) + RELOC_NUMBER (R_PPC_GOT_TLSGD16, 79) + RELOC_NUMBER (R_PPC_GOT_TLSGD16_LO, 80) + RELOC_NUMBER (R_PPC_GOT_TLSGD16_HI, 81) + RELOC_NUMBER (R_PPC_GOT_TLSGD16_HA, 82) + RELOC_NUMBER (R_PPC_GOT_TLSLD16, 83) + RELOC_NUMBER (R_PPC_GOT_TLSLD16_LO, 84) + RELOC_NUMBER (R_PPC_GOT_TLSLD16_HI, 85) + RELOC_NUMBER (R_PPC_GOT_TLSLD16_HA, 86) + RELOC_NUMBER (R_PPC_GOT_TPREL16, 87) + RELOC_NUMBER (R_PPC_GOT_TPREL16_LO, 88) + RELOC_NUMBER (R_PPC_GOT_TPREL16_HI, 89) + RELOC_NUMBER (R_PPC_GOT_TPREL16_HA, 90) + RELOC_NUMBER (R_PPC_GOT_DTPREL16, 91) + RELOC_NUMBER (R_PPC_GOT_DTPREL16_LO, 92) + RELOC_NUMBER (R_PPC_GOT_DTPREL16_HI, 93) + RELOC_NUMBER (R_PPC_GOT_DTPREL16_HA, 94) + +/* The remaining relocs are from the Embedded ELF ABI, and are not + in the SVR4 ELF ABI. */ + RELOC_NUMBER (R_PPC_EMB_NADDR32, 101) + RELOC_NUMBER (R_PPC_EMB_NADDR16, 102) + RELOC_NUMBER (R_PPC_EMB_NADDR16_LO, 103) + RELOC_NUMBER (R_PPC_EMB_NADDR16_HI, 104) + RELOC_NUMBER (R_PPC_EMB_NADDR16_HA, 105) + RELOC_NUMBER (R_PPC_EMB_SDAI16, 106) + RELOC_NUMBER (R_PPC_EMB_SDA2I16, 107) + RELOC_NUMBER (R_PPC_EMB_SDA2REL, 108) + RELOC_NUMBER (R_PPC_EMB_SDA21, 109) + RELOC_NUMBER (R_PPC_EMB_MRKREF, 110) + RELOC_NUMBER (R_PPC_EMB_RELSEC16, 111) + RELOC_NUMBER (R_PPC_EMB_RELST_LO, 112) + RELOC_NUMBER (R_PPC_EMB_RELST_HI, 113) + RELOC_NUMBER (R_PPC_EMB_RELST_HA, 114) + RELOC_NUMBER (R_PPC_EMB_BIT_FLD, 115) + RELOC_NUMBER (R_PPC_EMB_RELSDA, 116) + +/* Fake relocations for branch stubs. This will keep them + together. */ +#define R_PPC_RELAX32 251 +#define R_PPC_RELAX32PC 252 + +/* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_PPC_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_PPC_GNU_VTENTRY, 254) + +/* This is a phony reloc to handle any old fashioned TOC16 references + that may still be in object files. */ + RELOC_NUMBER (R_PPC_TOC16, 255) + +END_RELOC_NUMBERS (R_PPC_max) + +#define IS_PPC_TLS_RELOC(R) \ + ((R) >= R_PPC_TLS && (R) <= R_PPC_GOT_DTPREL16_HA) + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag. */ + +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag. */ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag. */ + +/* Processor specific section headers, sh_type field. */ + +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +/* Processor specific section flags, sh_flags field. */ + +#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \ + this section from executable \ + and shared objects that it \ + builds when those objects \ + are not to be furhter \ + relocated. */ +#endif /* _ELF_PPC_H */ diff --git a/include/elf/ppc64.h b/include/elf/ppc64.h new file mode 100644 index 000000000..ee2b0ea53 --- /dev/null +++ b/include/elf/ppc64.h @@ -0,0 +1,156 @@ +/* PPC64 ELF support for BFD. + Copyright 2003 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_PPC64_H +#define _ELF_PPC64_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_ppc64_reloc_type) + RELOC_NUMBER (R_PPC64_NONE, 0) + RELOC_NUMBER (R_PPC64_ADDR32, 1) + RELOC_NUMBER (R_PPC64_ADDR24, 2) + RELOC_NUMBER (R_PPC64_ADDR16, 3) + RELOC_NUMBER (R_PPC64_ADDR16_LO, 4) + RELOC_NUMBER (R_PPC64_ADDR16_HI, 5) + RELOC_NUMBER (R_PPC64_ADDR16_HA, 6) + RELOC_NUMBER (R_PPC64_ADDR14, 7) + RELOC_NUMBER (R_PPC64_ADDR14_BRTAKEN, 8) + RELOC_NUMBER (R_PPC64_ADDR14_BRNTAKEN, 9) + RELOC_NUMBER (R_PPC64_REL24, 10) + RELOC_NUMBER (R_PPC64_REL14, 11) + RELOC_NUMBER (R_PPC64_REL14_BRTAKEN, 12) + RELOC_NUMBER (R_PPC64_REL14_BRNTAKEN, 13) + RELOC_NUMBER (R_PPC64_GOT16, 14) + RELOC_NUMBER (R_PPC64_GOT16_LO, 15) + RELOC_NUMBER (R_PPC64_GOT16_HI, 16) + RELOC_NUMBER (R_PPC64_GOT16_HA, 17) + /* 18 unused. 32-bit reloc is R_PPC_PLTREL24. */ + RELOC_NUMBER (R_PPC64_COPY, 19) + RELOC_NUMBER (R_PPC64_GLOB_DAT, 20) + RELOC_NUMBER (R_PPC64_JMP_SLOT, 21) + RELOC_NUMBER (R_PPC64_RELATIVE, 22) + /* 23 unused. 32-bit reloc is R_PPC_LOCAL24PC. */ + RELOC_NUMBER (R_PPC64_UADDR32, 24) + RELOC_NUMBER (R_PPC64_UADDR16, 25) + RELOC_NUMBER (R_PPC64_REL32, 26) + RELOC_NUMBER (R_PPC64_PLT32, 27) + RELOC_NUMBER (R_PPC64_PLTREL32, 28) + RELOC_NUMBER (R_PPC64_PLT16_LO, 29) + RELOC_NUMBER (R_PPC64_PLT16_HI, 30) + RELOC_NUMBER (R_PPC64_PLT16_HA, 31) + /* 32 unused. 32-bit reloc is R_PPC_SDAREL16. */ + RELOC_NUMBER (R_PPC64_SECTOFF, 33) + RELOC_NUMBER (R_PPC64_SECTOFF_LO, 34) + RELOC_NUMBER (R_PPC64_SECTOFF_HI, 35) + RELOC_NUMBER (R_PPC64_SECTOFF_HA, 36) + RELOC_NUMBER (R_PPC64_REL30, 37) + RELOC_NUMBER (R_PPC64_ADDR64, 38) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHER, 39) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHERA, 40) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHEST, 41) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHESTA, 42) + RELOC_NUMBER (R_PPC64_UADDR64, 43) + RELOC_NUMBER (R_PPC64_REL64, 44) + RELOC_NUMBER (R_PPC64_PLT64, 45) + RELOC_NUMBER (R_PPC64_PLTREL64, 46) + RELOC_NUMBER (R_PPC64_TOC16, 47) + RELOC_NUMBER (R_PPC64_TOC16_LO, 48) + RELOC_NUMBER (R_PPC64_TOC16_HI, 49) + RELOC_NUMBER (R_PPC64_TOC16_HA, 50) + RELOC_NUMBER (R_PPC64_TOC, 51) + RELOC_NUMBER (R_PPC64_PLTGOT16, 52) + RELOC_NUMBER (R_PPC64_PLTGOT16_LO, 53) + RELOC_NUMBER (R_PPC64_PLTGOT16_HI, 54) + RELOC_NUMBER (R_PPC64_PLTGOT16_HA, 55) + + /* The following relocs were added in the 64-bit PowerPC ELF ABI + revision 1.2. */ + RELOC_NUMBER (R_PPC64_ADDR16_DS, 56) + RELOC_NUMBER (R_PPC64_ADDR16_LO_DS, 57) + RELOC_NUMBER (R_PPC64_GOT16_DS, 58) + RELOC_NUMBER (R_PPC64_GOT16_LO_DS, 59) + RELOC_NUMBER (R_PPC64_PLT16_LO_DS, 60) + RELOC_NUMBER (R_PPC64_SECTOFF_DS, 61) + RELOC_NUMBER (R_PPC64_SECTOFF_LO_DS, 62) + RELOC_NUMBER (R_PPC64_TOC16_DS, 63) + RELOC_NUMBER (R_PPC64_TOC16_LO_DS, 64) + RELOC_NUMBER (R_PPC64_PLTGOT16_DS, 65) + RELOC_NUMBER (R_PPC64_PLTGOT16_LO_DS, 66) + + /* Relocs added to support TLS. PowerPC64 ELF ABI revision 1.5. */ + RELOC_NUMBER (R_PPC64_TLS, 67) + RELOC_NUMBER (R_PPC64_DTPMOD64, 68) + RELOC_NUMBER (R_PPC64_TPREL16, 69) + RELOC_NUMBER (R_PPC64_TPREL16_LO, 70) + RELOC_NUMBER (R_PPC64_TPREL16_HI, 71) + RELOC_NUMBER (R_PPC64_TPREL16_HA, 72) + RELOC_NUMBER (R_PPC64_TPREL64, 73) + RELOC_NUMBER (R_PPC64_DTPREL16, 74) + RELOC_NUMBER (R_PPC64_DTPREL16_LO, 75) + RELOC_NUMBER (R_PPC64_DTPREL16_HI, 76) + RELOC_NUMBER (R_PPC64_DTPREL16_HA, 77) + RELOC_NUMBER (R_PPC64_DTPREL64, 78) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16, 79) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_LO, 80) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HI, 81) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HA, 82) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16, 83) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_LO, 84) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HI, 85) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HA, 86) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_DS, 87) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_LO_DS, 88) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_HI, 89) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_HA, 90) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_DS, 91) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_LO_DS, 92) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HI, 93) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HA, 94) + RELOC_NUMBER (R_PPC64_TPREL16_DS, 95) + RELOC_NUMBER (R_PPC64_TPREL16_LO_DS, 96) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHER, 97) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHERA, 98) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHEST, 99) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHESTA, 100) + RELOC_NUMBER (R_PPC64_DTPREL16_DS, 101) + RELOC_NUMBER (R_PPC64_DTPREL16_LO_DS, 102) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHER, 103) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHERA, 104) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHEST, 105) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHESTA, 106) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_PPC64_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_PPC64_GNU_VTENTRY, 254) + +END_RELOC_NUMBERS (R_PPC64_max) + +#define IS_PPC64_TLS_RELOC(R) \ + ((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA) + +/* Specify the start of the .glink section. */ +#define DT_PPC64_GLINK DT_LOPROC + +/* Specify the start and size of the .opd section. */ +#define DT_PPC64_OPD (DT_LOPROC + 1) +#define DT_PPC64_OPDSZ (DT_LOPROC + 2) + +#endif /* _ELF_PPC64_H */ diff --git a/include/elf/reloc-macros.h b/include/elf/reloc-macros.h new file mode 100644 index 000000000..4a3a60f7e --- /dev/null +++ b/include/elf/reloc-macros.h @@ -0,0 +1,101 @@ +/* Generic relocation support for BFD. + Copyright 1998, 1999, 2000, 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* These macros are used by the various *.h target specific header + files to either generate an enum containing all the known relocations + for that target, or if RELOC_MACROS_GEN_FUNC is defined, a recognition + function is generated instead. (This is used by binutils/readelf.c) + + Given a header file like this: + + START_RELOC_NUMBERS (foo) + RELOC_NUMBER (R_foo_NONE, 0) + RELOC_NUMBER (R_foo_32, 1) + EMPTY_RELOC (R_foo_good) + FAKE_RELOC (R_foo_illegal, 9) + END_RELOC_NUMBERS (R_foo_count) + + Then the following will be produced by default (ie if + RELOC_MACROS_GEN_FUNC is *not* defined). + + enum foo + { + R_foo_NONE = 0, + R_foo_32 = 1, + R_foo_good, + R_foo_illegal = 9, + R_foo_count + }; + + If RELOC_MACROS_GEN_FUNC *is* defined, then instead the + following function will be generated: + + static const char *foo (unsigned long rtype); + static const char * + foo (unsigned long rtype) + { + switch (rtype) + { + case 0: return "R_foo_NONE"; + case 1: return "R_foo_32"; + default: return NULL; + } + } + */ + +#ifndef _RELOC_MACROS_H +#define _RELOC_MACROS_H + +#ifdef RELOC_MACROS_GEN_FUNC + +/* This function takes the relocation number and returns the + string version name of the name of that relocation. If + the relocation is not recognised, NULL is returned. */ + +#define START_RELOC_NUMBERS(name) \ +static const char *name (unsigned long rtype); \ +static const char * \ +name (unsigned long rtype) \ +{ \ + switch (rtype) \ + { + +#define RELOC_NUMBER(name, number) \ + case number: return #name; + +#define FAKE_RELOC(name, number) +#define EMPTY_RELOC(name) + +#define END_RELOC_NUMBERS(name) \ + default: return NULL; \ + } \ +} + + +#else /* Default to generating enum. */ + +#define START_RELOC_NUMBERS(name) enum name { +#define RELOC_NUMBER(name, number) name = number, +#define FAKE_RELOC(name, number) name = number, +#define EMPTY_RELOC(name) name, +#define END_RELOC_NUMBERS(name) name }; + +#endif + +#endif /* RELOC_MACROS_H */ diff --git a/include/elf/s390.h b/include/elf/s390.h new file mode 100644 index 000000000..3a1306fa7 --- /dev/null +++ b/include/elf/s390.h @@ -0,0 +1,125 @@ +/* 390 ELF support for BFD. + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Carl B. Pedersen and Martin Schwidefsky. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef _ELF_390_H +#define _ELF_390_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Symbol types. */ + +#define STACK_REG 15 /* Global Stack reg */ +#define BACKL_REG 14 /* Global Backlink reg */ +#define BASE_REG 13 /* Global Base reg */ +#define GOT_REG 12 /* Holds addr of GOT */ + +#include "elf/reloc-macros.h" + +/* Relocation types. */ + +START_RELOC_NUMBERS (elf_s390_reloc_type) + RELOC_NUMBER (R_390_NONE, 0) /* No reloc. */ + RELOC_NUMBER (R_390_8, 1) /* Direct 8 bit. */ + RELOC_NUMBER (R_390_12, 2) /* Direct 12 bit. */ + RELOC_NUMBER (R_390_16, 3) /* Direct 16 bit. */ + RELOC_NUMBER (R_390_32, 4) /* Direct 32 bit. */ + RELOC_NUMBER (R_390_PC32, 5) /* PC relative 32 bit. */ + RELOC_NUMBER (R_390_GOT12, 6) /* 12 bit GOT offset. */ + RELOC_NUMBER (R_390_GOT32, 7) /* 32 bit GOT offset. */ + RELOC_NUMBER (R_390_PLT32, 8) /* 32 bit PC relative PLT address. */ + RELOC_NUMBER (R_390_COPY, 9) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_390_GLOB_DAT, 10) /* Create GOT entry. */ + RELOC_NUMBER (R_390_JMP_SLOT, 11) /* Create PLT entry. */ + RELOC_NUMBER (R_390_RELATIVE, 12) /* Adjust by program base. */ + RELOC_NUMBER (R_390_GOTOFF32, 13) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_390_GOTPC, 14) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_390_GOT16, 15) /* 16 bit GOT offset. */ + RELOC_NUMBER (R_390_PC16, 16) /* PC relative 16 bit. */ + RELOC_NUMBER (R_390_PC16DBL, 17) /* PC relative 16 bit shifted by 1. */ + RELOC_NUMBER (R_390_PLT16DBL, 18) /* 16 bit PC rel. PLT shifted by 1. */ + RELOC_NUMBER (R_390_PC32DBL, 19) /* PC relative 32 bit shifted by 1. */ + RELOC_NUMBER (R_390_PLT32DBL, 20) /* 32 bit PC rel. PLT shifted by 1. */ + RELOC_NUMBER (R_390_GOTPCDBL, 21) /* 32 bit PC rel. GOT shifted by 1. */ + RELOC_NUMBER (R_390_64, 22) /* Direct 64 bit. */ + RELOC_NUMBER (R_390_PC64, 23) /* PC relative 64 bit. */ + RELOC_NUMBER (R_390_GOT64, 24) /* 64 bit GOT offset. */ + RELOC_NUMBER (R_390_PLT64, 25) /* 64 bit PC relative PLT address. */ + RELOC_NUMBER (R_390_GOTENT, 26) /* 32 bit PC rel. to GOT entry >> 1. */ + RELOC_NUMBER (R_390_GOTOFF16, 27) /* 16 bit offset to GOT. */ + RELOC_NUMBER (R_390_GOTOFF64, 28) /* 64 bit offset to GOT. */ + RELOC_NUMBER (R_390_GOTPLT12, 29) /* 12 bit offset to jump slot. */ + RELOC_NUMBER (R_390_GOTPLT16, 30) /* 16 bit offset to jump slot. */ + RELOC_NUMBER (R_390_GOTPLT32, 31) /* 32 bit offset to jump slot. */ + RELOC_NUMBER (R_390_GOTPLT64, 32) /* 64 bit offset to jump slot. */ + RELOC_NUMBER (R_390_GOTPLTENT, 33) /* 32 bit rel. offset to jump slot. */ + RELOC_NUMBER (R_390_PLTOFF16, 34) /* 16 bit offset from GOT to PLT. */ + RELOC_NUMBER (R_390_PLTOFF32, 35) /* 32 bit offset from GOT to PLT. */ + RELOC_NUMBER (R_390_PLTOFF64, 36) /* 16 bit offset from GOT to PLT. */ + RELOC_NUMBER (R_390_TLS_LOAD, 37) /* Tag for load insn in TLS code. */ + RELOC_NUMBER (R_390_TLS_GDCALL, 38) /* Tag for function call in general + dynamic TLS code. */ + RELOC_NUMBER (R_390_TLS_LDCALL, 39) /* Tag for function call in local + dynamic TLS code. */ + RELOC_NUMBER (R_390_TLS_GD32, 40) /* Direct 32 bit for general dynamic + thread local data. */ + RELOC_NUMBER (R_390_TLS_GD64, 41) /* Direct 64 bit for general dynamic + thread local data. */ + RELOC_NUMBER (R_390_TLS_GOTIE12, 42)/* 12 bit GOT offset for static TLS + block offset. */ + RELOC_NUMBER (R_390_TLS_GOTIE32, 43)/* 32 bit GOT offset for static TLS + block offset. */ + RELOC_NUMBER (R_390_TLS_GOTIE64, 44)/* 64 bit GOT offset for static TLS + block offset. */ + RELOC_NUMBER (R_390_TLS_LDM32, 45) /* Direct 32 bit for local dynamic + thread local data in LD code. */ + RELOC_NUMBER (R_390_TLS_LDM64, 46) /* Direct 64 bit for local dynamic + thread local data in LD code. */ + RELOC_NUMBER (R_390_TLS_IE32, 47) /* 32 bit address of GOT entry for + negated static TLS block offset. */ + RELOC_NUMBER (R_390_TLS_IE64, 48) /* 64 bit address of GOT entry for + negated static TLS block offset. */ + RELOC_NUMBER (R_390_TLS_IEENT, 49) /* 32 bit rel. offset to GOT entry for + negated static TLS block offset. */ + RELOC_NUMBER (R_390_TLS_LE32, 50) /* 32 bit negated offset relative to + static TLS block. */ + RELOC_NUMBER (R_390_TLS_LE64, 51) /* 64 bit negated offset relative to + static TLS block. */ + RELOC_NUMBER (R_390_TLS_LDO32, 52) /* 32 bit offset relative to TLS + block. */ + RELOC_NUMBER (R_390_TLS_LDO64, 53) /* 64 bit offset relative to TLS + block. */ + RELOC_NUMBER (R_390_TLS_DTPMOD, 54) /* ID of module containing symbol. */ + RELOC_NUMBER (R_390_TLS_DTPOFF, 55) /* Offset in TLS block. */ + RELOC_NUMBER (R_390_TLS_TPOFF, 56) /* Negate offset in static TLS + block. */ + RELOC_NUMBER (R_390_20, 57) /* Direct 20 bit. */ + RELOC_NUMBER (R_390_GOT20, 58) /* 20 bit GOT offset. */ + RELOC_NUMBER (R_390_GOTPLT20, 59) /* 20 bit offset to jump slot. */ + RELOC_NUMBER (R_390_TLS_GOTIE20, 60)/* 20 bit GOT offset for statis TLS + block offset. */ + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_390_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_390_GNU_VTENTRY, 251) +END_RELOC_NUMBERS (R_390_max) + +#endif /* _ELF_390_H */ + + diff --git a/include/elf/sh.h b/include/elf/sh.h new file mode 100644 index 000000000..ddb387b18 --- /dev/null +++ b/include/elf/sh.h @@ -0,0 +1,224 @@ +/* SH ELF support for BFD. + Copyright 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_SH_H +#define _ELF_SH_H + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_SH_MACH_MASK 0x1f +#define EF_SH_UNKNOWN 0 /* For backwards compatibility. */ +#define EF_SH1 1 +#define EF_SH2 2 +#define EF_SH3 3 +#define EF_SH_DSP 4 +#define EF_SH3_DSP 5 +#define EF_SH4AL_DSP 6 +#define EF_SH3E 8 +#define EF_SH4 9 +#define EF_SH2E 11 +#define EF_SH4A 12 +#define EF_SH2A 13 + +#define EF_SH4_NOFPU 16 +#define EF_SH4A_NOFPU 17 +#define EF_SH4_NOMMU_NOFPU 18 +#define EF_SH2A_NOFPU 19 +#define EF_SH3_NOMMU 20 + +/* This one can only mix in objects from other EF_SH5 objects. */ +#define EF_SH5 10 + +/* Define the mapping from ELF to bfd mach numbers. + bfd_mach_* are defined in bfd_in2.h (generated from + archures.c). */ +#define EF_SH_BFD_TABLE \ +/* EF_SH_UNKNOWN */ bfd_mach_sh3 , \ +/* EF_SH1 */ bfd_mach_sh , \ +/* EF_SH2 */ bfd_mach_sh2 , \ +/* EF_SH3 */ bfd_mach_sh3 , \ +/* EF_SH_DSP */ bfd_mach_sh_dsp , \ +/* EF_SH3_DSP */ bfd_mach_sh3_dsp , \ +/* EF_SHAL_DSP */ bfd_mach_sh4al_dsp , \ +/* 7 */ 0, \ +/* EF_SH3E */ bfd_mach_sh3e , \ +/* EF_SH4 */ bfd_mach_sh4 , \ +/* EF_SH5 */ 0, \ +/* EF_SH2E */ bfd_mach_sh2e , \ +/* EF_SH4A */ bfd_mach_sh4a , \ +/* EF_SH2A */ bfd_mach_sh2a , \ +/* 14, 15 */ 0, 0, \ +/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ +/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ +/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +/* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \ +/* EF_SH3_NOMMU */ bfd_mach_sh3_nommu + +/* Convert arch_sh* into EF_SH*. */ +int sh_find_elf_flags (unsigned int arch_set); + +/* Convert bfd_mach_* into EF_SH*. */ +int sh_elf_get_flags_from_mach (unsigned long mach); + +/* Flags for the st_other symbol field. + Keep away from the STV_ visibility flags (bit 0..1). */ + +/* A reference to this symbol should by default add 1. */ +#define STO_SH5_ISA32 (1 << 2) + +/* Section contains only SHmedia code (no SHcompact code). */ +#define SHF_SH5_ISA32 0x40000000 + +/* Section contains both SHmedia and SHcompact code, and possibly also + constants. */ +#define SHF_SH5_ISA32_MIXED 0x20000000 + +/* If applied to a .cranges section, marks that the section is sorted by + increasing cr_addr values. */ +#define SHT_SH5_CR_SORTED 0x80000001 + +/* Symbol should be handled as DataLabel (attached to global SHN_UNDEF + symbols). */ +#define STT_DATALABEL STT_LOPROC + +#include "elf/reloc-macros.h" + +/* Relocations. */ +/* Relocations 10-32 and 128-255 are GNU extensions. + 25..32 and 10 are used for relaxation. */ +START_RELOC_NUMBERS (elf_sh_reloc_type) + RELOC_NUMBER (R_SH_NONE, 0) + RELOC_NUMBER (R_SH_DIR32, 1) + RELOC_NUMBER (R_SH_REL32, 2) + RELOC_NUMBER (R_SH_DIR8WPN, 3) + RELOC_NUMBER (R_SH_IND12W, 4) + RELOC_NUMBER (R_SH_DIR8WPL, 5) + RELOC_NUMBER (R_SH_DIR8WPZ, 6) + RELOC_NUMBER (R_SH_DIR8BP, 7) + RELOC_NUMBER (R_SH_DIR8W, 8) + RELOC_NUMBER (R_SH_DIR8L, 9) + + RELOC_NUMBER (R_SH_LOOP_START, 10) + RELOC_NUMBER (R_SH_LOOP_END, 11) + + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC, 12) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC, 21) + + RELOC_NUMBER (R_SH_GNU_VTINHERIT, 22) + RELOC_NUMBER (R_SH_GNU_VTENTRY, 23) + RELOC_NUMBER (R_SH_SWITCH8, 24) + RELOC_NUMBER (R_SH_SWITCH16, 25) + RELOC_NUMBER (R_SH_SWITCH32, 26) + RELOC_NUMBER (R_SH_USES, 27) + RELOC_NUMBER (R_SH_COUNT, 28) + RELOC_NUMBER (R_SH_ALIGN, 29) + RELOC_NUMBER (R_SH_CODE, 30) + RELOC_NUMBER (R_SH_DATA, 31) + RELOC_NUMBER (R_SH_LABEL, 32) + + RELOC_NUMBER (R_SH_DIR16, 33) + RELOC_NUMBER (R_SH_DIR8, 34) + RELOC_NUMBER (R_SH_DIR8UL, 35) + RELOC_NUMBER (R_SH_DIR8UW, 36) + RELOC_NUMBER (R_SH_DIR8U, 37) + RELOC_NUMBER (R_SH_DIR8SW, 38) + RELOC_NUMBER (R_SH_DIR8S, 39) + RELOC_NUMBER (R_SH_DIR4UL, 40) + RELOC_NUMBER (R_SH_DIR4UW, 41) + RELOC_NUMBER (R_SH_DIR4U, 42) + RELOC_NUMBER (R_SH_PSHA, 43) + RELOC_NUMBER (R_SH_PSHL, 44) + RELOC_NUMBER (R_SH_DIR5U, 45) + RELOC_NUMBER (R_SH_DIR6U, 46) + RELOC_NUMBER (R_SH_DIR6S, 47) + RELOC_NUMBER (R_SH_DIR10S, 48) + RELOC_NUMBER (R_SH_DIR10SW, 49) + RELOC_NUMBER (R_SH_DIR10SL, 50) + RELOC_NUMBER (R_SH_DIR10SQ, 51) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_2, 52) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_2, 52) + RELOC_NUMBER (R_SH_DIR16S, 53) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_3, 54) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_3, 143) + RELOC_NUMBER (R_SH_TLS_GD_32, 144) + RELOC_NUMBER (R_SH_TLS_LD_32, 145) + RELOC_NUMBER (R_SH_TLS_LDO_32, 146) + RELOC_NUMBER (R_SH_TLS_IE_32, 147) + RELOC_NUMBER (R_SH_TLS_LE_32, 148) + RELOC_NUMBER (R_SH_TLS_DTPMOD32, 149) + RELOC_NUMBER (R_SH_TLS_DTPOFF32, 150) + RELOC_NUMBER (R_SH_TLS_TPOFF32, 151) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_4, 152) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_4, 159) + RELOC_NUMBER (R_SH_GOT32, 160) + RELOC_NUMBER (R_SH_PLT32, 161) + RELOC_NUMBER (R_SH_COPY, 162) + RELOC_NUMBER (R_SH_GLOB_DAT, 163) + RELOC_NUMBER (R_SH_JMP_SLOT, 164) + RELOC_NUMBER (R_SH_RELATIVE, 165) + RELOC_NUMBER (R_SH_GOTOFF, 166) + RELOC_NUMBER (R_SH_GOTPC, 167) + RELOC_NUMBER (R_SH_GOTPLT32, 168) + RELOC_NUMBER (R_SH_GOT_LOW16, 169) + RELOC_NUMBER (R_SH_GOT_MEDLOW16, 170) + RELOC_NUMBER (R_SH_GOT_MEDHI16, 171) + RELOC_NUMBER (R_SH_GOT_HI16, 172) + RELOC_NUMBER (R_SH_GOTPLT_LOW16, 173) + RELOC_NUMBER (R_SH_GOTPLT_MEDLOW16, 174) + RELOC_NUMBER (R_SH_GOTPLT_MEDHI16, 175) + RELOC_NUMBER (R_SH_GOTPLT_HI16, 176) + RELOC_NUMBER (R_SH_PLT_LOW16, 177) + RELOC_NUMBER (R_SH_PLT_MEDLOW16, 178) + RELOC_NUMBER (R_SH_PLT_MEDHI16, 179) + RELOC_NUMBER (R_SH_PLT_HI16, 180) + RELOC_NUMBER (R_SH_GOTOFF_LOW16, 181) + RELOC_NUMBER (R_SH_GOTOFF_MEDLOW16, 182) + RELOC_NUMBER (R_SH_GOTOFF_MEDHI16, 183) + RELOC_NUMBER (R_SH_GOTOFF_HI16, 184) + RELOC_NUMBER (R_SH_GOTPC_LOW16, 185) + RELOC_NUMBER (R_SH_GOTPC_MEDLOW16, 186) + RELOC_NUMBER (R_SH_GOTPC_MEDHI16, 187) + RELOC_NUMBER (R_SH_GOTPC_HI16, 188) + RELOC_NUMBER (R_SH_GOT10BY4, 189) + RELOC_NUMBER (R_SH_GOTPLT10BY4, 190) + RELOC_NUMBER (R_SH_GOT10BY8, 191) + RELOC_NUMBER (R_SH_GOTPLT10BY8, 192) + RELOC_NUMBER (R_SH_COPY64, 193) + RELOC_NUMBER (R_SH_GLOB_DAT64, 194) + RELOC_NUMBER (R_SH_JMP_SLOT64, 195) + RELOC_NUMBER (R_SH_RELATIVE64, 196) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_5, 197) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_5, 241) + RELOC_NUMBER (R_SH_SHMEDIA_CODE, 242) + RELOC_NUMBER (R_SH_PT_16, 243) + RELOC_NUMBER (R_SH_IMMS16, 244) + RELOC_NUMBER (R_SH_IMMU16, 245) + RELOC_NUMBER (R_SH_IMM_LOW16, 246) + RELOC_NUMBER (R_SH_IMM_LOW16_PCREL, 247) + RELOC_NUMBER (R_SH_IMM_MEDLOW16, 248) + RELOC_NUMBER (R_SH_IMM_MEDLOW16_PCREL, 249) + RELOC_NUMBER (R_SH_IMM_MEDHI16, 250) + RELOC_NUMBER (R_SH_IMM_MEDHI16_PCREL, 251) + RELOC_NUMBER (R_SH_IMM_HI16, 252) + RELOC_NUMBER (R_SH_IMM_HI16_PCREL, 253) + RELOC_NUMBER (R_SH_64, 254) + RELOC_NUMBER (R_SH_64_PCREL, 255) +END_RELOC_NUMBERS (R_SH_max) + +#endif diff --git a/include/elf/sparc.h b/include/elf/sparc.h new file mode 100644 index 000000000..2d28d26f9 --- /dev/null +++ b/include/elf/sparc.h @@ -0,0 +1,175 @@ +/* SPARC ELF support for BFD. + Copyright 1996, 1997, 1998, 1999, 2000, 2002 Free Software Foundation, Inc. + By Doug Evans, Cygnus Support, <dje@cygnus.com>. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_SPARC_H +#define _ELF_SPARC_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* These are defined by Sun. */ + +#define EF_SPARC_32PLUS_MASK 0xffff00 /* bits indicating V8+ type */ +#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ +#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ +#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ +#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ + +#define EF_SPARC_LEDATA 0x800000 /* little endian data */ + +/* This name is used in the V9 ABI. */ +#define EF_SPARC_EXT_MASK 0xffff00 /* reserved for vendor extensions */ + +/* V9 memory models */ +#define EF_SPARCV9_MM 0x3 /* memory model mask */ +#define EF_SPARCV9_TSO 0x0 /* total store ordering */ +#define EF_SPARCV9_PSO 0x1 /* partial store ordering */ +#define EF_SPARCV9_RMO 0x2 /* relaxed store ordering */ + +/* Section indices. */ + +#define SHN_BEFORE 0xff00 /* used with SHF_ORDERED */ +#define SHN_AFTER 0xff01 /* used with SHF_ORDERED */ + +/* Section flags. */ + +#define SHF_EXCLUDE 0x80000000 /* exclude from linking */ +#define SHF_ORDERED 0x40000000 /* treat sh_link,sh_info specially */ + +/* Symbol types. */ + +#define STT_REGISTER 13 /* global reg reserved to app. */ + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_sparc_reloc_type) + RELOC_NUMBER (R_SPARC_NONE, 0) + RELOC_NUMBER (R_SPARC_8, 1) + RELOC_NUMBER (R_SPARC_16, 2) + RELOC_NUMBER (R_SPARC_32, 3) + RELOC_NUMBER (R_SPARC_DISP8, 4) + RELOC_NUMBER (R_SPARC_DISP16, 5) + RELOC_NUMBER (R_SPARC_DISP32, 6) + RELOC_NUMBER (R_SPARC_WDISP30, 7) + RELOC_NUMBER (R_SPARC_WDISP22, 8) + RELOC_NUMBER (R_SPARC_HI22, 9) + RELOC_NUMBER (R_SPARC_22, 10) + RELOC_NUMBER (R_SPARC_13, 11) + RELOC_NUMBER (R_SPARC_LO10, 12) + RELOC_NUMBER (R_SPARC_GOT10, 13) + RELOC_NUMBER (R_SPARC_GOT13, 14) + RELOC_NUMBER (R_SPARC_GOT22, 15) + RELOC_NUMBER (R_SPARC_PC10, 16) + RELOC_NUMBER (R_SPARC_PC22, 17) + RELOC_NUMBER (R_SPARC_WPLT30, 18) + RELOC_NUMBER (R_SPARC_COPY, 19) + RELOC_NUMBER (R_SPARC_GLOB_DAT, 20) + RELOC_NUMBER (R_SPARC_JMP_SLOT, 21) + RELOC_NUMBER (R_SPARC_RELATIVE, 22) + RELOC_NUMBER (R_SPARC_UA32, 23) + + /* ??? These 6 relocs are new but not currently used. For binary + compatibility in the sparc64-elf toolchain, we leave them out. + A non-binary upward compatible change is expected for sparc64-elf. */ +#ifndef SPARC64_OLD_RELOCS + /* ??? New relocs on the UltraSPARC. Not sure what they're for yet. */ + RELOC_NUMBER (R_SPARC_PLT32, 24) + RELOC_NUMBER (R_SPARC_HIPLT22, 25) + RELOC_NUMBER (R_SPARC_LOPLT10, 26) + RELOC_NUMBER (R_SPARC_PCPLT32, 27) + RELOC_NUMBER (R_SPARC_PCPLT22, 28) + RELOC_NUMBER (R_SPARC_PCPLT10, 29) +#endif + + /* v9 relocs */ + RELOC_NUMBER (R_SPARC_10, 30) + RELOC_NUMBER (R_SPARC_11, 31) + RELOC_NUMBER (R_SPARC_64, 32) + RELOC_NUMBER (R_SPARC_OLO10, 33) + RELOC_NUMBER (R_SPARC_HH22, 34) + RELOC_NUMBER (R_SPARC_HM10, 35) + RELOC_NUMBER (R_SPARC_LM22, 36) + RELOC_NUMBER (R_SPARC_PC_HH22, 37) + RELOC_NUMBER (R_SPARC_PC_HM10, 38) + RELOC_NUMBER (R_SPARC_PC_LM22, 39) + RELOC_NUMBER (R_SPARC_WDISP16, 40) + RELOC_NUMBER (R_SPARC_WDISP19, 41) + RELOC_NUMBER (R_SPARC_UNUSED_42, 42) + RELOC_NUMBER (R_SPARC_7, 43) + RELOC_NUMBER (R_SPARC_5, 44) + RELOC_NUMBER (R_SPARC_6, 45) + RELOC_NUMBER (R_SPARC_DISP64, 46) + RELOC_NUMBER (R_SPARC_PLT64, 47) + RELOC_NUMBER (R_SPARC_HIX22, 48) + RELOC_NUMBER (R_SPARC_LOX10, 49) + RELOC_NUMBER (R_SPARC_H44, 50) + RELOC_NUMBER (R_SPARC_M44, 51) + RELOC_NUMBER (R_SPARC_L44, 52) + RELOC_NUMBER (R_SPARC_REGISTER, 53) + RELOC_NUMBER (R_SPARC_UA64, 54) + RELOC_NUMBER (R_SPARC_UA16, 55) + + RELOC_NUMBER (R_SPARC_TLS_GD_HI22, 56) + RELOC_NUMBER (R_SPARC_TLS_GD_LO10, 57) + RELOC_NUMBER (R_SPARC_TLS_GD_ADD, 58) + RELOC_NUMBER (R_SPARC_TLS_GD_CALL, 59) + RELOC_NUMBER (R_SPARC_TLS_LDM_HI22, 60) + RELOC_NUMBER (R_SPARC_TLS_LDM_LO10, 61) + RELOC_NUMBER (R_SPARC_TLS_LDM_ADD, 62) + RELOC_NUMBER (R_SPARC_TLS_LDM_CALL, 63) + RELOC_NUMBER (R_SPARC_TLS_LDO_HIX22, 64) + RELOC_NUMBER (R_SPARC_TLS_LDO_LOX10, 65) + RELOC_NUMBER (R_SPARC_TLS_LDO_ADD, 66) + RELOC_NUMBER (R_SPARC_TLS_IE_HI22, 67) + RELOC_NUMBER (R_SPARC_TLS_IE_LO10, 68) + RELOC_NUMBER (R_SPARC_TLS_IE_LD, 69) + RELOC_NUMBER (R_SPARC_TLS_IE_LDX, 70) + RELOC_NUMBER (R_SPARC_TLS_IE_ADD, 71) + RELOC_NUMBER (R_SPARC_TLS_LE_HIX22, 72) + RELOC_NUMBER (R_SPARC_TLS_LE_LOX10, 73) + RELOC_NUMBER (R_SPARC_TLS_DTPMOD32, 74) + RELOC_NUMBER (R_SPARC_TLS_DTPMOD64, 75) + RELOC_NUMBER (R_SPARC_TLS_DTPOFF32, 76) + RELOC_NUMBER (R_SPARC_TLS_DTPOFF64, 77) + RELOC_NUMBER (R_SPARC_TLS_TPOFF32, 78) + RELOC_NUMBER (R_SPARC_TLS_TPOFF64, 79) + + EMPTY_RELOC (R_SPARC_max_std) + + RELOC_NUMBER (R_SPARC_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_SPARC_GNU_VTENTRY, 251) + RELOC_NUMBER (R_SPARC_REV32, 252) + +END_RELOC_NUMBERS (R_SPARC_max) + +/* Relocation macros. */ + +#define ELF64_R_TYPE_DATA(info) \ + (((bfd_signed_vma)(ELF64_R_TYPE(info) >> 8) ^ 0x800000) - 0x800000) +#define ELF64_R_TYPE_ID(info) \ + ((info) & 0xff) +#define ELF64_R_TYPE_INFO(data, type) \ + (((bfd_vma) ((data) & 0xffffff) << 8) | (bfd_vma) (type)) + +/* Values for Elf64_Dyn.d_tag. */ + +#define DT_SPARC_REGISTER 0x70000001 + +#endif /* _ELF_SPARC_H */ diff --git a/include/elf/v850.h b/include/elf/v850.h new file mode 100644 index 000000000..7d5110b33 --- /dev/null +++ b/include/elf/v850.h @@ -0,0 +1,121 @@ +/* V850 ELF support for BFD. + Copyright 1997, 1998, 2000, 2002, 2003 Free Software Foundation, Inc. + Created by Michael Meissner, Cygnus Support <meissner@cygnus.com> + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MIPS ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_V850_H +#define _ELF_V850_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Four bit V850 architecture field. */ +#define EF_V850_ARCH 0xf0000000 + +/* v850 code. */ +#define E_V850_ARCH 0x00000000 + +/* v850e code. */ +#define E_V850E_ARCH 0x10000000 + +/* v850e1 code. */ +#define E_V850E1_ARCH 0x20000000 + + +/* Flags for the st_other field. */ +#define V850_OTHER_SDA 0x01 /* Symbol had SDA relocations. */ +#define V850_OTHER_ZDA 0x02 /* Symbol had ZDA relocations. */ +#define V850_OTHER_TDA 0x04 /* Symbol had TDA relocations. */ +#define V850_OTHER_TDA_BYTE 0x08 /* Symbol had TDA byte relocations. */ +#define V850_OTHER_ERROR 0x80 /* Symbol had an error reported. */ + +/* V850 relocations. */ +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (v850_reloc_type) + RELOC_NUMBER (R_V850_NONE, 0) + RELOC_NUMBER (R_V850_9_PCREL, 1) + RELOC_NUMBER (R_V850_22_PCREL, 2) + RELOC_NUMBER (R_V850_HI16_S, 3) + RELOC_NUMBER (R_V850_HI16, 4) + RELOC_NUMBER (R_V850_LO16, 5) + RELOC_NUMBER (R_V850_ABS32, 6) + RELOC_NUMBER (R_V850_16, 7) + RELOC_NUMBER (R_V850_8, 8) + RELOC_NUMBER( R_V850_SDA_16_16_OFFSET, 9) /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_SDA_15_16_OFFSET, 10) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER( R_V850_ZDA_16_16_OFFSET, 11) /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_ZDA_15_16_OFFSET, 12) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER( R_V850_TDA_6_8_OFFSET, 13) /* For sst.w, sld.w */ + RELOC_NUMBER( R_V850_TDA_7_8_OFFSET, 14) /* For sst.h, sld.h */ + RELOC_NUMBER( R_V850_TDA_7_7_OFFSET, 15) /* For sst.b, sld.b */ + RELOC_NUMBER( R_V850_TDA_16_16_OFFSET, 16) /* For set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_TDA_4_5_OFFSET, 17) /* For sld.hu */ + RELOC_NUMBER( R_V850_TDA_4_4_OFFSET, 18) /* For sld.bu */ + RELOC_NUMBER( R_V850_SDA_16_16_SPLIT_OFFSET, 19) /* For ld.bu */ + RELOC_NUMBER( R_V850_ZDA_16_16_SPLIT_OFFSET, 20) /* For ld.bu */ + RELOC_NUMBER( R_V850_CALLT_6_7_OFFSET, 21) /* For callt */ + RELOC_NUMBER( R_V850_CALLT_16_16_OFFSET, 22) /* For callt */ + RELOC_NUMBER (R_V850_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_V850_GNU_VTENTRY, 24) + RELOC_NUMBER (R_V850_LONGCALL, 25) + RELOC_NUMBER (R_V850_LONGJUMP, 26) + RELOC_NUMBER (R_V850_ALIGN, 27) + RELOC_NUMBER (R_V850_REL32, 28) +END_RELOC_NUMBERS (R_V850_max) + + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Small data area common symbol. */ +#define SHN_V850_SCOMMON 0xff00 + +/* Tiny data area common symbol. */ +#define SHN_V850_TCOMMON 0xff01 + +/* Zero data area common symbol. */ +#define SHN_V850_ZCOMMON 0xff02 + + +/* Processor specific section types. */ + +/* Section contains the .scommon data. */ +#define SHT_V850_SCOMMON 0x70000000 + +/* Section contains the .scommon data. */ +#define SHT_V850_TCOMMON 0x70000001 + +/* Section contains the .scommon data. */ +#define SHT_V850_ZCOMMON 0x70000002 + +/* Processor specific section flags. */ + +/* This section must be in the small data area (pointed to by GP). */ +#define SHF_V850_GPREL 0x10000000 + +/* This section must be in the tiny data area (pointed to by EP). */ +#define SHF_V850_EPREL 0x20000000 + +/* This section must be in the zero data area (pointed to by R0). */ +#define SHF_V850_R0REL 0x40000000 + +#endif /* _ELF_V850_H */ diff --git a/include/elf/vax.h b/include/elf/vax.h new file mode 100644 index 000000000..c1b5c2b30 --- /dev/null +++ b/include/elf/vax.h @@ -0,0 +1,51 @@ +/* VAX ELF support for BFD. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by Matt Thomas <matt@3am-software.com>. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_VAX_H +#define _ELF_VAX_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_vax_reloc_type) + RELOC_NUMBER (R_VAX_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_VAX_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_VAX_16, 2) /* Direct 16 bit */ + RELOC_NUMBER (R_VAX_8, 3) /* Direct 8 bit */ + RELOC_NUMBER (R_VAX_PC32, 4) /* PC relative 32 bit */ + RELOC_NUMBER (R_VAX_PC16, 5) /* PC relative 16 bit */ + RELOC_NUMBER (R_VAX_PC8, 6) /* PC relative 8 bit */ + RELOC_NUMBER (R_VAX_GOT32, 7) /* 32 bit PC relative GOT entry */ + RELOC_NUMBER (R_VAX_PLT32, 13) /* 32 bit PC relative PLT address */ + RELOC_NUMBER (R_VAX_COPY, 19) /* Copy symbol at runtime */ + RELOC_NUMBER (R_VAX_GLOB_DAT, 20) /* Create GOT entry */ + RELOC_NUMBER (R_VAX_JMP_SLOT, 21) /* Create PLT entry */ + RELOC_NUMBER (R_VAX_RELATIVE, 22) /* Adjust by program base */ + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_VAX_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_VAX_GNU_VTENTRY, 24) +END_RELOC_NUMBERS (R_VAX_max) + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_VAX_NONPIC 0x0001 /* Object contains non-PIC code */ +#define EF_VAX_DFLOAT 0x0100 /* Object contains D-Float insn. */ +#define EF_VAX_GFLOAT 0x0200 /* Object contains G-Float insn. */ + +#endif diff --git a/include/elf/x86-64.h b/include/elf/x86-64.h new file mode 100644 index 000000000..7e9100dba --- /dev/null +++ b/include/elf/x86-64.h @@ -0,0 +1,56 @@ +/* x86_64 ELF support for BFD. + Copyright (C) 2000, 2002 Free Software Foundation, Inc. + Contributed by Jan Hubicka <jh@suse.cz> + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_X86_64_H +#define _ELF_X86_64_H + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_x86_64_reloc_type) + RELOC_NUMBER (R_X86_64_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_X86_64_64, 1) /* Direct 64 bit */ + RELOC_NUMBER (R_X86_64_PC32, 2) /* PC relative 32 bit signed */ + RELOC_NUMBER (R_X86_64_GOT32, 3) /* 32 bit GOT entry */ + RELOC_NUMBER (R_X86_64_PLT32, 4) /* 32 bit PLT address */ + RELOC_NUMBER (R_X86_64_COPY, 5) /* Copy symbol at runtime */ + RELOC_NUMBER (R_X86_64_GLOB_DAT, 6) /* Create GOT entry */ + RELOC_NUMBER (R_X86_64_JUMP_SLOT,7) /* Create PLT entry */ + RELOC_NUMBER (R_X86_64_RELATIVE, 8) /* Adjust by program base */ + RELOC_NUMBER (R_X86_64_GOTPCREL, 9) /* 32 bit signed pc relative + offset to GOT */ + RELOC_NUMBER (R_X86_64_32, 10) /* Direct 32 bit zero extended */ + RELOC_NUMBER (R_X86_64_32S, 11) /* Direct 32 bit sign extended */ + RELOC_NUMBER (R_X86_64_16, 12) /* Direct 16 bit zero extended */ + RELOC_NUMBER (R_X86_64_PC16, 13) /* 16 bit sign extended pc relative*/ + RELOC_NUMBER (R_X86_64_8, 14) /* Direct 8 bit sign extended */ + RELOC_NUMBER (R_X86_64_PC8, 15) /* 8 bit sign extended pc relative*/ + RELOC_NUMBER (R_X86_64_DTPMOD64, 16) /* ID of module containing symbol */ + RELOC_NUMBER (R_X86_64_DTPOFF64, 17) /* Offset in TLS block */ + RELOC_NUMBER (R_X86_64_TPOFF64, 18) /* Offset in initial TLS block */ + RELOC_NUMBER (R_X86_64_TLSGD, 19) /* PC relative offset to GD GOT block */ + RELOC_NUMBER (R_X86_64_TLSLD, 20) /* PC relative offset to LD GOT block */ + RELOC_NUMBER (R_X86_64_DTPOFF32, 21) /* Offset in TLS block */ + RELOC_NUMBER (R_X86_64_GOTTPOFF, 22) /* PC relative offset to IE GOT entry */ + RELOC_NUMBER (R_X86_64_TPOFF32, 23) /* Offset in initial TLS block */ + RELOC_NUMBER (R_X86_64_GNU_VTINHERIT, 250) /* GNU C++ hack */ + RELOC_NUMBER (R_X86_64_GNU_VTENTRY, 251) /* GNU C++ hack */ +END_RELOC_NUMBERS (R_X86_64_max) + +#endif diff --git a/include/elf/xstormy16.h b/include/elf/xstormy16.h new file mode 100644 index 000000000..6b1e98f57 --- /dev/null +++ b/include/elf/xstormy16.h @@ -0,0 +1,57 @@ +/* XSTORMY16 ELF support for BFD. + Copyright (C) 2001, 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_XSTORMY16_H +#define _ELF_XSTORMY16_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_xstormy16_reloc_type) + RELOC_NUMBER (R_XSTORMY16_NONE, 0) + + RELOC_NUMBER (R_XSTORMY16_32, 1) + RELOC_NUMBER (R_XSTORMY16_16, 2) + RELOC_NUMBER (R_XSTORMY16_8, 3) + RELOC_NUMBER (R_XSTORMY16_PC32, 4) + RELOC_NUMBER (R_XSTORMY16_PC16, 5) + RELOC_NUMBER (R_XSTORMY16_PC8, 6) + + RELOC_NUMBER (R_XSTORMY16_REL_12, 7) + RELOC_NUMBER (R_XSTORMY16_24, 8) + RELOC_NUMBER (R_XSTORMY16_FPTR16, 9) + + RELOC_NUMBER (R_XSTORMY16_LO16, 10) + RELOC_NUMBER (R_XSTORMY16_HI16, 11) + RELOC_NUMBER (R_XSTORMY16_12, 12) + + RELOC_NUMBER (R_XSTORMY16_GNU_VTINHERIT, 128) + RELOC_NUMBER (R_XSTORMY16_GNU_VTENTRY, 129) +END_RELOC_NUMBERS (R_XSTORMY16_max) + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & XSTORMY16_INSN_MASK) == XSTORMY16_INSN_VALUE), and similarly + for the data space. See also `ld/emulparams/elf32xstormy16.sh'. */ +#define XSTORMY16_DATA_MASK 0xffc00000 +#define XSTORMY16_DATA_VALUE 0x00000000 +#define XSTORMY16_INSN_MASK 0xffc00000 +#define XSTORMY16_INSN_VALUE 0x00400000 + +#endif /* _ELF_XSTORMY16_H */ diff --git a/include/elf/xtensa.h b/include/elf/xtensa.h new file mode 100644 index 000000000..6c584c715 --- /dev/null +++ b/include/elf/xtensa.h @@ -0,0 +1,88 @@ +/* Xtensa ELF support for BFD. + Copyright 2003 Free Software Foundation, Inc. + Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ + +/* This file holds definitions specific to the Xtensa ELF ABI. */ + +#ifndef _ELF_XTENSA_H +#define _ELF_XTENSA_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_xtensa_reloc_type) + RELOC_NUMBER (R_XTENSA_NONE, 0) + RELOC_NUMBER (R_XTENSA_32, 1) + RELOC_NUMBER (R_XTENSA_RTLD, 2) + RELOC_NUMBER (R_XTENSA_GLOB_DAT, 3) + RELOC_NUMBER (R_XTENSA_JMP_SLOT, 4) + RELOC_NUMBER (R_XTENSA_RELATIVE, 5) + RELOC_NUMBER (R_XTENSA_PLT, 6) + RELOC_NUMBER (R_XTENSA_OP0, 8) + RELOC_NUMBER (R_XTENSA_OP1, 9) + RELOC_NUMBER (R_XTENSA_OP2, 10) + RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11) + RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12) + RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15) + RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16) +END_RELOC_NUMBERS (R_XTENSA_max) + +/* Processor-specific flags for the ELF header e_flags field. */ + +/* Four-bit Xtensa machine type field. */ +#define EF_XTENSA_MACH 0x0000000f + +/* Various CPU types. */ +#define E_XTENSA_MACH 0x00000000 + +/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. + Highly unlikely, but what the heck. */ + +#define EF_XTENSA_XT_INSN 0x00000100 +#define EF_XTENSA_XT_LIT 0x00000200 + + +/* Processor-specific dynamic array tags. */ + +/* Offset of the table that records the GOT location(s). */ +#define DT_XTENSA_GOT_LOC_OFF 0x70000000 + +/* Number of entries in the GOT location table. */ +#define DT_XTENSA_GOT_LOC_SZ 0x70000001 + + +/* Definitions for instruction and literal property tables. The + tables for ".gnu.linkonce.*" sections are placed in the following + sections: + + instruction tables: .gnu.linkonce.x.* + literal tables: .gnu.linkonce.p.* +*/ + +#define XTENSA_INSN_SEC_NAME ".xt.insn" +#define XTENSA_LIT_SEC_NAME ".xt.lit" + +typedef struct property_table_entry_t +{ + bfd_vma address; + bfd_vma size; +} property_table_entry; + +#endif /* _ELF_XTENSA_H */ diff --git a/include/fibheap.h b/include/fibheap.h new file mode 100644 index 000000000..4eebaf13b --- /dev/null +++ b/include/fibheap.h @@ -0,0 +1,86 @@ +/* A Fibonacci heap datatype. + Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by Daniel Berlin (dan@cgsoftware.com). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Fibonacci heaps are somewhat complex, but, there's an article in + DDJ that explains them pretty well: + + http://www.ddj.com/articles/1997/9701/9701o/9701o.htm?topic=algoritms + + Introduction to algorithms by Corman and Rivest also goes over them. + + The original paper that introduced them is "Fibonacci heaps and their + uses in improved network optimization algorithms" by Tarjan and + Fredman (JACM 34(3), July 1987). + + Amortized and real worst case time for operations: + + ExtractMin: O(lg n) amortized. O(n) worst case. + DecreaseKey: O(1) amortized. O(lg n) worst case. + Insert: O(2) amortized. O(1) actual. + Union: O(1) amortized. O(1) actual. */ + +#ifndef _FIBHEAP_H_ +#define _FIBHEAP_H_ + +#include "ansidecl.h" + +typedef long fibheapkey_t; + +typedef struct fibheap +{ + size_t nodes; + struct fibnode *min; + struct fibnode *root; +} *fibheap_t; + +typedef struct fibnode +{ + struct fibnode *parent; + struct fibnode *child; + struct fibnode *left; + struct fibnode *right; + fibheapkey_t key; + void *data; +#ifdef __GNUC__ + __extension__ unsigned long int degree : 31; + __extension__ unsigned long int mark : 1; +#else + unsigned int degree : 31; + unsigned int mark : 1; +#endif +} *fibnode_t; + +extern fibheap_t fibheap_new PARAMS ((void)); +extern fibnode_t fibheap_insert PARAMS ((fibheap_t, fibheapkey_t, void *)); +extern int fibheap_empty PARAMS ((fibheap_t)); +extern fibheapkey_t fibheap_min_key PARAMS ((fibheap_t)); +extern fibheapkey_t fibheap_replace_key PARAMS ((fibheap_t, fibnode_t, + fibheapkey_t)); +extern void *fibheap_replace_key_data PARAMS ((fibheap_t, fibnode_t, + fibheapkey_t, void *)); +extern void *fibheap_extract_min PARAMS ((fibheap_t)); +extern void *fibheap_min PARAMS ((fibheap_t)); +extern void *fibheap_replace_data PARAMS ((fibheap_t, fibnode_t, void *)); +extern void *fibheap_delete_node PARAMS ((fibheap_t, fibnode_t)); +extern void fibheap_delete PARAMS ((fibheap_t)); +extern fibheap_t fibheap_union PARAMS ((fibheap_t, fibheap_t)); + +#endif /* _FIBHEAP_H_ */ diff --git a/include/filenames.h b/include/filenames.h new file mode 100644 index 000000000..ca9e2732a --- /dev/null +++ b/include/filenames.h @@ -0,0 +1,51 @@ +/* Macros for taking apart, interpreting and processing file names. + + These are here because some non-Posix (a.k.a. DOSish) systems have + drive letter brain-damage at the beginning of an absolute file name, + use forward- and back-slash in path names interchangeably, and + some of them have case-insensitive file names. + + Copyright 2000, 2001 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef FILENAMES_H +#define FILENAMES_H + +#if defined(__MSDOS__) || defined(_WIN32) || defined(__OS2__) || defined (__CYGWIN__) + +#ifndef HAVE_DOS_BASED_FILE_SYSTEM +#define HAVE_DOS_BASED_FILE_SYSTEM 1 +#endif + +#define IS_DIR_SEPARATOR(c) ((c) == '/' || (c) == '\\') +/* Note that IS_ABSOLUTE_PATH accepts d:foo as well, although it is + only semi-absolute. This is because the users of IS_ABSOLUTE_PATH + want to know whether to prepend the current working directory to + a file name, which should not be done with a name like d:foo. */ +#define IS_ABSOLUTE_PATH(f) (IS_DIR_SEPARATOR((f)[0]) || (((f)[0]) && ((f)[1] == ':'))) +#define FILENAME_CMP(s1, s2) strcasecmp(s1, s2) + +#else /* not DOSish */ + +#define IS_DIR_SEPARATOR(c) ((c) == '/') +#define IS_ABSOLUTE_PATH(f) (IS_DIR_SEPARATOR((f)[0])) +#define FILENAME_CMP(s1, s2) strcmp(s1, s2) + +#endif /* not DOSish */ + +#endif /* FILENAMES_H */ diff --git a/include/floatformat.h b/include/floatformat.h new file mode 100644 index 000000000..a8244ada5 --- /dev/null +++ b/include/floatformat.h @@ -0,0 +1,133 @@ +/* IEEE floating point support declarations, for GDB, the GNU Debugger. + Copyright 1991, 1994, 1995, 1997, 2000, 2003 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (FLOATFORMAT_H) +#define FLOATFORMAT_H 1 + +#include "ansidecl.h" + +/* A floatformat consists of a sign bit, an exponent and a mantissa. Once the + bytes are concatenated according to the byteorder flag, then each of those + fields is contiguous. We number the bits with 0 being the most significant + (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field + contains with the *_start and *_len fields. */ + +/* What is the order of the bytes. */ + +enum floatformat_byteorders { + + /* Standard little endian byte order. + EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */ + + floatformat_little, + + /* Standard big endian byte order. + EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */ + + floatformat_big, + + /* Little endian byte order but big endian word order. + EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */ + + floatformat_littlebyte_bigword + +}; + +enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no }; + +struct floatformat +{ + enum floatformat_byteorders byteorder; + unsigned int totalsize; /* Total size of number in bits */ + + /* Sign bit is always one bit long. 1 means negative, 0 means positive. */ + unsigned int sign_start; + + unsigned int exp_start; + unsigned int exp_len; + /* Bias added to a "true" exponent to form the biased exponent. It + is intentionally signed as, otherwize, -exp_bias can turn into a + very large number (e.g., given the exp_bias of 0x3fff and a 64 + bit long, the equation (long)(1 - exp_bias) evaluates to + 4294950914) instead of -16382). */ + int exp_bias; + /* Exponent value which indicates NaN. This is the actual value stored in + the float, not adjusted by the exp_bias. This usually consists of all + one bits. */ + unsigned int exp_nan; + + unsigned int man_start; + unsigned int man_len; + + /* Is the integer bit explicit or implicit? */ + enum floatformat_intbit intbit; + + /* Internal name for debugging. */ + const char *name; + + /* Validator method. */ + int (*is_valid) PARAMS ((const struct floatformat *fmt, const char *from)); +}; + +/* floatformats for IEEE single and double, big and little endian. */ + +extern const struct floatformat floatformat_ieee_single_big; +extern const struct floatformat floatformat_ieee_single_little; +extern const struct floatformat floatformat_ieee_double_big; +extern const struct floatformat floatformat_ieee_double_little; + +/* floatformat for ARM IEEE double, little endian bytes and big endian words */ + +extern const struct floatformat floatformat_ieee_double_littlebyte_bigword; + +/* floatformats for various extendeds. */ + +extern const struct floatformat floatformat_i387_ext; +extern const struct floatformat floatformat_m68881_ext; +extern const struct floatformat floatformat_i960_ext; +extern const struct floatformat floatformat_m88110_ext; +extern const struct floatformat floatformat_m88110_harris_ext; +extern const struct floatformat floatformat_arm_ext_big; +extern const struct floatformat floatformat_arm_ext_littlebyte_bigword; +/* IA-64 Floating Point register spilt into memory. */ +extern const struct floatformat floatformat_ia64_spill_big; +extern const struct floatformat floatformat_ia64_spill_little; +extern const struct floatformat floatformat_ia64_quad_big; +extern const struct floatformat floatformat_ia64_quad_little; + +/* Convert from FMT to a double. + FROM is the address of the extended float. + Store the double in *TO. */ + +extern void +floatformat_to_double PARAMS ((const struct floatformat *, const char *, double *)); + +/* The converse: convert the double *FROM to FMT + and store where TO points. */ + +extern void +floatformat_from_double PARAMS ((const struct floatformat *, + const double *, char *)); + +/* Return non-zero iff the data at FROM is a valid number in format FMT. */ + +extern int +floatformat_is_valid PARAMS ((const struct floatformat *fmt, const char *from)); + +#endif /* defined (FLOATFORMAT_H) */ diff --git a/include/fnmatch.h b/include/fnmatch.h new file mode 100644 index 000000000..37d23ee1b --- /dev/null +++ b/include/fnmatch.h @@ -0,0 +1,70 @@ +/* Copyright 1991, 1992, 1993, 1996 Free Software Foundation, Inc. + +NOTE: The canonical source of this file is maintained with the GNU C Library. +Bugs can be reported to bug-glibc@prep.ai.mit.edu. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef _FNMATCH_H + +#define _FNMATCH_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__cplusplus) || (defined (__STDC__) && __STDC__) +#undef __P +#define __P(args) args +#else /* Not C++ or ANSI C. */ +#undef __P +#define __P(args) () +/* We can get away without defining `const' here only because in this file + it is used only inside the prototype for `fnmatch', which is elided in + non-ANSI C where `const' is problematical. */ +#endif /* C++ or ANSI C. */ + + +/* We #undef these before defining them because some losing systems + (HP-UX A.08.07 for example) define these in <unistd.h>. */ +#undef FNM_PATHNAME +#undef FNM_NOESCAPE +#undef FNM_PERIOD + +/* Bits set in the FLAGS argument to `fnmatch'. */ +#define FNM_PATHNAME (1 << 0) /* No wildcard can ever match `/'. */ +#define FNM_NOESCAPE (1 << 1) /* Backslashes don't quote special chars. */ +#define FNM_PERIOD (1 << 2) /* Leading `.' is matched only explicitly. */ + +#if !defined (_POSIX_C_SOURCE) || _POSIX_C_SOURCE < 2 || defined (_GNU_SOURCE) +#define FNM_FILE_NAME FNM_PATHNAME /* Preferred GNU name. */ +#define FNM_LEADING_DIR (1 << 3) /* Ignore `/...' after a match. */ +#define FNM_CASEFOLD (1 << 4) /* Compare without regard to case. */ +#endif + +/* Value returned by `fnmatch' if STRING does not match PATTERN. */ +#define FNM_NOMATCH 1 + +/* Match STRING against the filename pattern PATTERN, + returning zero if it matches, FNM_NOMATCH if not. */ +extern int fnmatch __P ((const char *__pattern, const char *__string, + int __flags)); + +#ifdef __cplusplus +} +#endif + +#endif /* fnmatch.h */ diff --git a/include/fopen-bin.h b/include/fopen-bin.h new file mode 100644 index 000000000..b868f63d4 --- /dev/null +++ b/include/fopen-bin.h @@ -0,0 +1,27 @@ +/* Macros for the 'type' part of an fopen, freopen or fdopen. + + <Read|Write>[Update]<Binary file|text file> + + This version is for "binary" systems, where text and binary files are + different. An example is Mess-Dose. Many Unix systems could also + cope with a "b" in the string, indicating binary files, but some reject this + (and thereby don't conform to ANSI C, but what else is new?). + + This file is designed for inclusion by host-dependent .h files. No + user application should include it directly, since that would make + the application unable to be configured for both "same" and "binary" + variant systems. */ + +#define FOPEN_RB "rb" +#define FOPEN_WB "wb" +#define FOPEN_AB "ab" +#define FOPEN_RUB "r+b" +#define FOPEN_WUB "w+b" +#define FOPEN_AUB "a+b" + +#define FOPEN_RT "r" +#define FOPEN_WT "w" +#define FOPEN_AT "a" +#define FOPEN_RUT "r+" +#define FOPEN_WUT "w+" +#define FOPEN_AUT "a+" diff --git a/include/fopen-same.h b/include/fopen-same.h new file mode 100644 index 000000000..0f37529d3 --- /dev/null +++ b/include/fopen-same.h @@ -0,0 +1,27 @@ +/* Macros for the 'type' part of an fopen, freopen or fdopen. + + <Read|Write>[Update]<Binary file|text file> + + This version is for "same" systems, where text and binary files are + the same. An example is Unix. Many Unix systems could also add a + "b" to the string, indicating binary files, but some reject this + (and thereby don't conform to ANSI C, but what else is new?). + + This file is designed for inclusion by host-dependent .h files. No + user application should include it directly, since that would make + the application unable to be configured for both "same" and "binary" + variant systems. */ + +#define FOPEN_RB "r" +#define FOPEN_WB "w" +#define FOPEN_AB "a" +#define FOPEN_RUB "r+" +#define FOPEN_WUB "w+" +#define FOPEN_AUB "a+" + +#define FOPEN_RT "r" +#define FOPEN_WT "w" +#define FOPEN_AT "a" +#define FOPEN_RUT "r+" +#define FOPEN_WUT "w+" +#define FOPEN_AUT "a+" diff --git a/include/fopen-vms.h b/include/fopen-vms.h new file mode 100644 index 000000000..da76b7fb5 --- /dev/null +++ b/include/fopen-vms.h @@ -0,0 +1,24 @@ +/* Macros for the 'type' part of an fopen, freopen or fdopen. + + <Read|Write>[Update]<Binary file|text file> + + This version is for VMS systems, where text and binary files are + different. + This file is designed for inclusion by host-dependent .h files. No + user application should include it directly, since that would make + the application unable to be configured for both "same" and "binary" + variant systems. */ + +#define FOPEN_RB "rb","rfm=var" +#define FOPEN_WB "wb","rfm=var" +#define FOPEN_AB "ab","rfm=var" +#define FOPEN_RUB "r+b","rfm=var" +#define FOPEN_WUB "w+b","rfm=var" +#define FOPEN_AUB "a+b","rfm=var" + +#define FOPEN_RT "r" +#define FOPEN_WT "w" +#define FOPEN_AT "a" +#define FOPEN_RUT "r+" +#define FOPEN_WUT "w+" +#define FOPEN_AUT "a+" diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog new file mode 100644 index 000000000..06c02af58 --- /dev/null +++ b/include/gdb/ChangeLog @@ -0,0 +1,130 @@ +2004-09-08 Michael Snyder <msnyder@redhat.com> + + Commited by Corinna Vinschen <vinschen@redhat.com> + * sim-sh.h: Add new sh2a banked registers. + +2004-08-04 Andrew Cagney <cagney@gnu.org> + + * sim-ppc.h: Add extern "C" wrapper. + (enum sim_ppc_regnum): Add full list of SPRs. + +2004-08-04 Jim Blandy <jimb@redhat.com> + + * sim-ppc.h: New file. + +2004-06-25 J"orn Rennecke <joern.rennecke@superh.com> + + * callback.h (host_callback_struct): Replace members fdopen and + alwaysopen with fd_buddy. + [sim/common: * callback.c: Changed all users. ] + +2003-10-31 Kevin Buettner <kevin@redhat.com> + + * sim-frv.h: New file. + +2003-10-15 J"orn Rennecke <joern.rennecke@superh.com> + + * callback.h (struct host_callback_struct): New members ftruncate + and truncate. + +2003-06-10 Corinna Vinschen <vinschen@redhat.com> + + * gdb/fileio.h: New file. + +2003-05-07 Andrew Cagney <cagney@redhat.com> + + * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. + (sim_d10v_translate_imap_addr): Add regcache parameter. + (sim_d10v_translate_dmap_addr): Ditto. + +2003-03-27 Nick Clifton <nickc@redhat.com> + + * sim-arm.h (sim_arm_regs): Add iWMMXt registers. + +2003-03-20 Nick Clifton <nickc@redhat.com> + + * sim-arm.h (sim_arm_regs): Add Maverick co-processor + registers. + +2003-02-27 Andrew Cagney <cagney@redhat.com> + + * remote-sim.h (sim_open, sim_load, sim_create_inferior): Rename + _bfd to bfd. + +2003-02-20 Andrew Cagney <ac131313@redhat.com> + + * remote-sim.h (SIM_RC): Delete unused SIM_RC_UNKNOWN_BREAKPOINT, + SIM_RC_INSUFFICIENT_RESOURCES and SIM_RC_DUPLICATE_BREAKPOINT. + (sim_set_breakpoint, sim_clear_breakpoint): Delete declarations. + (sim_clear_all_breakpoints, sim_enable_breakpoint): Ditto. + (sim_enable_all_breakpoints, sim_disable_breakpoint): Ditto. + (sim_disable_all_breakpoints): Ditto. + +2002-12-26 Kazu Hirata <kazu@cs.umass.edu> + + * sim-h8300.h: Remove ^M. + +2002-07-29 Andrey Volkov <avolkov@transas.com> + + * sim-h8300.h: Rename all enums from H8300_ to SIM_H8300_ + prefix. + +2002-07-23 Andrey Volkov <avolkov@transas.com> + + * sim-h8300.h: New file. + +2002-07-17 Andrew Cagney <cagney@redhat.com> + + * remote-sim.h: Update copyright. + (sim_set_callbacks, sim_size, sim_trace) + (sim_set_trace, sim_set_profile_size, sim_kill): Delete. Moved to + "sim/common/run-sim.h". + +Wed Jul 17 19:36:38 2002 J"orn Rennecke <joern.rennecke@superh.com> + + * sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp, + renumbering the sh-dsp registers to use distinct numbers. + +2002-06-15 Andrew Cagney <ac131313@redhat.com> + + * sim-arm.h (enum sim_arm_regs): Rename sim_arm_regnum. + +2002-06-12 Andrew Cagney <ac131313@redhat.com> + + * sim-arm.h: New file. + +2002-06-08 Andrew Cagney <cagney@redhat.com> + + * callback.h: Copy to here from directory above. + * remote-sim.h: Copy to here from directory above. + +2002-06-01 Andrew Cagney <ac131313@redhat.com> + + * sim-d10v.h (sim_d10v_regs): Expand to include all registers. + Update copyright. + +2002-05-23 Andrew Cagney <ac131313@redhat.com> + + * sim-d10v.h: New file. Moved from include/sim-d10v.h. + +2002-05-10 Elena Zannoni <ezannoni@redhat.com> + + * sim-sh.h: New file, for sh gdb<->sim interface. + +2002-05-09 Daniel Jacobowitz <drow@mvista.com> + + * signals.h: Update comments. + (enum target_signal): Remove conditional compilation around + Mach-specific signals. Move them to after TARGET_SIGNAL_DEFAULT. + +2002-03-10 Daniel Jacobowitz <drow@mvista.com> + + * signals.h: New file, from gdb/defs.h. + + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/include/gdb/callback.h b/include/gdb/callback.h new file mode 100644 index 000000000..aa956d05f --- /dev/null +++ b/include/gdb/callback.h @@ -0,0 +1,279 @@ +/* Remote target system call callback support. + Copyright 1997 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This interface isn't intended to be specific to any particular kind + of remote (hardware, simulator, whatever). As such, support for it + (e.g. sim/common/callback.c) should *not* live in the simulator source + tree, nor should it live in the gdb source tree. */ + +/* There are various ways to handle system calls: + + 1) Have a simulator intercept the appropriate trap instruction and + directly perform the system call on behalf of the target program. + This is the typical way of handling system calls for embedded targets. + [Handling system calls for embedded targets isn't that much of an + oxymoron as running compiler testsuites make use of the capability.] + + This method of system call handling is done when STATE_ENVIRONMENT + is ENVIRONMENT_USER. + + 2) Have a simulator emulate the hardware as much as possible. + If the program running on the real hardware communicates with some sort + of target manager, one would want to be able to run this program on the + simulator as well. + + This method of system call handling is done when STATE_ENVIRONMENT + is ENVIRONMENT_OPERATING. +*/ + +#ifndef CALLBACK_H +#define CALLBACK_H + +/* ??? The reason why we check for va_start here should be documented. */ + +#ifndef va_start +#include <ansidecl.h> +#ifdef ANSI_PROTOTYPES +#include <stdarg.h> +#else +#include <varargs.h> +#endif +#endif + +/* Mapping of host/target values. */ +/* ??? For debugging purposes, one might want to add a string of the + name of the symbol. */ + +typedef struct { + int host_val; + int target_val; +} CB_TARGET_DEFS_MAP; + +#define MAX_CALLBACK_FDS 10 + +/* Forward decl for stat/fstat. */ +struct stat; + +typedef struct host_callback_struct host_callback; + +struct host_callback_struct +{ + int (*close) PARAMS ((host_callback *,int)); + int (*get_errno) PARAMS ((host_callback *)); + int (*isatty) PARAMS ((host_callback *, int)); + int (*lseek) PARAMS ((host_callback *, int, long , int)); + int (*open) PARAMS ((host_callback *, const char*, int mode)); + int (*read) PARAMS ((host_callback *,int, char *, int)); + int (*read_stdin) PARAMS (( host_callback *, char *, int)); + int (*rename) PARAMS ((host_callback *, const char *, const char *)); + int (*system) PARAMS ((host_callback *, const char *)); + long (*time) PARAMS ((host_callback *, long *)); + int (*unlink) PARAMS ((host_callback *, const char *)); + int (*write) PARAMS ((host_callback *,int, const char *, int)); + int (*write_stdout) PARAMS ((host_callback *, const char *, int)); + void (*flush_stdout) PARAMS ((host_callback *)); + int (*write_stderr) PARAMS ((host_callback *, const char *, int)); + void (*flush_stderr) PARAMS ((host_callback *)); + int (*stat) PARAMS ((host_callback *, const char *, struct stat *)); + int (*fstat) PARAMS ((host_callback *, int, struct stat *)); + int (*ftruncate) PARAMS ((host_callback *, int, long)); + int (*truncate) PARAMS ((host_callback *, const char *, long)); + + /* When present, call to the client to give it the oportunity to + poll any io devices for a request to quit (indicated by a nonzero + return value). */ + int (*poll_quit) PARAMS ((host_callback *)); + + /* Used when the target has gone away, so we can close open + handles and free memory etc etc. */ + int (*shutdown) PARAMS ((host_callback *)); + int (*init) PARAMS ((host_callback *)); + + /* depreciated, use vprintf_filtered - Talk to the user on a console. */ + void (*printf_filtered) PARAMS ((host_callback *, const char *, ...)); + + /* Talk to the user on a console. */ + void (*vprintf_filtered) PARAMS ((host_callback *, const char *, va_list)); + + /* Same as vprintf_filtered but to stderr. */ + void (*evprintf_filtered) PARAMS ((host_callback *, const char *, va_list)); + + /* Print an error message and "exit". + In the case of gdb "exiting" means doing a longjmp back to the main + command loop. */ + void (*error) PARAMS ((host_callback *, const char *, ...)); + + int last_errno; /* host format */ + + int fdmap[MAX_CALLBACK_FDS]; + /* fd_buddy is used to contruct circular lists of target fds that point to + the same host fd. A uniquely mapped fd points to itself; for a closed + one, fd_buddy has the value -1. The host file descriptors for stdin / + stdout / stderr are never closed by the simulators, so they are put + in a special fd_buddy circular list which also has MAX_CALLBACK_FDS + as a member. */ + /* ??? We don't have a callback entry for dup, although it is trival to + implement now. */ + short fd_buddy[MAX_CALLBACK_FDS+1]; + + /* System call numbers. */ + CB_TARGET_DEFS_MAP *syscall_map; + /* Errno values. */ + CB_TARGET_DEFS_MAP *errno_map; + /* Flags to the open system call. */ + CB_TARGET_DEFS_MAP *open_map; + /* Signal numbers. */ + CB_TARGET_DEFS_MAP *signal_map; + /* Layout of `stat' struct. + The format is a series of "name,length" pairs separated by colons. + Empty space is indicated with a `name' of "space". + All padding must be explicitly mentioned. + Lengths are in bytes. If this needs to be extended to bits, + use "name.bits". + Example: "st_dev,4:st_ino,4:st_mode,4:..." */ + const char *stat_map; + + /* Marker for those wanting to do sanity checks. + This should remain the last member of this struct to help catch + miscompilation errors. */ +#define HOST_CALLBACK_MAGIC 4705 /* teds constant */ + int magic; +}; + +extern host_callback default_callback; + +/* Canonical versions of system call numbers. + It's not intended to willy-nilly throw every system call ever heard + of in here. Only include those that have an important use. + ??? One can certainly start a discussion over the ones that are currently + here, but that will always be true. */ + +/* These are used by the ANSI C support of libc. */ +#define CB_SYS_exit 1 +#define CB_SYS_open 2 +#define CB_SYS_close 3 +#define CB_SYS_read 4 +#define CB_SYS_write 5 +#define CB_SYS_lseek 6 +#define CB_SYS_unlink 7 +#define CB_SYS_getpid 8 +#define CB_SYS_kill 9 +#define CB_SYS_fstat 10 +/*#define CB_SYS_sbrk 11 - not currently a system call, but reserved. */ + +/* ARGV support. */ +#define CB_SYS_argvlen 12 +#define CB_SYS_argv 13 + +/* These are extras added for one reason or another. */ +#define CB_SYS_chdir 14 +#define CB_SYS_stat 15 +#define CB_SYS_chmod 16 +#define CB_SYS_utime 17 +#define CB_SYS_time 18 + +/* Struct use to pass and return information necessary to perform a + system call. */ +/* FIXME: Need to consider target word size. */ + +typedef struct cb_syscall { + /* The target's value of what system call to perform. */ + int func; + /* The arguments to the syscall. */ + long arg1, arg2, arg3, arg4; + + /* The result. */ + long result; + /* Some system calls have two results. */ + long result2; + /* The target's errno value, or 0 if success. + This is converted to the target's value with host_to_target_errno. */ + int errcode; + + /* Working space to be used by memory read/write callbacks. */ + PTR p1; + PTR p2; + long x1,x2; + + /* Callbacks for reading/writing memory (e.g. for read/write syscalls). + ??? long or unsigned long might be better to use for the `count' + argument here. We mimic sim_{read,write} for now. Be careful to + test any changes with -Wall -Werror, mixed signed comparisons + will get you. */ + int (*read_mem) PARAMS ((host_callback * /*cb*/, struct cb_syscall * /*sc*/, + unsigned long /*taddr*/, char * /*buf*/, + int /*bytes*/)); + int (*write_mem) PARAMS ((host_callback * /*cb*/, struct cb_syscall * /*sc*/, + unsigned long /*taddr*/, const char * /*buf*/, + int /*bytes*/)); + + /* For sanity checking, should be last entry. */ + int magic; +} CB_SYSCALL; + +/* Magic number sanity checker. */ +#define CB_SYSCALL_MAGIC 0x12344321 + +/* Macro to initialize CB_SYSCALL. Called first, before filling in + any fields. */ +#define CB_SYSCALL_INIT(sc) \ +do { \ + memset ((sc), 0, sizeof (*(sc))); \ + (sc)->magic = CB_SYSCALL_MAGIC; \ +} while (0) + +/* Return codes for various interface routines. */ + +typedef enum { + CB_RC_OK = 0, + /* generic error */ + CB_RC_ERR, + /* either file not found or no read access */ + CB_RC_ACCESS, + CB_RC_NO_MEM +} CB_RC; + +/* Read in target values for system call numbers, errno values, signals. */ +CB_RC cb_read_target_syscall_maps PARAMS ((host_callback *, const char *)); + +/* Translate target to host syscall function numbers. */ +int cb_target_to_host_syscall PARAMS ((host_callback *, int)); + +/* Translate host to target errno value. */ +int cb_host_to_target_errno PARAMS ((host_callback *, int)); + +/* Translate target to host open flags. */ +int cb_target_to_host_open PARAMS ((host_callback *, int)); + +/* Translate target signal number to host. */ +int cb_target_to_host_signal PARAMS ((host_callback *, int)); + +/* Translate host signal number to target. */ +int cb_host_to_target_signal PARAMS ((host_callback *, int)); + +/* Translate host stat struct to target. + If stat struct ptr is NULL, just compute target stat struct size. + Result is size of target stat struct or 0 if error. */ +int cb_host_to_target_stat PARAMS ((host_callback *, const struct stat *, PTR)); + +/* Perform a system call. */ +CB_RC cb_syscall PARAMS ((host_callback *, CB_SYSCALL *)); + +#endif diff --git a/include/gdb/fileio.h b/include/gdb/fileio.h new file mode 100644 index 000000000..d84478103 --- /dev/null +++ b/include/gdb/fileio.h @@ -0,0 +1,146 @@ +/* Hosted File I/O interface definitions, for GDB, the GNU Debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef GDB_FILEIO_H_ +#define GDB_FILEIO_H_ + +/* The following flags are defined to be independent of the host + as well as the target side implementation of these constants. + All constants are defined with a leading FILEIO_ in the name + to allow the usage of these constants together with the + corresponding implementation dependent constants in one module. */ + +/* open(2) flags */ +#define FILEIO_O_RDONLY 0x0 +#define FILEIO_O_WRONLY 0x1 +#define FILEIO_O_RDWR 0x2 +#define FILEIO_O_APPEND 0x8 +#define FILEIO_O_CREAT 0x200 +#define FILEIO_O_TRUNC 0x400 +#define FILEIO_O_EXCL 0x800 +#define FILEIO_O_SUPPORTED (FILEIO_O_RDONLY | FILEIO_O_WRONLY| \ + FILEIO_O_RDWR | FILEIO_O_APPEND| \ + FILEIO_O_CREAT | FILEIO_O_TRUNC| \ + FILEIO_O_EXCL) + +/* mode_t bits */ +#define FILEIO_S_IFREG 0100000 +#define FILEIO_S_IFDIR 040000 +#define FILEIO_S_IFCHR 020000 +#define FILEIO_S_IRUSR 0400 +#define FILEIO_S_IWUSR 0200 +#define FILEIO_S_IXUSR 0100 +#define FILEIO_S_IRWXU 0700 +#define FILEIO_S_IRGRP 040 +#define FILEIO_S_IWGRP 020 +#define FILEIO_S_IXGRP 010 +#define FILEIO_S_IRWXG 070 +#define FILEIO_S_IROTH 04 +#define FILEIO_S_IWOTH 02 +#define FILEIO_S_IXOTH 01 +#define FILEIO_S_IRWXO 07 +#define FILEIO_S_SUPPORTED (FILEIO_S_IFREG|FILEIO_S_IFDIR| \ + FILEIO_S_IRWXU|FILEIO_S_IRWXG| \ + FILEIO_S_IRWXO) + +/* lseek(2) flags */ +#define FILEIO_SEEK_SET 0 +#define FILEIO_SEEK_CUR 1 +#define FILEIO_SEEK_END 2 + +/* errno values */ +#define FILEIO_EPERM 1 +#define FILEIO_ENOENT 2 +#define FILEIO_EINTR 4 +#define FILEIO_EIO 5 +#define FILEIO_EBADF 9 +#define FILEIO_EACCES 13 +#define FILEIO_EFAULT 14 +#define FILEIO_EBUSY 16 +#define FILEIO_EEXIST 17 +#define FILEIO_ENODEV 19 +#define FILEIO_ENOTDIR 20 +#define FILEIO_EISDIR 21 +#define FILEIO_EINVAL 22 +#define FILEIO_ENFILE 23 +#define FILEIO_EMFILE 24 +#define FILEIO_EFBIG 27 +#define FILEIO_ENOSPC 28 +#define FILEIO_ESPIPE 29 +#define FILEIO_EROFS 30 +#define FILEIO_ENOSYS 88 +#define FILEIO_ENAMETOOLONG 91 +#define FILEIO_EUNKNOWN 9999 + +/* limits */ +#define FILEIO_INT_MIN -2147483648L +#define FILEIO_INT_MAX 2147483647L +#define FILEIO_UINT_MAX 4294967295UL +#define FILEIO_LONG_MIN -9223372036854775808LL +#define FILEIO_LONG_MAX 9223372036854775807LL +#define FILEIO_ULONG_MAX 18446744073709551615ULL + +/* Integral types as used in protocol. */ +#if 0 +typedef __int32_t fio_int_t; +typedef __uint32_t fio_uint_t, fio_mode_t, fio_time_t; +typedef __int64_t fio_long_t; +typedef __uint64_t fio_ulong_t; +#endif + +#define FIO_INT_LEN 4 +#define FIO_UINT_LEN 4 +#define FIO_MODE_LEN 4 +#define FIO_TIME_LEN 4 +#define FIO_LONG_LEN 8 +#define FIO_ULONG_LEN 8 + +typedef char fio_int_t[FIO_INT_LEN]; +typedef char fio_uint_t[FIO_UINT_LEN]; +typedef char fio_mode_t[FIO_MODE_LEN]; +typedef char fio_time_t[FIO_TIME_LEN]; +typedef char fio_long_t[FIO_LONG_LEN]; +typedef char fio_ulong_t[FIO_ULONG_LEN]; + +/* Struct stat as used in protocol. For complete independence + of host/target systems, it's defined as an array with offsets + to the members. */ + +struct fio_stat { + fio_uint_t fst_dev; + fio_uint_t fst_ino; + fio_mode_t fst_mode; + fio_uint_t fst_nlink; + fio_uint_t fst_uid; + fio_uint_t fst_gid; + fio_uint_t fst_rdev; + fio_ulong_t fst_size; + fio_ulong_t fst_blksize; + fio_ulong_t fst_blocks; + fio_time_t fst_atime; + fio_time_t fst_mtime; + fio_time_t fst_ctime; +}; + +struct fio_timeval { + fio_time_t ftv_sec; + fio_long_t ftv_usec; +}; + +#endif /* GDB_FILEIO_H_ */ diff --git a/include/gdb/remote-sim.h b/include/gdb/remote-sim.h new file mode 100644 index 000000000..a49ba1a89 --- /dev/null +++ b/include/gdb/remote-sim.h @@ -0,0 +1,282 @@ +/* This file defines the interface between the simulator and gdb. + + Copyright 1993, 1994, 1996, 1997, 1998, 2000, 2002 Free Software + Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (REMOTE_SIM_H) +#define REMOTE_SIM_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* This file is used when building stand-alone simulators, so isolate this + file from gdb. */ + +/* Pick up CORE_ADDR_TYPE if defined (from gdb), otherwise use same value as + gdb does (unsigned int - from defs.h). */ + +#ifndef CORE_ADDR_TYPE +typedef unsigned int SIM_ADDR; +#else +typedef CORE_ADDR_TYPE SIM_ADDR; +#endif + + +/* Semi-opaque type used as result of sim_open and passed back to all + other routines. "desc" is short for "descriptor". + It is up to each simulator to define `sim_state'. */ + +typedef struct sim_state *SIM_DESC; + + +/* Values for `kind' arg to sim_open. */ + +typedef enum { + SIM_OPEN_STANDALONE, /* simulator used standalone (run.c) */ + SIM_OPEN_DEBUG /* simulator used by debugger (gdb) */ +} SIM_OPEN_KIND; + + +/* Return codes from various functions. */ + +typedef enum { + SIM_RC_FAIL = 0, + SIM_RC_OK = 1 +} SIM_RC; + + +/* The bfd struct, as an opaque type. */ + +struct bfd; + + +/* Main simulator entry points. */ + + +/* Create a fully initialized simulator instance. + + (This function is called when the simulator is selected from the + gdb command line.) + + KIND specifies how the simulator shall be used. Currently there + are only two kinds: stand-alone and debug. + + CALLBACK specifies a standard host callback (defined in callback.h). + + ABFD, when non NULL, designates a target program. The program is + not loaded. + + ARGV is a standard ARGV pointer such as that passed from the + command line. The syntax of the argument list is is assumed to be + ``SIM-PROG { SIM-OPTION } [ TARGET-PROGRAM { TARGET-OPTION } ]''. + The trailing TARGET-PROGRAM and args are only valid for a + stand-alone simulator. + + On success, the result is a non NULL descriptor that shall be + passed to the other sim_foo functions. While the simulator + configuration can be parameterized by (in decreasing precedence) + ARGV's SIM-OPTION, ARGV's TARGET-PROGRAM and the ABFD argument, the + successful creation of the simulator shall not dependent on the + presence of any of these arguments/options. + + Hardware simulator: The created simulator shall be sufficiently + initialized to handle, with out restrictions any client requests + (including memory reads/writes, register fetch/stores and a + resume). + + Process simulator: that process is not created until a call to + sim_create_inferior. FIXME: What should the state of the simulator + be? */ + +SIM_DESC sim_open PARAMS ((SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd *abfd, char **argv)); + + +/* Destory a simulator instance. + + QUITTING is non-zero if we cannot hang on errors. + + This may involve freeing target memory and closing any open files + and mmap'd areas. You cannot assume sim_kill has already been + called. */ + +void sim_close PARAMS ((SIM_DESC sd, int quitting)); + + +/* Load program PROG into the simulators memory. + + If ABFD is non-NULL, the bfd for the file has already been opened. + The result is a return code indicating success. + + Hardware simulator: Normally, each program section is written into + memory according to that sections LMA using physical (direct) + addressing. The exception being systems, such as PPC/CHRP, which + support more complicated program loaders. A call to this function + should not effect the state of the processor registers. Multiple + calls to this function are permitted and have an accumulative + effect. + + Process simulator: Calls to this function may be ignored. + + FIXME: Most hardware simulators load the image at the VMA using + virtual addressing. + + FIXME: For some hardware targets, before a loaded program can be + executed, it requires the manipulation of VM registers and tables. + Such manipulation should probably (?) occure in + sim_create_inferior. */ + +SIM_RC sim_load PARAMS ((SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty)); + + +/* Prepare to run the simulated program. + + ABFD, if not NULL, provides initial processor state information. + ARGV and ENV, if non NULL, are NULL terminated lists of pointers. + + Hardware simulator: This function shall initialize the processor + registers to a known value. The program counter and possibly stack + pointer shall be set using information obtained from ABFD (or + hardware reset defaults). ARGV and ENV, dependant on the target + ABI, may be written to memory. + + Process simulator: After a call to this function, a new process + instance shall exist. The TEXT, DATA, BSS and stack regions shall + all be initialized, ARGV and ENV shall be written to process + address space (according to the applicable ABI) and the program + counter and stack pointer set accordingly. */ + +SIM_RC sim_create_inferior PARAMS ((SIM_DESC sd, struct bfd *abfd, char **argv, char **env)); + + +/* Fetch LENGTH bytes of the simulated program's memory. Start fetch + at virtual address MEM and store in BUF. Result is number of bytes + read, or zero if error. */ + +int sim_read PARAMS ((SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)); + + +/* Store LENGTH bytes from BUF into the simulated program's + memory. Store bytes starting at virtual address MEM. Result is + number of bytes write, or zero if error. */ + +int sim_write PARAMS ((SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)); + + +/* Fetch register REGNO storing its raw (target endian) value in the + LENGTH byte buffer BUF. Return the actual size of the register or + zero if REGNO is not applicable. + + Legacy implementations ignore LENGTH and always return -1. + + If LENGTH does not match the size of REGNO no data is transfered + (the actual register size is still returned). */ + +int sim_fetch_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int length)); + + +/* Store register REGNO from the raw (target endian) value in BUF. + Return the actual size of the register or zero if REGNO is not + applicable. + + Legacy implementations ignore LENGTH and always return -1. + + If LENGTH does not match the size of REGNO no data is transfered + (the actual register size is still returned). */ + +int sim_store_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int length)); + + +/* Print whatever statistics the simulator has collected. + + VERBOSE is currently unused and must always be zero. */ + +void sim_info PARAMS ((SIM_DESC sd, int verbose)); + + +/* Run (or resume) the simulated program. + + STEP, when non-zero indicates that only a single simulator cycle + should be emulated. + + SIGGNAL, if non-zero is a (HOST) SIGRC value indicating the type of + event (hardware interrupt, signal) to be delivered to the simulated + program. + + Hardware simulator: If the SIGRC value returned by + sim_stop_reason() is passed back to the simulator via SIGGNAL then + the hardware simulator shall correctly deliver the hardware event + indicated by that signal. If a value of zero is passed in then the + simulation will continue as if there were no outstanding signal. + The effect of any other SIGGNAL value is is implementation + dependant. + + Process simulator: If SIGRC is non-zero then the corresponding + signal is delivered to the simulated program and execution is then + continued. A zero SIGRC value indicates that the program should + continue as normal. */ + +void sim_resume PARAMS ((SIM_DESC sd, int step, int siggnal)); + + +/* Asynchronous request to stop the simulation. + A nonzero return indicates that the simulator is able to handle + the request */ + +int sim_stop PARAMS ((SIM_DESC sd)); + + +/* Fetch the REASON why the program stopped. + + SIM_EXITED: The program has terminated. SIGRC indicates the target + dependant exit status. + + SIM_STOPPED: The program has stopped. SIGRC uses the host's signal + numbering as a way of identifying the reaon: program interrupted by + user via a sim_stop request (SIGINT); a breakpoint instruction + (SIGTRAP); a completed single step (SIGTRAP); an internal error + condition (SIGABRT); an illegal instruction (SIGILL); Access to an + undefined memory region (SIGSEGV); Mis-aligned memory access + (SIGBUS). For some signals information in addition to the signal + number may be retained by the simulator (e.g. offending address), + that information is not directly accessable via this interface. + + SIM_SIGNALLED: The program has been terminated by a signal. The + simulator has encountered target code that causes the the program + to exit with signal SIGRC. + + SIM_RUNNING, SIM_POLLING: The return of one of these values + indicates a problem internal to the simulator. */ + +enum sim_stop { sim_running, sim_polling, sim_exited, sim_stopped, sim_signalled }; + +void sim_stop_reason PARAMS ((SIM_DESC sd, enum sim_stop *reason, int *sigrc)); + + +/* Passthru for other commands that the simulator might support. + Simulators should be prepared to deal with any combination of NULL + or empty CMD. */ + +void sim_do_command PARAMS ((SIM_DESC sd, char *cmd)); + +#ifdef __cplusplus +} +#endif + +#endif /* !defined (REMOTE_SIM_H) */ diff --git a/include/gdb/signals.h b/include/gdb/signals.h new file mode 100644 index 000000000..b6f5d4853 --- /dev/null +++ b/include/gdb/signals.h @@ -0,0 +1,237 @@ +/* Target signal numbers for GDB and the GDB remote protocol. + Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, + 1997, 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef GDB_SIGNALS_H +#define GDB_SIGNALS_H + +/* The numbering of these signals is chosen to match traditional unix + signals (insofar as various unices use the same numbers, anyway). + It is also the numbering of the GDB remote protocol. Other remote + protocols, if they use a different numbering, should make sure to + translate appropriately. + + Since these numbers have actually made it out into other software + (stubs, etc.), you mustn't disturb the assigned numbering. If you + need to add new signals here, add them to the end of the explicitly + numbered signals, at the comment marker. Add them unconditionally, + not within any #if or #ifdef. + + This is based strongly on Unix/POSIX signals for several reasons: + (1) This set of signals represents a widely-accepted attempt to + represent events of this sort in a portable fashion, (2) we want a + signal to make it from wait to child_wait to the user intact, (3) many + remote protocols use a similar encoding. However, it is + recognized that this set of signals has limitations (such as not + distinguishing between various kinds of SIGSEGV, or not + distinguishing hitting a breakpoint from finishing a single step). + So in the future we may get around this either by adding additional + signals for breakpoint, single-step, etc., or by adding signal + codes; the latter seems more in the spirit of what BSD, System V, + etc. are doing to address these issues. */ + +/* For an explanation of what each signal means, see + target_signal_to_string. */ + +enum target_signal + { + /* Used some places (e.g. stop_signal) to record the concept that + there is no signal. */ + TARGET_SIGNAL_0 = 0, + TARGET_SIGNAL_FIRST = 0, + TARGET_SIGNAL_HUP = 1, + TARGET_SIGNAL_INT = 2, + TARGET_SIGNAL_QUIT = 3, + TARGET_SIGNAL_ILL = 4, + TARGET_SIGNAL_TRAP = 5, + TARGET_SIGNAL_ABRT = 6, + TARGET_SIGNAL_EMT = 7, + TARGET_SIGNAL_FPE = 8, + TARGET_SIGNAL_KILL = 9, + TARGET_SIGNAL_BUS = 10, + TARGET_SIGNAL_SEGV = 11, + TARGET_SIGNAL_SYS = 12, + TARGET_SIGNAL_PIPE = 13, + TARGET_SIGNAL_ALRM = 14, + TARGET_SIGNAL_TERM = 15, + TARGET_SIGNAL_URG = 16, + TARGET_SIGNAL_STOP = 17, + TARGET_SIGNAL_TSTP = 18, + TARGET_SIGNAL_CONT = 19, + TARGET_SIGNAL_CHLD = 20, + TARGET_SIGNAL_TTIN = 21, + TARGET_SIGNAL_TTOU = 22, + TARGET_SIGNAL_IO = 23, + TARGET_SIGNAL_XCPU = 24, + TARGET_SIGNAL_XFSZ = 25, + TARGET_SIGNAL_VTALRM = 26, + TARGET_SIGNAL_PROF = 27, + TARGET_SIGNAL_WINCH = 28, + TARGET_SIGNAL_LOST = 29, + TARGET_SIGNAL_USR1 = 30, + TARGET_SIGNAL_USR2 = 31, + TARGET_SIGNAL_PWR = 32, + /* Similar to SIGIO. Perhaps they should have the same number. */ + TARGET_SIGNAL_POLL = 33, + TARGET_SIGNAL_WIND = 34, + TARGET_SIGNAL_PHONE = 35, + TARGET_SIGNAL_WAITING = 36, + TARGET_SIGNAL_LWP = 37, + TARGET_SIGNAL_DANGER = 38, + TARGET_SIGNAL_GRANT = 39, + TARGET_SIGNAL_RETRACT = 40, + TARGET_SIGNAL_MSG = 41, + TARGET_SIGNAL_SOUND = 42, + TARGET_SIGNAL_SAK = 43, + TARGET_SIGNAL_PRIO = 44, + TARGET_SIGNAL_REALTIME_33 = 45, + TARGET_SIGNAL_REALTIME_34 = 46, + TARGET_SIGNAL_REALTIME_35 = 47, + TARGET_SIGNAL_REALTIME_36 = 48, + TARGET_SIGNAL_REALTIME_37 = 49, + TARGET_SIGNAL_REALTIME_38 = 50, + TARGET_SIGNAL_REALTIME_39 = 51, + TARGET_SIGNAL_REALTIME_40 = 52, + TARGET_SIGNAL_REALTIME_41 = 53, + TARGET_SIGNAL_REALTIME_42 = 54, + TARGET_SIGNAL_REALTIME_43 = 55, + TARGET_SIGNAL_REALTIME_44 = 56, + TARGET_SIGNAL_REALTIME_45 = 57, + TARGET_SIGNAL_REALTIME_46 = 58, + TARGET_SIGNAL_REALTIME_47 = 59, + TARGET_SIGNAL_REALTIME_48 = 60, + TARGET_SIGNAL_REALTIME_49 = 61, + TARGET_SIGNAL_REALTIME_50 = 62, + TARGET_SIGNAL_REALTIME_51 = 63, + TARGET_SIGNAL_REALTIME_52 = 64, + TARGET_SIGNAL_REALTIME_53 = 65, + TARGET_SIGNAL_REALTIME_54 = 66, + TARGET_SIGNAL_REALTIME_55 = 67, + TARGET_SIGNAL_REALTIME_56 = 68, + TARGET_SIGNAL_REALTIME_57 = 69, + TARGET_SIGNAL_REALTIME_58 = 70, + TARGET_SIGNAL_REALTIME_59 = 71, + TARGET_SIGNAL_REALTIME_60 = 72, + TARGET_SIGNAL_REALTIME_61 = 73, + TARGET_SIGNAL_REALTIME_62 = 74, + TARGET_SIGNAL_REALTIME_63 = 75, + + /* Used internally by Solaris threads. See signal(5) on Solaris. */ + TARGET_SIGNAL_CANCEL = 76, + + /* Yes, this pains me, too. But LynxOS didn't have SIG32, and now + GNU/Linux does, and we can't disturb the numbering, since it's + part of the remote protocol. Note that in some GDB's + TARGET_SIGNAL_REALTIME_32 is number 76. */ + TARGET_SIGNAL_REALTIME_32, + /* Yet another pain, IRIX 6 has SIG64. */ + TARGET_SIGNAL_REALTIME_64, + /* Yet another pain, GNU/Linux MIPS might go up to 128. */ + TARGET_SIGNAL_REALTIME_65, + TARGET_SIGNAL_REALTIME_66, + TARGET_SIGNAL_REALTIME_67, + TARGET_SIGNAL_REALTIME_68, + TARGET_SIGNAL_REALTIME_69, + TARGET_SIGNAL_REALTIME_70, + TARGET_SIGNAL_REALTIME_71, + TARGET_SIGNAL_REALTIME_72, + TARGET_SIGNAL_REALTIME_73, + TARGET_SIGNAL_REALTIME_74, + TARGET_SIGNAL_REALTIME_75, + TARGET_SIGNAL_REALTIME_76, + TARGET_SIGNAL_REALTIME_77, + TARGET_SIGNAL_REALTIME_78, + TARGET_SIGNAL_REALTIME_79, + TARGET_SIGNAL_REALTIME_80, + TARGET_SIGNAL_REALTIME_81, + TARGET_SIGNAL_REALTIME_82, + TARGET_SIGNAL_REALTIME_83, + TARGET_SIGNAL_REALTIME_84, + TARGET_SIGNAL_REALTIME_85, + TARGET_SIGNAL_REALTIME_86, + TARGET_SIGNAL_REALTIME_87, + TARGET_SIGNAL_REALTIME_88, + TARGET_SIGNAL_REALTIME_89, + TARGET_SIGNAL_REALTIME_90, + TARGET_SIGNAL_REALTIME_91, + TARGET_SIGNAL_REALTIME_92, + TARGET_SIGNAL_REALTIME_93, + TARGET_SIGNAL_REALTIME_94, + TARGET_SIGNAL_REALTIME_95, + TARGET_SIGNAL_REALTIME_96, + TARGET_SIGNAL_REALTIME_97, + TARGET_SIGNAL_REALTIME_98, + TARGET_SIGNAL_REALTIME_99, + TARGET_SIGNAL_REALTIME_100, + TARGET_SIGNAL_REALTIME_101, + TARGET_SIGNAL_REALTIME_102, + TARGET_SIGNAL_REALTIME_103, + TARGET_SIGNAL_REALTIME_104, + TARGET_SIGNAL_REALTIME_105, + TARGET_SIGNAL_REALTIME_106, + TARGET_SIGNAL_REALTIME_107, + TARGET_SIGNAL_REALTIME_108, + TARGET_SIGNAL_REALTIME_109, + TARGET_SIGNAL_REALTIME_110, + TARGET_SIGNAL_REALTIME_111, + TARGET_SIGNAL_REALTIME_112, + TARGET_SIGNAL_REALTIME_113, + TARGET_SIGNAL_REALTIME_114, + TARGET_SIGNAL_REALTIME_115, + TARGET_SIGNAL_REALTIME_116, + TARGET_SIGNAL_REALTIME_117, + TARGET_SIGNAL_REALTIME_118, + TARGET_SIGNAL_REALTIME_119, + TARGET_SIGNAL_REALTIME_120, + TARGET_SIGNAL_REALTIME_121, + TARGET_SIGNAL_REALTIME_122, + TARGET_SIGNAL_REALTIME_123, + TARGET_SIGNAL_REALTIME_124, + TARGET_SIGNAL_REALTIME_125, + TARGET_SIGNAL_REALTIME_126, + TARGET_SIGNAL_REALTIME_127, + + TARGET_SIGNAL_INFO, + + /* Some signal we don't know about. */ + TARGET_SIGNAL_UNKNOWN, + + /* Use whatever signal we use when one is not specifically specified + (for passing to proceed and so on). */ + TARGET_SIGNAL_DEFAULT, + + /* Mach exceptions. In versions of GDB before 5.2, these were just before + TARGET_SIGNAL_INFO if you were compiling on a Mach host (and missing + otherwise). */ + TARGET_EXC_BAD_ACCESS, + TARGET_EXC_BAD_INSTRUCTION, + TARGET_EXC_ARITHMETIC, + TARGET_EXC_EMULATION, + TARGET_EXC_SOFTWARE, + TARGET_EXC_BREAKPOINT, + + /* If you are adding a new signal, add it just above this comment. */ + + /* Last and unused enum value, for sizing arrays, etc. */ + TARGET_SIGNAL_LAST + }; + +#endif /* #ifndef GDB_SIGNALS_H */ diff --git a/include/gdb/sim-arm.h b/include/gdb/sim-arm.h new file mode 100644 index 000000000..5598f73fa --- /dev/null +++ b/include/gdb/sim-arm.h @@ -0,0 +1,114 @@ +/* This file defines the interface between the Arm simulator and GDB. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#if !defined (SIM_ARM_H) +#define SIM_ARM_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_arm_regs +{ + SIM_ARM_R0_REGNUM, + SIM_ARM_R1_REGNUM, + SIM_ARM_R2_REGNUM, + SIM_ARM_R3_REGNUM, + SIM_ARM_R4_REGNUM, + SIM_ARM_R5_REGNUM, + SIM_ARM_R6_REGNUM, + SIM_ARM_R7_REGNUM, + SIM_ARM_R8_REGNUM, + SIM_ARM_R9_REGNUM, + SIM_ARM_R10_REGNUM, + SIM_ARM_R11_REGNUM, + SIM_ARM_R12_REGNUM, + SIM_ARM_R13_REGNUM, + SIM_ARM_R14_REGNUM, + SIM_ARM_R15_REGNUM, /* PC */ + SIM_ARM_FP0_REGNUM, + SIM_ARM_FP1_REGNUM, + SIM_ARM_FP2_REGNUM, + SIM_ARM_FP3_REGNUM, + SIM_ARM_FP4_REGNUM, + SIM_ARM_FP5_REGNUM, + SIM_ARM_FP6_REGNUM, + SIM_ARM_FP7_REGNUM, + SIM_ARM_FPS_REGNUM, + SIM_ARM_PS_REGNUM, + SIM_ARM_MAVERIC_COP0R0_REGNUM, + SIM_ARM_MAVERIC_COP0R1_REGNUM, + SIM_ARM_MAVERIC_COP0R2_REGNUM, + SIM_ARM_MAVERIC_COP0R3_REGNUM, + SIM_ARM_MAVERIC_COP0R4_REGNUM, + SIM_ARM_MAVERIC_COP0R5_REGNUM, + SIM_ARM_MAVERIC_COP0R6_REGNUM, + SIM_ARM_MAVERIC_COP0R7_REGNUM, + SIM_ARM_MAVERIC_COP0R8_REGNUM, + SIM_ARM_MAVERIC_COP0R9_REGNUM, + SIM_ARM_MAVERIC_COP0R10_REGNUM, + SIM_ARM_MAVERIC_COP0R11_REGNUM, + SIM_ARM_MAVERIC_COP0R12_REGNUM, + SIM_ARM_MAVERIC_COP0R13_REGNUM, + SIM_ARM_MAVERIC_COP0R14_REGNUM, + SIM_ARM_MAVERIC_COP0R15_REGNUM, + SIM_ARM_MAVERIC_DSPSC_REGNUM, + SIM_ARM_IWMMXT_COP0R0_REGNUM, + SIM_ARM_IWMMXT_COP0R1_REGNUM, + SIM_ARM_IWMMXT_COP0R2_REGNUM, + SIM_ARM_IWMMXT_COP0R3_REGNUM, + SIM_ARM_IWMMXT_COP0R4_REGNUM, + SIM_ARM_IWMMXT_COP0R5_REGNUM, + SIM_ARM_IWMMXT_COP0R6_REGNUM, + SIM_ARM_IWMMXT_COP0R7_REGNUM, + SIM_ARM_IWMMXT_COP0R8_REGNUM, + SIM_ARM_IWMMXT_COP0R9_REGNUM, + SIM_ARM_IWMMXT_COP0R10_REGNUM, + SIM_ARM_IWMMXT_COP0R11_REGNUM, + SIM_ARM_IWMMXT_COP0R12_REGNUM, + SIM_ARM_IWMMXT_COP0R13_REGNUM, + SIM_ARM_IWMMXT_COP0R14_REGNUM, + SIM_ARM_IWMMXT_COP0R15_REGNUM, + SIM_ARM_IWMMXT_COP1R0_REGNUM, + SIM_ARM_IWMMXT_COP1R1_REGNUM, + SIM_ARM_IWMMXT_COP1R2_REGNUM, + SIM_ARM_IWMMXT_COP1R3_REGNUM, + SIM_ARM_IWMMXT_COP1R4_REGNUM, + SIM_ARM_IWMMXT_COP1R5_REGNUM, + SIM_ARM_IWMMXT_COP1R6_REGNUM, + SIM_ARM_IWMMXT_COP1R7_REGNUM, + SIM_ARM_IWMMXT_COP1R8_REGNUM, + SIM_ARM_IWMMXT_COP1R9_REGNUM, + SIM_ARM_IWMMXT_COP1R10_REGNUM, + SIM_ARM_IWMMXT_COP1R11_REGNUM, + SIM_ARM_IWMMXT_COP1R12_REGNUM, + SIM_ARM_IWMMXT_COP1R13_REGNUM, + SIM_ARM_IWMMXT_COP1R14_REGNUM, + SIM_ARM_IWMMXT_COP1R15_REGNUM +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/gdb/sim-d10v.h b/include/gdb/sim-d10v.h new file mode 100644 index 000000000..8294b1485 --- /dev/null +++ b/include/gdb/sim-d10v.h @@ -0,0 +1,142 @@ +/* This file defines the interface between the d10v simulator and gdb. + + Copyright 1999, 2002 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (SIM_D10V_H) +#define SIM_D10V_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +/* GDB interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + 0x10xxxxxx: Logical data address segment (DMAP translated memory) + 0x11xxxxxx: Logical instruction address segment (IMAP translated memory) + + The remote d10v board interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + + The following translate a virtual DMAP/IMAP offset into a physical + memory segment assigning the translated address to PHYS. Since a + memory access may cross a page boundrary the number of bytes for + which the translation is applicable (or 0 for an invalid virtual + offset) is returned. */ + +enum + { + SIM_D10V_MEMORY_UNIFIED = 0x00000000, + SIM_D10V_MEMORY_INSN = 0x01000000, + SIM_D10V_MEMORY_DATA = 0x02000000, + SIM_D10V_MEMORY_DMAP = 0x10000000, + SIM_D10V_MEMORY_IMAP = 0x11000000 + }; + +extern unsigned long sim_d10v_translate_dmap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, int reg_nr)); + +extern unsigned long sim_d10v_translate_imap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*imap_register) (void *regcache, int reg_nr)); + +extern unsigned long sim_d10v_translate_addr + (unsigned long vaddr, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, int reg_nr), + unsigned long (*imap_register) (void *regcache, int reg_nr)); + + +/* The simulator makes use of the following register information. */ + +enum sim_d10v_regs +{ + SIM_D10V_R0_REGNUM, + SIM_D10V_R1_REGNUM, + SIM_D10V_R2_REGNUM, + SIM_D10V_R3_REGNUM, + SIM_D10V_R4_REGNUM, + SIM_D10V_R5_REGNUM, + SIM_D10V_R6_REGNUM, + SIM_D10V_R7_REGNUM, + SIM_D10V_R8_REGNUM, + SIM_D10V_R9_REGNUM, + SIM_D10V_R10_REGNUM, + SIM_D10V_R11_REGNUM, + SIM_D10V_R12_REGNUM, + SIM_D10V_R13_REGNUM, + SIM_D10V_R14_REGNUM, + SIM_D10V_R15_REGNUM, + SIM_D10V_CR0_REGNUM, + SIM_D10V_CR1_REGNUM, + SIM_D10V_CR2_REGNUM, + SIM_D10V_CR3_REGNUM, + SIM_D10V_CR4_REGNUM, + SIM_D10V_CR5_REGNUM, + SIM_D10V_CR6_REGNUM, + SIM_D10V_CR7_REGNUM, + SIM_D10V_CR8_REGNUM, + SIM_D10V_CR9_REGNUM, + SIM_D10V_CR10_REGNUM, + SIM_D10V_CR11_REGNUM, + SIM_D10V_CR12_REGNUM, + SIM_D10V_CR13_REGNUM, + SIM_D10V_CR14_REGNUM, + SIM_D10V_CR15_REGNUM, + SIM_D10V_A0_REGNUM, + SIM_D10V_A1_REGNUM, + SIM_D10V_SPI_REGNUM, + SIM_D10V_SPU_REGNUM, + SIM_D10V_IMAP0_REGNUM, + SIM_D10V_IMAP1_REGNUM, + SIM_D10V_DMAP0_REGNUM, + SIM_D10V_DMAP1_REGNUM, + SIM_D10V_DMAP2_REGNUM, + SIM_D10V_DMAP3_REGNUM, + SIM_D10V_TS2_DMAP_REGNUM +}; + +enum +{ + SIM_D10V_NR_R_REGS = 16, + SIM_D10V_NR_A_REGS = 2, + SIM_D10V_NR_IMAP_REGS = 2, + SIM_D10V_NR_DMAP_REGS = 4, + SIM_D10V_NR_CR_REGS = 16 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/gdb/sim-frv.h b/include/gdb/sim-frv.h new file mode 100644 index 000000000..0a1e0212e --- /dev/null +++ b/include/gdb/sim-frv.h @@ -0,0 +1,53 @@ +/* This file defines the interface between the FR-V simulator and GDB. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#if !defined (SIM_FRV_H) +#define SIM_FRV_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_frv_regs +{ + SIM_FRV_GR0_REGNUM = 0, + SIM_FRV_GR63_REGNUM = 63, + SIM_FRV_FR0_REGNUM = 64, + SIM_FRV_FR63_REGNUM = 127, + SIM_FRV_PC_REGNUM = 128, + + /* An FR-V architecture may have up to 4096 special purpose registers + (SPRs). In order to determine a specific constant used to access + a particular SPR, one of the H_SPR_ prefixed offsets defined in + opcodes/frv-desc.h should be added to SIM_FRV_SPR0_REGNUM. So, + for example, the number that GDB uses to fetch the link register + from the simulator is (SIM_FRV_SPR0_REGNUM + H_SPR_LR). */ + SIM_FRV_SPR0_REGNUM = 129, + SIM_FRV_SPR4095_REGNUM = SIM_FRV_SPR0_REGNUM + 4095 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/gdb/sim-h8300.h b/include/gdb/sim-h8300.h new file mode 100644 index 000000000..246370aec --- /dev/null +++ b/include/gdb/sim-h8300.h @@ -0,0 +1,78 @@ +/* This file defines the interface between the h8300 simulator and gdb. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (SIM_H8300_H) +#define SIM_H8300_H + +#ifdef __cplusplus +extern "C" { //} +#endif + +/* The simulator makes use of the following register information. */ + + enum sim_h8300_regs + { + /* Registers common to all the H8 variants. */ + /* Start here: */ + SIM_H8300_R0_REGNUM, + SIM_H8300_R1_REGNUM, + SIM_H8300_R2_REGNUM, + SIM_H8300_R3_REGNUM, + SIM_H8300_R4_REGNUM, + SIM_H8300_R5_REGNUM, + SIM_H8300_R6_REGNUM, + SIM_H8300_R7_REGNUM, + + SIM_H8300_CCR_REGNUM, /* Contains processor status */ + SIM_H8300_PC_REGNUM, /* Contains program counter */ + /* End here */ + + SIM_H8300_EXR_REGNUM, /* Contains extended processor status + H8S and higher */ + SIM_H8300_MACL_REGNUM, /* Lower part of MAC register (26xx only)*/ + SIM_H8300_MACH_REGNUM, /* High part of MAC register (26xx only) */ + + SIM_H8300_CYCLE_REGNUM, + SIM_H8300_INST_REGNUM, + SIM_H8300_TICK_REGNUM + }; + + enum + { + SIM_H8300_ARG_FIRST_REGNUM = SIM_H8300_R0_REGNUM, /* first reg in which an arg + may be passed */ + SIM_H8300_ARG_LAST_REGNUM = SIM_H8300_R3_REGNUM, /* last reg in which an arg + may be passed */ + SIM_H8300_FP_REGNUM = SIM_H8300_R6_REGNUM, /* Contain address of executing + stack frame */ + SIM_H8300_SP_REGNUM = SIM_H8300_R7_REGNUM /* Contains address of top of stack */ + }; + + enum + { + SIM_H8300_NUM_COMMON_REGS = 10, + SIM_H8300_S_NUM_REGS = 13, + SIM_H8300_NUM_REGS = 16 + }; + +#ifdef __cplusplus +} +#endif + +#endif /* SIM_H8300_H */ diff --git a/include/gdb/sim-ppc.h b/include/gdb/sim-ppc.h new file mode 100644 index 000000000..e31a67112 --- /dev/null +++ b/include/gdb/sim-ppc.h @@ -0,0 +1,771 @@ +/* sim-ppc.h --- interface between PowerPC simulator and GDB. + + Copyright 2004 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#if !defined (SIM_PPC_H) +#define SIM_PPC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* The register access functions, sim_fetch_register and + sim_store_register, use the following numbering for PowerPC + registers. */ + +enum sim_ppc_regnum + { + /* General-purpose registers, r0 -- r31. */ + sim_ppc_r0_regnum, + sim_ppc_r1_regnum, + sim_ppc_r2_regnum, + sim_ppc_r3_regnum, + sim_ppc_r4_regnum, + sim_ppc_r5_regnum, + sim_ppc_r6_regnum, + sim_ppc_r7_regnum, + sim_ppc_r8_regnum, + sim_ppc_r9_regnum, + sim_ppc_r10_regnum, + sim_ppc_r11_regnum, + sim_ppc_r12_regnum, + sim_ppc_r13_regnum, + sim_ppc_r14_regnum, + sim_ppc_r15_regnum, + sim_ppc_r16_regnum, + sim_ppc_r17_regnum, + sim_ppc_r18_regnum, + sim_ppc_r19_regnum, + sim_ppc_r20_regnum, + sim_ppc_r21_regnum, + sim_ppc_r22_regnum, + sim_ppc_r23_regnum, + sim_ppc_r24_regnum, + sim_ppc_r25_regnum, + sim_ppc_r26_regnum, + sim_ppc_r27_regnum, + sim_ppc_r28_regnum, + sim_ppc_r29_regnum, + sim_ppc_r30_regnum, + sim_ppc_r31_regnum, + + /* Floating-point registers, f0 -- f31. */ + sim_ppc_f0_regnum, + sim_ppc_f1_regnum, + sim_ppc_f2_regnum, + sim_ppc_f3_regnum, + sim_ppc_f4_regnum, + sim_ppc_f5_regnum, + sim_ppc_f6_regnum, + sim_ppc_f7_regnum, + sim_ppc_f8_regnum, + sim_ppc_f9_regnum, + sim_ppc_f10_regnum, + sim_ppc_f11_regnum, + sim_ppc_f12_regnum, + sim_ppc_f13_regnum, + sim_ppc_f14_regnum, + sim_ppc_f15_regnum, + sim_ppc_f16_regnum, + sim_ppc_f17_regnum, + sim_ppc_f18_regnum, + sim_ppc_f19_regnum, + sim_ppc_f20_regnum, + sim_ppc_f21_regnum, + sim_ppc_f22_regnum, + sim_ppc_f23_regnum, + sim_ppc_f24_regnum, + sim_ppc_f25_regnum, + sim_ppc_f26_regnum, + sim_ppc_f27_regnum, + sim_ppc_f28_regnum, + sim_ppc_f29_regnum, + sim_ppc_f30_regnum, + sim_ppc_f31_regnum, + + /* Altivec vector registers, vr0 -- vr31. */ + sim_ppc_vr0_regnum, + sim_ppc_vr1_regnum, + sim_ppc_vr2_regnum, + sim_ppc_vr3_regnum, + sim_ppc_vr4_regnum, + sim_ppc_vr5_regnum, + sim_ppc_vr6_regnum, + sim_ppc_vr7_regnum, + sim_ppc_vr8_regnum, + sim_ppc_vr9_regnum, + sim_ppc_vr10_regnum, + sim_ppc_vr11_regnum, + sim_ppc_vr12_regnum, + sim_ppc_vr13_regnum, + sim_ppc_vr14_regnum, + sim_ppc_vr15_regnum, + sim_ppc_vr16_regnum, + sim_ppc_vr17_regnum, + sim_ppc_vr18_regnum, + sim_ppc_vr19_regnum, + sim_ppc_vr20_regnum, + sim_ppc_vr21_regnum, + sim_ppc_vr22_regnum, + sim_ppc_vr23_regnum, + sim_ppc_vr24_regnum, + sim_ppc_vr25_regnum, + sim_ppc_vr26_regnum, + sim_ppc_vr27_regnum, + sim_ppc_vr28_regnum, + sim_ppc_vr29_regnum, + sim_ppc_vr30_regnum, + sim_ppc_vr31_regnum, + + /* SPE APU GPR upper halves. These are the upper 32 bits of the + gprs; there is one upper-half register for each gpr, so it is + appropriate to use sim_ppc_num_gprs for iterating through + these. */ + sim_ppc_rh0_regnum, + sim_ppc_rh1_regnum, + sim_ppc_rh2_regnum, + sim_ppc_rh3_regnum, + sim_ppc_rh4_regnum, + sim_ppc_rh5_regnum, + sim_ppc_rh6_regnum, + sim_ppc_rh7_regnum, + sim_ppc_rh8_regnum, + sim_ppc_rh9_regnum, + sim_ppc_rh10_regnum, + sim_ppc_rh11_regnum, + sim_ppc_rh12_regnum, + sim_ppc_rh13_regnum, + sim_ppc_rh14_regnum, + sim_ppc_rh15_regnum, + sim_ppc_rh16_regnum, + sim_ppc_rh17_regnum, + sim_ppc_rh18_regnum, + sim_ppc_rh19_regnum, + sim_ppc_rh20_regnum, + sim_ppc_rh21_regnum, + sim_ppc_rh22_regnum, + sim_ppc_rh23_regnum, + sim_ppc_rh24_regnum, + sim_ppc_rh25_regnum, + sim_ppc_rh26_regnum, + sim_ppc_rh27_regnum, + sim_ppc_rh28_regnum, + sim_ppc_rh29_regnum, + sim_ppc_rh30_regnum, + sim_ppc_rh31_regnum, + + /* SPE APU GPR full registers. Each of these registers is the + 64-bit concatenation of a 32-bit GPR (providing the lower bits) + and a 32-bit upper-half register (providing the higher bits). + As for the upper-half registers, it is appropriate to use + sim_ppc_num_gprs with these. */ + sim_ppc_ev0_regnum, + sim_ppc_ev1_regnum, + sim_ppc_ev2_regnum, + sim_ppc_ev3_regnum, + sim_ppc_ev4_regnum, + sim_ppc_ev5_regnum, + sim_ppc_ev6_regnum, + sim_ppc_ev7_regnum, + sim_ppc_ev8_regnum, + sim_ppc_ev9_regnum, + sim_ppc_ev10_regnum, + sim_ppc_ev11_regnum, + sim_ppc_ev12_regnum, + sim_ppc_ev13_regnum, + sim_ppc_ev14_regnum, + sim_ppc_ev15_regnum, + sim_ppc_ev16_regnum, + sim_ppc_ev17_regnum, + sim_ppc_ev18_regnum, + sim_ppc_ev19_regnum, + sim_ppc_ev20_regnum, + sim_ppc_ev21_regnum, + sim_ppc_ev22_regnum, + sim_ppc_ev23_regnum, + sim_ppc_ev24_regnum, + sim_ppc_ev25_regnum, + sim_ppc_ev26_regnum, + sim_ppc_ev27_regnum, + sim_ppc_ev28_regnum, + sim_ppc_ev29_regnum, + sim_ppc_ev30_regnum, + sim_ppc_ev31_regnum, + + /* Segment registers, sr0 -- sr15. */ + sim_ppc_sr0_regnum, + sim_ppc_sr1_regnum, + sim_ppc_sr2_regnum, + sim_ppc_sr3_regnum, + sim_ppc_sr4_regnum, + sim_ppc_sr5_regnum, + sim_ppc_sr6_regnum, + sim_ppc_sr7_regnum, + sim_ppc_sr8_regnum, + sim_ppc_sr9_regnum, + sim_ppc_sr10_regnum, + sim_ppc_sr11_regnum, + sim_ppc_sr12_regnum, + sim_ppc_sr13_regnum, + sim_ppc_sr14_regnum, + sim_ppc_sr15_regnum, + + /* Miscellaneous --- but non-SPR --- registers. */ + sim_ppc_pc_regnum, + sim_ppc_ps_regnum, + sim_ppc_cr_regnum, + sim_ppc_fpscr_regnum, + sim_ppc_acc_regnum, + sim_ppc_vscr_regnum, + + /* Special-purpose registers. */ + sim_ppc_spr0_regnum, sim_ppc_spr1_regnum, + sim_ppc_spr2_regnum, sim_ppc_spr3_regnum, + sim_ppc_spr4_regnum, sim_ppc_spr5_regnum, + sim_ppc_spr6_regnum, sim_ppc_spr7_regnum, + sim_ppc_spr8_regnum, sim_ppc_spr9_regnum, + sim_ppc_spr10_regnum, sim_ppc_spr11_regnum, + sim_ppc_spr12_regnum, sim_ppc_spr13_regnum, + sim_ppc_spr14_regnum, sim_ppc_spr15_regnum, + sim_ppc_spr16_regnum, sim_ppc_spr17_regnum, + sim_ppc_spr18_regnum, sim_ppc_spr19_regnum, + sim_ppc_spr20_regnum, sim_ppc_spr21_regnum, + sim_ppc_spr22_regnum, sim_ppc_spr23_regnum, + sim_ppc_spr24_regnum, sim_ppc_spr25_regnum, + sim_ppc_spr26_regnum, sim_ppc_spr27_regnum, + sim_ppc_spr28_regnum, sim_ppc_spr29_regnum, + sim_ppc_spr30_regnum, sim_ppc_spr31_regnum, + sim_ppc_spr32_regnum, sim_ppc_spr33_regnum, + sim_ppc_spr34_regnum, sim_ppc_spr35_regnum, + sim_ppc_spr36_regnum, sim_ppc_spr37_regnum, + sim_ppc_spr38_regnum, sim_ppc_spr39_regnum, + sim_ppc_spr40_regnum, sim_ppc_spr41_regnum, + sim_ppc_spr42_regnum, sim_ppc_spr43_regnum, + sim_ppc_spr44_regnum, sim_ppc_spr45_regnum, + sim_ppc_spr46_regnum, sim_ppc_spr47_regnum, + sim_ppc_spr48_regnum, sim_ppc_spr49_regnum, + sim_ppc_spr50_regnum, sim_ppc_spr51_regnum, + sim_ppc_spr52_regnum, sim_ppc_spr53_regnum, + sim_ppc_spr54_regnum, sim_ppc_spr55_regnum, + sim_ppc_spr56_regnum, sim_ppc_spr57_regnum, + sim_ppc_spr58_regnum, sim_ppc_spr59_regnum, + sim_ppc_spr60_regnum, sim_ppc_spr61_regnum, + sim_ppc_spr62_regnum, sim_ppc_spr63_regnum, + sim_ppc_spr64_regnum, sim_ppc_spr65_regnum, + sim_ppc_spr66_regnum, sim_ppc_spr67_regnum, + sim_ppc_spr68_regnum, sim_ppc_spr69_regnum, + sim_ppc_spr70_regnum, sim_ppc_spr71_regnum, + sim_ppc_spr72_regnum, sim_ppc_spr73_regnum, + sim_ppc_spr74_regnum, sim_ppc_spr75_regnum, + sim_ppc_spr76_regnum, sim_ppc_spr77_regnum, + sim_ppc_spr78_regnum, sim_ppc_spr79_regnum, + sim_ppc_spr80_regnum, sim_ppc_spr81_regnum, + sim_ppc_spr82_regnum, sim_ppc_spr83_regnum, + sim_ppc_spr84_regnum, sim_ppc_spr85_regnum, + sim_ppc_spr86_regnum, sim_ppc_spr87_regnum, + sim_ppc_spr88_regnum, sim_ppc_spr89_regnum, + sim_ppc_spr90_regnum, sim_ppc_spr91_regnum, + sim_ppc_spr92_regnum, sim_ppc_spr93_regnum, + sim_ppc_spr94_regnum, sim_ppc_spr95_regnum, + sim_ppc_spr96_regnum, sim_ppc_spr97_regnum, + sim_ppc_spr98_regnum, sim_ppc_spr99_regnum, + sim_ppc_spr100_regnum, sim_ppc_spr101_regnum, + sim_ppc_spr102_regnum, sim_ppc_spr103_regnum, + sim_ppc_spr104_regnum, sim_ppc_spr105_regnum, + sim_ppc_spr106_regnum, sim_ppc_spr107_regnum, + sim_ppc_spr108_regnum, sim_ppc_spr109_regnum, + sim_ppc_spr110_regnum, sim_ppc_spr111_regnum, + sim_ppc_spr112_regnum, sim_ppc_spr113_regnum, + sim_ppc_spr114_regnum, sim_ppc_spr115_regnum, + sim_ppc_spr116_regnum, sim_ppc_spr117_regnum, + sim_ppc_spr118_regnum, sim_ppc_spr119_regnum, + sim_ppc_spr120_regnum, sim_ppc_spr121_regnum, + sim_ppc_spr122_regnum, sim_ppc_spr123_regnum, + sim_ppc_spr124_regnum, sim_ppc_spr125_regnum, + sim_ppc_spr126_regnum, sim_ppc_spr127_regnum, + sim_ppc_spr128_regnum, sim_ppc_spr129_regnum, + sim_ppc_spr130_regnum, sim_ppc_spr131_regnum, + sim_ppc_spr132_regnum, sim_ppc_spr133_regnum, + sim_ppc_spr134_regnum, sim_ppc_spr135_regnum, + sim_ppc_spr136_regnum, sim_ppc_spr137_regnum, + sim_ppc_spr138_regnum, sim_ppc_spr139_regnum, + sim_ppc_spr140_regnum, sim_ppc_spr141_regnum, + sim_ppc_spr142_regnum, sim_ppc_spr143_regnum, + sim_ppc_spr144_regnum, sim_ppc_spr145_regnum, + sim_ppc_spr146_regnum, sim_ppc_spr147_regnum, + sim_ppc_spr148_regnum, sim_ppc_spr149_regnum, + sim_ppc_spr150_regnum, sim_ppc_spr151_regnum, + sim_ppc_spr152_regnum, sim_ppc_spr153_regnum, + sim_ppc_spr154_regnum, sim_ppc_spr155_regnum, + sim_ppc_spr156_regnum, sim_ppc_spr157_regnum, + sim_ppc_spr158_regnum, sim_ppc_spr159_regnum, + sim_ppc_spr160_regnum, sim_ppc_spr161_regnum, + sim_ppc_spr162_regnum, sim_ppc_spr163_regnum, + sim_ppc_spr164_regnum, sim_ppc_spr165_regnum, + sim_ppc_spr166_regnum, sim_ppc_spr167_regnum, + sim_ppc_spr168_regnum, sim_ppc_spr169_regnum, + sim_ppc_spr170_regnum, sim_ppc_spr171_regnum, + sim_ppc_spr172_regnum, sim_ppc_spr173_regnum, + sim_ppc_spr174_regnum, sim_ppc_spr175_regnum, + sim_ppc_spr176_regnum, sim_ppc_spr177_regnum, + sim_ppc_spr178_regnum, sim_ppc_spr179_regnum, + sim_ppc_spr180_regnum, sim_ppc_spr181_regnum, + sim_ppc_spr182_regnum, sim_ppc_spr183_regnum, + sim_ppc_spr184_regnum, sim_ppc_spr185_regnum, + sim_ppc_spr186_regnum, sim_ppc_spr187_regnum, + sim_ppc_spr188_regnum, sim_ppc_spr189_regnum, + sim_ppc_spr190_regnum, sim_ppc_spr191_regnum, + sim_ppc_spr192_regnum, sim_ppc_spr193_regnum, + sim_ppc_spr194_regnum, sim_ppc_spr195_regnum, + sim_ppc_spr196_regnum, sim_ppc_spr197_regnum, + sim_ppc_spr198_regnum, sim_ppc_spr199_regnum, + sim_ppc_spr200_regnum, sim_ppc_spr201_regnum, + sim_ppc_spr202_regnum, sim_ppc_spr203_regnum, + sim_ppc_spr204_regnum, sim_ppc_spr205_regnum, + sim_ppc_spr206_regnum, sim_ppc_spr207_regnum, + sim_ppc_spr208_regnum, sim_ppc_spr209_regnum, + sim_ppc_spr210_regnum, sim_ppc_spr211_regnum, + sim_ppc_spr212_regnum, sim_ppc_spr213_regnum, + sim_ppc_spr214_regnum, sim_ppc_spr215_regnum, + sim_ppc_spr216_regnum, sim_ppc_spr217_regnum, + sim_ppc_spr218_regnum, sim_ppc_spr219_regnum, + sim_ppc_spr220_regnum, sim_ppc_spr221_regnum, + sim_ppc_spr222_regnum, sim_ppc_spr223_regnum, + sim_ppc_spr224_regnum, sim_ppc_spr225_regnum, + sim_ppc_spr226_regnum, sim_ppc_spr227_regnum, + sim_ppc_spr228_regnum, sim_ppc_spr229_regnum, + sim_ppc_spr230_regnum, sim_ppc_spr231_regnum, + sim_ppc_spr232_regnum, sim_ppc_spr233_regnum, + sim_ppc_spr234_regnum, sim_ppc_spr235_regnum, + sim_ppc_spr236_regnum, sim_ppc_spr237_regnum, + sim_ppc_spr238_regnum, sim_ppc_spr239_regnum, + sim_ppc_spr240_regnum, sim_ppc_spr241_regnum, + sim_ppc_spr242_regnum, sim_ppc_spr243_regnum, + sim_ppc_spr244_regnum, sim_ppc_spr245_regnum, + sim_ppc_spr246_regnum, sim_ppc_spr247_regnum, + sim_ppc_spr248_regnum, sim_ppc_spr249_regnum, + sim_ppc_spr250_regnum, sim_ppc_spr251_regnum, + sim_ppc_spr252_regnum, sim_ppc_spr253_regnum, + sim_ppc_spr254_regnum, sim_ppc_spr255_regnum, + sim_ppc_spr256_regnum, sim_ppc_spr257_regnum, + sim_ppc_spr258_regnum, sim_ppc_spr259_regnum, + sim_ppc_spr260_regnum, sim_ppc_spr261_regnum, + sim_ppc_spr262_regnum, sim_ppc_spr263_regnum, + sim_ppc_spr264_regnum, sim_ppc_spr265_regnum, + sim_ppc_spr266_regnum, sim_ppc_spr267_regnum, + sim_ppc_spr268_regnum, sim_ppc_spr269_regnum, + sim_ppc_spr270_regnum, sim_ppc_spr271_regnum, + sim_ppc_spr272_regnum, sim_ppc_spr273_regnum, + sim_ppc_spr274_regnum, sim_ppc_spr275_regnum, + sim_ppc_spr276_regnum, sim_ppc_spr277_regnum, + sim_ppc_spr278_regnum, sim_ppc_spr279_regnum, + sim_ppc_spr280_regnum, sim_ppc_spr281_regnum, + sim_ppc_spr282_regnum, sim_ppc_spr283_regnum, + sim_ppc_spr284_regnum, sim_ppc_spr285_regnum, + sim_ppc_spr286_regnum, sim_ppc_spr287_regnum, + sim_ppc_spr288_regnum, sim_ppc_spr289_regnum, + sim_ppc_spr290_regnum, sim_ppc_spr291_regnum, + sim_ppc_spr292_regnum, sim_ppc_spr293_regnum, + sim_ppc_spr294_regnum, sim_ppc_spr295_regnum, + sim_ppc_spr296_regnum, sim_ppc_spr297_regnum, + sim_ppc_spr298_regnum, sim_ppc_spr299_regnum, + sim_ppc_spr300_regnum, sim_ppc_spr301_regnum, + sim_ppc_spr302_regnum, sim_ppc_spr303_regnum, + sim_ppc_spr304_regnum, sim_ppc_spr305_regnum, + sim_ppc_spr306_regnum, sim_ppc_spr307_regnum, + sim_ppc_spr308_regnum, sim_ppc_spr309_regnum, + sim_ppc_spr310_regnum, sim_ppc_spr311_regnum, + sim_ppc_spr312_regnum, sim_ppc_spr313_regnum, + sim_ppc_spr314_regnum, sim_ppc_spr315_regnum, + sim_ppc_spr316_regnum, sim_ppc_spr317_regnum, + sim_ppc_spr318_regnum, sim_ppc_spr319_regnum, + sim_ppc_spr320_regnum, sim_ppc_spr321_regnum, + sim_ppc_spr322_regnum, sim_ppc_spr323_regnum, + sim_ppc_spr324_regnum, sim_ppc_spr325_regnum, + sim_ppc_spr326_regnum, sim_ppc_spr327_regnum, + sim_ppc_spr328_regnum, sim_ppc_spr329_regnum, + sim_ppc_spr330_regnum, sim_ppc_spr331_regnum, + sim_ppc_spr332_regnum, sim_ppc_spr333_regnum, + sim_ppc_spr334_regnum, sim_ppc_spr335_regnum, + sim_ppc_spr336_regnum, sim_ppc_spr337_regnum, + sim_ppc_spr338_regnum, sim_ppc_spr339_regnum, + sim_ppc_spr340_regnum, sim_ppc_spr341_regnum, + sim_ppc_spr342_regnum, sim_ppc_spr343_regnum, + sim_ppc_spr344_regnum, sim_ppc_spr345_regnum, + sim_ppc_spr346_regnum, sim_ppc_spr347_regnum, + sim_ppc_spr348_regnum, sim_ppc_spr349_regnum, + sim_ppc_spr350_regnum, sim_ppc_spr351_regnum, + sim_ppc_spr352_regnum, sim_ppc_spr353_regnum, + sim_ppc_spr354_regnum, sim_ppc_spr355_regnum, + sim_ppc_spr356_regnum, sim_ppc_spr357_regnum, + sim_ppc_spr358_regnum, sim_ppc_spr359_regnum, + sim_ppc_spr360_regnum, sim_ppc_spr361_regnum, + sim_ppc_spr362_regnum, sim_ppc_spr363_regnum, + sim_ppc_spr364_regnum, sim_ppc_spr365_regnum, + sim_ppc_spr366_regnum, sim_ppc_spr367_regnum, + sim_ppc_spr368_regnum, sim_ppc_spr369_regnum, + sim_ppc_spr370_regnum, sim_ppc_spr371_regnum, + sim_ppc_spr372_regnum, sim_ppc_spr373_regnum, + sim_ppc_spr374_regnum, sim_ppc_spr375_regnum, + sim_ppc_spr376_regnum, sim_ppc_spr377_regnum, + sim_ppc_spr378_regnum, sim_ppc_spr379_regnum, + sim_ppc_spr380_regnum, sim_ppc_spr381_regnum, + sim_ppc_spr382_regnum, sim_ppc_spr383_regnum, + sim_ppc_spr384_regnum, sim_ppc_spr385_regnum, + sim_ppc_spr386_regnum, sim_ppc_spr387_regnum, + sim_ppc_spr388_regnum, sim_ppc_spr389_regnum, + sim_ppc_spr390_regnum, sim_ppc_spr391_regnum, + sim_ppc_spr392_regnum, sim_ppc_spr393_regnum, + sim_ppc_spr394_regnum, sim_ppc_spr395_regnum, + sim_ppc_spr396_regnum, sim_ppc_spr397_regnum, + sim_ppc_spr398_regnum, sim_ppc_spr399_regnum, + sim_ppc_spr400_regnum, sim_ppc_spr401_regnum, + sim_ppc_spr402_regnum, sim_ppc_spr403_regnum, + sim_ppc_spr404_regnum, sim_ppc_spr405_regnum, + sim_ppc_spr406_regnum, sim_ppc_spr407_regnum, + sim_ppc_spr408_regnum, sim_ppc_spr409_regnum, + sim_ppc_spr410_regnum, sim_ppc_spr411_regnum, + sim_ppc_spr412_regnum, sim_ppc_spr413_regnum, + sim_ppc_spr414_regnum, sim_ppc_spr415_regnum, + sim_ppc_spr416_regnum, sim_ppc_spr417_regnum, + sim_ppc_spr418_regnum, sim_ppc_spr419_regnum, + sim_ppc_spr420_regnum, sim_ppc_spr421_regnum, + sim_ppc_spr422_regnum, sim_ppc_spr423_regnum, + sim_ppc_spr424_regnum, sim_ppc_spr425_regnum, + sim_ppc_spr426_regnum, sim_ppc_spr427_regnum, + sim_ppc_spr428_regnum, sim_ppc_spr429_regnum, + sim_ppc_spr430_regnum, sim_ppc_spr431_regnum, + sim_ppc_spr432_regnum, sim_ppc_spr433_regnum, + sim_ppc_spr434_regnum, sim_ppc_spr435_regnum, + sim_ppc_spr436_regnum, sim_ppc_spr437_regnum, + sim_ppc_spr438_regnum, sim_ppc_spr439_regnum, + sim_ppc_spr440_regnum, sim_ppc_spr441_regnum, + sim_ppc_spr442_regnum, sim_ppc_spr443_regnum, + sim_ppc_spr444_regnum, sim_ppc_spr445_regnum, + sim_ppc_spr446_regnum, sim_ppc_spr447_regnum, + sim_ppc_spr448_regnum, sim_ppc_spr449_regnum, + sim_ppc_spr450_regnum, sim_ppc_spr451_regnum, + sim_ppc_spr452_regnum, sim_ppc_spr453_regnum, + sim_ppc_spr454_regnum, sim_ppc_spr455_regnum, + sim_ppc_spr456_regnum, sim_ppc_spr457_regnum, + sim_ppc_spr458_regnum, sim_ppc_spr459_regnum, + sim_ppc_spr460_regnum, sim_ppc_spr461_regnum, + sim_ppc_spr462_regnum, sim_ppc_spr463_regnum, + sim_ppc_spr464_regnum, sim_ppc_spr465_regnum, + sim_ppc_spr466_regnum, sim_ppc_spr467_regnum, + sim_ppc_spr468_regnum, sim_ppc_spr469_regnum, + sim_ppc_spr470_regnum, sim_ppc_spr471_regnum, + sim_ppc_spr472_regnum, sim_ppc_spr473_regnum, + sim_ppc_spr474_regnum, sim_ppc_spr475_regnum, + sim_ppc_spr476_regnum, sim_ppc_spr477_regnum, + sim_ppc_spr478_regnum, sim_ppc_spr479_regnum, + sim_ppc_spr480_regnum, sim_ppc_spr481_regnum, + sim_ppc_spr482_regnum, sim_ppc_spr483_regnum, + sim_ppc_spr484_regnum, sim_ppc_spr485_regnum, + sim_ppc_spr486_regnum, sim_ppc_spr487_regnum, + sim_ppc_spr488_regnum, sim_ppc_spr489_regnum, + sim_ppc_spr490_regnum, sim_ppc_spr491_regnum, + sim_ppc_spr492_regnum, sim_ppc_spr493_regnum, + sim_ppc_spr494_regnum, sim_ppc_spr495_regnum, + sim_ppc_spr496_regnum, sim_ppc_spr497_regnum, + sim_ppc_spr498_regnum, sim_ppc_spr499_regnum, + sim_ppc_spr500_regnum, sim_ppc_spr501_regnum, + sim_ppc_spr502_regnum, sim_ppc_spr503_regnum, + sim_ppc_spr504_regnum, sim_ppc_spr505_regnum, + sim_ppc_spr506_regnum, sim_ppc_spr507_regnum, + sim_ppc_spr508_regnum, sim_ppc_spr509_regnum, + sim_ppc_spr510_regnum, sim_ppc_spr511_regnum, + sim_ppc_spr512_regnum, sim_ppc_spr513_regnum, + sim_ppc_spr514_regnum, sim_ppc_spr515_regnum, + sim_ppc_spr516_regnum, sim_ppc_spr517_regnum, + sim_ppc_spr518_regnum, sim_ppc_spr519_regnum, + sim_ppc_spr520_regnum, sim_ppc_spr521_regnum, + sim_ppc_spr522_regnum, sim_ppc_spr523_regnum, + sim_ppc_spr524_regnum, sim_ppc_spr525_regnum, + sim_ppc_spr526_regnum, sim_ppc_spr527_regnum, + sim_ppc_spr528_regnum, sim_ppc_spr529_regnum, + sim_ppc_spr530_regnum, sim_ppc_spr531_regnum, + sim_ppc_spr532_regnum, sim_ppc_spr533_regnum, + sim_ppc_spr534_regnum, sim_ppc_spr535_regnum, + sim_ppc_spr536_regnum, sim_ppc_spr537_regnum, + sim_ppc_spr538_regnum, sim_ppc_spr539_regnum, + sim_ppc_spr540_regnum, sim_ppc_spr541_regnum, + sim_ppc_spr542_regnum, sim_ppc_spr543_regnum, + sim_ppc_spr544_regnum, sim_ppc_spr545_regnum, + sim_ppc_spr546_regnum, sim_ppc_spr547_regnum, + sim_ppc_spr548_regnum, sim_ppc_spr549_regnum, + sim_ppc_spr550_regnum, sim_ppc_spr551_regnum, + sim_ppc_spr552_regnum, sim_ppc_spr553_regnum, + sim_ppc_spr554_regnum, sim_ppc_spr555_regnum, + sim_ppc_spr556_regnum, sim_ppc_spr557_regnum, + sim_ppc_spr558_regnum, sim_ppc_spr559_regnum, + sim_ppc_spr560_regnum, sim_ppc_spr561_regnum, + sim_ppc_spr562_regnum, sim_ppc_spr563_regnum, + sim_ppc_spr564_regnum, sim_ppc_spr565_regnum, + sim_ppc_spr566_regnum, sim_ppc_spr567_regnum, + sim_ppc_spr568_regnum, sim_ppc_spr569_regnum, + sim_ppc_spr570_regnum, sim_ppc_spr571_regnum, + sim_ppc_spr572_regnum, sim_ppc_spr573_regnum, + sim_ppc_spr574_regnum, sim_ppc_spr575_regnum, + sim_ppc_spr576_regnum, sim_ppc_spr577_regnum, + sim_ppc_spr578_regnum, sim_ppc_spr579_regnum, + sim_ppc_spr580_regnum, sim_ppc_spr581_regnum, + sim_ppc_spr582_regnum, sim_ppc_spr583_regnum, + sim_ppc_spr584_regnum, sim_ppc_spr585_regnum, + sim_ppc_spr586_regnum, sim_ppc_spr587_regnum, + sim_ppc_spr588_regnum, sim_ppc_spr589_regnum, + sim_ppc_spr590_regnum, sim_ppc_spr591_regnum, + sim_ppc_spr592_regnum, sim_ppc_spr593_regnum, + sim_ppc_spr594_regnum, sim_ppc_spr595_regnum, + sim_ppc_spr596_regnum, sim_ppc_spr597_regnum, + sim_ppc_spr598_regnum, sim_ppc_spr599_regnum, + sim_ppc_spr600_regnum, sim_ppc_spr601_regnum, + sim_ppc_spr602_regnum, sim_ppc_spr603_regnum, + sim_ppc_spr604_regnum, sim_ppc_spr605_regnum, + sim_ppc_spr606_regnum, sim_ppc_spr607_regnum, + sim_ppc_spr608_regnum, sim_ppc_spr609_regnum, + sim_ppc_spr610_regnum, sim_ppc_spr611_regnum, + sim_ppc_spr612_regnum, sim_ppc_spr613_regnum, + sim_ppc_spr614_regnum, sim_ppc_spr615_regnum, + sim_ppc_spr616_regnum, sim_ppc_spr617_regnum, + sim_ppc_spr618_regnum, sim_ppc_spr619_regnum, + sim_ppc_spr620_regnum, sim_ppc_spr621_regnum, + sim_ppc_spr622_regnum, sim_ppc_spr623_regnum, + sim_ppc_spr624_regnum, sim_ppc_spr625_regnum, + sim_ppc_spr626_regnum, sim_ppc_spr627_regnum, + sim_ppc_spr628_regnum, sim_ppc_spr629_regnum, + sim_ppc_spr630_regnum, sim_ppc_spr631_regnum, + sim_ppc_spr632_regnum, sim_ppc_spr633_regnum, + sim_ppc_spr634_regnum, sim_ppc_spr635_regnum, + sim_ppc_spr636_regnum, sim_ppc_spr637_regnum, + sim_ppc_spr638_regnum, sim_ppc_spr639_regnum, + sim_ppc_spr640_regnum, sim_ppc_spr641_regnum, + sim_ppc_spr642_regnum, sim_ppc_spr643_regnum, + sim_ppc_spr644_regnum, sim_ppc_spr645_regnum, + sim_ppc_spr646_regnum, sim_ppc_spr647_regnum, + sim_ppc_spr648_regnum, sim_ppc_spr649_regnum, + sim_ppc_spr650_regnum, sim_ppc_spr651_regnum, + sim_ppc_spr652_regnum, sim_ppc_spr653_regnum, + sim_ppc_spr654_regnum, sim_ppc_spr655_regnum, + sim_ppc_spr656_regnum, sim_ppc_spr657_regnum, + sim_ppc_spr658_regnum, sim_ppc_spr659_regnum, + sim_ppc_spr660_regnum, sim_ppc_spr661_regnum, + sim_ppc_spr662_regnum, sim_ppc_spr663_regnum, + sim_ppc_spr664_regnum, sim_ppc_spr665_regnum, + sim_ppc_spr666_regnum, sim_ppc_spr667_regnum, + sim_ppc_spr668_regnum, sim_ppc_spr669_regnum, + sim_ppc_spr670_regnum, sim_ppc_spr671_regnum, + sim_ppc_spr672_regnum, sim_ppc_spr673_regnum, + sim_ppc_spr674_regnum, sim_ppc_spr675_regnum, + sim_ppc_spr676_regnum, sim_ppc_spr677_regnum, + sim_ppc_spr678_regnum, sim_ppc_spr679_regnum, + sim_ppc_spr680_regnum, sim_ppc_spr681_regnum, + sim_ppc_spr682_regnum, sim_ppc_spr683_regnum, + sim_ppc_spr684_regnum, sim_ppc_spr685_regnum, + sim_ppc_spr686_regnum, sim_ppc_spr687_regnum, + sim_ppc_spr688_regnum, sim_ppc_spr689_regnum, + sim_ppc_spr690_regnum, sim_ppc_spr691_regnum, + sim_ppc_spr692_regnum, sim_ppc_spr693_regnum, + sim_ppc_spr694_regnum, sim_ppc_spr695_regnum, + sim_ppc_spr696_regnum, sim_ppc_spr697_regnum, + sim_ppc_spr698_regnum, sim_ppc_spr699_regnum, + sim_ppc_spr700_regnum, sim_ppc_spr701_regnum, + sim_ppc_spr702_regnum, sim_ppc_spr703_regnum, + sim_ppc_spr704_regnum, sim_ppc_spr705_regnum, + sim_ppc_spr706_regnum, sim_ppc_spr707_regnum, + sim_ppc_spr708_regnum, sim_ppc_spr709_regnum, + sim_ppc_spr710_regnum, sim_ppc_spr711_regnum, + sim_ppc_spr712_regnum, sim_ppc_spr713_regnum, + sim_ppc_spr714_regnum, sim_ppc_spr715_regnum, + sim_ppc_spr716_regnum, sim_ppc_spr717_regnum, + sim_ppc_spr718_regnum, sim_ppc_spr719_regnum, + sim_ppc_spr720_regnum, sim_ppc_spr721_regnum, + sim_ppc_spr722_regnum, sim_ppc_spr723_regnum, + sim_ppc_spr724_regnum, sim_ppc_spr725_regnum, + sim_ppc_spr726_regnum, sim_ppc_spr727_regnum, + sim_ppc_spr728_regnum, sim_ppc_spr729_regnum, + sim_ppc_spr730_regnum, sim_ppc_spr731_regnum, + sim_ppc_spr732_regnum, sim_ppc_spr733_regnum, + sim_ppc_spr734_regnum, sim_ppc_spr735_regnum, + sim_ppc_spr736_regnum, sim_ppc_spr737_regnum, + sim_ppc_spr738_regnum, sim_ppc_spr739_regnum, + sim_ppc_spr740_regnum, sim_ppc_spr741_regnum, + sim_ppc_spr742_regnum, sim_ppc_spr743_regnum, + sim_ppc_spr744_regnum, sim_ppc_spr745_regnum, + sim_ppc_spr746_regnum, sim_ppc_spr747_regnum, + sim_ppc_spr748_regnum, sim_ppc_spr749_regnum, + sim_ppc_spr750_regnum, sim_ppc_spr751_regnum, + sim_ppc_spr752_regnum, sim_ppc_spr753_regnum, + sim_ppc_spr754_regnum, sim_ppc_spr755_regnum, + sim_ppc_spr756_regnum, sim_ppc_spr757_regnum, + sim_ppc_spr758_regnum, sim_ppc_spr759_regnum, + sim_ppc_spr760_regnum, sim_ppc_spr761_regnum, + sim_ppc_spr762_regnum, sim_ppc_spr763_regnum, + sim_ppc_spr764_regnum, sim_ppc_spr765_regnum, + sim_ppc_spr766_regnum, sim_ppc_spr767_regnum, + sim_ppc_spr768_regnum, sim_ppc_spr769_regnum, + sim_ppc_spr770_regnum, sim_ppc_spr771_regnum, + sim_ppc_spr772_regnum, sim_ppc_spr773_regnum, + sim_ppc_spr774_regnum, sim_ppc_spr775_regnum, + sim_ppc_spr776_regnum, sim_ppc_spr777_regnum, + sim_ppc_spr778_regnum, sim_ppc_spr779_regnum, + sim_ppc_spr780_regnum, sim_ppc_spr781_regnum, + sim_ppc_spr782_regnum, sim_ppc_spr783_regnum, + sim_ppc_spr784_regnum, sim_ppc_spr785_regnum, + sim_ppc_spr786_regnum, sim_ppc_spr787_regnum, + sim_ppc_spr788_regnum, sim_ppc_spr789_regnum, + sim_ppc_spr790_regnum, sim_ppc_spr791_regnum, + sim_ppc_spr792_regnum, sim_ppc_spr793_regnum, + sim_ppc_spr794_regnum, sim_ppc_spr795_regnum, + sim_ppc_spr796_regnum, sim_ppc_spr797_regnum, + sim_ppc_spr798_regnum, sim_ppc_spr799_regnum, + sim_ppc_spr800_regnum, sim_ppc_spr801_regnum, + sim_ppc_spr802_regnum, sim_ppc_spr803_regnum, + sim_ppc_spr804_regnum, sim_ppc_spr805_regnum, + sim_ppc_spr806_regnum, sim_ppc_spr807_regnum, + sim_ppc_spr808_regnum, sim_ppc_spr809_regnum, + sim_ppc_spr810_regnum, sim_ppc_spr811_regnum, + sim_ppc_spr812_regnum, sim_ppc_spr813_regnum, + sim_ppc_spr814_regnum, sim_ppc_spr815_regnum, + sim_ppc_spr816_regnum, sim_ppc_spr817_regnum, + sim_ppc_spr818_regnum, sim_ppc_spr819_regnum, + sim_ppc_spr820_regnum, sim_ppc_spr821_regnum, + sim_ppc_spr822_regnum, sim_ppc_spr823_regnum, + sim_ppc_spr824_regnum, sim_ppc_spr825_regnum, + sim_ppc_spr826_regnum, sim_ppc_spr827_regnum, + sim_ppc_spr828_regnum, sim_ppc_spr829_regnum, + sim_ppc_spr830_regnum, sim_ppc_spr831_regnum, + sim_ppc_spr832_regnum, sim_ppc_spr833_regnum, + sim_ppc_spr834_regnum, sim_ppc_spr835_regnum, + sim_ppc_spr836_regnum, sim_ppc_spr837_regnum, + sim_ppc_spr838_regnum, sim_ppc_spr839_regnum, + sim_ppc_spr840_regnum, sim_ppc_spr841_regnum, + sim_ppc_spr842_regnum, sim_ppc_spr843_regnum, + sim_ppc_spr844_regnum, sim_ppc_spr845_regnum, + sim_ppc_spr846_regnum, sim_ppc_spr847_regnum, + sim_ppc_spr848_regnum, sim_ppc_spr849_regnum, + sim_ppc_spr850_regnum, sim_ppc_spr851_regnum, + sim_ppc_spr852_regnum, sim_ppc_spr853_regnum, + sim_ppc_spr854_regnum, sim_ppc_spr855_regnum, + sim_ppc_spr856_regnum, sim_ppc_spr857_regnum, + sim_ppc_spr858_regnum, sim_ppc_spr859_regnum, + sim_ppc_spr860_regnum, sim_ppc_spr861_regnum, + sim_ppc_spr862_regnum, sim_ppc_spr863_regnum, + sim_ppc_spr864_regnum, sim_ppc_spr865_regnum, + sim_ppc_spr866_regnum, sim_ppc_spr867_regnum, + sim_ppc_spr868_regnum, sim_ppc_spr869_regnum, + sim_ppc_spr870_regnum, sim_ppc_spr871_regnum, + sim_ppc_spr872_regnum, sim_ppc_spr873_regnum, + sim_ppc_spr874_regnum, sim_ppc_spr875_regnum, + sim_ppc_spr876_regnum, sim_ppc_spr877_regnum, + sim_ppc_spr878_regnum, sim_ppc_spr879_regnum, + sim_ppc_spr880_regnum, sim_ppc_spr881_regnum, + sim_ppc_spr882_regnum, sim_ppc_spr883_regnum, + sim_ppc_spr884_regnum, sim_ppc_spr885_regnum, + sim_ppc_spr886_regnum, sim_ppc_spr887_regnum, + sim_ppc_spr888_regnum, sim_ppc_spr889_regnum, + sim_ppc_spr890_regnum, sim_ppc_spr891_regnum, + sim_ppc_spr892_regnum, sim_ppc_spr893_regnum, + sim_ppc_spr894_regnum, sim_ppc_spr895_regnum, + sim_ppc_spr896_regnum, sim_ppc_spr897_regnum, + sim_ppc_spr898_regnum, sim_ppc_spr899_regnum, + sim_ppc_spr900_regnum, sim_ppc_spr901_regnum, + sim_ppc_spr902_regnum, sim_ppc_spr903_regnum, + sim_ppc_spr904_regnum, sim_ppc_spr905_regnum, + sim_ppc_spr906_regnum, sim_ppc_spr907_regnum, + sim_ppc_spr908_regnum, sim_ppc_spr909_regnum, + sim_ppc_spr910_regnum, sim_ppc_spr911_regnum, + sim_ppc_spr912_regnum, sim_ppc_spr913_regnum, + sim_ppc_spr914_regnum, sim_ppc_spr915_regnum, + sim_ppc_spr916_regnum, sim_ppc_spr917_regnum, + sim_ppc_spr918_regnum, sim_ppc_spr919_regnum, + sim_ppc_spr920_regnum, sim_ppc_spr921_regnum, + sim_ppc_spr922_regnum, sim_ppc_spr923_regnum, + sim_ppc_spr924_regnum, sim_ppc_spr925_regnum, + sim_ppc_spr926_regnum, sim_ppc_spr927_regnum, + sim_ppc_spr928_regnum, sim_ppc_spr929_regnum, + sim_ppc_spr930_regnum, sim_ppc_spr931_regnum, + sim_ppc_spr932_regnum, sim_ppc_spr933_regnum, + sim_ppc_spr934_regnum, sim_ppc_spr935_regnum, + sim_ppc_spr936_regnum, sim_ppc_spr937_regnum, + sim_ppc_spr938_regnum, sim_ppc_spr939_regnum, + sim_ppc_spr940_regnum, sim_ppc_spr941_regnum, + sim_ppc_spr942_regnum, sim_ppc_spr943_regnum, + sim_ppc_spr944_regnum, sim_ppc_spr945_regnum, + sim_ppc_spr946_regnum, sim_ppc_spr947_regnum, + sim_ppc_spr948_regnum, sim_ppc_spr949_regnum, + sim_ppc_spr950_regnum, sim_ppc_spr951_regnum, + sim_ppc_spr952_regnum, sim_ppc_spr953_regnum, + sim_ppc_spr954_regnum, sim_ppc_spr955_regnum, + sim_ppc_spr956_regnum, sim_ppc_spr957_regnum, + sim_ppc_spr958_regnum, sim_ppc_spr959_regnum, + sim_ppc_spr960_regnum, sim_ppc_spr961_regnum, + sim_ppc_spr962_regnum, sim_ppc_spr963_regnum, + sim_ppc_spr964_regnum, sim_ppc_spr965_regnum, + sim_ppc_spr966_regnum, sim_ppc_spr967_regnum, + sim_ppc_spr968_regnum, sim_ppc_spr969_regnum, + sim_ppc_spr970_regnum, sim_ppc_spr971_regnum, + sim_ppc_spr972_regnum, sim_ppc_spr973_regnum, + sim_ppc_spr974_regnum, sim_ppc_spr975_regnum, + sim_ppc_spr976_regnum, sim_ppc_spr977_regnum, + sim_ppc_spr978_regnum, sim_ppc_spr979_regnum, + sim_ppc_spr980_regnum, sim_ppc_spr981_regnum, + sim_ppc_spr982_regnum, sim_ppc_spr983_regnum, + sim_ppc_spr984_regnum, sim_ppc_spr985_regnum, + sim_ppc_spr986_regnum, sim_ppc_spr987_regnum, + sim_ppc_spr988_regnum, sim_ppc_spr989_regnum, + sim_ppc_spr990_regnum, sim_ppc_spr991_regnum, + sim_ppc_spr992_regnum, sim_ppc_spr993_regnum, + sim_ppc_spr994_regnum, sim_ppc_spr995_regnum, + sim_ppc_spr996_regnum, sim_ppc_spr997_regnum, + sim_ppc_spr998_regnum, sim_ppc_spr999_regnum, + sim_ppc_spr1000_regnum, sim_ppc_spr1001_regnum, + sim_ppc_spr1002_regnum, sim_ppc_spr1003_regnum, + sim_ppc_spr1004_regnum, sim_ppc_spr1005_regnum, + sim_ppc_spr1006_regnum, sim_ppc_spr1007_regnum, + sim_ppc_spr1008_regnum, sim_ppc_spr1009_regnum, + sim_ppc_spr1010_regnum, sim_ppc_spr1011_regnum, + sim_ppc_spr1012_regnum, sim_ppc_spr1013_regnum, + sim_ppc_spr1014_regnum, sim_ppc_spr1015_regnum, + sim_ppc_spr1016_regnum, sim_ppc_spr1017_regnum, + sim_ppc_spr1018_regnum, sim_ppc_spr1019_regnum, + sim_ppc_spr1020_regnum, sim_ppc_spr1021_regnum, + sim_ppc_spr1022_regnum, sim_ppc_spr1023_regnum + }; + + +/* Sizes of various register sets. */ +enum + { + sim_ppc_num_gprs = 32, + sim_ppc_num_fprs = 32, + sim_ppc_num_vrs = 32, + sim_ppc_num_srs = 16, + sim_ppc_num_sprs = 1024, + }; + + +#ifdef __cplusplus +} +#endif + +#endif /* SIM_PPC_H */ diff --git a/include/gdb/sim-sh.h b/include/gdb/sim-sh.h new file mode 100644 index 000000000..a40eff631 --- /dev/null +++ b/include/gdb/sim-sh.h @@ -0,0 +1,170 @@ +/* This file defines the interface between the sh simulator and gdb. + Copyright (C) 2000, 2002, 2004 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (SIM_SH_H) +#define SIM_SH_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +/* The simulator makes use of the following register information. */ + +enum +{ + SIM_SH_R0_REGNUM = 0, + SIM_SH_R1_REGNUM, + SIM_SH_R2_REGNUM, + SIM_SH_R3_REGNUM, + SIM_SH_R4_REGNUM, + SIM_SH_R5_REGNUM, + SIM_SH_R6_REGNUM, + SIM_SH_R7_REGNUM, + SIM_SH_R8_REGNUM, + SIM_SH_R9_REGNUM, + SIM_SH_R10_REGNUM, + SIM_SH_R11_REGNUM, + SIM_SH_R12_REGNUM, + SIM_SH_R13_REGNUM, + SIM_SH_R14_REGNUM, + SIM_SH_R15_REGNUM, + SIM_SH_PC_REGNUM, + SIM_SH_PR_REGNUM, + SIM_SH_GBR_REGNUM, + SIM_SH_VBR_REGNUM, + SIM_SH_MACH_REGNUM, + SIM_SH_MACL_REGNUM, + SIM_SH_SR_REGNUM, + SIM_SH_FPUL_REGNUM, + SIM_SH_FPSCR_REGNUM, + SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */ + SIM_SH_FR1_REGNUM, + SIM_SH_FR2_REGNUM, + SIM_SH_FR3_REGNUM, + SIM_SH_FR4_REGNUM, + SIM_SH_FR5_REGNUM, + SIM_SH_FR6_REGNUM, + SIM_SH_FR7_REGNUM, + SIM_SH_FR8_REGNUM, + SIM_SH_FR9_REGNUM, + SIM_SH_FR10_REGNUM, + SIM_SH_FR11_REGNUM, + SIM_SH_FR12_REGNUM, + SIM_SH_FR13_REGNUM, + SIM_SH_FR14_REGNUM, + SIM_SH_FR15_REGNUM, + SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */ + SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */ + SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */ + SIM_SH_R1_BANK0_REGNUM, + SIM_SH_R2_BANK0_REGNUM, + SIM_SH_R3_BANK0_REGNUM, + SIM_SH_R4_BANK0_REGNUM, + SIM_SH_R5_BANK0_REGNUM, + SIM_SH_R6_BANK0_REGNUM, + SIM_SH_R7_BANK0_REGNUM, + SIM_SH_R0_BANK1_REGNUM, + SIM_SH_R1_BANK1_REGNUM, + SIM_SH_R2_BANK1_REGNUM, + SIM_SH_R3_BANK1_REGNUM, + SIM_SH_R4_BANK1_REGNUM, + SIM_SH_R5_BANK1_REGNUM, + SIM_SH_R6_BANK1_REGNUM, + SIM_SH_R7_BANK1_REGNUM, + SIM_SH_XF0_REGNUM, + SIM_SH_XF1_REGNUM, + SIM_SH_XF2_REGNUM, + SIM_SH_XF3_REGNUM, + SIM_SH_XF4_REGNUM, + SIM_SH_XF5_REGNUM, + SIM_SH_XF6_REGNUM, + SIM_SH_XF7_REGNUM, + SIM_SH_XF8_REGNUM, + SIM_SH_XF9_REGNUM, + SIM_SH_XF10_REGNUM, + SIM_SH_XF11_REGNUM, + SIM_SH_XF12_REGNUM, + SIM_SH_XF13_REGNUM, + SIM_SH_XF14_REGNUM, + SIM_SH_XF15_REGNUM, + SIM_SH_SGR_REGNUM, + SIM_SH_DBR_REGNUM, + SIM_SH4_NUM_REGS, /* 77 */ + + /* sh[3]-dsp */ + SIM_SH_DSR_REGNUM, + SIM_SH_A0G_REGNUM, + SIM_SH_A0_REGNUM, + SIM_SH_A1G_REGNUM, + SIM_SH_A1_REGNUM, + SIM_SH_M0_REGNUM, + SIM_SH_M1_REGNUM, + SIM_SH_X0_REGNUM, + SIM_SH_X1_REGNUM, + SIM_SH_Y0_REGNUM, + SIM_SH_Y1_REGNUM, + SIM_SH_MOD_REGNUM, + SIM_SH_RS_REGNUM, + SIM_SH_RE_REGNUM, + SIM_SH_R0_BANK_REGNUM, + SIM_SH_R1_BANK_REGNUM, + SIM_SH_R2_BANK_REGNUM, + SIM_SH_R3_BANK_REGNUM, + SIM_SH_R4_BANK_REGNUM, + SIM_SH_R5_BANK_REGNUM, + SIM_SH_R6_BANK_REGNUM, + SIM_SH_R7_BANK_REGNUM, + /* 109..127: room for expansion. */ + SIM_SH_TBR_REGNUM, + SIM_SH_IBNR_REGNUM, + SIM_SH_IBCR_REGNUM, + SIM_SH_BANK_REGNUM, + SIM_SH_BANK_MACL_REGNUM, + SIM_SH_BANK_GBR_REGNUM, + SIM_SH_BANK_PR_REGNUM, + SIM_SH_BANK_IVN_REGNUM, + SIM_SH_BANK_MACH_REGNUM +}; + +enum +{ + SIM_SH64_R0_REGNUM = 0, + SIM_SH64_SP_REGNUM = 15, + SIM_SH64_PC_REGNUM = 64, + SIM_SH64_SR_REGNUM = 65, + SIM_SH64_SSR_REGNUM = 66, + SIM_SH64_SPC_REGNUM = 67, + SIM_SH64_TR0_REGNUM = 68, + SIM_SH64_FPCSR_REGNUM = 76, + SIM_SH64_FR0_REGNUM = 77 +}; + +enum +{ + SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ + SIM_SH64_NR_R_REGS = 64, /* number of general registers */ + SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ + SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/gdbm.h b/include/gdbm.h new file mode 100644 index 000000000..3ebc26d19 --- /dev/null +++ b/include/gdbm.h @@ -0,0 +1,91 @@ +/* GNU DBM - DataBase Manager include file + Copyright 1989, 1991 Free Software Foundation, Inc. + Written by Philip A. Nelson. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* You may contact the author by: + e-mail: phil@wwu.edu + us-mail: Philip A. Nelson + Computer Science Department + Western Washington University + Bellingham, WA 98226 + phone: (206) 676-3035 + +*************************************************************************/ + +/* Parameters to gdbm_open for READERS, WRITERS, and WRITERS who + can create the database. */ +#define GDBM_READER 0 +#define GDBM_WRITER 1 +#define GDBM_WRCREAT 2 +#define GDBM_NEWDB 3 + +/* Parameters to gdbm_store for simple insertion or replacement. */ +#define GDBM_INSERT 0 +#define GDBM_REPLACE 1 + + +/* The data and key structure. This structure is defined for compatibility. */ +typedef struct { + char *dptr; + int dsize; + } datum; + + +/* The file information header. This is good enough for most applications. */ +typedef struct {int dummy[10];} *GDBM_FILE; + + +/* These are the routines! */ + +extern GDBM_FILE gdbm_open (); + +extern void gdbm_close (); + +extern datum gdbm_fetch (); + +extern int gdbm_store (); + +extern int gdbm_delete (); + +extern datum gdbm_firstkey (); + +extern datum gdbm_nextkey (); + +extern int gdbm_reorganize (); + + +/* gdbm sends back the following error codes in the variable gdbm_errno. */ +typedef enum { NO_ERROR, + MALLOC_ERROR, + BLOCK_SIZE_ERROR, + FILE_OPEN_ERROR, + FILE_WRITE_ERROR, + FILE_SEEK_ERROR, + FILE_READ_ERROR, + BAD_MAGIC_NUMBER, + EMPTY_DATABASE, + CANT_BE_READER, + CANT_BE_WRITER, + READER_CANT_RECOVER, + READER_CANT_DELETE, + READER_CANT_STORE, + READER_CANT_REORGANIZE, + UNKNOWN_UPDATE, + ITEM_NOT_FOUND, + REORGANIZE_FAILED, + CANNOT_REPLACE} + gdbm_error; diff --git a/include/getopt.h b/include/getopt.h new file mode 100644 index 000000000..a99a22901 --- /dev/null +++ b/include/getopt.h @@ -0,0 +1,144 @@ +/* Declarations for getopt. + Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, + 2002 Free Software Foundation, Inc. + + NOTE: The canonical source of this file is maintained with the GNU C Library. + Bugs can be reported to bug-glibc@gnu.org. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ + +#ifndef _GETOPT_H +#define _GETOPT_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* For communication from `getopt' to the caller. + When `getopt' finds an option that takes an argument, + the argument value is returned here. + Also, when `ordering' is RETURN_IN_ORDER, + each non-option ARGV-element is returned here. */ + +extern char *optarg; + +/* Index in ARGV of the next element to be scanned. + This is used for communication to and from the caller + and for communication between successive calls to `getopt'. + + On entry to `getopt', zero means this is the first call; initialize. + + When `getopt' returns -1, this is the index of the first of the + non-option elements that the caller should itself scan. + + Otherwise, `optind' communicates from one call to the next + how much of ARGV has been scanned so far. */ + +extern int optind; + +/* Callers store zero here to inhibit the error message `getopt' prints + for unrecognized options. */ + +extern int opterr; + +/* Set to an option character which was unrecognized. */ + +extern int optopt; + +/* Describe the long-named options requested by the application. + The LONG_OPTIONS argument to getopt_long or getopt_long_only is a vector + of `struct option' terminated by an element containing a name which is + zero. + + The field `has_arg' is: + no_argument (or 0) if the option does not take an argument, + required_argument (or 1) if the option requires an argument, + optional_argument (or 2) if the option takes an optional argument. + + If the field `flag' is not NULL, it points to a variable that is set + to the value given in the field `val' when the option is found, but + left unchanged if the option is not found. + + To have a long-named option do something other than set an `int' to + a compiled-in constant, such as set a value from `optarg', set the + option's `flag' field to zero and its `val' field to a nonzero + value (the equivalent single-letter option character, if there is + one). For long options that have a zero `flag' field, `getopt' + returns the contents of the `val' field. */ + +struct option +{ +#if defined (__STDC__) && __STDC__ + const char *name; +#else + char *name; +#endif + /* has_arg can't be an enum because some compilers complain about + type mismatches in all the code that assumes it is an int. */ + int has_arg; + int *flag; + int val; +}; + +/* Names for the values of the `has_arg' field of `struct option'. */ + +#define no_argument 0 +#define required_argument 1 +#define optional_argument 2 + +#if defined (__STDC__) && __STDC__ +/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is + undefined, we haven't run the autoconf check so provide the + declaration without arguments. If it is 0, we checked and failed + to find the declaration so provide a fully prototyped one. If it + is 1, we found it so don't provide any declaration at all. */ +#if !HAVE_DECL_GETOPT +#if defined (__GNU_LIBRARY__) || defined (HAVE_DECL_GETOPT) +/* Many other libraries have conflicting prototypes for getopt, with + differences in the consts, in unistd.h. To avoid compilation + errors, only prototype getopt for the GNU C library. */ +extern int getopt (int argc, char *const *argv, const char *shortopts); +#else +#ifndef __cplusplus +extern int getopt (); +#endif /* __cplusplus */ +#endif +#endif /* !HAVE_DECL_GETOPT */ + +extern int getopt_long (int argc, char *const *argv, const char *shortopts, + const struct option *longopts, int *longind); +extern int getopt_long_only (int argc, char *const *argv, + const char *shortopts, + const struct option *longopts, int *longind); + +/* Internal only. Users should not call this directly. */ +extern int _getopt_internal (int argc, char *const *argv, + const char *shortopts, + const struct option *longopts, int *longind, + int long_only); +#else /* not __STDC__ */ +extern int getopt (); +extern int getopt_long (); +extern int getopt_long_only (); + +extern int _getopt_internal (); +#endif /* __STDC__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* getopt.h */ diff --git a/include/hashtab.h b/include/hashtab.h new file mode 100644 index 000000000..de24dedb9 --- /dev/null +++ b/include/hashtab.h @@ -0,0 +1,200 @@ +/* An expandable hash tables datatype. + Copyright (C) 1999, 2000, 2002, 2003, 2004 Free Software Foundation, Inc. + Contributed by Vladimir Makarov (vmakarov@cygnus.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This package implements basic hash table functionality. It is possible + to search for an entry, create an entry and destroy an entry. + + Elements in the table are generic pointers. + + The size of the table is not fixed; if the occupancy of the table + grows too high the hash table will be expanded. + + The abstract data implementation is based on generalized Algorithm D + from Knuth's book "The art of computer programming". Hash table is + expanded by creation of new hash table and transferring elements from + the old table to the new table. */ + +#ifndef __HASHTAB_H__ +#define __HASHTAB_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ansidecl.h" + +#ifndef GTY +#define GTY(X) +#endif + +/* The type for a hash code. */ +typedef unsigned int hashval_t; + +/* Callback function pointer types. */ + +/* Calculate hash of a table entry. */ +typedef hashval_t (*htab_hash) PARAMS ((const void *)); + +/* Compare a table entry with a possible entry. The entry already in + the table always comes first, so the second element can be of a + different type (but in this case htab_find and htab_find_slot + cannot be used; instead the variants that accept a hash value + must be used). */ +typedef int (*htab_eq) PARAMS ((const void *, const void *)); + +/* Cleanup function called whenever a live element is removed from + the hash table. */ +typedef void (*htab_del) PARAMS ((void *)); + +/* Function called by htab_traverse for each live element. The first + arg is the slot of the element (which can be passed to htab_clear_slot + if desired), the second arg is the auxiliary pointer handed to + htab_traverse. Return 1 to continue scan, 0 to stop. */ +typedef int (*htab_trav) PARAMS ((void **, void *)); + +/* Memory-allocation function, with the same functionality as calloc(). + Iff it returns NULL, the hash table implementation will pass an error + code back to the user, so if your code doesn't handle errors, + best if you use xcalloc instead. */ +typedef PTR (*htab_alloc) PARAMS ((size_t, size_t)); + +/* We also need a free() routine. */ +typedef void (*htab_free) PARAMS ((PTR)); + +/* Memory allocation and deallocation; variants which take an extra + argument. */ +typedef PTR (*htab_alloc_with_arg) PARAMS ((void *, size_t, size_t)); +typedef void (*htab_free_with_arg) PARAMS ((void *, void *)); + +/* Hash tables are of the following type. The structure + (implementation) of this type is not needed for using the hash + tables. All work with hash table should be executed only through + functions mentioned below. The size of this structure is subject to + change. */ + +struct htab GTY(()) +{ + /* Pointer to hash function. */ + htab_hash hash_f; + + /* Pointer to comparison function. */ + htab_eq eq_f; + + /* Pointer to cleanup function. */ + htab_del del_f; + + /* Table itself. */ + PTR * GTY ((use_param, length ("%h.size"))) entries; + + /* Current size (in entries) of the hash table. */ + size_t size; + + /* Current number of elements including also deleted elements. */ + size_t n_elements; + + /* Current number of deleted elements in the table. */ + size_t n_deleted; + + /* The following member is used for debugging. Its value is number + of all calls of `htab_find_slot' for the hash table. */ + unsigned int searches; + + /* The following member is used for debugging. Its value is number + of collisions fixed for time of work with the hash table. */ + unsigned int collisions; + + /* Pointers to allocate/free functions. */ + htab_alloc alloc_f; + htab_free free_f; + + /* Alternate allocate/free functions, which take an extra argument. */ + PTR GTY((skip)) alloc_arg; + htab_alloc_with_arg alloc_with_arg_f; + htab_free_with_arg free_with_arg_f; + + /* Current size (in entries) of the hash table, as an index into the + table of primes. */ + unsigned int size_prime_index; +}; + +typedef struct htab *htab_t; + +/* An enum saying whether we insert into the hash table or not. */ +enum insert_option {NO_INSERT, INSERT}; + +/* The prototypes of the package functions. */ + +extern htab_t htab_create_alloc PARAMS ((size_t, htab_hash, + htab_eq, htab_del, + htab_alloc, htab_free)); + +extern htab_t htab_create_alloc_ex PARAMS ((size_t, htab_hash, + htab_eq, htab_del, + PTR, htab_alloc_with_arg, + htab_free_with_arg)); + +/* Backward-compatibility functions. */ +extern htab_t htab_create PARAMS ((size_t, htab_hash, htab_eq, htab_del)); +extern htab_t htab_try_create PARAMS ((size_t, htab_hash, htab_eq, htab_del)); + +extern void htab_set_functions_ex PARAMS ((htab_t, htab_hash, + htab_eq, htab_del, + PTR, htab_alloc_with_arg, + htab_free_with_arg)); + +extern void htab_delete PARAMS ((htab_t)); +extern void htab_empty PARAMS ((htab_t)); + +extern PTR htab_find PARAMS ((htab_t, const void *)); +extern PTR *htab_find_slot PARAMS ((htab_t, const void *, + enum insert_option)); +extern PTR htab_find_with_hash PARAMS ((htab_t, const void *, + hashval_t)); +extern PTR *htab_find_slot_with_hash PARAMS ((htab_t, const void *, + hashval_t, + enum insert_option)); +extern void htab_clear_slot PARAMS ((htab_t, void **)); +extern void htab_remove_elt PARAMS ((htab_t, void *)); +extern void htab_remove_elt_with_hash PARAMS ((htab_t, void *, hashval_t)); + +extern void htab_traverse PARAMS ((htab_t, htab_trav, void *)); +extern void htab_traverse_noresize PARAMS ((htab_t, htab_trav, void *)); + +extern size_t htab_size PARAMS ((htab_t)); +extern size_t htab_elements PARAMS ((htab_t)); +extern double htab_collisions PARAMS ((htab_t)); + +/* A hash function for pointers. */ +extern htab_hash htab_hash_pointer; + +/* An equality function for pointers. */ +extern htab_eq htab_eq_pointer; + +/* A hash function for null-terminated strings. */ +extern hashval_t htab_hash_string PARAMS ((const PTR)); + +/* An iterative hash function for arbitrary data. */ +extern hashval_t iterative_hash PARAMS ((const PTR, size_t, hashval_t)); +/* Shorthand for hashing something with an intrinsic size. */ +#define iterative_hash_object(OB,INIT) iterative_hash (&OB, sizeof (OB), INIT) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __HASHTAB_H */ diff --git a/include/hp-symtab.h b/include/hp-symtab.h new file mode 100644 index 000000000..6267d5572 --- /dev/null +++ b/include/hp-symtab.h @@ -0,0 +1,1866 @@ +/* Definitions and structures for reading debug symbols from the + native HP C compiler. + + Written by the Center for Software Science at the University of Utah + and by Cygnus Support. + + Copyright 1994, 1995, 1998, 1999, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef HP_SYMTAB_INCLUDED +#define HP_SYMTAB_INCLUDED + +/* General information: + + This header file defines and describes only the data structures + necessary to read debug symbols produced by the HP C compiler, + HP ANSI C++ compiler, and HP FORTRAN 90 compiler using the + SOM object file format. + (For a full description of the debug format, ftp hpux-symtab.h from + jaguar.cs.utah.edu:/dist). + + Additional notes (Rich Title) + This file is a reverse-engineered version of a file called + "symtab.h" which exists internal to HP's Computer Languages Organization + in /CLO/Components/DDE/obj/som/symtab.h. Because HP's version of + the file is copyrighted and not distributed, it is necessary for + GDB to use the reverse-engineered version that follows. + Work was done by Cygnus to reverse-engineer the C subset of symtab.h. + The WDB project has extended this to also contain the C++ + symbol definitions, the F90 symbol definitions, + and the DOC (debugging-optimized-code) symbol definitions. + In some cases (the C++ symbol definitions) + I have added internal documentation here that + goes beyond what is supplied in HP's symtab.h. If we someday + unify these files again, the extra comments should be merged back + into HP's symtab.h. + + ------------------------------------------------------------------- + + Debug symbols are contained entirely within an unloadable space called + $DEBUG$. $DEBUG$ contains several subspaces which group related + debug symbols. + + $GNTT$ contains information for global variables, types and contants. + + $LNTT$ contains information for procedures (including nesting), scoping + information, local variables, types, and constants. + + $SLT$ contains source line information so that code addresses may be + mapped to source lines. + + $VT$ contains various strings and constants for named objects (variables, + typedefs, functions, etc). Strings are stored as null-terminated character + lists. Constants always begin on word boundaries. The first byte of + the VT must be zero (a null string). + + $XT$ is not currently used by GDB. + + Many structures within the subspaces point to other structures within + the same subspace, or to structures within a different subspace. These + pointers are represented as a structure index from the beginning of + the appropriate subspace. */ + +/* Used to describe where a constant is stored. */ +enum location_type +{ + LOCATION_IMMEDIATE, + LOCATION_PTR, + LOCATION_VT, +}; + +/* Languages supported by this debug format. Within the data structures + this type is limited to 4 bits for a maximum of 16 languages. */ +enum hp_language +{ + HP_LANGUAGE_UNKNOWN, + HP_LANGUAGE_C, + HP_LANGUAGE_FORTRAN, + HP_LANGUAGE_F77 = HP_LANGUAGE_FORTRAN, + HP_LANGUAGE_PASCAL, + HP_LANGUAGE_MODCAL, + HP_LANGUAGE_COBOL, + HP_LANGUAGE_BASIC, + HP_LANGUAGE_ADA, + HP_LANGUAGE_CPLUSPLUS, + HP_LANGUAGE_DMPASCAL +}; + + +/* Basic data types available in this debug format. Within the data + structures this type is limited to 5 bits for a maximum of 32 basic + data types. */ +enum hp_type +{ + HP_TYPE_UNDEFINED, /* 0 */ + HP_TYPE_BOOLEAN, /* 1 */ + HP_TYPE_CHAR, /* 2 */ + HP_TYPE_INT, /* 3 */ + HP_TYPE_UNSIGNED_INT, /* 4 */ + HP_TYPE_REAL, /* 5 */ + HP_TYPE_COMPLEX, /* 6 */ + HP_TYPE_STRING200, /* 7 */ + HP_TYPE_LONGSTRING200, /* 8 */ + HP_TYPE_TEXT, /* 9 */ + HP_TYPE_FLABEL, /* 10 */ + HP_TYPE_FTN_STRING_SPEC, /* 11 */ + HP_TYPE_MOD_STRING_SPEC, /* 12 */ + HP_TYPE_PACKED_DECIMAL, /* 13 */ + HP_TYPE_REAL_3000, /* 14 */ + HP_TYPE_MOD_STRING_3000, /* 15 */ + HP_TYPE_ANYPOINTER, /* 16 */ + HP_TYPE_GLOBAL_ANYPOINTER, /* 17 */ + HP_TYPE_LOCAL_ANYPOINTER, /* 18 */ + HP_TYPE_COMPLEXS3000, /* 19 */ + HP_TYPE_FTN_STRING_S300_COMPAT, /* 20 */ + HP_TYPE_FTN_STRING_VAX_COMPAT, /* 21 */ + HP_TYPE_BOOLEAN_S300_COMPAT, /* 22 */ + HP_TYPE_BOOLEAN_VAX_COMPAT, /* 23 */ + HP_TYPE_WIDE_CHAR, /* 24 */ + HP_TYPE_LONG, /* 25 */ + HP_TYPE_UNSIGNED_LONG, /* 26 */ + HP_TYPE_DOUBLE, /* 27 */ + HP_TYPE_TEMPLATE_ARG, /* 28 */ + HP_TYPE_VOID /* 29 */ +}; + +/* An immediate name and type table entry. + + extension and immediate will always be one. + global will always be zero. + hp_type is the basic type this entry describes. + bitlength is the length in bits for the basic type. */ +struct dnttp_immediate +{ + unsigned int extension: 1; + unsigned int immediate: 1; + unsigned int global: 1; + unsigned int type: 5; + unsigned int bitlength: 24; +}; + +/* A nonimmediate name and type table entry. + + extension will always be one. + immediate will always be zero. + if global is zero, this entry points into the LNTT + if global is one, this entry points into the GNTT + index is the index within the GNTT or LNTT for this entry. */ +struct dnttp_nonimmediate +{ + unsigned int extension: 1; + unsigned int immediate: 1; + unsigned int global: 1; + unsigned int index: 29; +}; + +/* A pointer to an entry in the GNTT and LNTT tables. It has two + forms depending on the type being described. + + The immediate form is used for simple entries and is one + word. + + The nonimmediate form is used for complex entries and contains + an index into the LNTT or GNTT which describes the entire type. + + If a dnttpointer is -1, then it is a NIL entry. */ + +#define DNTTNIL (-1) +typedef union dnttpointer +{ + struct dnttp_immediate dntti; + struct dnttp_nonimmediate dnttp; + int word; +} dnttpointer; + +/* An index into the source line table. As with dnttpointers, a sltpointer + of -1 indicates a NIL entry. */ +#define SLTNIL (-1) +typedef int sltpointer; + +/* Index into DOC (= "Debugging Optimized Code") line table. */ +#define LTNIL (-1) +typedef int ltpointer; + +/* Index into context table. */ +#define CTXTNIL (-1) +typedef int ctxtpointer; + +/* Unsigned byte offset into the VT. */ +typedef unsigned int vtpointer; + +/* A DNTT entry (used within the GNTT and LNTT). + + DNTT entries are variable sized objects, but are always a multiple + of 3 words (we call each group of 3 words a "block"). + + The first bit in each block is an extension bit. This bit is zero + for the first block of a DNTT entry. If the entry requires more + than one block, then this bit is set to one in all blocks after + the first one. */ + +/* Each DNTT entry describes a particular debug symbol (beginning of + a source file, a function, variables, structures, etc. + + The type of the DNTT entry is stored in the "kind" field within the + DNTT entry itself. */ + +enum dntt_entry_type +{ + DNTT_TYPE_NIL = -1, + DNTT_TYPE_SRCFILE, + DNTT_TYPE_MODULE, + DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BEGIN, + DNTT_TYPE_END, + DNTT_TYPE_IMPORT, + DNTT_TYPE_LABEL, + DNTT_TYPE_FPARAM, + DNTT_TYPE_SVAR, + DNTT_TYPE_DVAR, + DNTT_TYPE_HOLE1, + DNTT_TYPE_CONST, + DNTT_TYPE_TYPEDEF, + DNTT_TYPE_TAGDEF, + DNTT_TYPE_POINTER, + DNTT_TYPE_ENUM, + DNTT_TYPE_MEMENUM, + DNTT_TYPE_SET, + DNTT_TYPE_SUBRANGE, + DNTT_TYPE_ARRAY, + DNTT_TYPE_STRUCT, + DNTT_TYPE_UNION, + DNTT_TYPE_FIELD, + DNTT_TYPE_VARIANT, + DNTT_TYPE_FILE, + DNTT_TYPE_FUNCTYPE, + DNTT_TYPE_WITH, + DNTT_TYPE_COMMON, + DNTT_TYPE_COBSTRUCT, + DNTT_TYPE_XREF, + DNTT_TYPE_SA, + DNTT_TYPE_MACRO, + DNTT_TYPE_BLOCKDATA, + DNTT_TYPE_CLASS_SCOPE, + DNTT_TYPE_REFERENCE, + DNTT_TYPE_PTRMEM, + DNTT_TYPE_PTRMEMFUNC, + DNTT_TYPE_CLASS, + DNTT_TYPE_GENFIELD, + DNTT_TYPE_VFUNC, + DNTT_TYPE_MEMACCESS, + DNTT_TYPE_INHERITANCE, + DNTT_TYPE_FRIEND_CLASS, + DNTT_TYPE_FRIEND_FUNC, + DNTT_TYPE_MODIFIER, + DNTT_TYPE_OBJECT_ID, + DNTT_TYPE_MEMFUNC, + DNTT_TYPE_TEMPLATE, + DNTT_TYPE_TEMPLATE_ARG, + DNTT_TYPE_FUNC_TEMPLATE, + DNTT_TYPE_LINK, + DNTT_TYPE_DYN_ARRAY_DESC, + DNTT_TYPE_DESC_SUBRANGE, + DNTT_TYPE_BEGIN_EXT, + DNTT_TYPE_INLN, + DNTT_TYPE_INLN_LIST, + DNTT_TYPE_ALIAS, + DNTT_TYPE_DOC_FUNCTION, + DNTT_TYPE_DOC_MEMFUNC, + DNTT_TYPE_MAX +}; + +/* DNTT_TYPE_SRCFILE: + + One DNTT_TYPE_SRCFILE symbol is output for the start of each source + file and at the begin and end of an included file. A DNTT_TYPE_SRCFILE + entry is also output before each DNTT_TYPE_FUNC symbol so that debuggers + can determine what file a function was defined in. + + LANGUAGE describes the source file's language. + + NAME points to an VT entry providing the source file's name. + + Note the name used for DNTT_TYPE_SRCFILE entries are exactly as seen + by the compiler (ie they may be relative or absolute). C include files + via <> inclusion must use absolute paths. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_srcfile +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_SRCFILE */ + unsigned int language: 4; + unsigned int unused: 17; + vtpointer name; + sltpointer address; +}; + +/* DNTT_TYPE_MODULE: + + A DNTT_TYPE_MODULE symbol is emitted for the start of a pascal + module or C source file. A module indicates a compilation unit + for name-scoping purposes; in that regard there should be + a 1-1 correspondence between GDB "symtab"'s and MODULE symbol records. + + Each DNTT_TYPE_MODULE must have an associated DNTT_TYPE_END symbol. + + NAME points to a VT entry providing the module's name. Note C + source files are considered nameless modules. + + ALIAS point to a VT entry providing a secondary name. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_module +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_MODULE */ + unsigned int unused: 21; + vtpointer name; + vtpointer alias; + dnttpointer unused2; + sltpointer address; +}; + +/* DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BLOCKDATA, + DNTT_TYPE_MEMFUNC: + + A DNTT_TYPE_FUNCTION symbol is emitted for each function definition; + a DNTT_TYPE_ENTRY symbols is used for secondary entry points. Both + symbols used the dntt_type_function structure. + A DNTT_TYPE_BLOCKDATA symbol is emitted ...? + A DNTT_TYPE_MEMFUNC symbol is emitted for inlined member functions (C++). + + Each of DNTT_TYPE_FUNCTION must have a matching DNTT_TYPE_END. + + GLOBAL is nonzero if the function has global scope. + + LANGUAGE describes the function's source language. + + OPT_LEVEL describes the optimization level the function was compiled + with. + + VARARGS is nonzero if the function uses varargs. + + NAME points to a VT entry providing the function's name. + + ALIAS points to a VT entry providing a secondary name for the function. + + FIRSTPARAM points to a LNTT entry which describes the parameter list. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. + + ENTRYADDR is the memory address corresponding the function's entry point + + RETVAL points to a LNTT entry describing the function's return value. + + LOWADDR is the lowest memory address associated with this function. + + HIADDR is the highest memory address associated with this function. */ + +struct dntt_type_function +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BLOCKDATA + or DNTT_TYPE_MEMFUNC */ + unsigned int global: 1; + unsigned int language: 4; + unsigned int nest_level: 5; + unsigned int opt_level: 2; + unsigned int varargs: 1; + unsigned int lang_info: 4; + unsigned int inlined: 1; + unsigned int localalloc: 1; + unsigned int expansion: 1; + unsigned int unused: 1; + vtpointer name; + vtpointer alias; + dnttpointer firstparam; + sltpointer address; + CORE_ADDR entryaddr; + dnttpointer retval; + CORE_ADDR lowaddr; + CORE_ADDR hiaddr; +}; + +/* DNTT_TYPE_BEGIN: + + A DNTT_TYPE_BEGIN symbol is emitted to begin a new nested scope. + Every DNTT_TYPE_BEGIN symbol must have a matching DNTT_TYPE_END symbol. + + CLASSFLAG is nonzero if this is the beginning of a c++ class definition. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_begin +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int classflag: 1; + unsigned int unused: 20; + sltpointer address; +}; + +/* DNTT_TYPE_END: + + A DNTT_TYPE_END symbol is emitted when closing a scope started by + a DNTT_TYPE_MODULE, DNTT_TYPE_FUNCTION, DNTT_TYPE_WITH, + DNTT_TYPE_COMMON, DNTT_TYPE_BEGIN, and DNTT_TYPE_CLASS_SCOPE symbols. + + ENDKIND describes what type of scope the DNTT_TYPE_END is closing + (one of the above 6 kinds). + + CLASSFLAG is nonzero if this is the end of a c++ class definition. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. + + BEGINSCOPE points to the LNTT entry which opened the scope. */ + +struct dntt_type_end +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int endkind: 10; + unsigned int classflag: 1; + unsigned int unused: 10; + sltpointer address; + dnttpointer beginscope; +}; + +/* DNTT_TYPE_IMPORT is unused by GDB. */ +/* DNTT_TYPE_LABEL is unused by GDB. */ + +/* DNTT_TYPE_FPARAM: + + A DNTT_TYPE_FPARAM symbol is emitted for a function argument. When + chained together the symbols represent an argument list for a function. + + REGPARAM is nonzero if this parameter was passed in a register. + + INDIRECT is nonzero if this parameter is a pointer to the parameter + (pass by reference or pass by value for large items). + + LONGADDR is nonzero if the parameter is a 64bit pointer. + + NAME is a pointer into the VT for the parameter's name. + + LOCATION describes where the parameter is stored. Depending on the + parameter type LOCATION could be a register number, or an offset + from the stack pointer. + + TYPE points to a NTT entry describing the type of this parameter. + + NEXTPARAM points to the LNTT entry describing the next parameter. */ + +struct dntt_type_fparam +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int regparam: 1; + unsigned int indirect: 1; + unsigned int longaddr: 1; + unsigned int copyparam: 1; + unsigned int dflt: 1; + unsigned int doc_ranges: 1; + unsigned int misc_kind: 1; + unsigned int unused: 14; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + dnttpointer nextparam; + int misc; +}; + +/* DNTT_TYPE_SVAR: + + A DNTT_TYPE_SVAR is emitted to describe a variable in static storage. + + GLOBAL is nonzero if the variable has global scope. + + INDIRECT is nonzero if the variable is a pointer to an object. + + LONGADDR is nonzero if the variable is in long pointer space. + + STATICMEM is nonzero if the variable is a member of a class. + + A_UNION is nonzero if the variable is an anonymous union member. + + NAME is a pointer into the VT for the variable's name. + + LOCATION provides the memory address for the variable. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_svar +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int longaddr: 1; + unsigned int staticmem: 1; + unsigned int a_union: 1; + unsigned int unused1: 1; + unsigned int thread_specific: 1; + unsigned int unused2: 14; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + unsigned int offset; + unsigned int displacement; +}; + +/* DNTT_TYPE_DVAR: + + A DNTT_TYPE_DVAR is emitted to describe automatic variables and variables + held in registers. + + GLOBAL is nonzero if the variable has global scope. + + INDIRECT is nonzero if the variable is a pointer to an object. + + REGVAR is nonzero if the variable is in a register. + + A_UNION is nonzero if the variable is an anonymous union member. + + NAME is a pointer into the VT for the variable's name. + + LOCATION provides the memory address or register number for the variable. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_dvar +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int regvar: 1; + unsigned int a_union: 1; + unsigned int unused: 17; + vtpointer name; + int location; + dnttpointer type; + unsigned int offset; +}; + +/* DNTT_TYPE_CONST: + + A DNTT_TYPE_CONST symbol is emitted for program constants. + + GLOBAL is nonzero if the constant has global scope. + + INDIRECT is nonzero if the constant is a pointer to an object. + + LOCATION_TYPE describes where to find the constant's value + (in the VT, memory, or embedded in an instruction). + + CLASSMEM is nonzero if the constant is a member of a class. + + NAME is a pointer into the VT for the constant's name. + + LOCATION provides the memory address, register number or pointer + into the VT for the constant's value. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_const +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int location_type: 3; + unsigned int classmem: 1; + unsigned int unused: 15; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + unsigned int offset; + unsigned int displacement; +}; + +/* DNTT_TYPE_TYPEDEF and DNTT_TYPE_TAGDEF: + + The same structure is used to describe typedefs and tagdefs. + + DNTT_TYPE_TYPEDEFS are associated with C "typedefs". + + DNTT_TYPE_TAGDEFs are associated with C "struct", "union", and "enum" + tags, which may have the same name as a typedef in the same scope. + Also they are associated with C++ "class" tags, which implicitly have + the same name as the class type. + + GLOBAL is nonzero if the typedef/tagdef has global scope. + + TYPEINFO is used to determine if full type information is available + for a tag. (usually 1, but can be zero for opaque types in C). + + NAME is a pointer into the VT for the constant's name. + + TYPE points to the underlying type for the typedef/tagdef in the + GNTT or LNTT. */ + +struct dntt_type_type +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_TYPEDEF or + DNTT_TYPE_TAGDEF. */ + unsigned int global: 1; + unsigned int typeinfo: 1; + unsigned int unused: 19; + vtpointer name; + dnttpointer type; /* Underlying type, which for TAGDEF's may be + DNTT_TYPE_STRUCT, DNTT_TYPE_UNION, + DNTT_TYPE_ENUM, or DNTT_TYPE_CLASS. + For TYPEDEF's other underlying types + are also possible. */ +}; + +/* DNTT_TYPE_POINTER: + + Used to describe a pointer to an underlying type. + + POINTSTO is a pointer into the GNTT or LNTT for the type which this + pointer points to. + + BITLENGTH is the length of the pointer (not the underlying type). */ + +struct dntt_type_pointer +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer pointsto; + unsigned int bitlength; +}; + + +/* DNTT_TYPE_ENUM: + + Used to describe enumerated types. + + FIRSTMEM is a pointer to a DNTT_TYPE_MEMENUM in the GNTT/LNTT which + describes the first member (and contains a pointer to the chain of + members). + + BITLENGTH is the number of bits used to hold the values of the enum's + members. */ + +struct dntt_type_enum +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer firstmem; + unsigned int bitlength; +}; + +/* DNTT_TYPE_MEMENUM + + Used to describe members of an enumerated type. + + CLASSMEM is nonzero if this member is part of a class. + + NAME points into the VT for the name of this member. + + VALUE is the value of this enumeration member. + + NEXTMEM points to the next DNTT_TYPE_MEMENUM in the chain. */ + +struct dntt_type_memenum +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int classmem: 1; + unsigned int unused: 20; + vtpointer name; + unsigned int value; + dnttpointer nextmem; +}; + +/* DNTT_TYPE_SET + + Used to describe PASCAL "set" type. + + DECLARATION describes the bitpacking of the set. + + SUBTYPE points to a DNTT entry describing the type of the members. + + BITLENGTH is the size of the set. */ + +struct dntt_type_set +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int unused: 19; + dnttpointer subtype; + unsigned int bitlength; +}; + +/* DNTT_TYPE_SUBRANGE + + Used to describe subrange type. + + DYN_LOW describes the lower bound of the subrange: + + 00 for a constant lower bound (found in LOWBOUND). + + 01 for a dynamic lower bound with the lower bound found in the + memory address pointed to by LOWBOUND. + + 10 for a dynamic lower bound described by an variable found in the + DNTT/LNTT (LOWBOUND would be a pointer into the DNTT/LNTT). + + DYN_HIGH is similar to DYN_LOW, except it describes the upper bound. + + SUBTYPE points to the type of the subrange. + + BITLENGTH is the length in bits needed to describe the subrange's + values. */ + +struct dntt_type_subrange +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int dyn_low: 2; + unsigned int dyn_high: 2; + unsigned int unused: 17; + int lowbound; + int highbound; + dnttpointer subtype; + unsigned int bitlength; +}; + +/* DNTT_TYPE_ARRAY + + Used to describe an array type. + + DECLARATION describes the bit packing used in the array. + + ARRAYISBYTES is nonzero if the field in arraylength describes the + length in bytes rather than in bits. A value of zero is used to + describe an array with size 2**32. + + ELEMISBYTES is nonzero if the length if each element in the array + is describes in bytes rather than bits. A value of zero is used + to an element with size 2**32. + + ELEMORDER is nonzero if the elements are indexed in increasing order. + + JUSTIFIED if the elements are left justified to index zero. + + ARRAYLENGTH is the length of the array. + + INDEXTYPE is a DNTT pointer to the type used to index the array. + + ELEMTYPE is a DNTT pointer to the type for the array elements. + + ELEMLENGTH is the length of each element in the array (including + any padding). + + Multi-dimensional arrays are represented by ELEMTYPE pointing to + another DNTT_TYPE_ARRAY. */ + +struct dntt_type_array +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int dyn_low: 2; + unsigned int dyn_high: 2; + unsigned int arrayisbytes: 1; + unsigned int elemisbytes: 1; + unsigned int elemorder: 1; + unsigned int justified: 1; + unsigned int unused: 11; + unsigned int arraylength; + dnttpointer indextype; + dnttpointer elemtype; + unsigned int elemlength; +}; + +/* DNTT_TYPE_STRUCT + + DNTT_TYPE_STRUCT is used to describe a C structure. + + DECLARATION describes the bitpacking used. + + FIRSTFIELD is a DNTT pointer to the first field of the structure + (each field contains a pointer to the next field, walk the list + to access all fields of the structure). + + VARTAGFIELD and VARLIST are used for Pascal variant records. + + BITLENGTH is the size of the structure in bits. */ + +struct dntt_type_struct +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int unused: 19; + dnttpointer firstfield; + dnttpointer vartagfield; + dnttpointer varlist; + unsigned int bitlength; +}; + +/* DNTT_TYPE_UNION + + DNTT_TYPE_UNION is used to describe a C union. + + FIRSTFIELD is a DNTT pointer to the beginning of the field chain. + + BITLENGTH is the size of the union in bits. */ + +struct dntt_type_union +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer firstfield; + unsigned int bitlength; +}; + +/* DNTT_TYPE_FIELD + + DNTT_TYPE_FIELD describes one field in a structure or union + or C++ class. + + VISIBILITY is used to describe the visibility of the field + (for c++. public = 0, protected = 1, private = 2). + + A_UNION is nonzero if this field is a member of an anonymous union. + + STATICMEM is nonzero if this field is a static member of a template. + + NAME is a pointer into the VT for the name of the field. + + BITOFFSET gives the offset of this field in bits from the beginning + of the structure or union this field is a member of. + + TYPE is a DNTT pointer to the type describing this field. + + BITLENGTH is the size of the entry in bits. + + NEXTFIELD is a DNTT pointer to the next field in the chain. */ + +struct dntt_type_field +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int visibility: 2; + unsigned int a_union: 1; + unsigned int staticmem: 1; + unsigned int unused: 17; + vtpointer name; + unsigned int bitoffset; + dnttpointer type; + unsigned int bitlength; + dnttpointer nextfield; +}; + +/* DNTT_TYPE_VARIANT is unused by GDB. */ +/* DNTT_TYPE_FILE is unused by GDB. */ + +/* DNTT_TYPE_FUNCTYPE + + I think this is used to describe a function type (e.g., would + be emitted as part of a function-pointer description). + + VARARGS is nonzero if this function uses varargs. + + FIRSTPARAM is a DNTT pointer to the first entry in the parameter + chain. + + RETVAL is a DNTT pointer to the type of the return value. */ + +struct dntt_type_functype +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int varargs: 1; + unsigned int info: 4; + unsigned int unused: 16; + unsigned int bitlength; + dnttpointer firstparam; + dnttpointer retval; +}; + +/* DNTT_TYPE_WITH is emitted by C++ to indicate "with" scoping semantics. + (Probably also emitted by PASCAL to support "with"...). + + C++ example: Say "memfunc" is a method of class "c", and say + "m" is a data member of class "c". Then from within "memfunc", + it is legal to reference "m" directly (e.g. you don't have to + say "this->m". The symbol table indicates + this by emitting a DNTT_TYPE_WITH symbol within the function "memfunc", + pointing to the type symbol for class "c". + + In GDB, this symbol record is unnecessary, + because GDB's symbol lookup algorithm + infers the "with" semantics when it sees a "this" argument to the member + function. So GDB can safely ignore the DNTT_TYPE_WITH record. + + A DNTT_TYPE_WITH has a matching DNTT_TYPE_END symbol. */ + +struct dntt_type_with +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_WITH */ + unsigned int addrtype: 2; /* 0 => STATTYPE */ + /* 1 => DYNTYPE */ + /* 2 => REGTYPE */ + unsigned int indirect: 1; /* 1 => pointer to object */ + unsigned int longaddr: 1; /* 1 => in long pointer space */ + unsigned int nestlevel: 6; /* # of nesting levels back */ + unsigned int doc_ranges: 1; /* 1 => location is range list */ + unsigned int unused: 10; + long location; /* where stored (allocated) */ + sltpointer address; + dnttpointer type; /* type of with expression */ + vtpointer name; /* name of with expression */ + unsigned long offset; /* byte offset from location */ +}; + +/* DNTT_TYPE_COMMON is unsupported by GDB. */ +/* A DNTT_TYPE_COMMON symbol must have a matching DNTT_TYPE_END symbol */ + +/* DNTT_TYPE_COBSTRUCT is unsupported by GDB. */ +/* DNTT_TYPE_XREF is unsupported by GDB. */ +/* DNTT_TYPE_SA is unsupported by GDB. */ +/* DNTT_TYPE_MACRO is unsupported by GDB */ + +/* DNTT_TYPE_BLOCKDATA has the same structure as DNTT_TYPE_FUNCTION */ + +/* The following are the C++ specific SOM records */ + +/* The purpose of the DNTT_TYPE_CLASS_SCOPE is to bracket C++ methods + and indicate the method name belongs in the "class scope" rather + than in the module they are being defined in. For example: + + class c { + ... + void memfunc(); // member function + }; + + void c::memfunc() // definition of class c's "memfunc" + { + ... + } + + main() + { + ... + } + + In the above, the name "memfunc" is not directly visible from "main". + I.e., you have to say "break c::memfunc". + If it were a normal function (not a method), it would be visible + via the simple "break memfunc". Since "memfunc" otherwise looks + like a normal FUNCTION in the symbol table, the bracketing + CLASS_SCOPE is what is used to indicate it is really a method. + + + A DNTT_TYPE_CLASS_SCOPE symbol must have a matching DNTT_TYPE_END symbol. */ + +struct dntt_type_class_scope +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_CLASS_SCOPE. */ + unsigned int unused: 21; + sltpointer address ; /* Pointer to SLT entry. */ + dnttpointer type ; /* Pointer to class type DNTT. */ +}; + +/* C++ reference parameter. + The structure of this record is the same as DNTT_TYPE_POINTER - + refer to struct dntt_type_pointer. */ + +/* The next two describe C++ pointer-to-data-member type, and + pointer-to-member-function type, respectively. + DNTT_TYPE_PTRMEM and DNTT_TYPE_PTRMEMFUNC have the same structure. */ + +struct dntt_type_ptrmem +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_PTRMEM. */ + unsigned int unused: 21; + dnttpointer pointsto ; /* Pointer to class DNTT. */ + dnttpointer memtype ; /* Type of member. */ +}; + +struct dntt_type_ptrmemfunc +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_PTRMEMFUNC. */ + unsigned int unused: 21; + dnttpointer pointsto ; /* Pointer to class DNTT. */ + dnttpointer memtype ; /* Type of member. */ +}; + +/* The DNTT_TYPE_CLASS symbol is emitted to describe a class type. + "memberlist" points to a chained list of FIELD or GENFIELD records + indicating the class members. "parentlist" points to a chained list + of INHERITANCE records indicating classes from which we inherit + fields. */ + +struct dntt_type_class +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_CLASS. */ + unsigned int abstract: 1; /* Is this an abstract class? */ + unsigned int class_decl: 2; /* 0=class,1=union,2=struct. */ + unsigned int expansion: 1; /* 1=template expansion. */ + unsigned int unused: 17; + dnttpointer memberlist ; /* Ptr to chain of [GEN]FIELDs. */ + unsigned long vtbl_loc ; /* Offset in obj of ptr to vtbl. */ + dnttpointer parentlist ; /* Ptr to K_INHERITANCE list. */ + unsigned long bitlength ; /* Total at this level. */ + dnttpointer identlist ; /* Ptr to chain of class ident's. */ + dnttpointer friendlist ; /* Ptr to K_FRIEND list. */ + dnttpointer templateptr ; /* Ptr to template. */ + dnttpointer nextexp ; /* Ptr to next expansion. */ +}; + +/* Class members are indicated via either the FIELD record (for + data members, same as for C struct fields), or by the GENFIELD record + (for member functions). */ + +struct dntt_type_genfield +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_GENFIELD. */ + unsigned int visibility: 2; /* Pub = 0, prot = 1, priv = 2. */ + unsigned int a_union: 1; /* 1 => anonymous union member. */ + unsigned int unused: 18; + dnttpointer field ; /* Pointer to field or qualifier. */ + dnttpointer nextfield ; /* Pointer to next field. */ +}; + +/* C++ virtual functions. */ + +struct dntt_type_vfunc +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_VFUNC */ + unsigned int pure: 1; /* pure virtual function ? */ + unsigned int unused: 20; + dnttpointer funcptr ; /* points to FUNCTION symbol */ + unsigned long vtbl_offset ; /* offset into vtbl for virtual */ +}; + +/* Not precisely sure what this is intended for - DDE ignores it. */ + +struct dntt_type_memaccess +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_MEMACCESS */ + unsigned int unused: 21; + dnttpointer classptr ; /* pointer to base class */ + dnttpointer field ; /* pointer field */ +}; + +/* The DNTT_TYPE_INHERITANCE record describes derived classes. + In particular, the "parentlist" field of the CLASS record points + to a list of INHERITANCE records for classes from which we + inherit members. */ + +struct dntt_type_inheritance +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_INHERITANCE */ + unsigned int Virtual: 1; /* virtual base class ? */ + unsigned int visibility: 2; /* pub = 0, prot = 1, priv = 2 */ + unsigned int unused: 18; + dnttpointer classname ; /* first parent class, if any */ + unsigned long offset ; /* offset to start of base class */ + dnttpointer next ; /* pointer to next K_INHERITANCE */ + unsigned long future[2] ; /* padding to 3-word block end */ +}; + +/* C++ "friend" classes ... */ + +struct dntt_type_friend_class +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FRIEND_CLASS */ + unsigned int unused: 21; + dnttpointer classptr ; /* pointer to class DNTT */ + dnttpointer next ; /* next DNTT_FRIEND */ +}; + +struct dntt_type_friend_func +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FRIEND_FUNC */ + unsigned int unused: 21; + dnttpointer funcptr ; /* pointer to function */ + dnttpointer classptr ; /* pointer to class DNTT */ + dnttpointer next ; /* next DNTT_FRIEND */ + unsigned long future[2] ; /* padding to 3-word block end */ +}; + +/* DDE appears to ignore the DNTT_TYPE_MODIFIER record. + It could perhaps be used to give better "ptype" output in GDB; + otherwise it is probably safe for GDB to ignore it also. */ + +struct dntt_type_modifier +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_MODIFIER */ + unsigned int m_const: 1; /* const */ + unsigned int m_static: 1; /* static */ + unsigned int m_void: 1; /* void */ + unsigned int m_volatile: 1; /* volatile */ + unsigned int m_duplicate: 1; /* duplicate */ + unsigned int unused: 16; + dnttpointer type ; /* subtype */ + unsigned long future ; /* padding to 3-word block end */ +}; + +/* I'm not sure what this was intended for - DDE ignores it. */ + +struct dntt_type_object_id +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_OBJECT_ID */ + unsigned int indirect: 1; /* Is object_ident addr of addr? */ + unsigned int unused: 20; + unsigned long object_ident ; /* object identifier */ + unsigned long offset ; /* offset to start of base class */ + dnttpointer next ; /* pointer to next K_OBJECT_ID */ + unsigned long segoffset ; /* for linker fixup */ + unsigned long future ; /* padding to 3-word block end */ +}; + +/* No separate dntt_type_memfunc; same as dntt_type_func */ + +/* Symbol records to support templates. These only get used + in DDE's "describe" output (like GDB's "ptype"). */ + +/* The TEMPLATE record is the header for a template-class. + Like the CLASS record, a TEMPLATE record has a memberlist that + points to a list of template members. It also has an arglist + pointing to a list of TEMPLATE_ARG records. */ + +struct dntt_type_template +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_TEMPLATE */ + unsigned int abstract: 1; /* is this an abstract class? */ + unsigned int class_decl: 2; /* 0=class,1=union,2=struct */ + unsigned int unused: 18; + dnttpointer memberlist ; /* ptr to chain of K_[GEN]FIELDs */ + long unused2 ; /* offset in obj of ptr to vtbl */ + dnttpointer parentlist ; /* ptr to K_INHERITANCE list */ + unsigned long bitlength ; /* total at this level */ + dnttpointer identlist ; /* ptr to chain of class ident's */ + dnttpointer friendlist ; /* ptr to K_FRIEND list */ + dnttpointer arglist ; /* ptr to argument list */ + dnttpointer expansions ; /* ptr to expansion list */ +}; + +/* Template-class arguments are a list of TEMPL_ARG records + chained together. The "name" field is the name of the formal. + E.g.: + + template <class T> class q { ... }; + + Then "T" is the name of the formal argument. */ + +struct dntt_type_templ_arg +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_TEMPL_ARG */ + unsigned int usagetype: 1; /* 0 type-name 1 expression */ + unsigned int unused: 20; + vtpointer name ; /* name of argument */ + dnttpointer type ; /* for non type arguments */ + dnttpointer nextarg ; /* Next argument if any */ + long future[2] ; /* padding to 3-word block end */ +}; + +/* FUNC_TEMPLATE records are sort of like FUNCTION, but are emitted + for template member functions. E.g., + + template <class T> class q + { + ... + void f(); + ... + }; + + Within the list of FIELDs/GENFIELDs defining the member list + of the template "q", "f" would appear as a FUNC_TEMPLATE. + We'll also see instances of FUNCTION "f" records for each + instantiation of the template. */ + +struct dntt_type_func_template +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FUNC_TEMPLATE */ + unsigned int public: 1; /* 1 => globally visible */ + unsigned int language: 4; /* type of language */ + unsigned int level: 5; /* nesting level (top level = 0)*/ + unsigned int optimize: 2; /* level of optimization */ + unsigned int varargs: 1; /* ellipses. Pascal/800 later */ + unsigned int info: 4; /* lang-specific stuff; F_xxxx */ + unsigned int inlined: 1; + unsigned int localloc: 1; /* 0 at top, 1 at end of block */ + unsigned int unused: 2; + vtpointer name ; /* name of function */ + vtpointer alias ; /* alternate name, if any */ + dnttpointer firstparam ; /* first FPARAM, if any */ + dnttpointer retval ; /* return type, if any */ + dnttpointer arglist ; /* ptr to argument list */ +}; + +/* LINK is apparently intended to link together function template + definitions with their instantiations. However, it is not clear + why this would be needed, except to provide the information on + a "ptype" command. And as far as I can tell, aCC does not + generate this record. */ + +struct dntt_type_link +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_LINK */ + unsigned int linkKind: 4; /* always LINK_UNKNOWN */ + unsigned int unused: 17; + long future1 ; /* expansion */ + dnttpointer ptr1 ; /* link from template */ + dnttpointer ptr2 ; /* to expansion */ + long future[2] ; /* padding to 3-word block end */ +}; + +/* end of C++ specific SOM's. */ + +/* DNTT_TYPE_DYN_ARRAY_DESC is unused by GDB */ +/* DNTT_TYPE_DESC_SUBRANGE is unused by GDB */ +/* DNTT_TYPE_BEGIN_EXT is unused by GDB */ +/* DNTT_TYPE_INLN is unused by GDB */ +/* DNTT_TYPE_INLN_LIST is unused by GDB */ +/* DNTT_TYPE_ALIAS is unused by GDB */ + +struct dntt_type_doc_function +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* K_DOC_FUNCTION or */ + /* K_DOC_MEMFUNC */ + unsigned int global: 1; /* 1 => globally visible */ + unsigned int language: 4; /* type of language */ + unsigned int level: 5; /* nesting level (top level = 0)*/ + unsigned int optimize: 2; /* level of optimization */ + unsigned int varargs: 1; /* ellipses. Pascal/800 later */ + unsigned int info: 4; /* lang-specific stuff; F_xxxx */ + unsigned int inlined: 1; + unsigned int localloc: 1; /* 0 at top, 1 at end of block */ + unsigned int expansion: 1; /* 1 = function expansion */ + unsigned int doc_clone: 1; + vtpointer name; /* name of function */ + vtpointer alias; /* alternate name, if any */ + dnttpointer firstparam; /* first FPARAM, if any */ + sltpointer address; /* code and text locations */ + CORE_ADDR entryaddr; /* address of entry point */ + dnttpointer retval; /* return type, if any */ + CORE_ADDR lowaddr; /* lowest address of function */ + CORE_ADDR hiaddr; /* highest address of function */ + dnttpointer inline_list; /* pointer to first inline */ + ltpointer lt_offset; /* start of frag/cp line table */ + ctxtpointer ctxt_offset; /* start of context table for this routine */ +}; + +/* DNTT_TYPE_DOC_MEMFUNC is unused by GDB */ + +/* DNTT_TYPE_GENERIC and DNTT_TYPE_BLOCK are convience structures + so we can examine a DNTT entry in a generic fashion. */ +struct dntt_type_generic +{ + unsigned int word[9]; +}; + +struct dntt_type_block +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + unsigned int word[2]; +}; + +/* One entry in a DNTT (either the LNTT or GNTT). + This is a union of the above 60 or so structure definitions. */ + +union dnttentry +{ + struct dntt_type_srcfile dsfile; + struct dntt_type_module dmodule; + struct dntt_type_function dfunc; + struct dntt_type_function dentry; + struct dntt_type_begin dbegin; + struct dntt_type_end dend; + struct dntt_type_fparam dfparam; + struct dntt_type_svar dsvar; + struct dntt_type_dvar ddvar; + struct dntt_type_const dconst; + struct dntt_type_type dtype; + struct dntt_type_type dtag; + struct dntt_type_pointer dptr; + struct dntt_type_enum denum; + struct dntt_type_memenum dmember; + struct dntt_type_set dset; + struct dntt_type_subrange dsubr; + struct dntt_type_array darray; + struct dntt_type_struct dstruct; + struct dntt_type_union dunion; + struct dntt_type_field dfield; + struct dntt_type_functype dfunctype; + struct dntt_type_with dwith; + struct dntt_type_function dblockdata; + struct dntt_type_class_scope dclass_scope; + struct dntt_type_pointer dreference; + struct dntt_type_ptrmem dptrmem; + struct dntt_type_ptrmemfunc dptrmemfunc; + struct dntt_type_class dclass; + struct dntt_type_genfield dgenfield; + struct dntt_type_vfunc dvfunc; + struct dntt_type_memaccess dmemaccess; + struct dntt_type_inheritance dinheritance; + struct dntt_type_friend_class dfriend_class; + struct dntt_type_friend_func dfriend_func; + struct dntt_type_modifier dmodifier; + struct dntt_type_object_id dobject_id; + struct dntt_type_template dtemplate; + struct dntt_type_templ_arg dtempl_arg; + struct dntt_type_func_template dfunc_template; + struct dntt_type_link dlink; + struct dntt_type_doc_function ddocfunc; + struct dntt_type_generic dgeneric; + struct dntt_type_block dblock; +}; + +/* Source line entry types. */ +enum slttype +{ + SLT_NORMAL, + SLT_SRCFILE, + SLT_MODULE, + SLT_FUNCTION, + SLT_ENTRY, + SLT_BEGIN, + SLT_END, + SLT_WITH, + SLT_EXIT, + SLT_ASSIST, + SLT_MARKER, + SLT_CLASS_SCOPE, + SLT_INLN, + SLT_NORMAL_OFFSET, +}; + +/* A normal source line entry. Simply provides a mapping of a source + line number to a code address. + + SLTDESC will always be SLT_NORMAL or SLT_EXIT. */ + +struct slt_normal +{ + unsigned int sltdesc: 4; + unsigned int line: 28; + CORE_ADDR address; +}; + +struct slt_normal_off +{ + unsigned int sltdesc: 4; + unsigned int offset: 6; + unsigned int line: 22; + CORE_ADDR address; +}; + +/* A special source line entry. Provides a mapping of a declaration + to a line number. These entries point back into the DNTT which + references them. */ + +struct slt_special +{ + unsigned int sltdesc: 4; + unsigned int line: 28; + dnttpointer backptr; +}; + +/* Used to describe nesting. + + For nested languages, an slt_assist entry must follow each SLT_FUNC + entry in the SLT. The address field will point forward to the + first slt_normal entry within the function's scope. */ + +struct slt_assist +{ + unsigned int sltdesc: 4; + unsigned int unused: 28; + sltpointer address; +}; + +struct slt_generic +{ + unsigned int word[2]; +}; + +union sltentry +{ + struct slt_normal snorm; + struct slt_normal_off snormoff; + struct slt_special sspec; + struct slt_assist sasst; + struct slt_generic sgeneric; +}; + +/* $LINES$ declarations + This is the line table used for optimized code, which is only present + in the new $PROGRAM_INFO$ debug space. */ + +#define DST_LN_ESCAPE_FLAG1 15 +#define DST_LN_ESCAPE_FLAG2 14 +#define DST_LN_CTX_SPEC1 13 +#define DST_LN_CTX_SPEC2 12 + +/* Escape function codes: */ + +typedef enum +{ + dst_ln_pad, /* pad byte */ + dst_ln_escape_1, /* reserved */ + dst_ln_dpc1_dln1, /* 1 byte line delta, 1 byte pc delta */ + dst_ln_dpc2_dln2, /* 2 bytes line delta, 2 bytes pc delta */ + dst_ln_pc4_ln4, /* 4 bytes ABSOLUTE line number, 4 bytes ABSOLUTE pc */ + dst_ln_dpc0_dln1, /* 1 byte line delta, pc delta = 0 */ + dst_ln_ln_off_1, /* statement escape, stmt # = 1 (2nd stmt on line) */ + dst_ln_ln_off, /* statement escape, stmt # = next byte */ + dst_ln_entry, /* entry escape, next byte is entry number */ + dst_ln_exit, /* exit escape */ + dst_ln_stmt_end, /* gap escape, 4 bytes pc delta */ + dst_ln_stmt_cp, /* current stmt is a critical point */ + dst_ln_escape_12, /* reserved */ + dst_ln_escape_13, /* this is an exception site record */ + dst_ln_nxt_byte, /* next byte contains the real escape code */ + dst_ln_end, /* end escape, final entry follows */ + dst_ln_escape1_END_OF_ENUM +} +dst_ln_escape1_t; + +typedef enum +{ + dst_ln_ctx_1, /* next byte describes context switch with 5-bit */ + /* index into the image table and 3-bit run length. */ + /* If run length is 0, end with another cxt specifier or ctx_end */ + dst_ln_ctx_2, /* next 2 bytes switch context: 13 bit index, 3 bit run length */ + dst_ln_ctx_4, /* next 4 bytes switch context: 29 bit index, 3 bit run length */ + dst_ln_ctx_end, /* end current context */ + dst_ln_col_run_1, /* next byte is column position of start of next statement, */ + /* following byte is length of statement */ + dst_ln_col_run_2, /* next 2 bytes is column position of start of next statement, */ + /* following 2 bytes is length of statement */ + dst_ln_init_base1, /* next 4 bytes are absolute PC, followed by 1 byte of line number */ + dst_ln_init_base2, /* next 4 bytes are absolute PC, followed by 2 bytes of line number */ + dst_ln_init_base3, /* next 4 bytes are absolute PC, followed by 3 bytes of line number */ + dst_ln_escape2_END_OF_ENUM +} +dst_ln_escape2_t; + +typedef union +{ + struct + { + unsigned int pc_delta : 4; /* 4 bit pc delta */ + int ln_delta : 4; /* 4 bit line number delta */ + } + delta; + + struct + { + unsigned int esc_flag : 4; /* alias for pc_delta */ + unsigned int esc_code : 4; /* escape function code (dst_ln_escape1_t, or ...2_t */ + } + esc; + + struct + { + unsigned int esc_flag : 4; /* dst_ln_ctx_spec1, or dst_ln_ctx_spec2 */ + unsigned int run_length : 2; + unsigned int ctx_index : 2; /* ...spec2 contains index; ...spec1, index - 4 */ + } + ctx_spec; + + char sdata; /* signed data byte */ + unsigned char udata; /* unsigned data byte */ +} +dst_ln_entry_t, + * dst_ln_entry_ptr_t; + +/* Warning: although the above union occupies only 1 byte the compiler treats + it as having size 2 (the minimum size of a struct). Therefore a sequence of + dst_ln_entry_t's cannot be described as an array, and walking through such a + sequence requires convoluted code such as + ln_ptr = (dst_ln_entry_ptr_t) (char*) ln_ptr + 1 + We regret the inconvenience. */ + +/* Structure for interpreting the byte following a dst_ln_ctx1 entry. */ +typedef struct +{ + unsigned int ctx1_index : 5; /* 5 bit index into context table */ + unsigned int ctx1_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx1_t, + *dst_ln_ctx1_ptr_t; + +/* Structure for interpreting the bytes following a dst_ln_ctx2 entry. */ +typedef struct +{ + unsigned int ctx2_index : 13; /* 13 bit index into context table */ + unsigned int ctx2_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx2_t, + *dst_ln_ctx2_ptr_t; + +/* Structure for interpreting the bytes following a dst_ln_ctx4 entry. */ +typedef struct +{ + unsigned int ctx4_index : 29; /* 29 bit index into context table */ + unsigned int ctx4_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx4_t, + *dst_ln_ctx4_ptr_t; + + +/* PXDB definitions. + + PXDB is a post-processor which takes the executable file + and massages the debug information so that the debugger may + start up and run more efficiently. Some of the tasks + performed by PXDB are: + + o Remove duplicate global type and variable information + from the GNTT, + + o Append the GNTT onto the end of the LNTT and place both + back in the LNTT section, + + o Build quick look-up tables (description follows) for + files, procedures, modules, and paragraphs (for Cobol), + placing these in the GNTT section, + + o Reconstruct the header appearing in the header section + to access this information. + + The "quick look-up" tables are in the $GNTT$ sub-space, in + the following order: + + Procedures -sorted by address + Source files -sorted by address (of the + generated code from routines) + Modules -sorted by address + Classes -<unsorted?> + Address Alias -sorted by index <?> + Object IDs -sorted by object identifier + + Most quick entries have (0-based) indices into the LNTT tables to + the full entries for the item it describes. + + The post-PXDB header is in the $HEADER$ sub-space. Alas, it + occurs in different forms, depending on the optimization level + in the compilation step and whether PXDB was run or not. The + worst part is the forms aren't self-describing, so we'll have + to grovel in the bits to figure out what kind we're looking at + (see hp_get_header in hp-psymtab-read.c). */ + +/* PXDB versions. */ + +#define PXDB_VERSION_CPLUSPLUS 1 +#define PXDB_VERSION_7_4 2 +#define PXDB_VERSION_CPP_30 3 +#define PXDB_VERSION_DDE_3_2A 4 +#define PXDB_VERSION_DDE_3_2 5 +#define PXDB_VERSION_DDE_4_0 6 + +#define PXDB_VERSION_2_1 1 + +/* Header version for the case that there is no DOC info + but the executable has been processed by pxdb (the easy + case, from "cc -g"). */ + +typedef struct PXDB_struct +{ + int pd_entries; /* # of entries in function look-up table */ + int fd_entries; /* # of entries in file look-up table */ + int md_entries; /* # of entries in module look-up table */ + unsigned int pxdbed : 1; /* 1 => file has been preprocessed */ + unsigned int bighdr : 1; /* 1 => this header contains 'time' word */ + unsigned int sa_header : 1;/* 1 => created by SA version of pxdb */ + /* used for version check in xdb */ + unsigned int inlined: 1; /* one or more functions have been inlined */ + unsigned int spare:12; + short version; /* pxdb header version */ + int globals; /* index into the DNTT where GNTT begins */ + unsigned int time; /* modify time of file before being pxdbed */ + int pg_entries; /* # of entries in label look-up table */ + int functions; /* actual number of functions */ + int files; /* actual number of files */ + int cd_entries; /* # of entries in class look-up table */ + int aa_entries; /* # of entries in addr alias look-up table */ + int oi_entries; /* # of entries in object id look-up table */ +} PXDB_header, *PXDB_header_ptr; + +/* Header version for the case that there is no DOC info and the + executable has NOT been processed by pxdb. */ + +typedef struct XDB_header_struct +{ + long gntt_length; + long lntt_length; + long slt_length; + long vt_length; + long xt_length; +} XDB_header; + +/* Header version for the case that there is DOC info and the + executable has been processed by pxdb. */ + +typedef struct DOC_info_PXDB_header_struct +{ + unsigned int xdb_header: 1; /* bit set if this is post-3.1 xdb */ + unsigned int doc_header: 1; /* bit set if this is doc-style header */ + unsigned int version: 8; /* version of pxdb see defines + PXDB_VERSION_* in this file. */ + unsigned int reserved_for_flags: 16;/* for future use; -- must be + set to zero. */ + unsigned int has_aux_pd_table: 1; /* $GNTT$ has aux PD table */ + unsigned int has_expr_table: 1; /* space has $EXPR$ */ + unsigned int has_range_table: 1; /* space has $RANGE$ */ + unsigned int has_context_table: 1; /* space has $SRC_CTXT$ */ + unsigned int has_lines_table: 1; /* space contains a $LINES$ + subspace for line tables. */ + unsigned int has_lt_offset_map: 1; /* space contains an lt_offset + subspace for line table mapping. */ + /* The following fields are the same as those in the PXDB_header in $DEBUG$ */ + int pd_entries; /* # of entries in function look-up table */ + int fd_entries; /* # of entries in file look-up table */ + int md_entries; /* # of entries in module look-up table */ + unsigned int pxdbed : 1; /* 1 => file has been preprocessed */ + unsigned int bighdr : 1; /* 1 => this header contains 'time' word */ + unsigned int sa_header : 1;/* 1 => created by SA version of pxdb */ + /* used for version check in xdb */ + unsigned int inlined: 1; /* one or more functions have been inlined */ + unsigned int spare : 28; + int globals; /* index into the DNTT where GNTT begins */ + unsigned int time; /* modify time of file before being pxdbed */ + int pg_entries; /* # of entries in label look-up table */ + int functions; /* actual number of functions */ + int files; /* actual number of files */ + int cd_entries; /* # of entries in class look-up table */ + int aa_entries; /* # of entries in addr alias look-up table */ + int oi_entries; /* # of entries in object id look-up table */ +} DOC_info_PXDB_header; + +/* Header version for the case that there is DOC info and the + executable has NOT been processed by pxdb. */ + +typedef struct DOC_info_header_struct +{ + unsigned int xdb_header: 1; /* bit set if this is post-3.1 xdb */ + unsigned int doc_header: 1; /* bit set if this is doc-style header*/ + unsigned int version: 8; /* version of debug/header + format. For 10.0 the value + will be 1. For "Davis" the value is 2. */ + unsigned int reserved_for_flags: 18; /* for future use; -- must be set to zero. */ + unsigned int has_range_table: 1; /* space contains a $RANGE$ subspace for variable ranges. */ + unsigned int has_context_table: 1; /* space contains a $CTXT$ subspace for context/inline table. */ + unsigned int has_lines_table: 1; /* space contains a $LINES$ subspace for line tables. */ + unsigned int has_lt_offset_map: 1; /* space contains an lt_offset subspace for line table mapping. */ + + long gntt_length; /* same as old header */ + long lntt_length; /* same as old header */ + long slt_length; /* same as old header */ + long vt_length; /* same as old header */ + long xt_length; /* same as old header */ + long ctxt_length; /* present only if version >= 2 */ + long range_length; /* present only if version >= 2 */ + long expr_length; /* present only if version >= 2 */ + +} DOC_info_header; + +typedef union GenericDebugHeader_union +{ + PXDB_header no_doc; + DOC_info_PXDB_header doc; + XDB_header no_pxdb_no_doc; + DOC_info_header no_pxdb_doc; +} GenericDebugHeader; + + +/* Procedure Descriptor: + An element of the procedure quick look-up table. */ + +typedef struct quick_procedure +{ + long isym; /* 0-based index of first symbol + for procedure in $LNTT$, + i.e. the procedure itself. */ + CORE_ADDR adrStart; /* memory adr of start of proc */ + CORE_ADDR adrEnd; /* memory adr of end of proc */ + char *sbAlias; /* alias name of procedure */ + char *sbProc; /* real name of procedure */ + CORE_ADDR adrBp; /* address of entry breakpoint */ + CORE_ADDR adrExitBp; /* address of exit breakpoint */ + int icd; /* member of this class (index) */ + unsigned int ipd; /* index of template for this */ + /* function (index) */ + unsigned int unused: 5; + unsigned int no_lt_offset: 1;/* no entry in lt_offset table */ + unsigned int fTemplate: 1; /* function template */ + unsigned int fExpansion: 1; /* function expansion */ + unsigned int linked : 1; /* linked with other expansions */ + unsigned int duplicate: 1; /* clone of another procedure */ + unsigned int overloaded:1; /* overloaded function */ + unsigned int member: 1; /* class member function */ + unsigned int constructor:1; /* constructor function */ + unsigned int destructor:1; /* destructor function */ + unsigned int Static: 1; /* static function */ + unsigned int Virtual: 1; /* virtual function */ + unsigned int constant: 1; /* constant function */ + unsigned int pure: 1; /* pure (virtual) function */ + unsigned int language: 4; /* procedure's language */ + unsigned int inlined: 1; /* function has been inlined */ + unsigned int Operator: 1; /* operator function */ + unsigned int stub: 1; /* bodyless function */ + unsigned int optimize: 2; /* optimization level */ + unsigned int level: 5; /* nesting level (top=0) */ +} quick_procedure_entry, *quick_procedure_entry_ptr; + +/* Source File Descriptor: + An element of the source file quick look-up table. */ + +typedef struct quick_source +{ + long isym; /* 0-based index in $LNTT$ of + first symbol for this file. */ + CORE_ADDR adrStart; /* mem adr of start of file's code */ + CORE_ADDR adrEnd; /* mem adr of end of file's code */ + char *sbFile; /* name of source file */ + unsigned int fHasDecl: 1; /* do we have a .d file? */ + unsigned int fWarned: 1; /* have warned about age problems? */ + unsigned int fSrcfile: 1; /* 0 => include 1=> source */ + unsigned short ilnMac; /* lines in file (0 if don't know) */ + int ipd; /* 0-based index of first procedure + in this file, in the quick + look-up table of procedures. */ + unsigned int *rgLn; /* line pointer array, if any */ +} quick_file_entry, *quick_file_entry_ptr; + +/* Module Descriptor: + An element of the module quick reference table. */ + +typedef struct quick_module +{ + long isym; /* 0-based index of first + symbol for module. */ + CORE_ADDR adrStart; /* adr of start of mod. */ + CORE_ADDR adrEnd; /* adr of end of mod. */ + char *sbAlias; /* alias name of module */ + char *sbMod; /* real name of module */ + unsigned int imports: 1; /* module have any imports? */ + unsigned int vars_in_front: 1; /* module globals in front? */ + unsigned int vars_in_gaps: 1; /* module globals in gaps? */ + unsigned int language: 4; /* type of language */ + unsigned int unused : 25; + unsigned int unused2; /* space for future stuff */ +} quick_module_entry, *quick_module_entry_ptr; + +/* Auxiliary Procedure Descriptor: + An element of the auxiliary procedure quick look-up table. */ + +typedef struct quick_aux_procedure +{ + long isym_inln; /* start on inline list for proc */ + long spare; +} quick_aux_procedure_entry, *quick_aux_procedure_entry_ptr; + +/* Paragraph Descriptor: + An element of the paragraph quick look-up table. */ + +typedef struct quick_paragraph +{ + long isym; /* first symbol for label (index) */ + CORE_ADDR adrStart; /* memory adr of start of label */ + CORE_ADDR adrEnd; /* memory adr of end of label */ + char *sbLab; /* name of label */ + unsigned int inst; /* Used in xdb to store inst @ bp */ + unsigned int sect: 1; /* true = section, false = parag. */ + unsigned int unused: 31; /* future use */ +} quick_paragraph_entry, *quick_paragraph_entry_ptr; + +/* Class Descriptor: + An element of the class quick look-up table. */ + +typedef struct quick_class +{ + char *sbClass; /* name of class */ + long isym; /* class symbol (tag) */ + unsigned int type : 2; /* 0=class, 1=union, 2=struct */ + unsigned int fTemplate : 1;/* class template */ + unsigned int expansion : 1;/* template expansion */ + unsigned int unused :28; + sltpointer lowscope; /* beginning of defined scope */ + sltpointer hiscope; /* end of defined scope */ +} quick_class_entry, *quick_class_entry_ptr; + +/* Address Alias Entry + An element of the address alias quick look-up table. */ + +typedef struct quick_alias +{ + CORE_ADDR low; + CORE_ADDR high; + int index; + unsigned int unused : 31; + unsigned int alternate : 1; /* alternate unnamed aliases? */ +} quick_alias_entry, *quick_alias_entry_ptr; + +/* Object Identification Entry + An element of the object identification quick look-up table. */ + +typedef struct quick_obj_ID +{ + CORE_ADDR obj_ident; /* class identifier */ + long isym; /* class symbol */ + long offset; /* offset to object start */ +} quick_obj_ID_entry, *quick_obj_ID_entry_ptr; + +#endif /* HP_SYMTAB_INCLUDED */ diff --git a/include/ieee.h b/include/ieee.h new file mode 100644 index 000000000..5abc32b62 --- /dev/null +++ b/include/ieee.h @@ -0,0 +1,165 @@ +/* IEEE Standard 695-1980 "Universal Format for Object Modules" header file + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + Contributed by Cygnus Support. */ + +#define N_W_VARIABLES 8 +#define Module_Beginning 0xe0 + +typedef struct ieee_module + { + char *processor; + char *module_name; + } +ieee_module_begin_type; + +#define Address_Descriptor 0xec +typedef struct ieee_address + { + bfd_vma number_of_bits_mau; + bfd_vma number_of_maus_in_address; + + unsigned char byte_order; +#define IEEE_LITTLE 0xcc +#define IEEE_BIG 0xcd + } +ieee_address_descriptor_type; + +typedef union ieee_w_variable + { + file_ptr offset[N_W_VARIABLES]; + + struct + { + file_ptr extension_record; + file_ptr environmental_record; + file_ptr section_part; + file_ptr external_part; + file_ptr debug_information_part; + file_ptr data_part; + file_ptr trailer_part; + file_ptr me_record; + } + r; + } +ieee_w_variable_type; + +typedef enum ieee_record + { + ieee_number_start_enum = 0x00, + ieee_number_end_enum=0x7f, + ieee_number_repeat_start_enum = 0x80, + ieee_number_repeat_end_enum = 0x88, + ieee_number_repeat_4_enum = 0x84, + ieee_number_repeat_3_enum = 0x83, + ieee_number_repeat_2_enum = 0x82, + ieee_number_repeat_1_enum = 0x81, + ieee_module_beginning_enum = 0xe0, + ieee_module_end_enum = 0xe1, + ieee_extension_length_1_enum = 0xde, + ieee_extension_length_2_enum = 0xdf, + ieee_section_type_enum = 0xe6, + ieee_section_alignment_enum = 0xe7, + ieee_external_symbol_enum = 0xe8, + ieee_comma = 0x90, + ieee_external_reference_enum = 0xe9, + ieee_set_current_section_enum = 0xe5, + ieee_address_descriptor_enum = 0xec, + ieee_load_constant_bytes_enum = 0xed, + ieee_load_with_relocation_enum = 0xe4, + + ieee_variable_A_enum = 0xc1, + ieee_variable_B_enum = 0xc2, + ieee_variable_C_enum = 0xc3, + ieee_variable_D_enum = 0xc4, + ieee_variable_E_enum = 0xc5, + ieee_variable_F_enum = 0xc6, + ieee_variable_G_enum = 0xc7, + ieee_variable_H_enum = 0xc8, + ieee_variable_I_enum = 0xc9, + ieee_variable_J_enum = 0xca, + ieee_variable_K_enum = 0xcb, + ieee_variable_L_enum = 0xcc, + ieee_variable_M_enum = 0xcd, + ieee_variable_N_enum = 0xce, + ieee_variable_O_enum = 0xcf, + ieee_variable_P_enum = 0xd0, + ieee_variable_Q_enum = 0xd1, + ieee_variable_R_enum = 0xd2, + ieee_variable_S_enum = 0xd3, + ieee_variable_T_enum = 0xd4, + ieee_variable_U_enum = 0xd5, + ieee_variable_V_enum = 0xd6, + ieee_variable_W_enum = 0xd7, + ieee_variable_X_enum = 0xd8, + ieee_variable_Y_enum = 0xd9, + ieee_variable_Z_enum = 0xda, + ieee_function_plus_enum = 0xa5, + ieee_function_minus_enum = 0xa6, + ieee_function_signed_open_b_enum = 0xba, + ieee_function_signed_close_b_enum = 0xbb, + + ieee_function_unsigned_open_b_enum = 0xbc, + ieee_function_unsigned_close_b_enum = 0xbd, + + ieee_function_either_open_b_enum = 0xbe, + ieee_function_either_close_b_enum = 0xbf, + ieee_record_seperator_enum = 0xdb, + + ieee_e2_first_byte_enum = 0xe2, + ieee_section_size_enum = 0xe2d3, + ieee_physical_region_size_enum = 0xe2c1, + ieee_region_base_address_enum = 0xe2c2, + ieee_mau_size_enum = 0xe2c6, + ieee_m_value_enum = 0xe2cd, + ieee_section_base_address_enum = 0xe2cc, + ieee_asn_record_enum = 0xe2ce, + ieee_section_offset_enum = 0xe2d2, + ieee_value_starting_address_enum = 0xe2c7, + ieee_assign_value_to_variable_enum = 0xe2d7, + ieee_set_current_pc_enum = 0xe2d0, + ieee_value_record_enum = 0xe2c9, + ieee_nn_record = 0xf0, + ieee_at_record_enum = 0xf1, + ieee_ty_record_enum = 0xf2, + ieee_attribute_record_enum = 0xf1c9, + ieee_atn_record_enum = 0xf1ce, + ieee_external_reference_info_record_enum = 0xf1d8, + ieee_weak_external_reference_enum= 0xf4, + ieee_repeat_data_enum = 0xf7, + ieee_bb_record_enum = 0xf8, + ieee_be_record_enum = 0xf9 + } +ieee_record_enum_type; + +typedef struct ieee_section + { + unsigned int section_index; + unsigned int section_type; + char * section_name; + unsigned int parent_section_index; + unsigned int sibling_section_index; + unsigned int context_index; + } +ieee_section_type; + +#define IEEE_REFERENCE_BASE 11 +#define IEEE_PUBLIC_BASE 32 +#define IEEE_SECTION_NUMBER_BASE 1 + diff --git a/include/libiberty.h b/include/libiberty.h new file mode 100644 index 000000000..c9f480aaf --- /dev/null +++ b/include/libiberty.h @@ -0,0 +1,366 @@ +/* Function declarations for libiberty. + + Copyright 2001, 2002 Free Software Foundation, Inc. + + Note - certain prototypes declared in this header file are for + functions whoes implementation copyright does not belong to the + FSF. Those prototypes are present in this file for reference + purposes only and their presence in this file should not construed + as an indication of ownership by the FSF of the implementation of + those functions in any way or form whatsoever. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + Written by Cygnus Support, 1994. + + The libiberty library provides a number of functions which are + missing on some operating systems. We do not declare those here, + to avoid conflicts with the system header files on operating + systems that do support those functions. In this file we only + declare those functions which are specific to libiberty. */ + +#ifndef LIBIBERTY_H +#define LIBIBERTY_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ansidecl.h" + +#ifdef ANSI_PROTOTYPES +/* Get a definition for size_t. */ +#include <stddef.h> +/* Get a definition for va_list. */ +#include <stdarg.h> +#endif + +/* Build an argument vector from a string. Allocates memory using + malloc. Use freeargv to free the vector. */ + +extern char **buildargv PARAMS ((const char *)) ATTRIBUTE_MALLOC; + +/* Free a vector returned by buildargv. */ + +extern void freeargv PARAMS ((char **)); + +/* Duplicate an argument vector. Allocates memory using malloc. Use + freeargv to free the vector. */ + +extern char **dupargv PARAMS ((char **)) ATTRIBUTE_MALLOC; + + +/* Return the last component of a path name. Note that we can't use a + prototype here because the parameter is declared inconsistently + across different systems, sometimes as "char *" and sometimes as + "const char *" */ + +/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is + undefined, we haven't run the autoconf check so provide the + declaration without arguments. If it is 0, we checked and failed + to find the declaration so provide a fully prototyped one. If it + is 1, we found it so don't provide any declaration at all. */ +#if !HAVE_DECL_BASENAME +#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined(__NetBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (__MINGW32__) || defined (HAVE_DECL_BASENAME) +extern char *basename PARAMS ((const char *)); +#else +extern char *basename (); +#endif +#endif + +/* A well-defined basename () that is always compiled in. */ + +extern const char *lbasename PARAMS ((const char *)); + +/* A well-defined realpath () that is always compiled in. */ + +extern char *lrealpath PARAMS ((const char *)); + +/* Concatenate an arbitrary number of strings. You must pass NULL as + the last argument of this function, to terminate the list of + strings. Allocates memory using xmalloc. */ + +extern char *concat PARAMS ((const char *, ...)) ATTRIBUTE_MALLOC ATTRIBUTE_SENTINEL; + +/* Concatenate an arbitrary number of strings. You must pass NULL as + the last argument of this function, to terminate the list of + strings. Allocates memory using xmalloc. The first argument is + not one of the strings to be concatenated, but if not NULL is a + pointer to be freed after the new string is created, similar to the + way xrealloc works. */ + +extern char *reconcat PARAMS ((char *, const char *, ...)) ATTRIBUTE_MALLOC ATTRIBUTE_SENTINEL; + +/* Determine the length of concatenating an arbitrary number of + strings. You must pass NULL as the last argument of this function, + to terminate the list of strings. */ + +extern unsigned long concat_length PARAMS ((const char *, ...)) ATTRIBUTE_SENTINEL; + +/* Concatenate an arbitrary number of strings into a SUPPLIED area of + memory. You must pass NULL as the last argument of this function, + to terminate the list of strings. The supplied memory is assumed + to be large enough. */ + +extern char *concat_copy PARAMS ((char *, const char *, ...)) ATTRIBUTE_SENTINEL; + +/* Concatenate an arbitrary number of strings into a GLOBAL area of + memory. You must pass NULL as the last argument of this function, + to terminate the list of strings. The supplied memory is assumed + to be large enough. */ + +extern char *concat_copy2 PARAMS ((const char *, ...)) ATTRIBUTE_SENTINEL; + +/* This is the global area used by concat_copy2. */ + +extern char *libiberty_concat_ptr; + +/* Concatenate an arbitrary number of strings. You must pass NULL as + the last argument of this function, to terminate the list of + strings. Allocates memory using alloca. The arguments are + evaluated twice! */ +#define ACONCAT(ACONCAT_PARAMS) \ + (libiberty_concat_ptr = alloca (concat_length ACONCAT_PARAMS + 1), \ + concat_copy2 ACONCAT_PARAMS) + +/* Check whether two file descriptors refer to the same file. */ + +extern int fdmatch PARAMS ((int fd1, int fd2)); + +/* Get the working directory. The result is cached, so don't call + chdir() between calls to getpwd(). */ + +extern char * getpwd PARAMS ((void)); + +/* Get the amount of time the process has run, in microseconds. */ + +extern long get_run_time PARAMS ((void)); + +/* Generate a relocated path to some installation directory. Allocates + return value using malloc. */ + +extern char *make_relative_prefix PARAMS ((const char *, const char *, + const char *)); + +/* Choose a temporary directory to use for scratch files. */ + +extern char *choose_temp_base PARAMS ((void)) ATTRIBUTE_MALLOC; + +/* Return a temporary file name or NULL if unable to create one. */ + +extern char *make_temp_file PARAMS ((const char *)) ATTRIBUTE_MALLOC; + +/* Allocate memory filled with spaces. Allocates using malloc. */ + +extern const char *spaces PARAMS ((int count)); + +/* Return the maximum error number for which strerror will return a + string. */ + +extern int errno_max PARAMS ((void)); + +/* Return the name of an errno value (e.g., strerrno (EINVAL) returns + "EINVAL"). */ + +extern const char *strerrno PARAMS ((int)); + +/* Given the name of an errno value, return the value. */ + +extern int strtoerrno PARAMS ((const char *)); + +/* ANSI's strerror(), but more robust. */ + +extern char *xstrerror PARAMS ((int)); + +/* Return the maximum signal number for which strsignal will return a + string. */ + +extern int signo_max PARAMS ((void)); + +/* Return a signal message string for a signal number + (e.g., strsignal (SIGHUP) returns something like "Hangup"). */ +/* This is commented out as it can conflict with one in system headers. + We still document its existence though. */ + +/*extern const char *strsignal PARAMS ((int));*/ + +/* Return the name of a signal number (e.g., strsigno (SIGHUP) returns + "SIGHUP"). */ + +extern const char *strsigno PARAMS ((int)); + +/* Given the name of a signal, return its number. */ + +extern int strtosigno PARAMS ((const char *)); + +/* Register a function to be run by xexit. Returns 0 on success. */ + +extern int xatexit PARAMS ((void (*fn) (void))); + +/* Exit, calling all the functions registered with xatexit. */ + +extern void xexit PARAMS ((int status)) ATTRIBUTE_NORETURN; + +/* Set the program name used by xmalloc. */ + +extern void xmalloc_set_program_name PARAMS ((const char *)); + +/* Report an allocation failure. */ +extern void xmalloc_failed PARAMS ((size_t)) ATTRIBUTE_NORETURN; + +/* Allocate memory without fail. If malloc fails, this will print a + message to stderr (using the name set by xmalloc_set_program_name, + if any) and then call xexit. */ + +extern PTR xmalloc PARAMS ((size_t)) ATTRIBUTE_MALLOC; + +/* Reallocate memory without fail. This works like xmalloc. Note, + realloc type functions are not suitable for attribute malloc since + they may return the same address across multiple calls. */ + +extern PTR xrealloc PARAMS ((PTR, size_t)); + +/* Allocate memory without fail and set it to zero. This works like + xmalloc. */ + +extern PTR xcalloc PARAMS ((size_t, size_t)) ATTRIBUTE_MALLOC; + +/* Copy a string into a memory buffer without fail. */ + +extern char *xstrdup PARAMS ((const char *)) ATTRIBUTE_MALLOC; + +/* Copy an existing memory buffer to a new memory buffer without fail. */ + +extern PTR xmemdup PARAMS ((const PTR, size_t, size_t)) ATTRIBUTE_MALLOC; + +/* Physical memory routines. Return values are in BYTES. */ +extern double physmem_total PARAMS ((void)); +extern double physmem_available PARAMS ((void)); + + +/* These macros provide a K&R/C89/C++-friendly way of allocating structures + with nice encapsulation. The XDELETE*() macros are technically + superfluous, but provided here for symmetry. Using them consistently + makes it easier to update client code to use different allocators such + as new/delete and new[]/delete[]. */ + +/* Scalar allocators. */ + +#define XNEW(T) ((T *) xmalloc (sizeof (T))) +#define XCNEW(T) ((T *) xcalloc (1, sizeof (T))) +#define XDELETE(P) free ((void*) (P)) + +/* Array allocators. */ + +#define XNEWVEC(T, N) ((T *) xmalloc (sizeof (T) * (N))) +#define XCNEWVEC(T, N) ((T *) xcalloc ((N), sizeof (T))) +#define XRESIZEVEC(T, P, N) ((T *) xrealloc ((void *) (P), sizeof (T) * (N))) +#define XDELETEVEC(P) free ((void*) (P)) + +/* Allocators for variable-sized structures and raw buffers. */ + +#define XNEWVAR(T, S) ((T *) xmalloc ((S))) +#define XCNEWVAR(T, S) ((T *) xcalloc (1, (S))) +#define XRESIZEVAR(T, P, S) ((T *) xrealloc ((P), (S))) + +/* Type-safe obstack allocator. */ + +#define XOBNEW(O, T) ((T *) obstack_alloc ((O), sizeof (T))) + + +/* hex character manipulation routines */ + +#define _hex_array_size 256 +#define _hex_bad 99 +extern const unsigned char _hex_value[_hex_array_size]; +extern void hex_init PARAMS ((void)); +#define hex_p(c) (hex_value (c) != _hex_bad) +/* If you change this, note well: Some code relies on side effects in + the argument being performed exactly once. */ +#define hex_value(c) ((unsigned int) _hex_value[(unsigned char) (c)]) + +/* Definitions used by the pexecute routine. */ + +#define PEXECUTE_FIRST 1 +#define PEXECUTE_LAST 2 +#define PEXECUTE_ONE (PEXECUTE_FIRST + PEXECUTE_LAST) +#define PEXECUTE_SEARCH 4 +#define PEXECUTE_VERBOSE 8 + +/* Execute a program. */ + +extern int pexecute PARAMS ((const char *, char * const *, const char *, + const char *, char **, char **, int)); + +/* Wait for pexecute to finish. */ + +extern int pwait PARAMS ((int, int *, int)); + +#if !HAVE_DECL_ASPRINTF +/* Like sprintf but provides a pointer to malloc'd storage, which must + be freed by the caller. */ + +extern int asprintf PARAMS ((char **, const char *, ...)) ATTRIBUTE_PRINTF_2; +#endif + +#if !HAVE_DECL_VASPRINTF +/* Like vsprintf but provides a pointer to malloc'd storage, which + must be freed by the caller. */ + +extern int vasprintf PARAMS ((char **, const char *, va_list)) + ATTRIBUTE_PRINTF(2,0); +#endif + +#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) + +/* Drastically simplified alloca configurator. If we're using GCC, + we use __builtin_alloca; otherwise we use the C alloca. The C + alloca is always available. You can override GCC by defining + USE_C_ALLOCA yourself. The canonical autoconf macro C_ALLOCA is + also set/unset as it is often used to indicate whether code needs + to call alloca(0). */ +extern PTR C_alloca PARAMS ((size_t)) ATTRIBUTE_MALLOC; +#undef alloca +#if GCC_VERSION >= 2000 && !defined USE_C_ALLOCA +# define alloca(x) __builtin_alloca(x) +# undef C_ALLOCA +# define ASTRDUP(X) \ + (__extension__ ({ const char *const libiberty_optr = (X); \ + const unsigned long libiberty_len = strlen (libiberty_optr) + 1; \ + char *const libiberty_nptr = (char *const) alloca (libiberty_len); \ + (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len); })) +#else +# define alloca(x) C_alloca(x) +# undef USE_C_ALLOCA +# define USE_C_ALLOCA 1 +# undef C_ALLOCA +# define C_ALLOCA 1 +extern const char *libiberty_optr; +extern char *libiberty_nptr; +extern unsigned long libiberty_len; +# define ASTRDUP(X) \ + (libiberty_optr = (X), \ + libiberty_len = strlen (libiberty_optr) + 1, \ + libiberty_nptr = (char *) alloca (libiberty_len), \ + (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len)) +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* ! defined (LIBIBERTY_H) */ diff --git a/include/md5.h b/include/md5.h new file mode 100644 index 000000000..ad51f1987 --- /dev/null +++ b/include/md5.h @@ -0,0 +1,142 @@ +/* md5.h - Declaration of functions and data types used for MD5 sum + computing library functions. + Copyright 1995, 1996, 2000 Free Software Foundation, Inc. + NOTE: The canonical source of this file is maintained with the GNU C + Library. Bugs can be reported to bug-glibc@prep.ai.mit.edu. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _MD5_H +#define _MD5_H 1 + +#include <stdio.h> + +#if defined HAVE_LIMITS_H || _LIBC +# include <limits.h> +#endif + +/* The following contortions are an attempt to use the C preprocessor + to determine an unsigned integral type that is 32 bits wide. An + alternative approach is to use autoconf's AC_CHECK_SIZEOF macro, but + doing that would require that the configure script compile and *run* + the resulting executable. Locally running cross-compiled executables + is usually not possible. */ + +#ifdef _LIBC +# include <sys/types.h> +typedef u_int32_t md5_uint32; +#else +# define INT_MAX_32_BITS 2147483647 + +/* If UINT_MAX isn't defined, assume it's a 32-bit type. + This should be valid for all systems GNU cares about because + that doesn't include 16-bit systems, and only modern systems + (that certainly have <limits.h>) have 64+-bit integral types. */ + +# ifndef INT_MAX +# define INT_MAX INT_MAX_32_BITS +# endif + +# if INT_MAX == INT_MAX_32_BITS + typedef unsigned int md5_uint32; +# else +# if SHRT_MAX == INT_MAX_32_BITS + typedef unsigned short md5_uint32; +# else +# if LONG_MAX == INT_MAX_32_BITS + typedef unsigned long md5_uint32; +# else + /* The following line is intended to evoke an error. + Using #error is not portable enough. */ + "Cannot determine unsigned 32-bit data type." +# endif +# endif +# endif +#endif + +#undef __P +#if defined (__STDC__) && __STDC__ +#define __P(x) x +#else +#define __P(x) () +#endif + +/* Structure to save state of computation between the single steps. */ +struct md5_ctx +{ + md5_uint32 A; + md5_uint32 B; + md5_uint32 C; + md5_uint32 D; + + md5_uint32 total[2]; + md5_uint32 buflen; + char buffer[128]; +}; + +/* + * The following three functions are build up the low level used in + * the functions `md5_stream' and `md5_buffer'. + */ + +/* Initialize structure containing state of computation. + (RFC 1321, 3.3: Step 3) */ +extern void md5_init_ctx __P ((struct md5_ctx *ctx)); + +/* Starting with the result of former calls of this function (or the + initialization function update the context for the next LEN bytes + starting at BUFFER. + It is necessary that LEN is a multiple of 64!!! */ +extern void md5_process_block __P ((const void *buffer, size_t len, + struct md5_ctx *ctx)); + +/* Starting with the result of former calls of this function (or the + initialization function update the context for the next LEN bytes + starting at BUFFER. + It is NOT required that LEN is a multiple of 64. */ +extern void md5_process_bytes __P ((const void *buffer, size_t len, + struct md5_ctx *ctx)); + +/* Process the remaining bytes in the buffer and put result from CTX + in first 16 bytes following RESBUF. The result is always in little + endian byte order, so that a byte-wise output yields to the wanted + ASCII representation of the message digest. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +extern void *md5_finish_ctx __P ((struct md5_ctx *ctx, void *resbuf)); + + +/* Put result from CTX in first 16 bytes following RESBUF. The result is + always in little endian byte order, so that a byte-wise output yields + to the wanted ASCII representation of the message digest. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +extern void *md5_read_ctx __P ((const struct md5_ctx *ctx, void *resbuf)); + + +/* Compute MD5 message digest for bytes read from STREAM. The + resulting message digest number will be written into the 16 bytes + beginning at RESBLOCK. */ +extern int md5_stream __P ((FILE *stream, void *resblock)); + +/* Compute MD5 message digest for LEN bytes beginning at BUFFER. The + result is always in little endian byte order, so that a byte-wise + output yields to the wanted ASCII representation of the message + digest. */ +extern void *md5_buffer __P ((const char *buffer, size_t len, void *resblock)); + +#endif diff --git a/include/nlm/ChangeLog b/include/nlm/ChangeLog new file mode 100644 index 000000000..b3c9529b8 --- /dev/null +++ b/include/nlm/ChangeLog @@ -0,0 +1,93 @@ +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * internal.h (Nlm_Internal_Custom_Header): Replace PTR with void *. + +2001-10-02 Alan Modra <amodra@bigpond.net.au> + + * common.h (NLM_CAT, NLM_CAT3): Don't define. + (NLM_CAT4): Update conditions under which this is defined. Document + why CONCAT4 can't be used. + +Fri May 6 13:31:04 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * external.h (nlmNAME(External_Custom_Header)): Add length, + dataOffset, and dataStamp field. + (nlmNAME(External_Cygnus_Ext_Header)): Remove. + * internal.h (Nlm_Internal_Custom_Header): Add hdrLength, + dataOffset, dataStamp and hdr fields. + +Fri Apr 22 11:12:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * external.h (struct nlmNAME(external_cygnus_ext_header)): Rename + from nlmNAME(external_cygnus_section_header). Change stamp field + to 8 bytes. Add bytes field. + * internal.h (nlm_internal_cygnus_ext_header): Rename from + nlm_internal_cygnus_section_header. Change stamp field to 8 + bytes. + +Thu Apr 21 11:57:09 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (struct nlm_internal_cygnus_section_header): Define. + * external.h (struct nlmNAME(external_cygnus_section_header): + Define. + +Wed Apr 20 14:27:43 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (struct nlm_internal_custom_header): Remove + debugRecOffset and debugRecLength fields. Add data field. + * external.h (struct nlmNAME(external_custom_header)): Remove + debugRecOffset and debugRecLength fields. + +Mon Feb 7 08:28:40 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * internal.h: Change HOST_64_BIT to BFD_HOST_64_BIT. + +Thu Dec 2 14:14:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * alpha-ext.h: New file describing formats of information in Alpha + NetWare files. + * common.h: Define some non-external Alpha information. + +Wed Nov 17 17:38:58 1993 Sean Eric Fagan (sef@cygnus.com) + + * external.h: Don't define external_fixed_header here. + * i386-ext.h, sparc32-ext.h: New header files to define + external_fixed_header for particular CPU's. + +Wed Oct 27 11:45:56 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (Nlm_Internal_Extended_Header): Added fields + sharedDebugRecordOffset and sharedDebugRecordCount. + * external.h (NlmNAME(External_Extended_Header)): Likewise. + + * common.h (NLM_SIGNATURE): Do not define (it's different for each + backend). + +Tue Aug 31 13:24:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h: Change length fields of type char to type unsigned + char. + +Sat Jul 31 02:12:14 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * common.h (NLM_HIBIT, NLM_HEADER_VERSION): Define. + +Thu Jul 22 16:09:47 1993 Fred Fish (fnf@deneb.cygnus.com) + + * common.h (NLM_CAT*, NLM_ARCH_SIZE, NLM_TARGET_LONG_SIZE, + NLM_TARGET_ADDRESS_SIZE, NLM_NAME, NlmNAME, nlmNAME): New + macros. + * external.h (TARGET_LONG_SIZE, TARGET_ADDRESS_SIZE): Remove + macros, convert usages to NLM_ equivalents. + * external.h: Use nlmNAME and NlmNAME macros to derive both + 32 and 64 bit versions. + +Mon Jul 19 22:12:40 1993 Fred Fish (fnf@deneb.cygnus.com) + + * (common.h, external.h, internal.h): New files for NLM/NetWare + support. + + +Local Variables: +version-control: never +End: diff --git a/include/nlm/alpha-ext.h b/include/nlm/alpha-ext.h new file mode 100644 index 000000000..ae6752402 --- /dev/null +++ b/include/nlm/alpha-ext.h @@ -0,0 +1,166 @@ +/* Alpha NLM (NetWare Loadable Module) support for BFD. + Copyright 1993 Free Software Foundation, Inc. + By Ian Lance Taylor, Cygnus Support + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* An Alpha NLM starts with an instance of this structure. */ + +struct nlm32_alpha_external_prefix_header +{ + /* Magic number. Must be NLM32_ALPHA_MAGIC. */ + unsigned char magic[4]; + /* Format descriptor. Current value is 2. */ + unsigned char format[4]; + /* Size of prefix header. */ + unsigned char size[4]; + /* Padding. */ + unsigned char pad1[4]; + /* More fields may be added later, supposedly. */ +}; + +/* The external format of an Alpha NLM reloc. This is the same as an + Alpha ECOFF reloc. */ + +struct nlm32_alpha_external_reloc +{ + unsigned char r_vaddr[8]; + unsigned char r_symndx[4]; + unsigned char r_bits[4]; +}; + +/* Constants to unpack the r_bits field of a reloc. */ + +#define RELOC_BITS0_TYPE_LITTLE 0xff +#define RELOC_BITS0_TYPE_SH_LITTLE 0 + +#define RELOC_BITS1_EXTERN_LITTLE 0x01 + +#define RELOC_BITS1_OFFSET_LITTLE 0x7e +#define RELOC_BITS1_OFFSET_SH_LITTLE 1 + +#define RELOC_BITS1_RESERVED_LITTLE 0x80 +#define RELOC_BITS1_RESERVED_SH_LITTLE 7 +#define RELOC_BITS2_RESERVED_LITTLE 0xff +#define RELOC_BITS2_RESERVED_SH_LEFT_LITTLE 1 +#define RELOC_BITS3_RESERVED_LITTLE 0x03 +#define RELOC_BITS3_RESERVED_SH_LEFT_LITTLE 9 + +#define RELOC_BITS3_SIZE_LITTLE 0xfc +#define RELOC_BITS3_SIZE_SH_LITTLE 2 + +/* The external format of the fixed header. */ + +typedef struct nlm32_alpha_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_alpha_External_Fixed_Header; diff --git a/include/nlm/common.h b/include/nlm/common.h new file mode 100644 index 000000000..208f4cfa7 --- /dev/null +++ b/include/nlm/common.h @@ -0,0 +1,123 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 2001 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of NLM support for BFD, and contains the portions + that are common to both the internal and external representations. */ + +/* If NLM_ARCH_SIZE is not defined, default to 32. NLM_ARCH_SIZE is + optionally defined by the application. */ + +#ifndef NLM_ARCH_SIZE +# define NLM_ARCH_SIZE 32 +#endif + +/* Due to horrible details of ANSI macro expansion, we can't use CONCAT4 + for NLM_NAME. CONCAT2 is used in BFD_JUMP_TABLE macros, and some of + them will expand to tokens that themselves are macros defined in terms + of NLM_NAME. If NLM_NAME were defined using CONCAT4 (which is itself + defined in bfd-in.h using CONCAT2), ANSI preprocessor rules say that + the CONCAT2 within NLM_NAME should not be expanded. + So use another name. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#ifdef SABER +#define NLM_CAT4(a,b,c,d) a##b##c##d +#else +/* This hack is to avoid a problem with some strict ANSI C preprocessors. + The problem is, "32_" is not a valid preprocessing token, and we don't + want extra underscores (e.g., "nlm_32_"). The NLM_XCAT2 macro will + cause the inner CAT2 macros to be evaluated first, producing + still-valid pp-tokens. Then the final concatenation can be done. */ +#define NLM_CAT2(a,b) a##b +#define NLM_XCAT2(a,b) NLM_CAT2(a,b) +#define NLM_CAT4(a,b,c,d) NLM_XCAT2(NLM_CAT2(a,b),NLM_CAT2(c,d)) +#endif +#else +#define NLM_CAT4(a,b,c,d) a/**/b/**/c/**/d +#endif + +#if NLM_ARCH_SIZE == 32 +# define NLM_TARGET_LONG_SIZE 4 +# define NLM_TARGET_ADDRESS_SIZE 4 +# define NLM_NAME(x,y) NLM_CAT4(x,32,_,y) +# define NLM_HIBIT (((bfd_vma) 1) << 31) +#endif +#if NLM_ARCH_SIZE == 64 +# define NLM_TARGET_LONG_SIZE 8 +# define NLM_TARGET_ADDRESS_SIZE 8 +# define NLM_NAME(x,y) NLM_CAT4(x,64,_,y) +# define NLM_HIBIT (((bfd_vma) 1) << 63) +#endif + +#define NlmNAME(X) NLM_NAME(Nlm,X) +#define nlmNAME(X) NLM_NAME(nlm,X) + +/* Give names to things that should not change. */ + +#define NLM_MAX_DESCRIPTION_LENGTH 127 +#define NLM_MAX_SCREEN_NAME_LENGTH 71 +#define NLM_MAX_THREAD_NAME_LENGTH 71 +#define NLM_MAX_COPYRIGHT_MESSAGE_LENGTH 255 +#define NLM_OTHER_DATA_LENGTH 400 /* FIXME */ +#define NLM_OLD_THREAD_NAME_LENGTH 5 +#define NLM_SIGNATURE_SIZE 24 +#define NLM_HEADER_VERSION 4 +#define NLM_MODULE_NAME_SIZE 14 +#define NLM_DEFAULT_STACKSIZE (8 * 1024) + +/* Alpha information. This should probably be in a separate Alpha + header file, but it can't go in alpha-ext.h because some of it is + needed by nlmconv.c. */ + +/* Magic number in Alpha prefix header. */ +#define NLM32_ALPHA_MAGIC (0x83561840) + +/* The r_type field in an Alpha reloc is one of the following values. */ +#define ALPHA_R_IGNORE 0 +#define ALPHA_R_REFLONG 1 +#define ALPHA_R_REFQUAD 2 +#define ALPHA_R_GPREL32 3 +#define ALPHA_R_LITERAL 4 +#define ALPHA_R_LITUSE 5 +#define ALPHA_R_GPDISP 6 +#define ALPHA_R_BRADDR 7 +#define ALPHA_R_HINT 8 +#define ALPHA_R_SREL16 9 +#define ALPHA_R_SREL32 10 +#define ALPHA_R_SREL64 11 +#define ALPHA_R_OP_PUSH 12 +#define ALPHA_R_OP_STORE 13 +#define ALPHA_R_OP_PSUB 14 +#define ALPHA_R_OP_PRSHIFT 15 +#define ALPHA_R_GPVALUE 16 +#define ALPHA_R_NW_RELOC 250 + +/* A local reloc, other than ALPHA_R_GPDISP or ALPHA_R_IGNORE, must be + against one of these symbol indices. */ +#define ALPHA_RELOC_SECTION_TEXT 1 +#define ALPHA_RELOC_SECTION_DATA 3 + +/* An ALPHA_R_NW_RELOC has one of these values in the size field. If + it is SETGP, the r_vaddr field holds the GP value to use. If it is + LITA, the r_vaddr field holds the address of the .lita section and + the r_symndx field holds the size of the .lita section. */ +#define ALPHA_R_NW_RELOC_SETGP 1 +#define ALPHA_R_NW_RELOC_LITA 2 diff --git a/include/nlm/external.h b/include/nlm/external.h new file mode 100644 index 000000000..12a486fd4 --- /dev/null +++ b/include/nlm/external.h @@ -0,0 +1,174 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 1994 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of NLM support for BFD, and contains the portions + that describe how NLM is represented externally by the BFD library. + I.E. it describes the in-file representation of NLM. It requires + the nlm/common.h file which contains the portions that are common to + both the internal and external representations. + + Note that an NLM header consists of three parts: + + (1) A fixed length header that has specific fields of known length, + at specific offsets in the file. + + (2) A variable length header that has specific fields in a specific + order, but some fields may be variable length. + + (3) A auxiliary header that has various optional fields in no specific + order. There is no way to identify the end of the auxiliary headers + except by finding a header without a recognized 'stamp'. + + The exact format of the fixed length header unfortunately varies + from one NLM target to another, due to padding. Each target + defines the correct external format in a separate header file. + +*/ + +/* NLM Header */ + +/* The version header is one of the optional auxiliary headers and + follows the fixed length and variable length NLM headers. */ + +typedef struct nlmNAME(external_version_header) +{ + + /* The header is recognized by "VeRsIoN#" in the stamp field. */ + char stamp[8]; + + unsigned char majorVersion[NLM_TARGET_LONG_SIZE]; + + unsigned char minorVersion[NLM_TARGET_LONG_SIZE]; + + unsigned char revision[NLM_TARGET_LONG_SIZE]; + + unsigned char year[NLM_TARGET_LONG_SIZE]; + + unsigned char month[NLM_TARGET_LONG_SIZE]; + + unsigned char day[NLM_TARGET_LONG_SIZE]; + +} NlmNAME(External_Version_Header); + + +typedef struct nlmNAME(external_copyright_header) +{ + + /* The header is recognized by "CoPyRiGhT=" in the stamp field. */ + + char stamp[10]; + + unsigned char copyrightMessageLength[1]; + + /* There is a variable length field here called 'copyrightMessage' + that is the length specified by copyrightMessageLength. */ + +} NlmNAME(External_Copyright_Header); + + +typedef struct nlmNAME(external_extended_header) +{ + + /* The header is recognized by "MeSsAgEs" in the stamp field. */ + + char stamp[8]; + + unsigned char languageID[NLM_TARGET_LONG_SIZE]; + + unsigned char messageFileOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char messageFileLength[NLM_TARGET_LONG_SIZE]; + + unsigned char messageCount[NLM_TARGET_LONG_SIZE]; + + unsigned char helpFileOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char helpFileLength[NLM_TARGET_LONG_SIZE]; + + unsigned char RPCDataOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char RPCDataLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedCodeOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedCodeLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDataOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDataLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedRelocationFixupOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedRelocationFixupCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedExternalReferenceOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedExternalReferenceCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedPublicsOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedPublicsCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDebugRecordOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDebugRecordCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedInitializationOffset[NLM_TARGET_ADDRESS_SIZE]; + + unsigned char SharedExitProcedureOffset[NLM_TARGET_ADDRESS_SIZE]; + + unsigned char productID[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved0[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved1[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved2[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved3[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved4[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved5[NLM_TARGET_LONG_SIZE]; + +} NlmNAME(External_Extended_Header); + + +typedef struct nlmNAME(external_custom_header) +{ + + /* The header is recognized by "CuStHeAd" in the stamp field. */ + char stamp[8]; + + /* Length of this header. */ + unsigned char length[NLM_TARGET_LONG_SIZE]; + + /* Offset to data. */ + unsigned char dataOffset[NLM_TARGET_LONG_SIZE]; + + /* Length of data. */ + unsigned char dataLength[NLM_TARGET_LONG_SIZE]; + + /* Stamp for this customer header--we recognize "CyGnUsEx". */ + char dataStamp[8]; + +} NlmNAME(External_Custom_Header); diff --git a/include/nlm/i386-ext.h b/include/nlm/i386-ext.h new file mode 100644 index 000000000..c7380120e --- /dev/null +++ b/include/nlm/i386-ext.h @@ -0,0 +1,116 @@ +/* i386 NLM (NetWare Loadable Module) support for BFD. + Copyright 1993 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_i386_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_i386_External_Fixed_Header; diff --git a/include/nlm/internal.h b/include/nlm/internal.h new file mode 100644 index 000000000..f61c42db8 --- /dev/null +++ b/include/nlm/internal.h @@ -0,0 +1,309 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 1994, 2003 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of NLM support for BFD, and contains the portions + that describe how NLM is represented internally in the BFD library. + I.E. it describes the in-memory representation of NLM. It requires + the nlm/common.h file which contains the portions that are common to + both the internal and external representations. */ + +#if 0 + +/* Types used by various structures, functions, etc. */ + +typedef unsigned long Nlm32_Addr; /* Unsigned program address */ +typedef unsigned long Nlm32_Off; /* Unsigned file offset */ +typedef long Nlm32_Sword; /* Signed large integer */ +typedef unsigned long Nlm32_Word; /* Unsigned large integer */ +typedef unsigned short Nlm32_Half; /* Unsigned medium integer */ +typedef unsigned char Nlm32_Char; /* Unsigned tiny integer */ + +#ifdef BFD_HOST_64_BIT +typedef unsigned BFD_HOST_64_BIT Nlm64_Addr; +typedef unsigned BFD_HOST_64_BIT Nlm64_Off; +typedef BFD_HOST_64_BIT Nlm64_Sxword; +typedef unsigned BFD_HOST_64_BIT Nlm64_Xword; +#endif +typedef long Nlm64_Sword; +typedef unsigned long Nlm64_Word; +typedef unsigned short Nlm64_Half; + +#endif /* 0 */ + +/* This structure contains the internal form of the portion of the NLM + header that is fixed length. */ + +typedef struct nlm_internal_fixed_header +{ + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + char signature[NLM_SIGNATURE_SIZE]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + long version; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension. The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + char moduleName[NLM_MODULE_NAME_SIZE]; + + /* The byte offset of the code image from the start of the file. */ + + file_ptr codeImageOffset; + + /* The size of the code image, in bytes. */ + + bfd_size_type codeImageSize; + + /* The byte offset of the data image from the start of the file. */ + + file_ptr dataImageOffset; + + /* The size of the data image, in bytes. */ + + bfd_size_type dataImageSize; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + bfd_size_type uninitializedDataSize; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. */ + + file_ptr customDataOffset; + + /* The size of the custom data, in bytes. */ + + bfd_size_type customDataSize; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + file_ptr moduleDependencyOffset; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + long numberOfModuleDependencies; + + /* The byte offset of the relocation fixup data from the start of the file */ + + file_ptr relocationFixupOffset; + long numberOfRelocationFixups; + file_ptr externalReferencesOffset; + long numberOfExternalReferences; + file_ptr publicsOffset; + long numberOfPublics; + file_ptr debugInfoOffset; + long numberOfDebugRecords; + file_ptr codeStartOffset; + file_ptr exitProcedureOffset; + file_ptr checkUnloadProcedureOffset; + long moduleType; + long flags; +} Nlm_Internal_Fixed_Header; + +#define nlm32_internal_fixed_header nlm_internal_fixed_header +#define Nlm32_Internal_Fixed_Header Nlm_Internal_Fixed_Header +#define nlm64_internal_fixed_header nlm_internal_fixed_header +#define Nlm64_Internal_Fixed_Header Nlm_Internal_Fixed_Header + +/* This structure contains the portions of the NLM header that are either + variable in size in the external representation, or else are not at a + fixed offset relative to the start of the NLM header due to preceding + variable sized fields. + + Note that all the fields must exist in the external header, and in + the order used here (the same order is used in the internal form + for consistency, not out of necessity). */ + +typedef struct nlm_internal_variable_header +{ + + /* The descriptionLength field contains the length of the text in + descriptionText, excluding the null terminator. The descriptionText + field contains the NLM description obtained from the DESCRIPTION + keyword in NLMLINK plus the null byte terminator. The descriptionText + can be up to NLM_MAX_DESCRIPTION_LENGTH characters. */ + + unsigned char descriptionLength; + char descriptionText[NLM_MAX_DESCRIPTION_LENGTH + 1]; + + /* The stackSize field contains the size of the stack in bytes, as + specified by the STACK or STACKSIZE keyword in NLMLINK. If no size + is specified, the default is NLM_DEFAULT_STACKSIZE. */ + + long stackSize; + + /* The reserved field is included only for completeness. It should contain + zero. */ + + long reserved; + + /* This field is fixed length, should contain " LONG" (note leading + space), and is unused. */ + + char oldThreadName[NLM_OLD_THREAD_NAME_LENGTH]; + + /* The screenNameLength field contains the length of the actual text stored + in the screenName field, excluding the null byte terminator. The + screenName field contains the screen name as specified by the SCREENNAME + keyword in NLMLINK, and can be up to NLM_MAX_SCREEN_NAME_LENGTH + characters. */ + + unsigned char screenNameLength; + char screenName[NLM_MAX_SCREEN_NAME_LENGTH + 1]; + + /* The threadNameLength field contains the length of the actual text stored + in the threadName field, excluding the null byte terminator. The + threadName field contains the thread name as specified by the THREADNAME + keyword in NLMLINK, and can be up to NLM_MAX_THREAD_NAME_LENGTH + characters. */ + + unsigned char threadNameLength; + char threadName[NLM_MAX_THREAD_NAME_LENGTH + 1]; + +} Nlm_Internal_Variable_Header; + +#define nlm32_internal_variable_header nlm_internal_variable_header +#define Nlm32_Internal_Variable_Header Nlm_Internal_Variable_Header +#define nlm64_internal_variable_header nlm_internal_variable_header +#define Nlm64_Internal_Variable_Header Nlm_Internal_Variable_Header + +/* The version header is one of the optional auxiliary headers and + follows the fixed length and variable length NLM headers. */ + +typedef struct nlm_internal_version_header +{ + /* The header is recognized by "VeRsIoN#" in the stamp field. */ + char stamp[8]; + long majorVersion; + long minorVersion; + long revision; + long year; + long month; + long day; +} Nlm_Internal_Version_Header; + +#define nlm32_internal_version_header nlm_internal_version_header +#define Nlm32_Internal_Version_Header Nlm_Internal_Version_Header +#define nlm64_internal_version_header nlm_internal_version_header +#define Nlm64_Internal_Version_Header Nlm_Internal_Version_Header + +typedef struct nlm_internal_copyright_header +{ + /* The header is recognized by "CoPyRiGhT=" in the stamp field. */ + char stamp[10]; + unsigned char copyrightMessageLength; + char copyrightMessage[NLM_MAX_COPYRIGHT_MESSAGE_LENGTH]; +} Nlm_Internal_Copyright_Header; + +#define nlm32_internal_copyright_header nlm_internal_copyright_header +#define Nlm32_Internal_Copyright_Header Nlm_Internal_Copyright_Header +#define nlm64_internal_copyright_header nlm_internal_copyright_header +#define Nlm64_Internal_Copyright_Header Nlm_Internal_Copyright_Header + +typedef struct nlm_internal_extended_header +{ + /* The header is recognized by "MeSsAgEs" in the stamp field. */ + char stamp[8]; + long languageID; + file_ptr messageFileOffset; + bfd_size_type messageFileLength; + long messageCount; + file_ptr helpFileOffset; + bfd_size_type helpFileLength; + file_ptr RPCDataOffset; + bfd_size_type RPCDataLength; + file_ptr sharedCodeOffset; + bfd_size_type sharedCodeLength; + file_ptr sharedDataOffset; + bfd_size_type sharedDataLength; + file_ptr sharedRelocationFixupOffset; + long sharedRelocationFixupCount; + file_ptr sharedExternalReferenceOffset; + long sharedExternalReferenceCount; + file_ptr sharedPublicsOffset; + long sharedPublicsCount; + file_ptr sharedDebugRecordOffset; + long sharedDebugRecordCount; + bfd_vma SharedInitializationOffset; + bfd_vma SharedExitProcedureOffset; + long productID; + long reserved0; + long reserved1; + long reserved2; + long reserved3; + long reserved4; + long reserved5; +} Nlm_Internal_Extended_Header; + +#define nlm32_internal_extended_header nlm_internal_extended_header +#define Nlm32_Internal_Extended_Header Nlm_Internal_Extended_Header +#define nlm64_internal_extended_header nlm_internal_extended_header +#define Nlm64_Internal_Extended_Header Nlm_Internal_Extended_Header + +/* The format of a custom header as stored internally is different + from the external format. This is how we store a custom header + which we do not recognize. */ + +typedef struct nlm_internal_custom_header +{ + /* The header is recognized by "CuStHeAd" in the stamp field. */ + char stamp[8]; + bfd_size_type hdrLength; + file_ptr dataOffset; + bfd_size_type dataLength; + char dataStamp[8]; + void *hdr; +} Nlm_Internal_Custom_Header; + +#define nlm32_internal_custom_header nlm_internal_custom_header +#define Nlm32_Internal_Custom_Header Nlm_Internal_Custom_Header +#define nlm64_internal_custom_header nlm_internal_custom_header +#define Nlm64_Internal_Custom_Header Nlm_Internal_Custom_Header + +/* The internal Cygnus header is written out externally as a custom + header. We don't try to replicate that structure here. */ + +typedef struct nlm_internal_cygnus_ext_header +{ + /* The header is recognized by "CyGnUsEx" in the stamp field. */ + char stamp[8]; + /* File location of debugging information. */ + file_ptr offset; + /* Length of debugging information. */ + bfd_size_type length; +} Nlm_Internal_Cygnus_Ext_Header; + +#define nlm32_internal_cygnus_ext_header nlm_internal_cygnus_ext_header +#define Nlm32_Internal_Cygnus_Ext_Header Nlm_Internal_Cygnus_Ext_Header +#define nlm64_internal_cygnus_ext_header nlm_internal_cygnus_ext_header +#define Nlm64_Internal_Cygnus_Ext_Header Nlm_Internal_Cygnus_Ext_Header diff --git a/include/nlm/ppc-ext.h b/include/nlm/ppc-ext.h new file mode 100644 index 000000000..0aae10772 --- /dev/null +++ b/include/nlm/ppc-ext.h @@ -0,0 +1,163 @@ +/* PowerPC NLM (NetWare Loadable Module) support for BFD. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifdef OLDFORMAT + +/* The format of a PowerPC NLM changed. These structures are only + used in the old format. */ + +/* A PowerPC NLM starts with an instance of this structure. */ + +struct nlm32_powerpc_external_prefix_header +{ + /* Signature. Must be "AppleNLM". */ + char signature[8]; + /* Version number. Current value is 1. */ + unsigned char headerVersion[4]; + /* ??. Should be set to 0. */ + unsigned char origins[4]; + /* File creation date in standard Unix time format (seconds since + 1/1/70). */ + unsigned char date[4]; +}; + +#define NLM32_POWERPC_SIGNATURE "AppleNLM" +#define NLM32_POWERPC_HEADER_VERSION 1 + +/* The external format of a PowerPC NLM reloc. This is the same as an + XCOFF dynamic reloc. */ + +struct nlm32_powerpc_external_reloc +{ + /* Address. */ + unsigned char l_vaddr[4]; + /* Symbol table index. This is 0 for .text and 1 for .data. 2 + means .bss, but I don't know if it is used. In XCOFF, larger + numbers are indices into the dynamic symbol table, but they are + presumably not used in an NLM. */ + unsigned char l_symndx[4]; + /* Relocation type. */ + unsigned char l_rtype[2]; + /* Section number being relocated. */ + unsigned char l_rsecnm[2]; +}; + +#endif /* OLDFORMAT */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_powerpc_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_powerpc_External_Fixed_Header; diff --git a/include/nlm/sparc32-ext.h b/include/nlm/sparc32-ext.h new file mode 100644 index 000000000..d73b644b4 --- /dev/null +++ b/include/nlm/sparc32-ext.h @@ -0,0 +1,120 @@ +/* SPARC NLM (NetWare Loadable Module) support for BFD. + Copyright 1993 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_sparc_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_sparc_External_Fixed_Header; diff --git a/include/oasys.h b/include/oasys.h new file mode 100644 index 000000000..c8f737a45 --- /dev/null +++ b/include/oasys.h @@ -0,0 +1,192 @@ +/* Oasys object format header file for BFD. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + Contributed by Cygnus Support. */ + +#define OASYS_MAX_SEC_COUNT 16 +/* **** */ + +typedef struct oasys_archive_header + { + unsigned int version; + char create_date[12]; + char revision_date[12]; + unsigned int mod_count; + file_ptr mod_tbl_offset; + unsigned int sym_tbl_size; + unsigned int sym_count; + file_ptr sym_tbl_offset; + unsigned int xref_count; + file_ptr xref_lst_offset; + } +oasys_archive_header_type; + +typedef struct oasys_extarchive_header + { + bfd_byte version[4]; + bfd_byte create_date[12]; + bfd_byte revision_date[12]; + bfd_byte mod_count[4]; + bfd_byte mod_tbl_offset[4]; + bfd_byte sym_tbl_size[4]; + bfd_byte sym_count[4]; + bfd_byte sym_tbl_offset[4]; + bfd_byte xref_count[4]; + bfd_byte xref_lst_offset[4]; + } +oasys_extarchive_header_type; + +typedef struct oasys_module_table + { + int mod_number; + char mod_date[12]; + unsigned int mod_size; + unsigned int dep_count; + unsigned int depee_count; + file_ptr file_offset; + unsigned int sect_count; + char *module_name; + unsigned int module_name_size; + } +oasys_module_table_type; + +typedef struct oasys_extmodule_table_a + { + bfd_byte mod_number[4]; + bfd_byte mod_date[12]; + bfd_byte mod_size[4]; + bfd_byte dep_count[4]; + bfd_byte depee_count[4]; + bfd_byte sect_count[4]; + bfd_byte file_offset[4]; + bfd_byte mod_name[32]; + } +oasys_extmodule_table_type_a_type; + +typedef struct oasys_extmodule_table_b + { + bfd_byte mod_number[4]; + bfd_byte mod_date[12]; + bfd_byte mod_size[4]; + bfd_byte dep_count[4]; + bfd_byte depee_count[4]; + bfd_byte sect_count[4]; + bfd_byte file_offset[4]; + bfd_byte mod_name_length[4]; + } +oasys_extmodule_table_type_b_type; + +typedef enum oasys_record + { + oasys_record_is_end_enum = 0, + oasys_record_is_data_enum = 1, + oasys_record_is_symbol_enum = 2, + oasys_record_is_header_enum = 3, + oasys_record_is_named_section_enum = 4, + oasys_record_is_com_enum = 5, + oasys_record_is_debug_enum = 6, + oasys_record_is_section_enum = 7, + oasys_record_is_debug_file_enum = 8, + oasys_record_is_module_enum = 9, + oasys_record_is_local_enum = 10 + } +oasys_record_enum_type; + +typedef struct oasys_record_header + { + unsigned char length; + unsigned char check_sum; + unsigned char type; + unsigned char fill; + } +oasys_record_header_type; + +typedef struct oasys_data_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte addr[4]; + /* maximum total size of data record is 255 bytes */ + bfd_byte data[246]; + } +oasys_data_record_type; + +typedef struct oasys_header_record + { + oasys_record_header_type header; + unsigned char version_number; + unsigned char rev_number; + char module_name[26-6]; + char description[64-26]; + } +oasys_header_record_type; + +#define OASYS_VERSION_NUMBER 0 +#define OASYS_REV_NUMBER 0 + +typedef struct oasys_symbol_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte value[4]; + bfd_byte refno[2]; + char name[64]; + } +oasys_symbol_record_type; + +#define RELOCATION_PCREL_BIT 0x80 +#define RELOCATION_32BIT_BIT 0x40 +#define RELOCATION_TYPE_BITS 0x30 +#define RELOCATION_TYPE_ABS 0x00 +#define RELOCATION_TYPE_REL 0x10 +#define RELOCATION_TYPE_UND 0x20 +#define RELOCATION_TYPE_COM 0x30 +#define RELOCATION_SECT_BITS 0x0f + +typedef struct oasys_section_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte value[4]; + bfd_byte vma[4]; + bfd_byte fill[3]; + } +oasys_section_record_type; + +typedef struct oasys_end_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte entry[4]; + bfd_byte fill[2]; + bfd_byte zero; + } +oasys_end_record_type; + +typedef union oasys_record_union + { + oasys_record_header_type header; + oasys_data_record_type data; + oasys_section_record_type section; + oasys_symbol_record_type symbol; + oasys_header_record_type first; + oasys_end_record_type end; + bfd_byte pad[256]; + } +oasys_record_union_type; diff --git a/include/objalloc.h b/include/objalloc.h new file mode 100644 index 000000000..c7106478d --- /dev/null +++ b/include/objalloc.h @@ -0,0 +1,115 @@ +/* objalloc.h -- routines to allocate memory for objects + Copyright 1997, 2001 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Solutions. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef OBJALLOC_H +#define OBJALLOC_H + +#include "ansidecl.h" + +/* These routines allocate space for an object. The assumption is + that the object will want to allocate space as it goes along, but + will never want to free any particular block. There is a function + to free a block, which also frees all more recently allocated + blocks. There is also a function to free all the allocated space. + + This is essentially a specialization of obstacks. The main + difference is that a block may not be allocated a bit at a time. + Another difference is that these routines are always built on top + of malloc, and always pass an malloc failure back to the caller, + unlike more recent versions of obstacks. */ + +/* This is what an objalloc structure looks like. Callers should not + refer to these fields, nor should they allocate these structure + themselves. Instead, they should only create them via + objalloc_init, and only access them via the functions and macros + listed below. The structure is only defined here so that we can + access it via macros. */ + +struct objalloc +{ + char *current_ptr; + unsigned int current_space; + PTR chunks; +}; + +/* Work out the required alignment. */ + +struct objalloc_align { char x; double d; }; + +#if defined (__STDC__) && __STDC__ +#ifndef offsetof +#include <stddef.h> +#endif +#endif +#ifndef offsetof +#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER) +#endif +#define OBJALLOC_ALIGN offsetof (struct objalloc_align, d) + +/* Create an objalloc structure. Returns NULL if malloc fails. */ + +extern struct objalloc *objalloc_create PARAMS ((void)); + +/* Allocate space from an objalloc structure. Returns NULL if malloc + fails. */ + +extern PTR _objalloc_alloc PARAMS ((struct objalloc *, unsigned long)); + +/* The macro version of objalloc_alloc. We only define this if using + gcc, because otherwise we would have to evaluate the arguments + multiple times, or use a temporary field as obstack.h does. */ + +#if defined (__GNUC__) && defined (__STDC__) && __STDC__ + +/* NextStep 2.0 cc is really gcc 1.93 but it defines __GNUC__ = 2 and + does not implement __extension__. But that compiler doesn't define + __GNUC_MINOR__. */ +#if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__) +#define __extension__ +#endif + +#define objalloc_alloc(o, l) \ + __extension__ \ + ({ struct objalloc *__o = (o); \ + unsigned long __len = (l); \ + if (__len == 0) \ + __len = 1; \ + __len = (__len + OBJALLOC_ALIGN - 1) &~ (OBJALLOC_ALIGN - 1); \ + (__len <= __o->current_space \ + ? (__o->current_ptr += __len, \ + __o->current_space -= __len, \ + (PTR) (__o->current_ptr - __len)) \ + : _objalloc_alloc (__o, __len)); }) + +#else /* ! __GNUC__ */ + +#define objalloc_alloc(o, l) _objalloc_alloc ((o), (l)) + +#endif /* ! __GNUC__ */ + +/* Free an entire objalloc structure. */ + +extern void objalloc_free PARAMS ((struct objalloc *)); + +/* Free a block allocated by objalloc_alloc. This also frees all more + recently allocated blocks. */ + +extern void objalloc_free_block PARAMS ((struct objalloc *, PTR)); + +#endif /* OBJALLOC_H */ diff --git a/include/obstack.h b/include/obstack.h new file mode 100644 index 000000000..007853e80 --- /dev/null +++ b/include/obstack.h @@ -0,0 +1,611 @@ +/* obstack.h - object stack macros + Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998, + 1999, 2000 + Free Software Foundation, Inc. + + + NOTE: The canonical source of this file is maintained with the GNU C Library. + Bugs can be reported to bug-glibc@gnu.org. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ + +/* Summary: + +All the apparent functions defined here are macros. The idea +is that you would use these pre-tested macros to solve a +very specific set of problems, and they would run fast. +Caution: no side-effects in arguments please!! They may be +evaluated MANY times!! + +These macros operate a stack of objects. Each object starts life +small, and may grow to maturity. (Consider building a word syllable +by syllable.) An object can move while it is growing. Once it has +been "finished" it never changes address again. So the "top of the +stack" is typically an immature growing object, while the rest of the +stack is of mature, fixed size and fixed address objects. + +These routines grab large chunks of memory, using a function you +supply, called `obstack_chunk_alloc'. On occasion, they free chunks, +by calling `obstack_chunk_free'. You must define them and declare +them before using any obstack macros. + +Each independent stack is represented by a `struct obstack'. +Each of the obstack macros expects a pointer to such a structure +as the first argument. + +One motivation for this package is the problem of growing char strings +in symbol tables. Unless you are "fascist pig with a read-only mind" +--Gosper's immortal quote from HAKMEM item 154, out of context--you +would not like to put any arbitrary upper limit on the length of your +symbols. + +In practice this often means you will build many short symbols and a +few long symbols. At the time you are reading a symbol you don't know +how long it is. One traditional method is to read a symbol into a +buffer, realloc()ating the buffer every time you try to read a symbol +that is longer than the buffer. This is beaut, but you still will +want to copy the symbol from the buffer to a more permanent +symbol-table entry say about half the time. + +With obstacks, you can work differently. Use one obstack for all symbol +names. As you read a symbol, grow the name in the obstack gradually. +When the name is complete, finalize it. Then, if the symbol exists already, +free the newly read name. + +The way we do this is to take a large chunk, allocating memory from +low addresses. When you want to build a symbol in the chunk you just +add chars above the current "high water mark" in the chunk. When you +have finished adding chars, because you got to the end of the symbol, +you know how long the chars are, and you can create a new object. +Mostly the chars will not burst over the highest address of the chunk, +because you would typically expect a chunk to be (say) 100 times as +long as an average object. + +In case that isn't clear, when we have enough chars to make up +the object, THEY ARE ALREADY CONTIGUOUS IN THE CHUNK (guaranteed) +so we just point to it where it lies. No moving of chars is +needed and this is the second win: potentially long strings need +never be explicitly shuffled. Once an object is formed, it does not +change its address during its lifetime. + +When the chars burst over a chunk boundary, we allocate a larger +chunk, and then copy the partly formed object from the end of the old +chunk to the beginning of the new larger chunk. We then carry on +accreting characters to the end of the object as we normally would. + +A special macro is provided to add a single char at a time to a +growing object. This allows the use of register variables, which +break the ordinary 'growth' macro. + +Summary: + We allocate large chunks. + We carve out one object at a time from the current chunk. + Once carved, an object never moves. + We are free to append data of any size to the currently + growing object. + Exactly one object is growing in an obstack at any one time. + You can run one obstack per control block. + You may have as many control blocks as you dare. + Because of the way we do it, you can `unwind' an obstack + back to a previous state. (You may remove objects much + as you would with a stack.) +*/ + + +/* Don't do the contents of this file more than once. */ + +#ifndef _OBSTACK_H +#define _OBSTACK_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* We use subtraction of (char *) 0 instead of casting to int + because on word-addressable machines a simple cast to int + may ignore the byte-within-word field of the pointer. */ + +#ifndef __PTR_TO_INT +# define __PTR_TO_INT(P) ((P) - (char *) 0) +#endif + +#ifndef __INT_TO_PTR +# define __INT_TO_PTR(P) ((P) + (char *) 0) +#endif + +/* We need the type of the resulting object. If __PTRDIFF_TYPE__ is + defined, as with GNU C, use that; that way we don't pollute the + namespace with <stddef.h>'s symbols. Otherwise, if <stddef.h> is + available, include it and use ptrdiff_t. In traditional C, long is + the best that we can do. */ + +#ifdef __PTRDIFF_TYPE__ +# define PTR_INT_TYPE __PTRDIFF_TYPE__ +#else +# ifdef HAVE_STDDEF_H +# include <stddef.h> +# define PTR_INT_TYPE ptrdiff_t +# else +# define PTR_INT_TYPE long +# endif +#endif + +#if defined _LIBC || defined HAVE_STRING_H +# include <string.h> +# if defined __STDC__ && __STDC__ +# define _obstack_memcpy(To, From, N) memcpy ((To), (From), (N)) +# else +# define _obstack_memcpy(To, From, N) memcpy ((To), (char *)(From), (N)) +# endif +#else +# ifdef memcpy +# define _obstack_memcpy(To, From, N) memcpy ((To), (char *)(From), (N)) +# else +# define _obstack_memcpy(To, From, N) bcopy ((char *)(From), (To), (N)) +# endif +#endif + +struct _obstack_chunk /* Lives at front of each chunk. */ +{ + char *limit; /* 1 past end of this chunk */ + struct _obstack_chunk *prev; /* address of prior chunk or NULL */ + char contents[4]; /* objects begin here */ +}; + +struct obstack /* control current object in current chunk */ +{ + long chunk_size; /* preferred size to allocate chunks in */ + struct _obstack_chunk *chunk; /* address of current struct obstack_chunk */ + char *object_base; /* address of object we are building */ + char *next_free; /* where to add next char to current object */ + char *chunk_limit; /* address of char after current chunk */ + PTR_INT_TYPE temp; /* Temporary for some macros. */ + int alignment_mask; /* Mask of alignment for each object. */ +#if defined __STDC__ && __STDC__ + /* These prototypes vary based on `use_extra_arg', and we use + casts to the prototypeless function type in all assignments, + but having prototypes here quiets -Wstrict-prototypes. */ + struct _obstack_chunk *(*chunkfun) (void *, long); + void (*freefun) (void *, struct _obstack_chunk *); + void *extra_arg; /* first arg for chunk alloc/dealloc funcs */ +#else + struct _obstack_chunk *(*chunkfun) (); /* User's fcn to allocate a chunk. */ + void (*freefun) (); /* User's function to free a chunk. */ + char *extra_arg; /* first arg for chunk alloc/dealloc funcs */ +#endif + unsigned use_extra_arg:1; /* chunk alloc/dealloc funcs take extra arg */ + unsigned maybe_empty_object:1;/* There is a possibility that the current + chunk contains a zero-length object. This + prevents freeing the chunk if we allocate + a bigger chunk to replace it. */ + unsigned alloc_failed:1; /* No longer used, as we now call the failed + handler on error, but retained for binary + compatibility. */ +}; + +/* Declare the external functions we use; they are in obstack.c. */ + +#if defined __STDC__ && __STDC__ +extern void _obstack_newchunk (struct obstack *, int); +extern void _obstack_free (struct obstack *, void *); +extern int _obstack_begin (struct obstack *, int, int, + void *(*) (long), void (*) (void *)); +extern int _obstack_begin_1 (struct obstack *, int, int, + void *(*) (void *, long), + void (*) (void *, void *), void *); +extern int _obstack_memory_used (struct obstack *); +#else +extern void _obstack_newchunk (); +extern void _obstack_free (); +extern int _obstack_begin (); +extern int _obstack_begin_1 (); +extern int _obstack_memory_used (); +#endif + +#if defined __STDC__ && __STDC__ + +/* Do the function-declarations after the structs + but before defining the macros. */ + +void obstack_init (struct obstack *obstack); + +void * obstack_alloc (struct obstack *obstack, int size); + +void * obstack_copy (struct obstack *obstack, void *address, int size); +void * obstack_copy0 (struct obstack *obstack, void *address, int size); + +void obstack_free (struct obstack *obstack, void *block); + +void obstack_blank (struct obstack *obstack, int size); + +void obstack_grow (struct obstack *obstack, void *data, int size); +void obstack_grow0 (struct obstack *obstack, void *data, int size); + +void obstack_1grow (struct obstack *obstack, int data_char); +void obstack_ptr_grow (struct obstack *obstack, void *data); +void obstack_int_grow (struct obstack *obstack, int data); + +void * obstack_finish (struct obstack *obstack); + +int obstack_object_size (struct obstack *obstack); + +int obstack_room (struct obstack *obstack); +void obstack_make_room (struct obstack *obstack, int size); +void obstack_1grow_fast (struct obstack *obstack, int data_char); +void obstack_ptr_grow_fast (struct obstack *obstack, void *data); +void obstack_int_grow_fast (struct obstack *obstack, int data); +void obstack_blank_fast (struct obstack *obstack, int size); + +void * obstack_base (struct obstack *obstack); +void * obstack_next_free (struct obstack *obstack); +int obstack_alignment_mask (struct obstack *obstack); +int obstack_chunk_size (struct obstack *obstack); +int obstack_memory_used (struct obstack *obstack); + +#endif /* __STDC__ */ + +/* Non-ANSI C cannot really support alternative functions for these macros, + so we do not declare them. */ + +/* Error handler called when `obstack_chunk_alloc' failed to allocate + more memory. This can be set to a user defined function. The + default action is to print a message and abort. */ +#if defined __STDC__ && __STDC__ +extern void (*obstack_alloc_failed_handler) (void); +#else +extern void (*obstack_alloc_failed_handler) (); +#endif + +/* Exit value used when `print_and_abort' is used. */ +extern int obstack_exit_failure; + +/* Pointer to beginning of object being allocated or to be allocated next. + Note that this might not be the final address of the object + because a new chunk might be needed to hold the final size. */ + +#define obstack_base(h) ((h)->object_base) + +/* Size for allocating ordinary chunks. */ + +#define obstack_chunk_size(h) ((h)->chunk_size) + +/* Pointer to next byte not yet allocated in current chunk. */ + +#define obstack_next_free(h) ((h)->next_free) + +/* Mask specifying low bits that should be clear in address of an object. */ + +#define obstack_alignment_mask(h) ((h)->alignment_mask) + +/* To prevent prototype warnings provide complete argument list in + standard C version. */ +#if defined __STDC__ && __STDC__ + +# define obstack_init(h) \ + _obstack_begin ((h), 0, 0, \ + (void *(*) (long)) obstack_chunk_alloc, (void (*) (void *)) obstack_chunk_free) + +# define obstack_begin(h, size) \ + _obstack_begin ((h), (size), 0, \ + (void *(*) (long)) obstack_chunk_alloc, (void (*) (void *)) obstack_chunk_free) + +# define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \ + _obstack_begin ((h), (size), (alignment), \ + (void *(*) (long)) (chunkfun), (void (*) (void *)) (freefun)) + +# define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \ + _obstack_begin_1 ((h), (size), (alignment), \ + (void *(*) (void *, long)) (chunkfun), \ + (void (*) (void *, void *)) (freefun), (arg)) + +# define obstack_chunkfun(h, newchunkfun) \ + ((h) -> chunkfun = (struct _obstack_chunk *(*)(void *, long)) (newchunkfun)) + +# define obstack_freefun(h, newfreefun) \ + ((h) -> freefun = (void (*)(void *, struct _obstack_chunk *)) (newfreefun)) + +#else + +# define obstack_init(h) \ + _obstack_begin ((h), 0, 0, \ + (void *(*) ()) obstack_chunk_alloc, (void (*) ()) obstack_chunk_free) + +# define obstack_begin(h, size) \ + _obstack_begin ((h), (size), 0, \ + (void *(*) ()) obstack_chunk_alloc, (void (*) ()) obstack_chunk_free) + +# define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \ + _obstack_begin ((h), (size), (alignment), \ + (void *(*) ()) (chunkfun), (void (*) ()) (freefun)) + +# define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \ + _obstack_begin_1 ((h), (size), (alignment), \ + (void *(*) ()) (chunkfun), (void (*) ()) (freefun), (arg)) + +# define obstack_chunkfun(h, newchunkfun) \ + ((h) -> chunkfun = (struct _obstack_chunk *(*)()) (newchunkfun)) + +# define obstack_freefun(h, newfreefun) \ + ((h) -> freefun = (void (*)()) (newfreefun)) + +#endif + +#define obstack_1grow_fast(h,achar) (*((h)->next_free)++ = (achar)) + +#define obstack_blank_fast(h,n) ((h)->next_free += (n)) + +#define obstack_memory_used(h) _obstack_memory_used (h) + +#if defined __GNUC__ && defined __STDC__ && __STDC__ +/* NextStep 2.0 cc is really gcc 1.93 but it defines __GNUC__ = 2 and + does not implement __extension__. But that compiler doesn't define + __GNUC_MINOR__. */ +# if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__) +# define __extension__ +# endif + +/* For GNU C, if not -traditional, + we can define these macros to compute all args only once + without using a global variable. + Also, we can avoid using the `temp' slot, to make faster code. */ + +# define obstack_object_size(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (unsigned) (__o->next_free - __o->object_base); }) + +# define obstack_room(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (unsigned) (__o->chunk_limit - __o->next_free); }) + +# define obstack_make_room(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->chunk_limit - __o->next_free < __len) \ + _obstack_newchunk (__o, __len); \ + (void) 0; }) + +# define obstack_empty_p(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (__o->chunk->prev == 0 && __o->next_free - __o->chunk->contents == 0); }) + +# define obstack_grow(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->next_free + __len > __o->chunk_limit) \ + _obstack_newchunk (__o, __len); \ + _obstack_memcpy (__o->next_free, (where), __len); \ + __o->next_free += __len; \ + (void) 0; }) + +# define obstack_grow0(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->next_free + __len + 1 > __o->chunk_limit) \ + _obstack_newchunk (__o, __len + 1); \ + _obstack_memcpy (__o->next_free, (where), __len); \ + __o->next_free += __len; \ + *(__o->next_free)++ = 0; \ + (void) 0; }) + +# define obstack_1grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + if (__o->next_free + 1 > __o->chunk_limit) \ + _obstack_newchunk (__o, 1); \ + obstack_1grow_fast (__o, datum); \ + (void) 0; }) + +/* These assume that the obstack alignment is good enough for pointers or ints, + and that the data added so far to the current object + shares that much alignment. */ + +# define obstack_ptr_grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + if (__o->next_free + sizeof (void *) > __o->chunk_limit) \ + _obstack_newchunk (__o, sizeof (void *)); \ + obstack_ptr_grow_fast (__o, datum); }) + +# define obstack_int_grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + if (__o->next_free + sizeof (int) > __o->chunk_limit) \ + _obstack_newchunk (__o, sizeof (int)); \ + obstack_int_grow_fast (__o, datum); }) + +# define obstack_ptr_grow_fast(OBSTACK,aptr) \ +__extension__ \ +({ struct obstack *__o1 = (OBSTACK); \ + *(const void **) __o1->next_free = (aptr); \ + __o1->next_free += sizeof (const void *); \ + (void) 0; }) + +# define obstack_int_grow_fast(OBSTACK,aint) \ +__extension__ \ +({ struct obstack *__o1 = (OBSTACK); \ + *(int *) __o1->next_free = (aint); \ + __o1->next_free += sizeof (int); \ + (void) 0; }) + +# define obstack_blank(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->chunk_limit - __o->next_free < __len) \ + _obstack_newchunk (__o, __len); \ + obstack_blank_fast (__o, __len); \ + (void) 0; }) + +# define obstack_alloc(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_blank (__h, (length)); \ + obstack_finish (__h); }) + +# define obstack_copy(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_grow (__h, (where), (length)); \ + obstack_finish (__h); }) + +# define obstack_copy0(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_grow0 (__h, (where), (length)); \ + obstack_finish (__h); }) + +/* The local variable is named __o1 to avoid a name conflict + when obstack_blank is called. */ +# define obstack_finish(OBSTACK) \ +__extension__ \ +({ struct obstack *__o1 = (OBSTACK); \ + void *value; \ + value = (void *) __o1->object_base; \ + if (__o1->next_free == value) \ + __o1->maybe_empty_object = 1; \ + __o1->next_free \ + = __INT_TO_PTR ((__PTR_TO_INT (__o1->next_free)+__o1->alignment_mask)\ + & ~ (__o1->alignment_mask)); \ + if (__o1->next_free - (char *)__o1->chunk \ + > __o1->chunk_limit - (char *)__o1->chunk) \ + __o1->next_free = __o1->chunk_limit; \ + __o1->object_base = __o1->next_free; \ + value; }) + +# define obstack_free(OBSTACK, OBJ) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + void *__obj = (void *) (OBJ); \ + if (__obj > (void *)__o->chunk && __obj < (void *)__o->chunk_limit) \ + __o->next_free = __o->object_base = (char *) __obj; \ + else (obstack_free) (__o, __obj); }) + +#else /* not __GNUC__ or not __STDC__ */ + +# define obstack_object_size(h) \ + (unsigned) ((h)->next_free - (h)->object_base) + +# define obstack_room(h) \ + (unsigned) ((h)->chunk_limit - (h)->next_free) + +# define obstack_empty_p(h) \ + ((h)->chunk->prev == 0 && (h)->next_free - (h)->chunk->contents == 0) + +/* Note that the call to _obstack_newchunk is enclosed in (..., 0) + so that we can avoid having void expressions + in the arms of the conditional expression. + Casting the third operand to void was tried before, + but some compilers won't accept it. */ + +# define obstack_make_room(h,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0)) + +# define obstack_grow(h,where,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0), \ + _obstack_memcpy ((h)->next_free, (where), (h)->temp), \ + (h)->next_free += (h)->temp) + +# define obstack_grow0(h,where,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp + 1 > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp + 1), 0) : 0), \ + _obstack_memcpy ((h)->next_free, (where), (h)->temp), \ + (h)->next_free += (h)->temp, \ + *((h)->next_free)++ = 0) + +# define obstack_1grow(h,datum) \ +( (((h)->next_free + 1 > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), 1), 0) : 0), \ + obstack_1grow_fast (h, datum)) + +# define obstack_ptr_grow(h,datum) \ +( (((h)->next_free + sizeof (char *) > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), sizeof (char *)), 0) : 0), \ + obstack_ptr_grow_fast (h, datum)) + +# define obstack_int_grow(h,datum) \ +( (((h)->next_free + sizeof (int) > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), sizeof (int)), 0) : 0), \ + obstack_int_grow_fast (h, datum)) + +# define obstack_ptr_grow_fast(h,aptr) \ + (((const void **) ((h)->next_free += sizeof (void *)))[-1] = (aptr)) + +# define obstack_int_grow_fast(h,aint) \ + (((int *) ((h)->next_free += sizeof (int)))[-1] = (aptr)) + +# define obstack_blank(h,length) \ +( (h)->temp = (length), \ + (((h)->chunk_limit - (h)->next_free < (h)->temp) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0), \ + obstack_blank_fast (h, (h)->temp)) + +# define obstack_alloc(h,length) \ + (obstack_blank ((h), (length)), obstack_finish ((h))) + +# define obstack_copy(h,where,length) \ + (obstack_grow ((h), (where), (length)), obstack_finish ((h))) + +# define obstack_copy0(h,where,length) \ + (obstack_grow0 ((h), (where), (length)), obstack_finish ((h))) + +# define obstack_finish(h) \ +( ((h)->next_free == (h)->object_base \ + ? (((h)->maybe_empty_object = 1), 0) \ + : 0), \ + (h)->temp = __PTR_TO_INT ((h)->object_base), \ + (h)->next_free \ + = __INT_TO_PTR ((__PTR_TO_INT ((h)->next_free)+(h)->alignment_mask) \ + & ~ ((h)->alignment_mask)), \ + (((h)->next_free - (char *) (h)->chunk \ + > (h)->chunk_limit - (char *) (h)->chunk) \ + ? ((h)->next_free = (h)->chunk_limit) : 0), \ + (h)->object_base = (h)->next_free, \ + __INT_TO_PTR ((h)->temp)) + +# if defined __STDC__ && __STDC__ +# define obstack_free(h,obj) \ +( (h)->temp = (char *) (obj) - (char *) (h)->chunk, \ + (((h)->temp > 0 && (h)->temp < (h)->chunk_limit - (char *) (h)->chunk)\ + ? (int) ((h)->next_free = (h)->object_base \ + = (h)->temp + (char *) (h)->chunk) \ + : (((obstack_free) ((h), (h)->temp + (char *) (h)->chunk), 0), 0))) +# else +# define obstack_free(h,obj) \ +( (h)->temp = (char *) (obj) - (char *) (h)->chunk, \ + (((h)->temp > 0 && (h)->temp < (h)->chunk_limit - (char *) (h)->chunk)\ + ? (int) ((h)->next_free = (h)->object_base \ + = (h)->temp + (char *) (h)->chunk) \ + : (_obstack_free ((h), (h)->temp + (char *) (h)->chunk), 0))) +# endif + +#endif /* not __GNUC__ or not __STDC__ */ + +#ifdef __cplusplus +} /* C++ */ +#endif + +#endif /* obstack.h */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog new file mode 100644 index 000000000..6d75eee99 --- /dev/null +++ b/include/opcode/ChangeLog @@ -0,0 +1,109 @@ +2004-09-30 Paul Brook <paul@codesourcery.com> + + * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. + (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. + +2004-09-11 Theodore A. Roth <troth@openavr.org> + + * avr.h: Add support for + atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. + +2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> + + * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. + +2004-08-24 Dmitry Diky <diwil@spec.ru> + + * msp430.h (msp430_opc): Add new instructions. + (msp430_rcodes): Declare new instructions. + (msp430_hcodes): Likewise.. + +2004-08-13 Nick Clifton <nickc@redhat.com> + + PR/301 + * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX + processors. + +2004-08-30 Michal Ludvig <mludvig@suse.cz> + + * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. + +2004-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. + +2004-07-21 Jan Beulich <jbeulich@novell.com> + + * i386.h: Adjust instruction descriptions to better match the + specification. + +2004-07-16 Richard Earnshaw <rearnsha@arm.com> + + * arm.h: Remove all old content. Replace with architecture defines + from gas/config/tc-arm.c. + +2004-07-09 Andreas Schwab <schwab@suse.de> + + * m68k.h: Fix comment. + +2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> + + * crx.h: New file. + +2004-06-24 Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. + +2004-05-24 Peter Barada <peter@the-baradas.com> + + * m68k.h: Add 'size' to m68k_opcode. + +2004-05-05 Peter Barada <peter@the-baradas.com> + + * m68k.h: Switch from ColdFire chip name to core variant. + +2004-04-22 Peter Barada <peter@the-baradas.com> + + * m68k.h: Add mcfmac/mcfemac definitions. Update operand + descriptions for new EMAC cases. + Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly + handle Motorola MAC syntax. + Allow disassembly of ColdFire V4e object files. + +2004-03-16 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. + +2004-03-12 Jakub Jelinek <jakub@redhat.com> + + * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. + +2004-03-12 Michal Ludvig <mludvig@suse.cz> + + * i386.h (i386_optab): Added xstore as an alias for xstorerng. + +2004-03-12 Michal Ludvig <mludvig@suse.cz> + + * i386.h (i386_optab): Added xstore/xcrypt insns. + +2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> + + * h8300.h (32bit ldc/stc): Add relaxing support. + +2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> + + * h8300.h (BITOP): Pass MEMRELAX flag. + +2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> + + * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 + except for the H8S. + +For older changes see ChangeLog-9103 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/include/opcode/ChangeLog-9103 b/include/opcode/ChangeLog-9103 new file mode 100644 index 000000000..0cdb1f3be --- /dev/null +++ b/include/opcode/ChangeLog-9103 @@ -0,0 +1,3102 @@ +2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com> + Bernardo Innocenti <bernie@develer.com> + + * m68k.h: Add MCFv4/MCF5528x support. + +2003-10-19 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix.h (JMP_INSN_BYTE): Define. + +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Document +E, +F, +G, +H, and +I operand types. + Update documentation of I, +B and +C operand types. + (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. + (M_DEXT, M_DINS): New enum values. + +2003-09-04 Nick Clifton <nickc@redhat.com> + + * v850.h (PROCESSOR_V850E1): Define. + +2003-08-19 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other + PPC_OPCODE_* defines. + +2003-08-16 Jason Eckhardt <jle@rice.edu> + + * i860.h (fmov.ds): Expand as famov.ds. + (fmov.sd): Expand as famov.sd. + (pfmov.ds): Expand as pfamov.ds. + +2003-08-07 Michael Meissner <gnu@the-meissners.org> + + * cgen.h: Remove PARAM macro usage in all prototypes. + (CGEN_EXTRACT_INFO): Use void * instead of PTR. + (cgen_print_fn): Ditto. + (CGEN_HW_ENTRY): Ditto. + (CGEN_MAYBE_MULTI_IFLD): Ditto. + (struct cgen_insn): Ditto. + (CGEN_CPU_TABLE): Ditto. + +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * alpha.h: Remove PARAMS macro. + * arc.h: Likewise. + * d10v.h: Likewise. + * d30v.h: Likewise. + * i370.h: Likewise. + * or32.h: Likewise. + * pj.h: Likewise. + * ppc.h: Likewise. + * sparc.h: Likewise. + * tic80.h: Likewise. + * v850.h: Likewise. + +2003-07-18 Michael Snyder <msnyder@redhat.com> + + * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting. + +2003-07-15 Richard Sandiford <rsandifo@redhat.com> + + * mips.h (CPU_RM7000): New macro. + (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns. + +2003-07-09 Alexandre Oliva <aoliva@redhat.com> + + 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> + * mn10300.h (AM33_2): Renamed from AM33. + 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> + * mn10300.h (AM332, FMT_D3): Defined. + (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise. + (MN10300_OPERAND_FPCR): Likewise. + +2003-07-01 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990. + +2003-06-25 Richard Sandiford <rsandifo@redhat.com> + + * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. + (IMM8U, IMM8U_NS): Define. + (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. + +2003-06-25 Richard Sandiford <rsandifo@redhat.com> + + * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and + mov.l ERs,@(dd:32,ERd) entries. + +2003-06-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Support Intel Precott New Instructions. + +2003-06-10 Gary Hade <garyhade@us.ibm.com> + + * ppc.h (PPC_OPERAND_DQ): Define. + +2003-06-10 Richard Sandiford <rsandifo@redhat.com> + + * h8300.h (IMM4_NS, IMM8_NS): New. + (h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries. + Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l. + +2003-06-03 Michael Snyder <msnyder@redhat.com> + + * h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H. + (ldc): Split ccr ops from exr ops (which are only available + on H8S or H8SX). + (stc): Ditto. + (andc, orc, xorc): Ditto. + (ldmac, stmac, clrmac, mac): Change access to AV_H8S. + +2003-06-03 Michael Snyder <msnyder@redhat.com> + and Bernd Schmidt <bernds@redhat.com> + and Alexandre Oliva <aoliva@redhat.com> + * h8300.h: Add support for h8300sx instruction set. + +2003-05-23 Jason Eckhardt <jle@rice.edu> + + * i860.h (expand_type): Add XP_ONLY. + (scyc.b): New XP instruction. + (ldio.l): Likewise. + (ldio.s): Likewise. + (ldio.b): Likewise. + (ldint.l): Likewise. + (ldint.s): Likewise. + (ldint.b): Likewise. + (stio.l): Likewise. + (stio.s): Likewise. + (stio.b): Likewise. + (pfld.q): Likewise. + +2003-05-20 Jason Eckhardt <jle@rice.edu> + + * i860.h (flush): Set lower 3 bits properly and use 'L' + for the immediate operand type instead of 'i'. + +2003-05-20 Jason Eckhardt <jle@rice.edu> + + * i860.h (fzchks): Both S and R bits must be set. + (pfzchks): Likewise. + (faddp): Likewise. + (pfaddp): Likewise. + (fix.ss): Remove (invalid instruction). + (pfix.ss): Likewise. + (ftrunc.ss): Likewise. + (pftrunc.ss): Likewise. + +2003-05-18 Jason Eckhardt <jle@rice.edu> + + * i860.h (form, pform): Add missing .dd suffix. + +2003-05-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000 + +2003-04-07 Michael Snyder <msnyder@redhat.com> + + * h8300.h (ldc/stc): Fix up src/dst swaps. + +2003-04-09 J. Grant <jg-binutils@jguk.org> + + * mips.h: Correct comment typo. + +2003-03-21 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val. + (S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH. + (s390_opcode): Remove architecture. Add modes and min_cpu. + +2003-03-17 D.Venkatasubramanian <dvenkat@noida.hcltech.com> + + * h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line + processing. + +2003-02-21 Noida D.Venkatasubramanian <dvenkat@noida.hcltech.com> + + * h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32. + +2003-01-23 Alan Modra <amodra@bigpond.net.au> + + * m68hc11.h (cpu6812s): Define. + +2003-01-07 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Fix missing space in comment. + (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5) + (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right + by four bits. + +2003-01-02 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Update copyright years to include 2002 (which had + been missed previously) and 2003. Make comments about "+A", + "+B", and "+C" operand types more descriptive. + +2002-12-31 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Note that the "+D" operand type name is now used. + +2002-12-30 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Document "+" as the start of two-character operand + type names, and add new "K", "+A", "+B", and "+C" operand types. + (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB) + (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New + defines. + +2002-12-24 Dmitry Diky <diwil@mail.ru> + + * msp430.h: New file. Defines msp430 opcodes. + +2002-12-30 D.Venkatasubramanian <dvenkat@noida.hcltech.com> + + * h8300.h: Added some more pseudo opcodes for system call + processing. + +2002-12-19 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3) + (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2) + (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1) + (OP_OP_SDC2, OP_OP_SDC3): Define. + +2002-12-16 Alan Modra <amodra@bigpond.net.au> + + * hppa.h (completer_chars): #if 0 out. + + * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and + "default_args". + (struct not_wot): Constify "args". + (struct not): Constify "name". + (numopcodes): Delete. + (endop): Delete. + +2002-12-13 Alan Modra <amodra@bigpond.net.au> + + * pj.h (pj_opc_info_t): Add union. + +2002-12-04 David Mosberger <davidm@hpl.hp.com> + + * ia64.h: Fix copyright message. + (IA64_OPND_AR_CSD): New operand kind. + +2002-12-03 Richard Henderson <rth@redhat.com> + + * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV. + +2002-12-03 Alan Modra <amodra@bigpond.net.au> + + * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union. + Constify "leaf" and "multi". + +2002-11-19 Klee Dienes <kdienes@apple.com> + + * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size' + fields. + (h8_opcodes). Modify initializer and initializer macros to no + longer initialize the removed fields. + +2002-11-19 Svein E. Seldal <Svein.Seldal@solidas.com> + + * tic4x.h (c4x_insts): Fixed LDHI constraint + +2002-11-18 Klee Dienes <kdienes@apple.com> + + * h8300.h (h8_opcode): Remove 'length' field. + (h8_opcodes): Mark as 'const' (both the declaration and + definition). Modify initializer and initializer macros to no + longer initialize the length field. + +2002-11-18 Klee Dienes <kdienes@apple.com> + + * arc.h (arc_ext_opcodes): Declare as extern. + (arc_ext_operands): Declare as extern. + * i860.h (i860_opcodes): Declare as const. + +2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> + + * tic4x.h: File reordering. Added enhanced opcodes. + +2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com> + + * tic4x.h: Major rewrite of entire file. Define instruction + classes, and put each instruction into a class. + +2002-11-11 Svein E. Seldal <Svein.Seldal@solidas.com> + + * tic4x.h: Added new opcodes and corrected some bugs. Add support + for new DSP types. + +2002-10-14 Alan Modra <amodra@bigpond.net.au> + + * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE. + +2002-09-30 Gavin Romig-Koch <gavin@redhat.com> + Ken Raeburn <raeburn@cygnus.com> + Aldy Hernandez <aldyh@redhat.com> + Eric Christopher <echristo@redhat.com> + Richard Sandiford <rsandifo@redhat.com> + + * mips.h: Update comment for new opcodes. + (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. + (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. + (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. + (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. + (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. + Don't match CPU_R4111 with INSN_4100. + +2002-08-19 Elena Zannoni <ezannoni@redhat.com> + + From matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500 + instructions. + (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR, + PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the + e500x2 Integer select, branch locking, performance monitor, + cache locking and machine check APUs, respectively. + (PPC_OPCODE_EFS): New opcode type for efs* instructions. + (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions. + +2002-08-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11.h (M6812_OP_PAGE): Define to identify call operand. + (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE, + M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12 + memory banks. + (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value. + +2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (INSN_MIPS16): New define. + +2002-07-08 Alan Modra <amodra@bigpond.net.au> + + * i386.h: Remove IgnoreSize from movsx and movzx. + +2002-06-08 Alan Modra <amodra@bigpond.net.au> + + * a29k.h: Replace CONST with const. + (CONST): Don't define. + * convex.h: Replace CONST with const. + (CONST): Don't define. + * dlx.h: Replace CONST with const. + * or32.h (CONST): Don't define. + +2002-05-30 Chris G. Demetriou <cgd@broadcom.com> + + * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) + (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) + (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) + (INSN_MDMX): New constants, for MDMX support. + (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. + +2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> + + * dlx.h: New file. + +2002-05-25 Alan Modra <amodra@bigpond.net.au> + + * ia64.h: Use #include "" instead of <> for local header files. + * sparc.h: Likewise. + +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases. + +2002-05-17 Andrey Volkov <avolkov@sources.redhat.com> + + * h8300.h: Corrected defs of all control regs + and eepmov instr. + +2002-04-11 Alan Modra <amodra@bigpond.net.au> + + * i386.h: Add intel mode cmpsd and movsd. + Put them before SSE2 insns, so that rep prefix works. + +2002-03-15 Chris G. Demetriou <cgd@broadcom.com> + + * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D + instructions. + (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks + may be passed along with the ISA bitmask. + +2002-03-05 Paul Koning <pkoning@equallogic.com> + + * pdp11.h: Add format codes for float instruction formats. + +2002-02-25 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define. + +Mon Feb 18 17:31:48 CET 2002 Jan Hubicka <jh@suse.cz> + + * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. + +Mon Feb 11 12:53:19 CET 2002 Jan Hubicka <jh@suse.cz> + + * i386.h (push,pop): Allow 16bit operands in 64bit mode. + (xchg): Fix. + (in, out): Disable 64bit operands. + (call, jmp): Avoid REX prefixes. + (jcxz): Prohibit in 64bit mode + (jrcxz, loop): Add 64bit variants. + (movq): Fix patterns. + (movmskps, pextrw, pinstrw): Add 64bit variants. + +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * or32.h: New file. + +2002-01-22 Graydon Hoare <graydon@redhat.com> + + * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. + (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. + +2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at> + + * h8300.h: Comment typo fix. + +2002-01-03 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. + (PPC_OPCODE_BOOKE64): Likewise. + +Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) + + * hppa.h (call, ret): Move to end of table. + (addb, addib): PA2.0 variants should have been PA2.0W. + (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler + happy. + (fldw, fldd, fstw, fstd, bb): Likewise. + (short loads/stores): Tweak format specifier slightly to keep + disassembler happy. + (indexed loads/stores): Likewise. + (absolute loads/stores): Likewise. + +2001-12-04 Alexandre Oliva <aoliva@redhat.com> + + * d10v.h (OPERAND_NOSP): New macro. + +2001-11-29 Alexandre Oliva <aoliva@redhat.com> + + * d10v.h (OPERAND_SP): New macro. + +2001-11-15 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * tic54x.h: Revise opcode layout; don't really need a separate + structure for parallel opcodes. + +2001-11-13 Zack Weinberg <zack@codesourcery.com> + Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to + accept WordReg. + +2001-11-04 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OPCODE_IS_MEMBER): Remove extra space. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix.h: New file. + +2001-10-18 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end + of the expression, to make source code merging easier. + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Sort coprocessor instruction argument characters + in comment, add a few more words of description for "H". + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h (INSN_SB1): New cpu-specific instruction bit. + (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 + if cpu is CPU_SB1. + +2001-10-17 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. + +2001-10-12 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New + opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 + instructions, respectively. + +2001-09-27 Nick Clifton <nickc@cambridge.redhat.com> + + * v850.h: Remove spurious comment. + +2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> + + * h8300.h: Fix compile time warning messages + +2001-09-04 Richard Henderson <rth@redhat.com> + + * alpha.h (struct alpha_operand): Pack elements into bitfields. + +2001-08-31 Eric Christopher <echristo@redhat.com> + + * mips.h: Remove CPU_MIPS32_4K. + +2001-08-27 Torbjorn Granlund <tege@swox.com> + + * ppc.h (PPC_OPERAND_DS): Define. + +2001-08-25 Andreas Jaeger <aj@suse.de> + + * d30v.h: Fix declaration of reg_name_cnt. + + * d10v.h: Fix declaration of d10v_reg_name_cnt. + + * arc.h: Add prototypes from opcodes/arc-opc.c. + +2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (INSN_10000): Define. + (OPCODE_IS_MEMBER): Check for INSN_10000. + +2001-08-10 Alan Modra <amodra@one.net.au> + + * ppc.h: Revert 2001-08-08. + +2001-08-10 Richard Sandiford <rsandifo@redhat.com> + + * mips.h (INSN_GP32): Remove. + (OPCODE_IS_MEMBER): Remove gp32 parameter. + (M_MOVE): New macro identifier. + +2001-08-08 Alan Modra <amodra@one.net.au> + + 1999-10-25 Torbjorn Granlund <tege@swox.com> + * ppc.h (struct powerpc_operand): New field `reloc'. + +2001-08-01 Aldy Hernandez <aldyh@redhat.com> + + * mips.h (INSN_ISA_MASK): Nuke bits 12-15. + +2001-07-12 Jeff Johnston <jjohnstn@redhat.com> + + * cgen.h (CGEN_INSN): Add regex support. + (build_insn_regex): Declare. + +2001-07-11 Frank Ch. Eigler <fche@redhat.com> + + * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. + (cgen_cpu_desc): Ditto. + +2001-07-07 Ben Elliston <bje@redhat.com> + + * m88k.h: Clean up and reformat. Remove unused code. + +2001-06-14 Geoffrey Keating <geoffk@redhat.com> + + * cgen.h (cgen_keyword): Add nonalpha_chars field. + +2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (CPU_R12000): Define. + +2001-05-23 John Healy <jhealy@redhat.com> + + * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48. + +2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (INSN_ISA_MASK): Define. + +2001-05-12 Alan Modra <amodra@one.net.au> + + * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg, + not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq, + and use InvMem as these insns must have register operands. + +2001-05-04 Alan Modra <amodra@one.net.au> + + * i386.h (i386_optab): Move InvMem to first operand of pmovmskb + and pextrw to swap reg/rm assignments. + +2001-04-05 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (enum cris_insn_version_usage): Correct comment for + cris_ver_v3p. + +2001-03-24 Alan Modra <alan@linuxcare.com.au> + + * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". + Add InvMem to first operand of "maskmovdqu". + +2001-03-22 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (ADD_PC_INCR_OPCODE): New macro. + +2001-03-21 Kazu Hirata <kazu@hxi.com> + + * h8300.h: Fix formatting. + +2001-03-22 Alan Modra <alan@linuxcare.com.au> + + * i386.h (i386_optab): Add paddq, psubq. + +2001-03-19 Alan Modra <alan@linuxcare.com.au> + + * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define. + +2001-02-28 Igor Shevlyakov <igor@windriver.com> + + * m68k.h: new defines for Coldfire V4. Update mcf to know + about mcf5407. + +2001-02-18 lars brinkhoff <lars@nocrew.org> + + * pdp11.h: New file. + +2001-02-12 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): SSE integer converison instructions have + 64bit versions on x86-64. + +2001-02-10 Nick Clifton <nickc@redhat.com> + + * mips.h: Remove extraneous whitespace. Formating change to allow + for future contribution. + +2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h: New file. + +2001-02-02 Patrick Macdonald <patrickm@redhat.com> + + * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. + (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. + (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. + +2001-01-24 Karsten Keil <kkeil@suse.de> + + * i386.h (i386_optab): Fix swapgs + +2001-01-14 Alan Modra <alan@linuxcare.com.au> + + * hppa.h: Describe new '<' and '>' operand types, and tidy + existing comments. + (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. + Remove duplicate "ldw j(s,b),x". Sort some entries. + +2001-01-13 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Fix pusha and ret templates. + +2001-01-11 Peter Targett <peter.targett@arccores.com> + + * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New + definitions for masking cpu type. + (arc_ext_operand_value) New structure for storing extended + operands. + (ARC_OPERAND_*) Flags for operand values. + +2001-01-10 Jan Hubicka <jh@suse.cz> + + * i386.h (pinsrw): Add. + (pshufw): Remove. + (cvttpd2dq): Fix operands. + (cvttps2dq): Likewise. + (movq2q): Rename to movdq2q. + +2001-01-10 Richard Schaal <richard.schaal@intel.com> + + * i386.h: Correct movnti instruction. + +2001-01-09 Jeff Johnston <jjohnstn@redhat.com> + + * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number + of operands (unsigned char or unsigned short). + (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. + (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char. + +2001-01-05 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Make [sml]fence template to use immext field. + +2001-01-03 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Fix 64bit pushf template; Add instructions + introduced by Pentium4 + +2000-12-30 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Add "rex*" instructions; + add swapgs; disable jmp/call far direct instructions for + 64bit mode; add syscall and sysret; disable registers for 0xc6 + template. Add 'q' suffixes to extendable instructions, disable + obsolete instructions, add new sign/zero extension ones. + (i386_regtab): Add extended registers. + (*Suf): Add No_qSuf. + (q_Suf, wlq_Suf, bwlq_Suf): New. + +2000-12-20 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Replace "Imm" with "EncImm". + (i386_regtab): Add flags field. + +2000-12-12 Nick Clifton <nickc@redhat.com> + + * mips.h: Fix formatting. + +2000-12-01 Chris Demetriou <cgd@sibyte.com> + + mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete. + (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old + OP_*_SYSCALL definitions. + (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as + 19 bit wait codes. + (MIPS operand specifier comments): Remove 'm', add 'U' and + 'J', and update the meaning of 'B' so that it's more general. + + * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, + INSN_ISA5): Renumber, redefine to mean the ISA at which the + instruction was added. + (INSN_ISA32): New constant. + (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32): + Renumber to avoid new and/or renumbered INSN_* constants. + (INSN_MIPS32): Delete. + (ISA_UNKNOWN): New constant to indicate unknown ISA. + (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, + ISA_MIPS32): New constants, defined to be the mask of INSN_* + constants available at that ISA level. + (CPU_UNKNOWN): New constant to indicate unknown CPU. + (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, + define it with a unique value. + (OPCODE_IS_MEMBER): Update for new ISA membership-related + constant meanings. + + * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New + definitions. + + * mips.h (CPU_SB1): New constant. + +2000-10-20 Jakub Jelinek <jakub@redhat.com> + + * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. + Note that '3' is used for siam operand. + +2000-09-22 Jim Wilson <wilson@cygnus.com> + + * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. + +2000-09-13 Anders Norlander <anorland@acc.umu.se> + + * mips.h: Use defines instead of hard-coded processor numbers. + (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, + CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, + CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, + CPU_4KC, CPU_4KM, CPU_4KP): Define.. + (OPCODE_IS_MEMBER): Use new defines. + (OP_MASK_SEL, OP_SH_SEL): Define. + (OP_MASK_CODE20, OP_SH_CODE20): Define. + Add 'P' to used characters. + Use 'H' for coprocessor select field. + Use 'm' for 20 bit breakpoint code. + Document new arg characters and add to used characters. + (INSN_MIPS32): New define for MIPS32 extensions. + (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. + +2000-09-05 Alan Modra <alan@linuxcare.com.au> + + * hppa.h: Mention cz completer. + +2000-08-16 Jim Wilson <wilson@cygnus.com> + + * ia64.h (IA64_OPCODE_POSTINC): New. + +2000-08-15 H.J. Lu <hjl@gnu.org> + + * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the + IgnoreSize change. + +2000-08-08 Jason Eckhardt <jle@cygnus.com> + + * i860.h: Small formatting adjustments. + +2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> + + * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. + Move related opcodes closer to each other. + Minor changes in comments, list undefined opcodes. + +2000-07-26 Dave Brolley <brolley@redhat.com> + + * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned. + +2000-07-22 Jason Eckhardt <jle@cygnus.com> + + * i860.h (btne, bte, bla): Changed these opcodes + to use sbroff ('r') instead of split16 ('s'). + (J, K, L, M): New operand types for 16-bit aligned fields. + (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to + use I, J, K, L, M instead of just I. + (T, U): New operand types for split 16-bit aligned fields. + (st.x): Changed these opcodes to use S, T, U instead of just S. + (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not + exist on the i860. + (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. + (pfeq.ss, pfeq.dd): New opcodes. + (st.s): Fixed incorrect mask bits. + (fmlow): Fixed incorrect mask bits. + (fzchkl, pfzchkl): Fixed incorrect mask bits. + (faddz, pfaddz): Fixed incorrect mask bits. + (form, pform): Fixed incorrect mask bits. + (pfld.l): Fixed incorrect mask bits. + (fst.q): Fixed incorrect mask bits. + (all floating point opcodes): Fixed incorrect mask bits for + handling of dual bit. + +2000-07-20 Hans-Peter Nilsson <hp@axis.com> + + cris.h: New file. + +2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl> + + * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA. + (AVR_ISA_ESPM): Remove, because ESPM removed in databook update. + (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx. + (AVR_ISA_M83): Define for ATmega83, ATmega85. + (espm): Remove, because ESPM removed in databook update. + (eicall, eijmp): Move to the end of opcode table. + +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * m68hc11.h: New file for support of Motorola 68hc11. + +Fri Jun 9 21:51:50 2000 Denis Chertykov <denisc@overta.ru> + + * avr.h: clr,lsl,rol, ... moved after add,adc, ... + +Wed Jun 7 21:39:54 2000 Denis Chertykov <denisc@overta.ru> + + * avr.h: New file with AVR opcodes. + +Wed Apr 12 17:11:20 2000 Donald Lindsay <dlindsay@hound.cygnus.com> + + * d10v.h: added ALONE attribute for d10v_opcode.exec_type. + +2000-05-23 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * i386.h: Allow d suffix on iret, and add DefaultSize modifier. + +2000-05-17 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * i386.h: Use sl_FP, not sl_Suf for fild. + +2000-05-16 Frank Ch. Eigler <fche@redhat.com> + + * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that + it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. + (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds + CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set. + +2000-05-13 Alan Modra <alan@linuxcare.com.au>, + + * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore. + +2000-05-13 Alan Modra <alan@linuxcare.com.au>, + Alexander Sokolov <robocop@netlink.ru> + + * i386.h (i386_optab): Add cpu_flags for all instructions. + +2000-05-13 Alan Modra <alan@linuxcare.com.au> + + From Gavin Romig-Koch <gavin@cygnus.com> + * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa. + +2000-05-04 Timothy Wall <twall@cygnus.com> + + * tic54x.h: New. + +2000-05-03 J.T. Conklin <jtc@redback.com> + + * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit. + (PPC_OPERAND_VR): New operand flag for vector registers. + +2000-05-01 Kazu Hirata <kazu@hxi.com> + + * h8300.h (EOP): Add missing initializer. + +Fri Apr 21 15:03:37 2000 Jason Eckhardt <jle@cygnus.com> + + * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode + forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). + New operand types l,y,&,fe,fE,fx added to support above forms. + (pa_opcodes): Replaced usage of 'x' as source/target for + floating point double-word loads/stores with 'fx'. + +Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + Timothy Wall <twall@cygnus.com> + Jim Wilson <wilson@cygnus.com> + + * ia64.h: New file. + +2000-03-27 Nick Clifton <nickc@cygnus.com> + + * d30v.h (SHORT_A1): Fix value. + (SHORT_AR): Renumber so that it is at the end of the list of short + instructions, not the end of the list of long instructions. + +2000-03-26 Alan Modra <alan@linuxcare.com> + + * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the + problem isn't really specific to Unixware. + (OLDGCC_COMPAT): Define. + (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with + destination %st(0). + Fix lots of comments. + +2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk> + + * d30v.h: + (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated. + (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated. + (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated. + (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated. + (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated. + (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated. + (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated. + +2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (fild, fistp): Change intel d_Suf form to fildd and + fistpd without suffix. + +2000-02-24 Nick Clifton <nickc@cygnus.com> + + * cgen.h (cgen_cpu_desc): Rename field 'flags' to + 'signed_overflow_ok_p'. + Delete prototypes for cgen_set_flags() and cgen_get_flags(). + +2000-02-24 Andrew Haley <aph@cygnus.com> + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + (CGEN_CPU_TABLE): flags: new field. + Add prototypes for new functions. + +2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add some more UNIXWARE_COMPAT comments. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * i370.h: New file. + +2000-02-22 Chandra Chavva <cchavva@cygnus.com> + + * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation + cannot be combined in parallel with ADD/SUBppp. + +2000-02-22 Andrew Haley <aph@cygnus.com> + + * mips.h: (OPCODE_IS_MEMBER): Add comment. + +1999-12-30 Andrew Haley <aph@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines + whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit + insns. + +2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Qualify intel mode far call and jmp with x_Suf. + +1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add JumpAbsolute qualifier to all non-intel mode + indirect jumps and calls. Add FF/3 call for intel mode. + +Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add new operand types. Add new instruction formats. + +Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" + instruction. + +1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (INSN_ISA5): New. + +1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): New. + +1999-10-29 Nick Clifton <nickc@cygnus.com> + + * d30v.h (SHORT_AR): Define. + +1999-10-18 Michael Meissner <meissner@cygnus.com> + + * alpha.h (alpha_num_opcodes): Convert to unsigned. + (alpha_num_operands): Ditto. + +Sun Oct 10 01:46:56 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> + + * hppa.h (pa_opcodes): Add load and store cache control to + instructions. Add ordered access load and store. + + * hppa.h (pa_opcode): Add new entries for addb and addib. + + * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. + + * hppa.h (pa_opcodes): Add entries for cmpb and cmpib. + +Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com> + + * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands. + +Thu Sep 23 07:08:38 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" + and "be" using completer prefixes. + + * hppa.h (pa_opcodes): Add initializers to silence compiler. + + * hppa.h: Update comments about character usage. + +Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning + up the new fstw & bve instructions. + +Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store + instructions. + + * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. + + * hppa.h (pa_opcodes): Add long offset double word load/store + instructions. + + * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and + stores. + + * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. + + * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. + + * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. + + * hppa.h (pa_opcodes): Add new syntax "be" instructions. + + * hppa.h (pa_opcodes): Note use of 'M' and 'L'. + + * hppa.h (pa_opcodes): Add support for "b,l". + + * hppa.h (pa_opcodes): Add support for "b,gate". + +Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Use 'fX' for first register operand + in xmpyu. + + * hppa.h (pa_opcodes): Fix mask for probe and probei. + + * hppa.h (pa_opcodes): Fix mask for depwi. + +Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as + an explicit output argument. + +Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. + Add a few PA2.0 loads and store variants. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * pj.h: New file. + +1999-08-29 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_regtab): Move %st to top of table, and split off + other fp reg entries. + (i386_float_regtab): To here. + +Sat Aug 28 00:25:25 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args + by 'f'. + + * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. + Add supporting args. + + * hppa.h: Document new completers and args. + * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor, + uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0 + extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions + pmenb and pmdis. + + * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, + hshr, hsub, mixh, mixw, permh. + + * hppa.h (pa_opcodes): Change completers in instructions to + use 'c' prefix. + + * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, + hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments. + + * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, + fnegabs to use 'I' instead of 'F'. + +1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd. + Document pf2iw and pi2fw as athlon insns. Remove pswapw. + Alphabetically sort PIII insns. + +Wed Aug 18 18:14:40 1999 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + +Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, + and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr. + + * hppa.h: Document 64 bit condition completers. + +Thu Aug 5 16:56:07 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Change condition args to use '?' prefix. + +1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Add DefaultSize modifier to all insns + that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf, + sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table. + +Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". + + * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. + + * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, + and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. + +1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. + +Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (struct pa_opcode): Add new field "flags". + (FLAGS_STRICT): Define. + +Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. + + * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. + +1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, + lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP + flag to fcomi and friends. + +Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Move integer arithmetic instructions after + integer logical instructions. + +1999-05-28 Linus Nordberg <linus.nordberg@canit.se> + + * m68k.h: Document new formats `E', `G', `H' and new places `N', + `n', `o'. + + * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' + and new places `m', `M', `h'. + +Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com + + * hppa.h (pa_opcodes): Add several processor specific system + instructions. + +Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + "addb", and "addib" to be used by the disassembler. + +1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> + + * i386.h (ReverseModrm): Remove all occurences. + (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, + movmskps, pextrw, pmovmskb, maskmovq. + Change NoSuf to FP on all MMX, XMM and AMD insns as these all + ignore the data size prefix. + + * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. + Mostly stolen from Doug Ledford <dledford@redhat.com> + +Sat May 8 23:27:35 1999 Richard Henderson <rth@cygnus.com> + + * ppc.h (PPC_OPCODE_64_BRIDGE): New. + +1999-04-14 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_ATTR): Delete member num_nonbools. + (CGEN_ATTR_TYPE): Update. + (CGEN_ATTR_MASK): Number booleans starting at 0. + (CGEN_ATTR_VALUE): Update. + (CGEN_INSN_ATTR): Update. + +Mon Apr 12 23:43:27 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0 + instructions. + +Tue Mar 23 11:24:38 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (bb, bvb): Tweak opcode/mask. + + +1999-03-22 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs. + (struct cgen_cpu_desc): Rename member mach to machs. New member isas. + New members word_bitsize,default_insn_bitsize,base_insn-bitsize, + min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables. + Delete member max_insn_size. + (enum cgen_cpu_open_arg): New enum. + (cpu_open): Update prototype. + (cpu_open_1): Declare. + (cgen_set_cpu): Delete. + +1999-03-11 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member. + (CGEN_OPERAND_NIL): New macro. + (CGEN_OPERAND): New member `type'. + (@arch@_cgen_operand_table): Delete decl. + (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete. + (CGEN_OPERAND_TABLE): New struct. + (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare. + (CGEN_OPINST): Pointer to operand table entry replaced with enum. + (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table', + now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to + {get,set}_{int,vma}_operand. + (@arch@_cgen_cpu_open): New arg `isa'. + (cgen_set_cpu): Ditto. + +Fri Feb 26 02:36:45 1999 Richard Henderson <rth@cygnus.com> + + * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms. + +1999-02-25 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE. + (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to + enum cgen_hw_type. + (CGEN_HW_TABLE): New struct. + (hw_table): Delete declaration. + (CGEN_OPERAND): Change member hw to hw_type, change type from pointer + to table entry to enum. + (CGEN_OPINST): Ditto. + (CGEN_CPU_TABLE): Change member hw_list to hw_table. + +Sat Feb 13 14:13:44 1999 Richard Henderson <rth@cygnus.com> + + * alpha.h (AXP_OPCODE_EV6): New. + (AXP_OPCODE_NOPAL): Include it. + +1999-02-09 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC. + All uses updated. New members int_insn_p, max_insn_size, + parse_operand,insert_operand,extract_operand,print_operand, + sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand, + get_vma_operand,set_vma_operand,parse_handlers,insert_handlers, + extract_handlers,print_handlers. + (CGEN_ATTR): Change type of num_nonbools to unsigned int. + (CGEN_ATTR_BOOL_OFFSET): New macro. + (CGEN_ATTR_MASK): Subtract it to compute bit number. + (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation. + (cgen_opcode_handler): Renamed from cgen_base. + (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated. + (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR, + all uses updated. + (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global. + (enum cgen_opinst_type): Renamed from cgen_operand_instance_type. + (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated. + (CGEN_OPCODE,CGEN_IBASE): New types. + (CGEN_INSN): Rewrite. + (CGEN_{ASM,DIS}_HASH*): Delete. + (init_opcode_table,init_ibld_table): Declare. + (CGEN_INSN_ATTR): New type. + +Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> + + * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. + (x_FP, d_FP, dls_FP, sldx_FP): Define. + Change *Suf definitions to include x and d suffixes. + (movsx): Use w_Suf and b_Suf. + (movzx): Likewise. + (movs): Use bwld_Suf. + (fld): Change ordering. Use sld_FP. + (fild): Add Intel Syntax equivalent of fildq. + (fst): Use sld_FP. + (fist): Use sld_FP. + (fstp): Use sld_FP. Add x_FP version. + (fistp): LLongMem version for Intel Syntax. + (fcom, fcomp): Use sld_FP. + (fadd, fiadd, fsub): Use sld_FP. + (fsubr): Use sld_FP. + (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP. + +1999-01-27 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, + CGEN_MODE_UINT. + +1999-01-16 Jeffrey A Law (law@cygnus.com) + + * hppa.h (bv): Fix mask. + +1999-01-05 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef. + (CGEN_ATTR): Use it. + (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto. + (CGEN_ATTR_TABLE): New member dfault. + +1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (MIPS16_INSN_BRANCH): New. + +Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com> + + The following is part of a change made by Edith Epstein + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes by HP; HP did not create ChangeLog entries. + + * hppa.h (completer_chars): list of chars to not put a space + after. + +Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com> + + * i386.h (i386_optab): Permit w suffix on processor control and + status word instructions. + +1998-11-30 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (struct cgen_hw_entry): Delete const on attrs member. + (struct cgen_keyword_entry): Ditto. + (struct cgen_operand): Ditto. + (CGEN_IFLD): New typedef, with associated access macros. + (CGEN_IFMT): New typedef, with associated access macros. + (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'. + (CGEN_IVALUE): New typedef. + (struct cgen_insn): Delete const on syntax,attrs members. + `format' now points to format data. Type of `value' is now + CGEN_IVALUE. + (struct cgen_opcode_table): New member ifld_table. + +1998-11-18 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (cgen_extract_fn): Update type of `base_insn' arg. + (CGEN_OPERAND_INSTANCE): New member `attrs'. + (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros. + (cgen_dis_lookup_insn): Update type of `base_insn' arg. + (cgen_opcode_table): Update type of dis_hash fn. + (extract_operand): Update type of `insn_value' arg. + +Thu Oct 29 11:38:36 1998 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete. + +Tue Oct 27 08:57:59 1998 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (INSN_MULT): Added. + +Tue Oct 20 11:31:34 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE. + +Mon Oct 19 12:50:00 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_INSN_INT): New typedef. + (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN. + (CGEN_INSN_BYTES): Renamed from cgen_insn_t. + (CGEN_INSN_BYTES_PTR): New typedef. + (CGEN_EXTRACT_INFO): New typedef. + (cgen_insert_fn,cgen_extract_fn): Update. + (cgen_opcode_table): New member `insn_endian'. + (assemble_insn,lookup_insn,lookup_get_insn_operands): Update. + (insert_operand,extract_operand): Update. + (cgen_get_insn_value,cgen_put_insn_value): Add prototypes. + +Fri Oct 9 13:38:13 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_ATTR_BOOLS): New macro. + (struct CGEN_HW_ENTRY): New member `attrs'. + (CGEN_HW_ATTR): New macro. + (struct CGEN_OPERAND_INSTANCE): New member `name'. + (CGEN_INSN_INVALID_P): New macro. + +Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add "fid". + +Sun Oct 4 21:00:00 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + From Robert Andrew Dale <rob@nb.net> + * i386.h (i386_optab): Add AMD 3DNow! instructions. + (AMD_3DNOW_OPCODE): Define. + +Tue Sep 22 17:53:47 1998 Nick Clifton <nickc@cygnus.com> + + * d30v.h (EITHER_BUT_PREFER_MU): Define. + +Mon Aug 10 14:09:38 1998 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (cgen_insn): #if 0 out element `cdx'. + +Mon Aug 3 12:21:57 1998 Doug Evans <devans@seba.cygnus.com> + + Move all global state data into opcode table struct, and treat + opcode table as something that is "opened/closed". + * cgen.h (CGEN_OPCODE_DESC): New type. + (all fns): New first arg of opcode table descriptor. + (cgen_set_parse_operand_fn): Add prototype. + (cgen_current_machine,cgen_current_endian): Delete. + (CGEN_OPCODE_TABLE): New members mach,endian,operand_table, + parse_operand_fn,asm_hash_table,asm_hash_table_entries, + dis_hash_table,dis_hash_table_entries. + (opcode_open,opcode_close): Add prototypes. + + * cgen.h (cgen_insn): New element `cdx'. + +Thu Jul 30 21:44:25 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions. + +Tue Jul 28 10:59:07 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add "no_match_operands" field for instructions. + (MN10300_MAX_OPERANDS): Define. + +Fri Jul 24 11:44:24 1998 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (cgen_macro_insn_count): Declare. + +Tue Jul 21 13:12:13 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define. + (cgen_insert_fn,cgen_extract_fn): New arg `pc'. + (get_operand,put_operand): Replaced with get_{int,vma}_operand, + set_{int,vma}_operand. + +Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add "machine" field for instructions. + (MN103, AM30): Define machine types. + +Fri Jun 19 16:09:09 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. + +1998-06-18 Ulrich Drepper <drepper@cygnus.com> + + * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit. + +Sat Jun 13 11:31:35 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Add general form of aad and aam. Add ud2a + and ud2b. + (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just + those that happen to be implemented on pentiums. + +Tue Jun 9 12:16:01 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Change occurences of Data16 to Size16, Data32 to Size32, + IgnoreDataSize to IgnoreSize. Flag address and data size prefixes + with Size16|IgnoreSize or Size32|IgnoreSize. + +Mon Jun 8 12:15:52 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE. + (REPE): Rename to REPE_PREFIX_OPCODE. + (i386_regtab_end): Remove. + (i386_prefixtab, i386_prefixtab_end): Remove. + (i386_optab): Use NULL as sentinel rather than "" to suit rewrite + of md_begin. + (MAX_OPCODE_SIZE): Define. + (i386_optab_end): Remove. + (sl_Suf): Define. + (sl_FP): Use sl_Suf. + + * i386.h (i386_optab): Allow 16 bit displacement for `mov + mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16 + bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32, + data32, dword, and adword prefixes. + (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index + regs. + +Fri Jun 5 23:42:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_regtab): Remove BaseIndex modifier from esp. + + * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with + register operands, because this is a common idiom. Flag them with + a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp, + fdivrp because gcc erroneously generates them. Also flag with a + warning. + + * i386.h: Add suffix modifiers to most insns, and tighter operand + checks in some cases. Fix a number of UnixWare compatibility + issues with float insns. Merge some floating point opcodes, using + new FloatMF modifier. + (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for + consistency. + + * i386.h: Change occurence of ShortformW to W|ShortForm. Add + IgnoreDataSize where appropriate. + +Wed Jun 3 18:28:45 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: (one_byte_segment_defaults): Remove. + (two_byte_segment_defaults): Remove. + (i386_regtab): Add BaseIndex to 32 bit regs reg_type. + +Fri May 15 15:59:04 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. + (cgen_hw_lookup_by_num): Declare. + +Thu May 7 09:27:58 1998 Frank Ch. Eigler <fche@cygnus.com> + + * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower + ten bits of MIPS ISA1 "break" instruction, and for "sdbbp" + +Thu May 7 02:14:08 1998 Doug Evans <devans@charmed.cygnus.com> + + * cgen.h (cgen_asm_init_parse): Delete. + (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete. + (cgen_asm_record_register,cgen_asm_finish_insn): Delete. + +Mon Apr 27 10:13:11 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses. + (cgen_asm_finish_insn): Update prototype. + (cgen_insn): New members num, data. + (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size, + dis_hash, dis_hash_table_size moved to ... + (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA. + All uses updated. New members asm_hash_p, dis_hash_p. + (CGEN_MINSN_EXPANSION): New struct. + (cgen_expand_macro_insn): Declare. + (cgen_macro_insn_count): Declare. + (get_insn_operands): Update prototype. + (lookup_get_insn_operands): Declare. + +Tue Apr 21 17:11:32 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Change iclrKludge and imulKludge to + regKludge. Add operands types for string instructions. + +Mon Apr 20 14:40:29 1998 Tom Tromey <tromey@cygnus.com> + + * i386.h (X): Renamed from `Z_' to preserve formatting of opcode + table. + +Sun Apr 19 13:54:06 1998 Tom Tromey <tromey@cygnus.com> + + * i386.h (Z_): Renamed from `_' to avoid clash with common alias + for `gettext'. + +Fri Apr 3 12:04:48 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Remove NoModrm flag from all insns: it's never checked. + Add IsString flag to string instructions. + (IS_STRING): Don't define. + (LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define. + (ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define. + (SS_PREFIX_OPCODE): Define. + +Mon Mar 30 21:31:56 1998 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Revert March 24 patch; no more LinearAddress. + +Mon Mar 30 10:25:54 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Remove fwait (9b) from all floating point + instructions, and instead add FWait opcode modifier. Add short + form of fldenv and fstenv. + (FWAIT_OPCODE): Define. + + * i386.h (i386_optab): Change second operand constraint of `mov + sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to + allow legal instructions such as `movl %gs,%esi' + +Fri Mar 27 18:30:52 1998 Ian Lance Taylor <ian@cygnus.com> + + * h8300.h: Various changes to fully bracket initializers. + +Tue Mar 24 18:32:47 1998 H.J. Lu <hjl@gnu.org> + + * i386.h: Set LinearAddress for lidt and lgdt. + +Mon Mar 2 10:44:07 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_BOOL_ATTR): New macro. + +Thu Feb 26 15:54:31 1998 Michael Meissner <meissner@cygnus.com> + + * d30v.h (FLAG_DELAY): New flag for delayed branches/jumps. + +Mon Feb 23 10:38:21 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now. + (cgen_insn): Record syntax and format entries here, rather than + separately. + +Tue Feb 17 21:42:56 1998 Nick Clifton <nickc@cygnus.com> + + * cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro. + +Tue Feb 17 16:00:56 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (cgen_insert_fn): Change type of result to const char *. + (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments. + (CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS. + +Thu Feb 12 18:30:41 1998 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (lookup_insn): New argument alias_p. + +Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> + +Fix rac to accept only a0: + * d10v.h (OPERAND_ACC): Split into: + (OPERAND_ACC0, OPERAND_ACC1) . + (OPERAND_GPR): Define. + +Wed Feb 11 17:31:53 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_FIELDS): Define here. + (CGEN_HW_ENTRY): New member `type'. + (hw_list): Delete decl. + (enum cgen_mode): Declare. + (CGEN_OPERAND): New member `hw'. + (enum cgen_operand_instance_type): Declare. + (CGEN_OPERAND_INSTANCE): New type. + (CGEN_INSN): New member `operands'. + (CGEN_OPCODE_DATA): Make hw_list const. + (get_insn_operands,lookup_insn): Add prototypes for. + +Tue Feb 3 17:11:23 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS. + (CGEN_HW_ENTRY): Move `next' entry to end of struct. + (CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS. + (CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS. + +Mon Feb 2 19:19:15 1998 Ian Lance Taylor <ian@cygnus.com> + + * cgen.h: Correct typo in comment end marker. + +Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> + + * tic30.h: New file. + +Thu Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com> + + * cgen.h: Add prototypes for cgen_save_fixups(), + cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype + of cgen_asm_finish_insn() to return a char *. + +Wed Jan 14 17:21:43 1998 Nick Clifton <nickc@cygnus.com> + + * cgen.h: Formatting changes to improve readability. + +Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (*): Clean up pass over `struct foo' usage. + (CGEN_ATTR): Make unsigned char. + (CGEN_ATTR_TYPE): Update. + (CGEN_ATTR_{ENTRY,TABLE}): New types. + (cgen_base): Move member `attrs' to cgen_insn. + (CGEN_KEYWORD): New member `null_entry'. + (CGEN_{SYNTAX,FORMAT}): New types. + (cgen_insn): Format and syntax separated from each other. + +Tue Dec 16 15:15:52 1997 Michael Meissner <meissner@cygnus.com> + + * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for + 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make + flags_{used,set} long. + (d30v_operand): Make flags field long. + +Mon Dec 1 12:24:44 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k.h: Fix comment describing operand types. + +Sun Nov 23 22:31:27 1997 Michael Meissner <meissner@cygnus.com> + + * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move + everything else after down. + +Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * d10v.h (OPERAND_FLAG): Split into: + (OPERAND_FFLAG, OPERAND_CFLAG) . + +Thu Nov 13 11:04:24 1997 Gavin Koch <gavin@cygnus.com> + + * mips.h (struct mips_opcode): Changed comments to reflect new + field usage. + +Fri Oct 24 22:36:20 1997 Ken Raeburn <raeburn@cygnus.com> + + * mips.h: Added to comments a quick-ref list of all assigned + operand type characters. + (OP_{MASK,SH}_PERFREG): New macros. + +Wed Oct 22 17:28:33 1997 Richard Henderson <rth@cygnus.com> + + * sparc.h: Add '_' and '/' for v9a asr's. + Patch from David Miller <davem@vger.rutgers.edu> + +Tue Oct 14 13:22:29 1997 Jeffrey A Law (law@cygnus.com) + + * h8300.h: Bit ops with absolute addresses not in the 8 bit + area are not available in the base model (H8/300). + +Thu Sep 25 13:03:41 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k.h: Remove documentation of ` operand specifier. + +Wed Sep 24 19:00:34 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k.h: Document q and v operand specifiers. + +Mon Sep 15 18:28:37 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (struct v850_opcode): Add processors field. + (PROCESSOR_V850, PROCESSOR_ALL): New bit constants. + (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants. + (PROCESSOR_V850EA): New bit constants. + +Mon Sep 15 11:29:43 1997 Ken Raeburn <raeburn@cygnus.com> + + Merge changes from Martin Hunt: + + * d30v.h: Allow up to 64 control registers. Add + SHORT_A5S format. + + * d30v.h (LONG_Db): New form for delayed branches. + + * d30v.h: (LONG_Db): New form for repeati. + + * d30v.h (SHORT_D2B): New form. + + * d30v.h (SHORT_A2): New form. + + * d30v.h (OPERAND_2REG): Add new operand to indicate 2 + registers are used. Needed for VLIW optimization. + +Mon Sep 8 14:05:45 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen.h: Move assembler interface section + up so cgen_parse_operand_result is defined for cgen_parse_address. + (cgen_parse_address): Update prototype. + +Tue Sep 2 15:32:32 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. + +Tue Aug 26 12:21:52 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386.h (two_byte_segment_defaults): Correct base register 5 in + modes 1 and 2 to be ss rather than ds. From Gabriel Paubert + <paubert@iram.es>. + + * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert + <paubert@iram.es>. + + * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert + <paubert@iram.es>. + + * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again). + (JUMP_ON_ECX_ZERO): Remove commented out macro. + +Fri Aug 22 10:38:29 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (V850_NOT_R0): New flag. + +Mon Aug 18 11:05:58 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (struct v850_opcode): Remove flags field. + +Wed Aug 13 18:45:48 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (struct v850_opcode): Add flags field. + (struct v850_operand): Extend meaning of 'bits' and 'shift' + fields. + (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags. + (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags. + +Fri Aug 8 16:58:42 1997 Doug Evans <dje@canuck.cygnus.com> + + * arc.h: New file. + +Thu Jul 24 21:16:58 1997 Doug Evans <dje@canuck.cygnus.com> + + * sparc.h (sparc_opcodes): Declare as const. + +Thu Jul 10 12:53:25 1997 Jeffrey A Law (law@cygnus.com) + + * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn + uses single or double precision floating point resources. + (INSN_NO_ISA, INSN_ISA1): Define. + (cpu specific INSN macros): Tweak into bitmasks outside the range + of INSN_ISA field. + +Mon Jun 16 14:10:00 1997 H.J. Lu <hjl@gnu.ai.mit.edu> + + * i386.h: Fix pand opcode. + +Mon Jun 2 11:35:09 1997 Gavin Koch <gavin@cygnus.com> + + * mips.h: Widen INSN_ISA and move it to a more convenient + bit position. Add INSN_3900. + +Tue May 20 11:25:29 1997 Gavin Koch <gavin@cygnus.com> + + * mips.h (struct mips_opcode): added new field membership. + +Mon May 12 16:26:50 1997 H.J. Lu <hjl@gnu.ai.mit.edu> + + * i386.h (movd): only Reg32 is allowed. + + * i386.h: add fcomp and ud2. From Wayne Scott + <wscott@ichips.intel.com>. + +Mon May 5 17:16:21 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Add MMX instructions. + +Mon May 5 12:45:19 1997 H.J. Lu <hjl@gnu.ai.mit.edu> + + * i386.h: Remove W modifier from conditional move instructions. + +Mon Apr 14 14:56:58 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp + with no arguments to match that generated by the UnixWare + assembler. + +Thu Apr 10 14:35:00 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg. + (cgen_parse_operand_fn): Declare. + (cgen_init_parse_operand): Declare. + (cgen_parse_operand): Renamed from cgen_asm_parse_operand, + new argument `want'. + (enum cgen_parse_operand_result): Renamed from cgen_asm_result. + (enum cgen_parse_operand_type): New enum. + +Sat Apr 5 13:14:05 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Revert last patch for the NON_BROKEN_OPCODES cases. + +Fri Apr 4 11:46:11 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen.h: New file. + +Fri Apr 4 14:02:32 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and + fdivrp. + +Tue Mar 25 22:57:26 1997 Stu Grossman (grossman@critters.cygnus.com) + + * v850.h (extract): Make unsigned. + +Mon Mar 24 14:38:15 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Add iclr. + +Thu Mar 20 19:49:10 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Change DW to W for cmpxchg and xadd, since they don't + take a direction bit. + +Sat Mar 15 19:03:29 1997 H.J. Lu <hjl@lucon.org> + + * sparc.h (sparc_opcode_lookup_arch): Use full prototype. + +Fri Mar 14 15:22:01 1997 Ian Lance Taylor <ian@cygnus.com> + + * sparc.h: Include <ansidecl.h>. Update function declarations to + use prototypes, and to use const when appropriate. + +Thu Mar 6 14:18:30 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_RELAX): Define. + +Mon Feb 24 15:15:56 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v.h: Change pre_defined_registers to + d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. + +Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> + + * mips.h: Add macros for cop0, cop1 cop2 and cop3. + Change mips_opcodes from const array to a pointer, + and change bfd_mips_num_opcodes from const int to int, + so that we can increase the size of the mips opcodes table + dynamically. + +Fri Feb 21 16:34:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d30v.h (FLAG_X): Remove unused flag. + +Tue Feb 18 17:37:20 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d30v.h: New file. + +Fri Feb 14 13:16:15 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (PDS_NAME): Macro to access name field of predefined symbols. + (PDS_VALUE): Macro to access value field of predefined symbols. + (tic80_next_predefined_symbol): Add prototype. + +Mon Feb 10 10:32:17 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (tic80_symbol_to_value): Change prototype to match + change in function, added class parameter. + +Thu Feb 6 17:30:15 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80 + endmask fields, which are somewhat weird in that 0 and 32 are + treated exactly the same. + +Thu Jan 30 13:46:18 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h: Change all the OPERAND defines to use the form (1 << X) + rather than a constant that is 2**X. Reorder them to put bits for + operands that have symbolic names in the upper bits, so they can + be packed into an int where the lower bits contain the value that + corresponds to that symbolic name. + (predefined_symbo): Add struct. + (tic80_predefined_symbols): Declare array of translations. + (tic80_num_predefined_symbols): Declare size of that array. + (tic80_value_to_symbol): Declare function. + (tic80_symbol_to_value): Declare function. + +Wed Jan 29 09:37:25 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200.h (MN10200_OPERAND_RELAX): Define. + +Sat Jan 18 15:18:59 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot + be the destination register. + +Thu Jan 16 20:48:55 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (struct tic80_opcode): Change "format" field to "flags". + (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete. + (TIC80_VECTOR): Define a flag bit for the flags. This one means + that the opcode can have two vector instructions in a single + 32 bit word and we have to encode/decode both. + +Tue Jan 14 19:37:09 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_PCREL): Renamed from + TIC80_OPERAND_RELATIVE for PC relative. + (TIC80_OPERAND_BASEREL): New flag bit for register + base relative. + +Mon Jan 13 15:56:38 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands. + +Mon Jan 6 10:51:15 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional + ":s" modifier for scaling. + +Sun Jan 5 12:12:19 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m". + (TIC80_OPERAND_M_LI): Ditto + +Sat Jan 4 19:02:44 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ. + (TIC80_OPERAND_CC): New define for condition code operand. + (TIC80_OPERAND_CR): New define for control register operand. + +Fri Jan 3 16:22:23 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (struct tic80_opcode): Name changed. + (struct tic80_opcode): Remove format field. + (struct tic80_operand): Add insertion and extraction functions. + (TIC80_OPERAND_*): Remove old bogus values, start adding new + correct ones. + (FMT_*): Ditto. + +Tue Dec 31 15:05:41 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust + type IV instruction offsets. + +Fri Dec 27 22:23:10 1996 Fred Fish <fnf@cygnus.com> + + * tic80.h: New file. + +Wed Dec 18 10:06:31 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200.h (MN10200_OPERAND_NOCHECK): Define. + +Sat Dec 14 10:48:31 1996 Fred Fish <fnf@ninemoons.com> + + * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. + * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. + * v850.h: Fix comment, v850_operand not powerpc_operand. + +Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200.h: Flesh out structures and definitions needed by + the mn10200 assembler & disassembler. + +Tue Nov 26 10:46:56 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips.h: Add mips16 definitions. + +Mon Nov 25 17:56:54 1996 J.T. Conklin <jtc@cygnus.com> + + * m68k.h: Document new <, >, m, n, o and p operand specifiers. + +Wed Nov 20 10:59:41 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_PCREL): Define. + (MN10300_OPERAND_MEMADDR): Define. + +Tue Nov 19 13:30:40 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_REG_LIST): Define. + +Wed Nov 6 13:41:08 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_SPLIT): Define. + +Tue Nov 5 13:26:12 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_EXTENDED): Define. + +Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_REPEATED): Define. + +Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu> + + * alpha.h: Don't include "bfd.h"; private relocation types are now + negative to minimize problems with shared libraries. Organize + instruction subsets by AMASK extensions and PALcode + implementation. + (struct alpha_operand): Move flags slot for better packing. + +Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (V850_OPERAND_RELAX): New operand flag. + +Thu Oct 10 14:29:11 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (FMT_*): Move operand format definitions + here. + +Tue Oct 8 14:48:07 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_PAREN): Define. + +Mon Oct 7 16:52:11 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (mn10300_opcode): Add "format" field. + (MN10300_OPERAND_*): Define. + +Thu Oct 3 10:33:46 1996 Jeffrey A Law (law@cygnus.com) + + * mn10x00.h: Delete. + * mn10200.h, mn10300.h: New files. + +Wed Oct 2 21:31:26 1996 Jeffrey A Law (law@cygnus.com) + + * mn10x00.h: New file. + +Fri Sep 27 18:26:46 1996 Stu Grossman (grossman@critters.cygnus.com) + + * v850.h: Add new flag to indicate this instruction uses a PC + displacement. + +Fri Sep 13 14:58:13 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (stmac): Add missing instruction. + +Sat Aug 31 16:02:03 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (v850_opcode): Remove "size" field. Add "memop" + field. + +Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (V850_OPERAND_EP): Define. + + * v850.h (v850_opcode): Add size field. + +Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * v850.h (v850_operands): Add insert and extract fields, pointers + to functions used to handle unusual operand encoding. + (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, + V850_OPERAND_SIGNED): Defined. + +Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * v850.h (v850_operands): Add flags field. + (OPERAND_REG, OPERAND_NUM): Defined. + +Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * v850.h: New file. + +Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk> + + * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, + OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, + OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, + OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, + OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): + Defined. + +Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept + a 3 bit space id instead of a 2 bit space id. + +Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v.h: Add some additional defines to support the + assembler in determining which operations can be done in parallel. + +Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (SN): Define. + (eepmov.b): Renamed from "eepmov" + (nop, bpt, rte, rts, sleep, clrmac): These have no size associated + with them. + +Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v.h (OPERAND_SHIFT): New operand flag. + +Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v.h: Changes for divs, parallel-only instructions, and + signed numbers. + +Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v.h (pd_reg): Define. Putting the definition here allows + the assembler and disassembler to share the same struct. + +Mon Jul 22 12:15:25 1996 Ian Lance Taylor <ian@cygnus.com> + + * i960.h (i960_opcodes): "halt" takes an argument. From Stephen + Williams <steve@icarus.com>. + +Wed Jul 17 14:46:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v.h: New file. + +Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (band, bclr): Force high bit of immediate nibble to zero. + +Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * m68k.h (mcf5200): New macro. + Document names of coldfire control registers. + +Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (SRC_IN_DST): Define. + + * h8300.h (UNOP3): Mark the register operand in this insn + as a source operand, not a destination operand. + (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references. + (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark + register operand with SRC_IN_DST. + +Fri Jun 21 13:52:17 1996 Richard Henderson <rth@tamu.edu> + + * alpha.h: New file. + +Thu Jun 20 15:02:57 1996 Ian Lance Taylor <ian@cygnus.com> + + * rs6k.h: Remove obsolete file. + +Wed Jun 19 15:29:38 1996 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp, + fdivp, and fdivrp. Add ffreep. + +Tue Jun 18 16:06:00 1996 Jeffrey A. Law <law@rtl.cygnus.com> + + * h8300.h: Reorder various #defines for readability. + (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define. + (BITOP): Accept additional (unused) argument. All callers changed. + (EBITOP): Likewise. + (O_LAST): Bump. + (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes. + + * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define. + (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define. + (BITOP, EBITOP): Handle new H8/S addressing modes for + bit insns. + (UNOP3): Handle new shift/rotate insns on the H8/S. + (insns using exr): New instructions. + (tas, mac, ldmac, clrmac, ldm, stm): New instructions. + +Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (add.l): Undo Apr 5th change. The manual I had + was incorrect. + +Mon May 6 23:38:22 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (START): Remove. + (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w + and mov.l insns that can be relaxed. + +Tue Apr 30 18:30:58 1996 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Remove Abs32 from lcall. + +Mon Apr 22 17:09:23 1996 Doug Evans <dje@blues.cygnus.com> + + * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro. + (SLCPOP): New macro. + Mark X,Y opcode letters as in use. + +Thu Apr 11 17:28:18 1996 Ian Lance Taylor <ian@cygnus.com> + + * sparc.h (F_FLOAT, F_FBR): Define. + +Fri Apr 5 16:55:34 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV + from all insns. + (ABS8SRC,ABS8DST): Add ABS8MEM. + (add.l): Fix reg+reg variant. + (eepmov.w): Renamed from eepmovw. + (ldc,stc): Fix many cases. + +Sun Mar 31 13:30:03 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro. + +Thu Mar 7 15:08:23 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc.h (O): Mark operand letter as in use. + +Tue Feb 20 20:46:21 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare. + Mark operand letters uU as in use. + +Mon Feb 19 01:59:08 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET. + (sparc_opcode_arch): Delete member `conflicts'. Add `supported'. + (SPARC_OPCODE_SUPPORTED): New macro. + (SPARC_OPCODE_CONFLICT_P): Rewrite. + (F_NOTV9): Delete. + +Fri Feb 16 12:23:34 1996 Jeffrey A Law (law@cygnus.com) + + * sparc.h (sparc_opcode_lookup_arch) Make return type in + declaration consistent with return type in definition. + +Wed Feb 14 18:14:11 1996 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Remove Data32 from pushf and popf. + +Thu Feb 8 14:27:21 1996 James Carlson <carlson@xylogics.com> + + * i386.h (i386_regtab): Add 80486 test registers. + +Mon Feb 5 18:35:46 1996 Ian Lance Taylor <ian@cygnus.com> + + * i960.h (I_HX): Define. + (i960_opcodes): Add HX instruction. + +Mon Jan 29 12:43:39 1996 Ken Raeburn <raeburn@cygnus.com> + + * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw, + and fclex. + +Wed Jan 24 22:36:59 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture. + (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P. + (bfd_* defines): Delete. + (sparc_opcode_archs): Replaces architecture_pname. + (sparc_opcode_lookup_arch): Declare. + (NUMOPCODES): Delete. + +Mon Jan 22 08:24:32 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc.h (enum sparc_architecture): Add v9a. + (ARCHITECTURES_CONFLICT_P): Update. + +Thu Dec 28 13:27:53 1995 John Hassey <hassey@rtp.dg.com> + + * i386.h: Added Pentium Pro instructions. + +Thu Nov 2 22:59:22 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k.h: Document new 'W' operand place. + +Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add lci and syncdma instructions. + +Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> + + * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific + instructions. + +Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for + assembler's -mcom and -many switches. + +Wed Oct 11 16:56:33 1995 Ken Raeburn <raeburn@cygnus.com> + + * i386.h: Fix cmpxchg8b extension opcode description. + +Thu Oct 5 18:03:36 1995 Ken Raeburn <raeburn@cygnus.com> + + * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b, + and register cr4. + +Tue Sep 19 15:26:43 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k.h: Change comment: split type P into types 0, 1 and 2. + +Wed Aug 30 13:50:55 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc.h (sparc_{encode,decode}_prefetch): Declare. + +Tue Aug 29 15:34:58 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare. + +Wed Aug 2 18:32:19 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68kmri.h: Remove. + + * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the + declarations. Remove F_ALIAS and flag field of struct + m68k_opcode. Change arch field of struct m68k_opcode to unsigned + int. Make name and args fields of struct m68k_opcode const. + +Wed Aug 2 08:16:46 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc.h (F_NOTV9): Define. + +Tue Jul 11 14:20:42 1995 Jeff Spiegel <jeffs@lsil.com> + + * mips.h (INSN_4010): Define. + +Wed Jun 21 18:49:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * m68k.h (TBL1): Reverse sense of "round" argument in result. + + Changes from Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>: + * m68k.h: Fix argument descriptions of coprocessor + instructions to allow only alterable operands where appropriate. + [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'. + (m68k_opcode_aliases): Add more aliases. + +Fri Apr 14 22:15:34 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * m68k.h: Added explcitly short-sized conditional branches, and a + bunch of aliases (fmov*, ftest*, tdivul) to support gcc's + svr4-based configurations. + +Mon Mar 13 21:30:01 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + Mon Feb 27 08:36:39 1995 Bryan Ford <baford@cs.utah.edu> + * i386.h: added missing Data16/Data32 flags to a few instructions. + +Wed Mar 8 15:19:53 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (OP_MASK_FR, OP_SH_FR): Define. + (OP_MASK_BCC, OP_SH_BCC): Define. + (OP_MASK_PREFX, OP_SH_PREFX): Define. + (OP_MASK_CCC, OP_SH_CCC): Define. + (INSN_READ_FPR_R): Define. + (INSN_RFE): Delete. + +Wed Mar 8 03:13:23 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * m68k.h (enum m68k_architecture): Deleted. + (struct m68k_opcode_alias): New type. + (m68k_opcodes): Now const. Deleted opcode aliases with exactly + matching constraints, values and flags. As a side effect of this, + the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far + as I know were never used, now may need re-examining. + (numopcodes): Now const. + (m68k_opcode_aliases, numaliases): New variables. + (endop): Deleted. + [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and + m68k_opcode_aliases; update declaration of m68k_opcodes. + +Mon Mar 6 10:02:00 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa.h (delay_type): Delete unused enumeration. + (pa_opcode): Replace unused delayed field with an architecture + field. + (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1. + +Fri Mar 3 16:10:24 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (INSN_ISA4): Define. + +Fri Feb 24 19:13:37 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (M_DLA_AB, M_DLI): Define. + +Thu Feb 23 17:33:09 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa.h (fstwx): Fix single-bit error. + +Wed Feb 15 12:19:52 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define. + +Mon Feb 6 10:35:23 1995 J.T. Conklin <jtc@rtl.cygnus.com> + + * i386.h: added cpuid instruction , and dr[0-7] aliases for the + debug registers. From Charles Hannum (mycroft@netbsd.org). + +Mon Feb 6 03:31:54 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + Changes from Bryan Ford <baford@schirf.cs.utah.edu> for 16-bit + i386 support: + * i386.h (MOV_AX_DISP32): New macro. + (i386_optab): Added Data16 and Data32 as needed. Added "w" forms + of several call/return instructions. + (ADDR_PREFIX_OPCODE): New macro. + +Mon Jan 23 16:45:43 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + Sat Jan 21 17:50:38 1995 Pat Rankin (rankin@eql.caltech.edu) + + * vax.h (struct vot_wot, field `args'): Make it pointer to const + char. + (struct vot, field `name'): ditto. + +Thu Jan 19 14:47:53 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * vax.h: Supply and properly group all values in end sentinel. + +Tue Jan 17 10:55:30 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * mips.h (INSN_ISA, INSN_4650): Define. + +Wed Oct 19 13:34:17 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On + systems with a separate instruction and data cache, such as the + 29040, these instructions take an optional argument. + +Wed Sep 14 17:44:20 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips.h (INSN_STORE_MEMORY): Correct value to not conflict with + INSN_TRAP. + +Tue Sep 6 11:39:08 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips.h (INSN_STORE_MEMORY): Define. + +Thu Jul 28 19:28:07 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * sparc.h: Document new operand type 'x'. + +Tue Jul 26 17:48:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i960.h (I_CX2): New instruction category. It includes + instructions available on Cx and Jx processors. + (I_JX): New instruction category, for JX-only instructions. + (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added + Jx-only instructions, in I_JX category. + +Wed Jul 13 18:43:47 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * ns32k.h (endop): Made pointer const too. + +Sun Jul 10 11:01:09 1994 Ian Dall (dall@hfrd.dsto.gov.au) + + * ns32k.h: Drop Q operand type as there is no correct use + for it. Add I and Z operand types which allow better checking. + +Thu Jul 7 12:34:48 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * h8300.h (xor.l) :fix bit pattern. + (L_2): New size of operand. + (trapa): Use it. + +Fri Jun 10 16:38:11 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m68k.h: Move "trap" before "tpcc" to change disassembly. + +Fri Jun 3 15:57:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * sparc.h: Include v9 definitions. + +Thu Jun 2 12:23:17 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * m68k.h (m68060): Defined. + (m68040up, mfloat, mmmu): Include it. + (struct m68k_opcode): Widen `arch' field. + (m68k_opcodes): Updated for M68060. Removed comments that were + instructions commented out by "JF" years ago. + +Thu Apr 28 18:31:14 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and + add a one-bit `flags' field. + (F_ALIAS): New macro. + +Wed Apr 27 11:29:52 1994 Steve Chamberlain (sac@cygnus.com) + + * h8300.h (dec, inc): Get encoding right. + +Mon Apr 4 13:12:43 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h (struct powerpc_operand): Removed signedp field; just use + a flag instead. + (PPC_OPERAND_SIGNED): Define. + (PPC_OPERAND_SIGNOPT): Define. + +Thu Mar 31 19:34:08 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size + prefix is 0x66, not 0x67. Patch from H.J. Lu (hlu@nynexst.com). + +Thu Mar 3 15:51:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i386.h: Reverse last change. It'll be handled in gas instead. + +Thu Feb 24 15:29:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i386.h (sar): Disabled the two-operand Imm1 form, since it was + slower on the 486 and used the implicit shift count despite the + explicit operand. The one-operand form is still available to get + the shorter form with the implicit shift count. + +Thu Feb 17 12:27:52 1994 Torbjorn Granlund (tege@mexican.cygnus.com) + + * hppa.h: Fix typo in fstws arg string. + +Wed Feb 9 21:23:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h (struct powerpc_opcode): Make operands field unsigned. + +Mon Feb 7 19:14:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h (PPC_OPCODE_601): Define. + +Fri Feb 4 23:43:50 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa.h (addb): Use '@' for addb and addib pseudo ops. + (so we can determine valid completers for both addb and addb[tf].) + + * hppa.h (xmpyu): No floating point format specifier for the + xmpyu instruction. + +Fri Feb 4 23:36:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h (PPC_OPERAND_NEXT): Define. + (PPC_OPERAND_NEGATIVE): Change value to make room for above. + (struct powerpc_macro): Define. + (powerpc_macros, powerpc_num_macros): Declare. + +Fri Jan 21 19:13:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h: New file. Header file for PowerPC opcode table. + +Mon Jan 17 00:14:23 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa.h: More minor template fixes for sfu and copr (to allow + for easier disassembly). + + * hppa.h: Fix templates for all the sfu and copr instructions. + +Wed Dec 15 15:12:42 1993 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i386.h (push): Permit Imm16 operand too. + +Sat Dec 11 16:14:06 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8300.h (andc): Exists in base arch. + +Wed Dec 1 12:15:32 1993 Jeffrey A. Law (law@snake.cs.utah.edu) + + * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp> + * hppa.h: #undef NONE to avoid conflict with hiux include files. + +Sun Nov 21 22:06:57 1993 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa.h: Add FP quadword store instructions. + +Wed Nov 17 17:13:16 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h: (M_J_A): Added. + (M_LA): Removed. + +Mon Nov 8 12:12:47 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define. From Ted Lemon + <mellon@pepper.ncd.com>. + +Sun Nov 7 00:30:11 1993 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa.h: Immediate field in probei instructions is unsigned, + not low-sign extended. + +Wed Nov 3 10:30:00 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00. + +Tue Nov 2 12:41:30 1993 Ken Raeburn (raeburn@rover.cygnus.com) + + * i386.h: Add "fxch" without operand. + +Mon Nov 1 18:13:03 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added. + +Sat Oct 2 22:26:11 1993 Jeffrey A Law (law@snake.cs.utah.edu) + + * hppa.h: Add gfw and gfr to the opcode table. + +Wed Sep 29 16:23:00 1993 K. Richard Pixley (rich@sendai.cygnus.com) + + * m88k.h: extended to handle m88110. + +Tue Sep 28 19:19:08 1993 Jeffrey A Law (law@snake.cs.utah.edu) + + * hppa.h (be, ble): Use operand type 'z' to denote absolute branch + addresses. + +Tue Sep 14 14:04:35 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i960.h (i960_opcodes): Properly bracket initializers. + +Mon Sep 13 12:50:52 1993 K. Richard Pixley (rich@sendai.cygnus.com) + + * m88k.h (BOFLAG): rewrite to avoid nested comment. + +Mon Sep 13 15:46:06 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m68k.h (two): Protect second argument with parentheses. + +Fri Sep 10 16:29:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * i386.h (i386_optab): Added new instruction "rsm" (for i386sl). + Deleted old in/out instructions in "#if 0" section. + +Thu Sep 9 17:42:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i386.h (i386_optab): Properly bracket initializers. + +Wed Aug 25 13:50:56 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa.h (pa_opcode): Use '|' for movb and movib insns. (From + Jeff Law, law@cs.utah.edu). + +Mon Aug 23 16:55:03 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * i386.h (lcall): Accept Imm32 operand also. + +Mon Aug 23 12:43:11 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (M_ABSU): Removed (absolute value of unsigned number??). + (M_DABS): Added. + +Thu Aug 19 15:08:37 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (INSN_*): Changed values. Removed unused definitions. + Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3. Split + INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and + INSN_LOAD_COPROC_DELAY. Split INSN_COPROC_DELAY into + INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY. + (M_*): Added new values for r6000 and r4000 macros. + (ANY_DELAY): Removed. + +Wed Aug 18 15:37:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h: Added M_LI_S and M_LI_SS. + +Tue Aug 17 07:08:08 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * h8300.h: Get some rare mov.bs correct. + +Thu Aug 5 09:15:17 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * sparc.h: Don't define const ourself; rely on ansidecl.h having + been included. + +Fri Jul 30 18:41:11 1993 John Gilmore (gnu@cygnus.com) + + * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark + jump instructions, for use in disassemblers. + +Thu Jul 22 07:25:27 1993 Ian Lance Taylor (ian@cygnus.com) + + * m88k.h: Make bitfields just unsigned, not unsigned long or + unsigned short. + +Wed Jul 21 11:55:31 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa.h: New argument type 'y'. Use in various float instructions. + +Mon Jul 19 17:17:03 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa.h (break): First immediate field is unsigned. + + * hppa.h: Add rfir instruction. + +Sun Jul 18 16:28:08 1993 Jim Kingdon (kingdon@rtl.cygnus.com) + + * mips.h: Split the actual table out into ../../opcodes/mips-opc.c. + +Fri Jul 16 09:59:29 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h: Reworked the hazard information somewhat, and fixed some + bugs in the instruction hazard descriptions. + +Thu Jul 15 12:42:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k.h: Corrected a couple of opcodes. + +Tue Jul 6 15:17:35 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h: Replaced with version from Ralph Campbell and OSF. The + new version includes instruction hazard information, but is + otherwise reasonably similar. + +Thu Jul 1 20:36:17 1993 Doug Evans (dje@canuck.cygnus.com) + + * h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l). + +Fri Jun 11 18:38:44 1993 Ken Raeburn (raeburn@cygnus.com) + + Patches from Jeff Law, law@cs.utah.edu: + * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage. + Make the tables be the same for the following instructions: + "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", + "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o", + "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", + "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", + "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", + "fcmp", and "ftest". + + * hppa.h: Make new and old tables the same for "break", "mtctl", + "mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub". + Fix typo in last patch. Collapse several #ifdefs into a + single #ifdef. + + * hppa.h: Delete remaining OLD_TABLE code. Bring some + of the comments up-to-date. + + * hppa.h: Update "free list" of letters and update + comments describing each letter's function. + +Thu Jul 8 09:05:26 1993 Doug Evans (dje@canuck.cygnus.com) + + * h8300.h: Lots of little fixes for the h8/300h. + +Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + Support for H8/300-H + * h8300.h: Lots of new opcodes. + +Fri Jun 4 15:41:37 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * h8300.h: checkpoint, includes H8/300-H opcodes. + +Thu Jun 3 15:42:59 1993 Stu Grossman (grossman@cygnus.com) + + * Patches from Jeffrey Law <law@cs.utah.edu>. + * hppa.h: Rework single precision FP + instructions so that they correctly disassemble code + PA1.1 code. + +Thu May 27 19:21:22 1993 Bruce Bauman (boot@osf.org) + + * i386.h (i386_optab, mov pattern): Remove Mem16 restriction from + mov to allow instructions like mov ss,xyz(ecx) to assemble. + +Tue May 25 00:39:40 1993 Ken Raeburn (raeburn@cygnus.com) + + * hppa.h: Use new version from Utah if OLD_TABLE isn't defined; + gdb will define it for now. + +Mon May 24 15:20:06 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * sparc.h: Don't end enumerator list with comma. + +Fri May 14 15:15:50 1993 Ian Lance Taylor (ian@cygnus.com) + + * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): + * mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define. + ("bc2t"): Correct typo. + ("[ls]wc[023]"): Use T rather than t. + ("c[0123]"): Define general coprocessor instructions. + +Mon May 10 06:02:25 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * m68k.h: Move split point for gcc compilation more towards + middle. + +Fri Apr 9 13:26:16 1993 Jim Kingdon (kingdon@cygnus.com) + + * rs6k.h: Clean up instructions for primary opcode 19 (many were + simply wrong, ics, rfi, & rfsvc were missing). + Add "a" to opr_ext for "bb". Doc fix. + +Thu Mar 18 13:45:31 1993 Per Bothner (bothner@rtl.cygnus.com) + + * i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com). + * mips.h: Add casts, to suppress warnings about shifting too much. + * m68k.h: Document the placement code '9'. + +Thu Feb 18 02:03:14 1993 John Gilmore (gnu@cygnus.com) + + * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which + allows callers to break up the large initialized struct full of + opcodes into two half-sized ones. This permits GCC to compile + this module, since it takes exponential space for initializers. + (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs. + +Thu Feb 4 02:06:56 1993 John Gilmore (gnu@cygnus.com) + + * a29k.h: Remove RCS crud, update GPL to v2, update copyrights. + * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all + initialized structs in it. + +Thu Jan 28 21:32:22 1993 John Gilmore (gnu@cygnus.com) + + Delta 88 changes inspired by Carl Greco, <cgreco@Creighton.Edu>: + * m88k.h (PMEM): Avoid previous definition from <sys/param.h>. + (AND): Change to AND_ to avoid ansidecl.h `AND' conflict. + +Sat Jan 23 18:10:49 PST 1993 Ralph Campbell (ralphc@pyramid.com) + + * mips.h: document "i" and "j" operands correctly. + +Thu Jan 7 15:58:13 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h: Removed endianness dependency. + +Sun Jan 3 14:13:35 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8300.h: include info on number of cycles per instruction. + +Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com) + + * hppa.h: Move handy aliases to the front. Fix masks for extract + and deposit instructions. + +Sat Dec 12 16:09:48 1992 Ian Lance Taylor (ian@cygnus.com) + + * i386.h: accept shld and shrd both with and without the shift + count argument, which is always %cl. + +Fri Nov 27 17:13:18 1992 Ken Raeburn (raeburn at cygnus.com) + + * i386.h (i386_optab_end, i386_regtab_end): Now const. + (one_byte_segment_defaults, two_byte_segment_defaults, + i386_prefixtab_end): Ditto. + +Mon Nov 23 10:47:25 1992 Ken Raeburn (raeburn@cygnus.com) + + * vax.h (bb*): Use "v" (bitfield type), not "a" (address operand) + for operand 2; from John Carr, jfc@dsg.dec.com. + +Wed Nov 4 07:36:49 1992 Ken Raeburn (raeburn@cygnus.com) + + * m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions + always use 16-bit offsets. Makes calculated-size jump tables + feasible. + +Fri Oct 16 22:52:43 1992 Ken Raeburn (raeburn@cygnus.com) + + * i386.h: Fix one-operand forms of in* and out* patterns. + +Tue Sep 22 14:08:14 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * m68k.h: Added CPU32 support. + +Tue Sep 22 00:38:41 1992 John Gilmore (gnu@cygnus.com) + + * mips.h (break): Disassemble the argument. Patch from + jonathan@cs.stanford.edu (Jonathan Stone). + +Wed Sep 9 11:25:28 1992 Ian Lance Taylor (ian@cygnus.com) + + * m68k.h: merged Motorola and MIT syntax. + +Thu Sep 3 09:33:22 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * m68k.h (pmove): make the tests less strict, the 68k book is + wrong. + +Tue Aug 25 23:25:19 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * m68k.h (m68ec030): Defined as alias for 68030. + (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t" + for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use + them. Tightened description of "fmovex" to distinguish it from + some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned + up descriptions that claimed versions were available for chips not + supporting them. Added "pmovefd". + +Mon Aug 24 12:04:51 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * m68k.h: fix where the . goes in divull + +Wed Aug 19 11:22:24 1992 Ian Lance Taylor (ian@cygnus.com) + + * m68k.h: the cas2 instruction is supposed to be written with + indirection on the last two operands, which can be either data or + address registers. Added a new operand type 'r' which accepts + either register type. Added new cases for cas2l and cas2w which + use them. Corrected masks for cas2 which failed to recognize use + of address register. + +Fri Aug 14 14:20:38 1992 Per Bothner (bothner@cygnus.com) + + * m68k.h: Merged in patches (mostly m68040-specific) from + Colin Smith <colin@wrs.com>. + + * m68k.h: Merged m68kmri.h and m68k.h (using the former as a + base). Also cleaned up duplicates, re-ordered instructions for + the sake of dis-assembling (so aliases come after standard names). + * m68kmri.h: Now just defines some macros, and #includes m68k.h. + +Wed Aug 12 16:38:15 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in + all missing .s + +Mon Aug 10 23:22:33 1992 Ken Raeburn (raeburn@cygnus.com) + + * sparc.h: Moved tables to BFD library. + + * i386.h (i386_optab): Add fildq, fistpq aliases used by gcc. + +Sun Jun 28 13:29:03 1992 Fred Fish (fnf@cygnus.com) + + * h8300.h: Finish filling in all the holes in the opcode table, + so that the Lucid C compiler can digest this as well... + +Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com) + + * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases. + Fix opcodes on various sizes of fild/fist instructions + (16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix). + Use tabs to indent for comments. Fixes suggested by Minh Tran-Le. + +Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com) + + * h8300.h: Fill in all the holes in the opcode table so that the + losing HPUX C compiler can digest this... + +Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com) + + * mips.h: Fix decoding of coprocessor instructions, somewhat. + (Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.) + +Thu May 28 11:17:44 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * sparc.h: Add new architecture variant sparclite; add its scan + and divscc opcodes. Define ARCHITECTURES_CONFLICT_P macro. + +Tue May 5 14:23:27 1992 Per Bothner (bothner@rtl.cygnus.com) + + * mips.h: Add some more opcode synonyms (from Frank Yellin, + fy@lucid.com). + +Thu Apr 16 18:25:26 1992 Per Bothner (bothner@cygnus.com) + + * rs6k.h: New version from IBM (Metin). + +Thu Apr 9 00:31:19 1992 Per Bothner (bothner@rtl.cygnus.com) + + * rs6k.h: Fix incorrect extended opcode for instructions `fm' + and `fd'. (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).) + +Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com) + + * rs6k.h: Move from ../../gdb/rs6k-opcode.h. + +Fri Apr 3 11:30:20 1992 Fred Fish (fnf@cygnus.com) + + * m68k.h (one, two): Cast macro args to unsigned to suppress + complaints from compiler and lint about integer overflow during + shift. + +Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com) + + * sparc.h (OP): Avoid signed overflow when shifting to high order bit. + +Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com) + + * mips.h: Make bitfield layout depend on the HOST compiler, + not on the TARGET system. + +Fri Feb 21 01:29:51 1992 K. Richard Pixley (rich@cygnus.com) + + * i386.h: added inb, inw, outb, outw opcodes, added att syntax for + scmp, slod, smov, ssca, ssto. Curtesy Minh Tran-Le + <TRANLE@INTELLICORP.COM>. + +Thu Jan 30 07:31:44 1992 Steve Chamberlain (sac at rtl.cygnus.com) + + * h8300.h: turned op_type enum into #define list + +Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com) + + * sparc.h: Remove "cypress" architecture. Remove "fitox" and + similar instructions -- they've been renamed to "fitoq", etc. + REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong + number of arguments. + * h8300.h: Remove extra ; which produces compiler warning. + +Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com) + + * sparc.h: fix opcode for tsubcctv. + +Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com) + + * sparc.h: fba and cba are now aliases for fb and cb respectively. + +Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com) + + * sparc.h (nop): Made the 'lose' field be even tighter, + so only a standard 'nop' is disassembled as a nop. + +Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com) + + * sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is + disassembled as a nop. + +Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) + + * m68k.h, sparc.h: ANSIfy enums. + +Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com) + + * sparc.h: fix a typo. + +Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h, + m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h, + vax.h: Renamed from ../<foo>-opcode.h. + + +Local Variables: +version-control: never +End: diff --git a/include/opcode/a29k.h b/include/opcode/a29k.h new file mode 100644 index 000000000..c6c8c3700 --- /dev/null +++ b/include/opcode/a29k.h @@ -0,0 +1,281 @@ +/* Table of opcodes for the AMD 29000 family. + Copyright 1990, 1991, 1993, 1994, 2002 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +struct a29k_opcode { + /* Name of the instruction. */ + char *name; + + /* Opcode word */ + unsigned long opcode; + + /* A string of characters which describe the operands. + Valid characters are: + , Itself. The character appears in the assembly code. + a RA. The register number is in bits 8-15 of the instruction. + b RB. The register number is in bits 0-7 of the instruction. + c RC. The register number is in bits 16-23 of the instruction. + i An immediate operand is in bits 0-7 of the instruction. + x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15 + (respectively) of the immediate operand. + h Same as x but the instruction contains bits 16-31 of the + immediate operand. + X Same as x but bits 16-31 of the signed immediate operand + are set to 1 (thus the operand is always negative). + P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17 + (respectively) of the immediate operand. + P=PC-relative, sign-extended to 32 bits. + A=Absolute, zero-extended to 32 bits. + e CE bit (bit 23) for a load/store instruction. + n Control field (bits 16-22) for a load/store instruction. + v Immediate operand in bits 16-23 of the instruction. + (used for trap numbers). + s SA. Special-purpose register number in bits 8-15 + of the instruction. + u UI--bit 7 of the instruction. + r RND--bits 4-6 of the instruction. + d FD--bits 2-3 of the instruction. + f FS--bits 0-1 of the instruction. + I ID--bits 16-17 of the instruction. + + Extensions for 29050: + + d FMT--bits 2-3 of the instruction (not really new). + f ACN--bits 0-1 of the instruction (not really new). + F FUNC--Special function in bits 18-21 of the instruction. + C ACN--bits 16-17 specifying the accumlator register. */ + char *args; +}; + +static const struct a29k_opcode a29k_opcodes[] = +{ + +{ "add", 0x14000000, "c,a,b" }, +{ "add", 0x15000000, "c,a,i" }, +{ "addc", 0x1c000000, "c,a,b" }, +{ "addc", 0x1d000000, "c,a,i" }, +{ "addcs", 0x18000000, "c,a,b" }, +{ "addcs", 0x19000000, "c,a,i" }, +{ "addcu", 0x1a000000, "c,a,b" }, +{ "addcu", 0x1b000000, "c,a,i" }, +{ "adds", 0x10000000, "c,a,b" }, +{ "adds", 0x11000000, "c,a,i" }, +{ "addu", 0x12000000, "c,a,b" }, +{ "addu", 0x13000000, "c,a,i" }, +{ "and", 0x90000000, "c,a,b" }, +{ "and", 0x91000000, "c,a,i" }, +{ "andn", 0x9c000000, "c,a,b" }, +{ "andn", 0x9d000000, "c,a,i" }, +{ "aseq", 0x70000000, "v,a,b" }, +{ "aseq", 0x71000000, "v,a,i" }, +{ "asge", 0x5c000000, "v,a,b" }, +{ "asge", 0x5d000000, "v,a,i" }, +{ "asgeu", 0x5e000000, "v,a,b" }, +{ "asgeu", 0x5f000000, "v,a,i" }, +{ "asgt", 0x58000000, "v,a,b" }, +{ "asgt", 0x59000000, "v,a,i" }, +{ "asgtu", 0x5a000000, "v,a,b" }, +{ "asgtu", 0x5b000000, "v,a,i" }, +{ "asle", 0x54000000, "v,a,b" }, +{ "asle", 0x55000000, "v,a,i" }, +{ "asleu", 0x56000000, "v,a,b" }, +{ "asleu", 0x57000000, "v,a,i" }, +{ "aslt", 0x50000000, "v,a,b" }, +{ "aslt", 0x51000000, "v,a,i" }, +{ "asltu", 0x52000000, "v,a,b" }, +{ "asltu", 0x53000000, "v,a,i" }, +{ "asneq", 0x72000000, "v,a,b" }, +{ "asneq", 0x73000000, "v,a,i" }, +{ "call", 0xa8000000, "a,P" }, +{ "call", 0xa9000000, "a,A" }, +{ "calli", 0xc8000000, "a,b" }, +{ "class", 0xe6000000, "c,a,f" }, +{ "clz", 0x08000000, "c,b" }, +{ "clz", 0x09000000, "c,i" }, +{ "const", 0x03000000, "a,x" }, +{ "consth", 0x02000000, "a,h" }, +{ "consthz", 0x05000000, "a,h" }, +{ "constn", 0x01000000, "a,X" }, +{ "convert", 0xe4000000, "c,a,u,r,d,f" }, +{ "cpbyte", 0x2e000000, "c,a,b" }, +{ "cpbyte", 0x2f000000, "c,a,i" }, +{ "cpeq", 0x60000000, "c,a,b" }, +{ "cpeq", 0x61000000, "c,a,i" }, +{ "cpge", 0x4c000000, "c,a,b" }, +{ "cpge", 0x4d000000, "c,a,i" }, +{ "cpgeu", 0x4e000000, "c,a,b" }, +{ "cpgeu", 0x4f000000, "c,a,i" }, +{ "cpgt", 0x48000000, "c,a,b" }, +{ "cpgt", 0x49000000, "c,a,i" }, +{ "cpgtu", 0x4a000000, "c,a,b" }, +{ "cpgtu", 0x4b000000, "c,a,i" }, +{ "cple", 0x44000000, "c,a,b" }, +{ "cple", 0x45000000, "c,a,i" }, +{ "cpleu", 0x46000000, "c,a,b" }, +{ "cpleu", 0x47000000, "c,a,i" }, +{ "cplt", 0x40000000, "c,a,b" }, +{ "cplt", 0x41000000, "c,a,i" }, +{ "cpltu", 0x42000000, "c,a,b" }, +{ "cpltu", 0x43000000, "c,a,i" }, +{ "cpneq", 0x62000000, "c,a,b" }, +{ "cpneq", 0x63000000, "c,a,i" }, +{ "dadd", 0xf1000000, "c,a,b" }, +{ "ddiv", 0xf7000000, "c,a,b" }, +{ "deq", 0xeb000000, "c,a,b" }, +{ "dge", 0xef000000, "c,a,b" }, +{ "dgt", 0xed000000, "c,a,b" }, +{ "div", 0x6a000000, "c,a,b" }, +{ "div", 0x6b000000, "c,a,i" }, +{ "div0", 0x68000000, "c,b" }, +{ "div0", 0x69000000, "c,i" }, +{ "divide", 0xe1000000, "c,a,b" }, +{ "dividu", 0xe3000000, "c,a,b" }, +{ "divl", 0x6c000000, "c,a,b" }, +{ "divl", 0x6d000000, "c,a,i" }, +{ "divrem", 0x6e000000, "c,a,b" }, +{ "divrem", 0x6f000000, "c,a,i" }, +{ "dmac", 0xd9000000, "F,C,a,b" }, +{ "dmsm", 0xdb000000, "c,a,b" }, +{ "dmul", 0xf5000000, "c,a,b" }, +{ "dsub", 0xf3000000, "c,a,b" }, +{ "emulate", 0xd7000000, "v,a,b" }, +{ "exbyte", 0x0a000000, "c,a,b" }, +{ "exbyte", 0x0b000000, "c,a,i" }, +{ "exhw", 0x7c000000, "c,a,b" }, +{ "exhw", 0x7d000000, "c,a,i" }, +{ "exhws", 0x7e000000, "c,a" }, +{ "extract", 0x7a000000, "c,a,b" }, +{ "extract", 0x7b000000, "c,a,i" }, +{ "fadd", 0xf0000000, "c,a,b" }, +{ "fdiv", 0xf6000000, "c,a,b" }, +{ "fdmul", 0xf9000000, "c,a,b" }, +{ "feq", 0xea000000, "c,a,b" }, +{ "fge", 0xee000000, "c,a,b" }, +{ "fgt", 0xec000000, "c,a,b" }, +{ "fmac", 0xd8000000, "F,C,a,b" }, +{ "fmsm", 0xda000000, "c,a,b" }, +{ "fmul", 0xf4000000, "c,a,b" }, +{ "fsub", 0xf2000000, "c,a,b" }, +{ "halt", 0x89000000, "" }, +{ "inbyte", 0x0c000000, "c,a,b" }, +{ "inbyte", 0x0d000000, "c,a,i" }, +{ "inhw", 0x78000000, "c,a,b" }, +{ "inhw", 0x79000000, "c,a,i" }, +{ "inv", 0x9f000000, "I" }, +{ "iret", 0x88000000, "" }, +{ "iretinv", 0x8c000000, "I" }, +{ "jmp", 0xa0000000, "P" }, +{ "jmp", 0xa1000000, "A" }, +{ "jmpf", 0xa4000000, "a,P" }, +{ "jmpf", 0xa5000000, "a,A" }, +{ "jmpfdec", 0xb4000000, "a,P" }, +{ "jmpfdec", 0xb5000000, "a,A" }, +{ "jmpfi", 0xc4000000, "a,b" }, +{ "jmpi", 0xc0000000, "b" }, +{ "jmpt", 0xac000000, "a,P" }, +{ "jmpt", 0xad000000, "a,A" }, +{ "jmpti", 0xcc000000, "a,b" }, +{ "load", 0x16000000, "e,n,a,b" }, +{ "load", 0x17000000, "e,n,a,i" }, +{ "loadl", 0x06000000, "e,n,a,b" }, +{ "loadl", 0x07000000, "e,n,a,i" }, +{ "loadm", 0x36000000, "e,n,a,b" }, +{ "loadm", 0x37000000, "e,n,a,i" }, +{ "loadset", 0x26000000, "e,n,a,b" }, +{ "loadset", 0x27000000, "e,n,a,i" }, +{ "mfacc", 0xe9000100, "c,d,f" }, +{ "mfsr", 0xc6000000, "c,s" }, +{ "mftlb", 0xb6000000, "c,a" }, +{ "mtacc", 0xe8010000, "a,d,f" }, +{ "mtsr", 0xce000000, "s,b" }, +{ "mtsrim", 0x04000000, "s,x" }, +{ "mttlb", 0xbe000000, "a,b" }, +{ "mul", 0x64000000, "c,a,b" }, +{ "mul", 0x65000000, "c,a,i" }, +{ "mull", 0x66000000, "c,a,b" }, +{ "mull", 0x67000000, "c,a,i" }, +{ "multiplu", 0xe2000000, "c,a,b" }, +{ "multiply", 0xe0000000, "c,a,b" }, +{ "multm", 0xde000000, "c,a,b" }, +{ "multmu", 0xdf000000, "c,a,b" }, +{ "mulu", 0x74000000, "c,a,b" }, +{ "mulu", 0x75000000, "c,a,i" }, +{ "nand", 0x9a000000, "c,a,b" }, +{ "nand", 0x9b000000, "c,a,i" }, +{ "nop", 0x70400101, "" }, +{ "nor", 0x98000000, "c,a,b" }, +{ "nor", 0x99000000, "c,a,i" }, +{ "or", 0x92000000, "c,a,b" }, +{ "or", 0x93000000, "c,a,i" }, +{ "orn", 0xaa000000, "c,a,b" }, +{ "orn", 0xab000000, "c,a,i" }, + +/* The description of "setip" in Chapter 8 ("instruction set") of the user's + manual claims that these are absolute register numbers. But section + 7.2.1 explains that they are not. The latter is correct, so print + these normally ("lr0", "lr5", etc.). */ +{ "setip", 0x9e000000, "c,a,b" }, + +{ "sll", 0x80000000, "c,a,b" }, +{ "sll", 0x81000000, "c,a,i" }, +{ "sqrt", 0xe5000000, "c,a,f" }, +{ "sra", 0x86000000, "c,a,b" }, +{ "sra", 0x87000000, "c,a,i" }, +{ "srl", 0x82000000, "c,a,b" }, +{ "srl", 0x83000000, "c,a,i" }, +{ "store", 0x1e000000, "e,n,a,b" }, +{ "store", 0x1f000000, "e,n,a,i" }, +{ "storel", 0x0e000000, "e,n,a,b" }, +{ "storel", 0x0f000000, "e,n,a,i" }, +{ "storem", 0x3e000000, "e,n,a,b" }, +{ "storem", 0x3f000000, "e,n,a,i" }, +{ "sub", 0x24000000, "c,a,b" }, +{ "sub", 0x25000000, "c,a,i" }, +{ "subc", 0x2c000000, "c,a,b" }, +{ "subc", 0x2d000000, "c,a,i" }, +{ "subcs", 0x28000000, "c,a,b" }, +{ "subcs", 0x29000000, "c,a,i" }, +{ "subcu", 0x2a000000, "c,a,b" }, +{ "subcu", 0x2b000000, "c,a,i" }, +{ "subr", 0x34000000, "c,a,b" }, +{ "subr", 0x35000000, "c,a,i" }, +{ "subrc", 0x3c000000, "c,a,b" }, +{ "subrc", 0x3d000000, "c,a,i" }, +{ "subrcs", 0x38000000, "c,a,b" }, +{ "subrcs", 0x39000000, "c,a,i" }, +{ "subrcu", 0x3a000000, "c,a,b" }, +{ "subrcu", 0x3b000000, "c,a,i" }, +{ "subrs", 0x30000000, "c,a,b" }, +{ "subrs", 0x31000000, "c,a,i" }, +{ "subru", 0x32000000, "c,a,b" }, +{ "subru", 0x33000000, "c,a,i" }, +{ "subs", 0x20000000, "c,a,b" }, +{ "subs", 0x21000000, "c,a,i" }, +{ "subu", 0x22000000, "c,a,b" }, +{ "subu", 0x23000000, "c,a,i" }, +{ "xnor", 0x96000000, "c,a,b" }, +{ "xnor", 0x97000000, "c,a,i" }, +{ "xor", 0x94000000, "c,a,b" }, +{ "xor", 0x95000000, "c,a,i" }, + +{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ +}; + +const unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1); diff --git a/include/opcode/alpha.h b/include/opcode/alpha.h new file mode 100644 index 000000000..efe16260e --- /dev/null +++ b/include/opcode/alpha.h @@ -0,0 +1,237 @@ +/* alpha.h -- Header file for Alpha opcode table + Copyright 1996, 1999, 2001, 2003 Free Software Foundation, Inc. + Contributed by Richard Henderson <rth@tamu.edu>, + patterned after the PPC opcode table written by Ian Lance Taylor. + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef OPCODE_ALPHA_H +#define OPCODE_ALPHA_H + +/* The opcode table is an array of struct alpha_opcode. */ + +struct alpha_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned mask; + + /* One bit flags for the opcode. These are primarily used to + indicate specific processors and environments support the + instructions. The defined values are listed below. */ + unsigned flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[4]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct alpha_opcode alpha_opcodes[]; +extern const unsigned alpha_num_opcodes; + +/* Values defined for the flags field of a struct alpha_opcode. */ + +/* CPU Availability */ +#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ +#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ +#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ +#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ +#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ +#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ +#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ + +#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) + +/* A macro to extract the major opcode from an instruction. */ +#define AXP_OP(i) (((i) >> 26) & 0x3F) + +/* The total number of major opcodes. */ +#define AXP_NOPS 0x40 + + +/* The operands table is an array of struct alpha_operand. */ + +struct alpha_operand +{ + /* The number of bits in the operand. */ + unsigned int bits : 5; + + /* How far the operand is left shifted in the instruction. */ + unsigned int shift : 5; + + /* The default relocation type for this operand. */ + signed int default_reloc : 16; + + /* One bit syntax flags. */ + unsigned int flags : 16; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned (*insert) (unsigned instruction, int op, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & AXP_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + int (*extract) (unsigned instruction, int *invalid); +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the alpha_opcodes table. */ + +extern const struct alpha_operand alpha_operands[]; +extern const unsigned alpha_num_operands; + +/* Values defined for the flags field of a struct alpha_operand. */ + +/* Mask for selecting the type for typecheck purposes */ +#define AXP_OPERAND_TYPECHECK_MASK \ + (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ + AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ + AXP_OPERAND_UNSIGNED) + +/* This operand does not actually exist in the assembler input. This + is used to support extended mnemonics, for which two operands fields + are identical. The assembler should call the insert function with + any op value. The disassembler should call the extract function, + ignore the return value, and check the value placed in the invalid + argument. */ +#define AXP_OPERAND_FAKE 01 + +/* The operand should be wrapped in parentheses rather than separated + from the previous by a comma. This is used for the load and store + instructions which want their operands to look like "Ra,disp(Rb)". */ +#define AXP_OPERAND_PARENS 02 + +/* Used in combination with PARENS, this supresses the supression of + the comma. This is used for "jmp Ra,(Rb),hint". */ +#define AXP_OPERAND_COMMA 04 + +/* This operand names an integer register. */ +#define AXP_OPERAND_IR 010 + +/* This operand names a floating point register. */ +#define AXP_OPERAND_FPR 020 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define AXP_OPERAND_RELATIVE 040 + +/* This operand takes signed values. */ +#define AXP_OPERAND_SIGNED 0100 + +/* This operand takes unsigned values. This exists primarily so that + a flags value of 0 can be treated as end-of-arguments. */ +#define AXP_OPERAND_UNSIGNED 0200 + +/* Supress overflow detection on this field. This is used for hints. */ +#define AXP_OPERAND_NOOVERFLOW 0400 + +/* Mask for optional argument default value. */ +#define AXP_OPERAND_OPTIONAL_MASK 07000 + +/* This operand defaults to zero. This is used for jump hints. */ +#define AXP_OPERAND_DEFAULT_ZERO 01000 + +/* This operand should default to the first (real) operand and is used + in conjunction with AXP_OPERAND_OPTIONAL. This allows + "and $0,3,$0" to be written as "and $0,3", etc. I don't like + it, but it's what DEC does. */ +#define AXP_OPERAND_DEFAULT_FIRST 02000 + +/* Similarly, this operand should default to the second (real) operand. + This allows "negl $0" instead of "negl $0,$0". */ +#define AXP_OPERAND_DEFAULT_SECOND 04000 + + +/* Register common names */ + +#define AXP_REG_V0 0 +#define AXP_REG_T0 1 +#define AXP_REG_T1 2 +#define AXP_REG_T2 3 +#define AXP_REG_T3 4 +#define AXP_REG_T4 5 +#define AXP_REG_T5 6 +#define AXP_REG_T6 7 +#define AXP_REG_T7 8 +#define AXP_REG_S0 9 +#define AXP_REG_S1 10 +#define AXP_REG_S2 11 +#define AXP_REG_S3 12 +#define AXP_REG_S4 13 +#define AXP_REG_S5 14 +#define AXP_REG_FP 15 +#define AXP_REG_A0 16 +#define AXP_REG_A1 17 +#define AXP_REG_A2 18 +#define AXP_REG_A3 19 +#define AXP_REG_A4 20 +#define AXP_REG_A5 21 +#define AXP_REG_T8 22 +#define AXP_REG_T9 23 +#define AXP_REG_T10 24 +#define AXP_REG_T11 25 +#define AXP_REG_RA 26 +#define AXP_REG_PV 27 +#define AXP_REG_T12 27 +#define AXP_REG_AT 28 +#define AXP_REG_GP 29 +#define AXP_REG_SP 30 +#define AXP_REG_ZERO 31 + +#endif /* OPCODE_ALPHA_H */ diff --git a/include/opcode/arc.h b/include/opcode/arc.h new file mode 100644 index 000000000..629979d54 --- /dev/null +++ b/include/opcode/arc.h @@ -0,0 +1,323 @@ +/* Opcode table for the ARC. + Copyright 1994, 1995, 1997, 2001, 2002, 2003 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and + the GNU Binutils. + + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, Boston, + MA 02111-1307, USA. */ + + +/* List of the various cpu types. + The tables currently use bit masks to say whether the instruction or + whatever is supported by a particular cpu. This lets us have one entry + apply to several cpus. + + The `base' cpu must be 0. The cpu type is treated independently of + endianness. The complete `mach' number includes endianness. + These values are internal to opcodes/bfd/binutils/gas. */ +#define ARC_MACH_5 0 +#define ARC_MACH_6 1 +#define ARC_MACH_7 2 +#define ARC_MACH_8 4 + +/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ +#define ARC_MACH_BIG 16 + +/* Mask of number of bits necessary to record cpu type. */ +#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) + +/* Mask of number of bits necessary to record cpu type + endianness. */ +#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) + +/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ + +typedef unsigned int arc_insn; + +struct arc_opcode { + char *syntax; /* syntax of insn */ + unsigned long mask, value; /* recognize insn if (op&mask) == value */ + int flags; /* various flag bits */ + +/* Values for `flags'. */ + +/* Return CPU number, given flag bits. */ +#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) + +/* Return MACH number, given flag bits. */ +#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) + +/* First opcode flag bit available after machine mask. */ +#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) + +/* This insn is a conditional branch. */ +#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) +#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) +#define SYNTAX_LENGTH (SYNTAX_3OP ) +#define SYNTAX_2OP (SYNTAX_3OP << 1) +#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) +#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) +#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) + +#define I(x) (((x) & 31) << 27) +#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) +#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) +#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) +#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ + +/* These values are used to optimize assembly and disassembly. Each insn + is on a list of related insns (same first letter for assembly, same + insn code for disassembly). */ + + struct arc_opcode *next_asm; /* Next instr to try during assembly. */ + struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ + +/* Macros to create the hash values for the lists. */ +#define ARC_HASH_OPCODE(string) \ + ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) +#define ARC_HASH_ICODE(insn) \ + ((unsigned int) (insn) >> 27) + + /* Macros to access `next_asm', `next_dis' so users needn't care about the + underlying mechanism. */ +#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) +#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) +}; + +/* this is an "insert at front" linked list per Metaware spec + that new definitions override older ones. */ +extern struct arc_opcode *arc_ext_opcodes; + +struct arc_operand_value { + char *name; /* eg: "eq" */ + short value; /* eg: 1 */ + unsigned char type; /* index into `arc_operands' */ + unsigned char flags; /* various flag bits */ + +/* Values for `flags'. */ + +/* Return CPU number, given flag bits. */ +#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* Return MACH number, given flag bits. */ +#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) +}; + +struct arc_ext_operand_value { + struct arc_ext_operand_value *next; + struct arc_operand_value operand; +}; + +extern struct arc_ext_operand_value *arc_ext_operands; + +struct arc_operand { +/* One of the insn format chars. */ + unsigned char fmt; + +/* The number of bits in the operand (may be unused for a modifier). */ + unsigned char bits; + +/* How far the operand is left shifted in the instruction, or + the modifier's flag bit (may be unused for a modifier. */ + unsigned char shift; + +/* Various flag bits. */ + int flags; + +/* Values for `flags'. */ + +/* This operand is a suffix to the opcode. */ +#define ARC_OPERAND_SUFFIX 1 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_RELATIVE_BRANCH 2 + +/* This operand is an absolute branch address. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_ABSOLUTE_BRANCH 4 + +/* This operand is an address. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_ADDRESS 8 + +/* This operand is a long immediate value. */ +#define ARC_OPERAND_LIMM 0x10 + +/* This operand takes signed values. */ +#define ARC_OPERAND_SIGNED 0x20 + +/* This operand takes signed values, but also accepts a full positive + range of values. That is, if bits is 16, it takes any value from + -0x8000 to 0xffff. */ +#define ARC_OPERAND_SIGNOPT 0x40 + +/* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ +#define ARC_OPERAND_NEGATIVE 0x80 + +/* This operand doesn't really exist. The program uses these operands + in special ways. */ +#define ARC_OPERAND_FAKE 0x100 + +/* separate flags operand for j and jl instructions */ +#define ARC_OPERAND_JUMPFLAGS 0x200 + +/* allow warnings and errors to be issued after call to insert_xxxxxx */ +#define ARC_OPERAND_WARN 0x400 +#define ARC_OPERAND_ERROR 0x800 + +/* this is a load operand */ +#define ARC_OPERAND_LOAD 0x8000 + +/* this is a store operand */ +#define ARC_OPERAND_STORE 0x10000 + +/* Modifier values. */ +/* A dot is required before a suffix. Eg: .le */ +#define ARC_MOD_DOT 0x1000 + +/* A normal register is allowed (not used, but here for completeness). */ +#define ARC_MOD_REG 0x2000 + +/* An auxiliary register name is expected. */ +#define ARC_MOD_AUXREG 0x4000 + +/* Sum of all ARC_MOD_XXX bits. */ +#define ARC_MOD_BITS 0x7000 + +/* Non-zero if the operand type is really a modifier. */ +#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) + +/* enforce read/write only register restrictions */ +#define ARC_REGISTER_READONLY 0x01 +#define ARC_REGISTER_WRITEONLY 0x02 +#define ARC_REGISTER_NOSHORT_CUT 0x04 + +/* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (p & ((1 << o->bits) - 1)) << o->shift; + (I is the instruction which we are filling in, O is a pointer to + this structure, and OP is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged. + + REG is non-NULL when inserting a register value. */ + + arc_insn (*insert) + (arc_insn insn, const struct arc_operand *operand, int mods, + const struct arc_operand_value *reg, long value, const char **errmsg); + +/* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & ARC_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (I is the instruction, O is a pointer to this structure, and OP + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. + + INSN is a pointer to an array of two `arc_insn's. The first element is + the insn, the second is the limm if present. + + Operands that have a printable form like registers and suffixes have + their struct arc_operand_value pointer stored in OPVAL. */ + + long (*extract) + (arc_insn *insn, const struct arc_operand *operand, int mods, + const struct arc_operand_value **opval, int *invalid); +}; + +/* Bits that say what version of cpu we have. These should be passed to + arc_init_opcode_tables. At present, all there is is the cpu type. */ + +/* CPU number, given value passed to `arc_init_opcode_tables'. */ +#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* MACH number, given value passed to `arc_init_opcode_tables'. */ +#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) + +/* Special register values: */ +#define ARC_REG_SHIMM_UPDATE 61 +#define ARC_REG_SHIMM 63 +#define ARC_REG_LIMM 62 + +/* Non-zero if REG is a constant marker. */ +#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) + +/* Positions and masks of various fields: */ +#define ARC_SHIFT_REGA 21 +#define ARC_SHIFT_REGB 15 +#define ARC_SHIFT_REGC 9 +#define ARC_MASK_REG 63 + +/* Delay slot types. */ +#define ARC_DELAY_NONE 0 /* no delay slot */ +#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ +#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ + +/* Non-zero if X will fit in a signed 9 bit field. */ +#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) + +extern const struct arc_operand arc_operands[]; +extern const int arc_operand_count; +extern struct arc_opcode arc_opcodes[]; +extern const int arc_opcodes_count; +extern const struct arc_operand_value arc_suffixes[]; +extern const int arc_suffixes_count; +extern const struct arc_operand_value arc_reg_names[]; +extern const int arc_reg_names_count; +extern unsigned char arc_operand_map[]; + +/* Utility fns in arc-opc.c. */ +int arc_get_opcode_mach (int, int); + +/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ +void arc_opcode_init_tables (int); +void arc_opcode_init_insert (void); +void arc_opcode_init_extract (void); +const struct arc_opcode *arc_opcode_lookup_asm (const char *); +const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); +int arc_opcode_limm_p (long *); +const struct arc_operand_value *arc_opcode_lookup_suffix + (const struct arc_operand *type, int value); +int arc_opcode_supported (const struct arc_opcode *); +int arc_opval_supported (const struct arc_operand_value *); +int arc_limm_fixup_adjust (arc_insn); +int arc_insn_is_j (arc_insn); +int arc_insn_not_jl (arc_insn); +int arc_operand_type (int); +struct arc_operand_value *get_ext_suffix (char *); +int arc_get_noshortcut_flag (void); diff --git a/include/opcode/arm.h b/include/opcode/arm.h new file mode 100644 index 000000000..dd90e2ac6 --- /dev/null +++ b/include/opcode/arm.h @@ -0,0 +1,96 @@ +/* ARM assembler/disassembler support. + Copyright 2004 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + GDB and GAS are free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 1, or (at + your option) any later version. + + GDB and GAS are distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB or GAS; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* The following bitmasks control CPU extensions: */ +#define ARM_EXT_V1 0x00000001 /* All processors (core set). */ +#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ +#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ +#define ARM_EXT_V3 0x00000008 /* MSR MRS. */ +#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ +#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ +#define ARM_EXT_V4T 0x00000040 /* Thumb v1. */ +#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ +#define ARM_EXT_V5T 0x00000100 /* Thumb v2. */ +#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ +#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ +#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ +#define ARM_EXT_V6 0x00001000 /* ARM V6. */ +#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ +#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ + +/* Co-processor space extensions. */ +#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */ +#define ARM_CEXT_MAVERICK 0x00400000 /* Use Cirrus/DSP coprocessor. */ +#define ARM_CEXT_IWMMXT 0x00200000 /* Intel Wireless MMX technology coprocessor. */ + +/* Architectures are the sum of the base and extensions. The ARM ARM (rev E) + defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, + ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add + three more to cover cores prior to ARM6. Finally, there are cores which + implement further extensions in the co-processor space. */ +#define ARM_ARCH_V1 ARM_EXT_V1 +#define ARM_ARCH_V2 (ARM_ARCH_V1 | ARM_EXT_V2) +#define ARM_ARCH_V2S (ARM_ARCH_V2 | ARM_EXT_V2S) +#define ARM_ARCH_V3 (ARM_ARCH_V2S | ARM_EXT_V3) +#define ARM_ARCH_V3M (ARM_ARCH_V3 | ARM_EXT_V3M) +#define ARM_ARCH_V4xM (ARM_ARCH_V3 | ARM_EXT_V4) +#define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_V4) +#define ARM_ARCH_V4TxM (ARM_ARCH_V4xM | ARM_EXT_V4T) +#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_V4T) +#define ARM_ARCH_V5xM (ARM_ARCH_V4xM | ARM_EXT_V5) +#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5) +#define ARM_ARCH_V5TxM (ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP) +#define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E) +#define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J) +#define ARM_ARCH_V6 (ARM_ARCH_V5TEJ | ARM_EXT_V6) +#define ARM_ARCH_V6K (ARM_ARCH_V6 | ARM_EXT_V6K) +#define ARM_ARCH_V6Z (ARM_ARCH_V6 | ARM_EXT_V6Z) +#define ARM_ARCH_V6ZK (ARM_ARCH_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) + +/* Processors with specific extensions in the co-processor space. */ +#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE) +#define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT) + +#define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */ +#define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */ +#define FPU_VFP_EXT_NONE 0x20000000 /* Use VFP word-ordering. */ +#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */ +#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */ +#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */ +#define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */ +#define FPU_NONE 0 + +#define FPU_ARCH_FPE FPU_FPA_EXT_V1 +#define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2) + +#define FPU_ARCH_VFP FPU_VFP_EXT_NONE +#define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE) +#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1) +#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2) + +#define FPU_ARCH_MAVERICK FPU_MAVERICK + +/* Some useful combinations: */ +#define ARM_ANY 0x0000ffff /* Any basic core. */ +#define ARM_ALL 0x00ffffff /* Any core + co-processor */ +#define CPROC_ANY 0x00ff0000 /* Any co-processor */ +#define FPU_ANY 0xff000000 /* Note this is ~ARM_ALL. */ diff --git a/include/opcode/avr.h b/include/opcode/avr.h new file mode 100644 index 000000000..463482348 --- /dev/null +++ b/include/opcode/avr.h @@ -0,0 +1,265 @@ +/* Opcode table for the Atmel AVR micro controllers. + + Copyright 2000 Free Software Foundation, Inc. + Contributed by Denis Chertykov <denisc@overta.ru> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define AVR_ISA_1200 0x0001 /* in the beginning there was ... */ +#define AVR_ISA_LPM 0x0002 /* device has LPM */ +#define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ +#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ +#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL + supported, no 8K wrap on RJMP and RCALL) */ +#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */ +#define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ +#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ +#define AVR_ISA_SPM 0x0200 /* device can program itself */ +#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ +#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ +#define AVR_ISA_MOVW 0x1000 /* device has MOVW */ + +#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) +#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) +#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \ + AVR_ISA_SPM | AVR_ISA_BRK) +#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \ + AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) +#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) +#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \ + AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX) +#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) +#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) + +#define AVR_ISA_ALL 0xFFFF + +#define REGISTER_P(x) ((x) == 'r' \ + || (x) == 'd' \ + || (x) == 'w' \ + || (x) == 'a' \ + || (x) == 'v') + +/* Undefined combination of operands - does the register + operand overlap with pre-decremented or post-incremented + pointer register (like ld r31,Z+)? */ +#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 || \ + ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE || \ + ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA || \ + ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2) + +/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}? */ +#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 || \ + ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00) + +/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as + `ld r,b' or `st b,r' respectively - next opcode entry)? */ +#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) + +/* constraint letters + r - any register + d - `ldi' register (r16-r31) + v - `movw' even register (r0, r2, ..., r28, r30) + a - `fmul' register (r16-r23) + w - `adiw' register (r24,r26,r28,r30) + e - pointer registers (X,Y,Z) + b - base pointer register and displacement ([YZ]+disp) + z - Z pointer register (for [e]lpm Rd,Z[+]) + M - immediate value from 0 to 255 + n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible + s - immediate value from 0 to 7 + P - Port address value from 0 to 63. (in, out) + p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) + K - immediate value from 0 to 63 (used in `adiw', `sbiw') + i - immediate value + l - signed pc relative offset from -64 to 63 + L - signed pc relative offset from -2048 to 2047 + h - absolute code address (call, jmp) + S - immediate value from 0 to 7 (S = s << 4) + ? - use this opcode entry if no parameters, else use next opcode entry + + Order is important - some binary opcodes have more than one name, + the disassembler will only see the first match. + + Remaining undefined opcodes (1699 total - some of them might work + as normal instructions if not all of the bits are decoded): + + 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) + "100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b] + "100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8 + "1001001xxxxx01xx" (128) 0x9[23][0-9a-f][4-7] + "1001010xxxxx0100" (32) 0x9[45][0-9a-f]4 + "1001010x001x1001" (4) 0x9[45][23]9 + "1001010x01xx1001" (8) 0x9[45][4-7]9 + "1001010x1xxx1001" (16) 0x9[45][8-9a-f]9 + "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b + "10010101001x1000" (2) 0x95[23]8 + "1001010101xx1000" (4) 0x95[4-7]8 + "1001010110111000" (1) 0x95b8 + "1001010111111000" (1) 0x95f8 (`espm' removed in databook update) + "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f] + */ + +AVR_INSN (clc, "", "1001010010001000", 1, AVR_ISA_1200, 0x9488) +AVR_INSN (clh, "", "1001010011011000", 1, AVR_ISA_1200, 0x94d8) +AVR_INSN (cli, "", "1001010011111000", 1, AVR_ISA_1200, 0x94f8) +AVR_INSN (cln, "", "1001010010101000", 1, AVR_ISA_1200, 0x94a8) +AVR_INSN (cls, "", "1001010011001000", 1, AVR_ISA_1200, 0x94c8) +AVR_INSN (clt, "", "1001010011101000", 1, AVR_ISA_1200, 0x94e8) +AVR_INSN (clv, "", "1001010010111000", 1, AVR_ISA_1200, 0x94b8) +AVR_INSN (clz, "", "1001010010011000", 1, AVR_ISA_1200, 0x9498) + +AVR_INSN (sec, "", "1001010000001000", 1, AVR_ISA_1200, 0x9408) +AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458) +AVR_INSN (sei, "", "1001010001111000", 1, AVR_ISA_1200, 0x9478) +AVR_INSN (sen, "", "1001010000101000", 1, AVR_ISA_1200, 0x9428) +AVR_INSN (ses, "", "1001010001001000", 1, AVR_ISA_1200, 0x9448) +AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468) +AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438) +AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) + + /* Same as {cl,se}[chinstvz] above. */ +AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) +AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) + +AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509) +AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409) + +AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) +AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) +AVR_INSN (elpm, "?", "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8) +AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006) + +AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000) +AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508) +AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518) +AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588) +AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598) +AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8) +AVR_INSN (spm, "", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8) + +AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) +AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) +AVR_INSN (and, "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) +AVR_INSN (cp, "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400) +AVR_INSN (cpc, "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400) +AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000) +AVR_INSN (eor, "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) +AVR_INSN (mov, "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00) +AVR_INSN (mul, "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL, 0x9c00) +AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800) +AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800) +AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800) + + /* Shorthand for {eor,add,adc,and} r,r above. */ +AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) +AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) +AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) +AVR_INSN (tst, "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) + +AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) + /*XXX special case*/ +AVR_INSN (cbr, "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) + +AVR_INSN (ldi, "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000) +AVR_INSN (ser, "d", "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f) + +AVR_INSN (ori, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) +AVR_INSN (sbr, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) + +AVR_INSN (cpi, "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000) +AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000) +AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000) + +AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00) +AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00) +AVR_INSN (bld, "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800) +AVR_INSN (bst, "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00) + +AVR_INSN (in, "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000) +AVR_INSN (out, "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800) + +AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600) +AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700) + +AVR_INSN (cbi, "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800) +AVR_INSN (sbi, "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00) +AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900) +AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00) + +AVR_INSN (brcc, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brcs, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) +AVR_INSN (breq, "l", "111100lllllll001", 1, AVR_ISA_1200, 0xf001) +AVR_INSN (brge, "l", "111101lllllll100", 1, AVR_ISA_1200, 0xf404) +AVR_INSN (brhc, "l", "111101lllllll101", 1, AVR_ISA_1200, 0xf405) +AVR_INSN (brhs, "l", "111100lllllll101", 1, AVR_ISA_1200, 0xf005) +AVR_INSN (brid, "l", "111101lllllll111", 1, AVR_ISA_1200, 0xf407) +AVR_INSN (brie, "l", "111100lllllll111", 1, AVR_ISA_1200, 0xf007) +AVR_INSN (brlo, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) +AVR_INSN (brlt, "l", "111100lllllll100", 1, AVR_ISA_1200, 0xf004) +AVR_INSN (brmi, "l", "111100lllllll010", 1, AVR_ISA_1200, 0xf002) +AVR_INSN (brne, "l", "111101lllllll001", 1, AVR_ISA_1200, 0xf401) +AVR_INSN (brpl, "l", "111101lllllll010", 1, AVR_ISA_1200, 0xf402) +AVR_INSN (brsh, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brtc, "l", "111101lllllll110", 1, AVR_ISA_1200, 0xf406) +AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006) +AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403) +AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003) + + /* Same as br?? above. */ +AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000) + +AVR_INSN (rcall, "L", "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000) +AVR_INSN (rjmp, "L", "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000) + +AVR_INSN (call, "h", "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e) +AVR_INSN (jmp, "h", "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c) + +AVR_INSN (asr, "r", "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405) +AVR_INSN (com, "r", "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400) +AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) +AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) +AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) +AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) +AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f) +AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f) +AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) +AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) + + /* Known to be decoded as `nop' by the old core. */ +AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) +AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) +AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) +AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) +AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) +AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) + +AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) +AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) + + /* Special case for b+0, `e' must be next entry after `b', + b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ +AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000) +AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000) +AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200) +AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200) + + /* These are for devices that don't exist yet + (>128K program memory, PC = EIND:Z). */ +AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) +AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) + diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h new file mode 100644 index 000000000..16366fd0d --- /dev/null +++ b/include/opcode/cgen.h @@ -0,0 +1,1460 @@ +/* Header file for targets using CGEN: Cpu tools GENerator. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 +Free Software Foundation, Inc. + +This file is part of GDB, the GNU debugger, and the GNU Binutils. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef CGEN_H +#define CGEN_H + +/* ??? This file requires bfd.h but only to get bfd_vma. + Seems like an awful lot to require just to get such a fundamental type. + Perhaps the definition of bfd_vma can be moved outside of bfd.h. + Or perhaps one could duplicate its definition in another file. + Until such time, this file conditionally compiles definitions that require + bfd_vma using __BFD_H_SEEN__. */ + +/* Enums must be defined before they can be used. + Allow them to be used in struct definitions, even though the enum must + be defined elsewhere. + If CGEN_ARCH isn't defined, this file is being included by something other + than <arch>-desc.h. */ + +/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. + The lack of spaces in the arg list is important for non-stdc systems. + This file is included by <arch>-desc.h. + It can be included independently of <arch>-desc.h, in which case the arch + dependent portions will be declared as "unknown_cgen_foo". */ + +#ifndef CGEN_SYM +#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) +#endif + +/* This file contains the static (unchanging) pieces and as much other stuff + as we can reasonably put here. It's generally cleaner to put stuff here + rather than having it machine generated if possible. */ + +/* The assembler syntax is made up of expressions (duh...). + At the lowest level the values are mnemonics, register names, numbers, etc. + Above that are subexpressions, if any (an example might be the + "effective address" in m68k cpus). Subexpressions are wip. + At the second highest level are the insns themselves. Above that are + pseudo-insns, synthetic insns, and macros, if any. */ + +/* Lots of cpu's have a fixed insn size, or one which rarely changes, + and it's generally easier to handle these by treating the insn as an + integer type, rather than an array of characters. So we allow targets + to control this. When an integer type the value is in host byte order, + when an array of characters the value is in target byte order. */ + +typedef unsigned int CGEN_INSN_INT; +#if CGEN_INT_INSN_P +typedef CGEN_INSN_INT CGEN_INSN_BYTES; +typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; +#else +typedef unsigned char *CGEN_INSN_BYTES; +typedef unsigned char *CGEN_INSN_BYTES_PTR; +#endif + +#ifdef __GNUC__ +#define CGEN_INLINE __inline__ +#else +#define CGEN_INLINE +#endif + +enum cgen_endian +{ + CGEN_ENDIAN_UNKNOWN, + CGEN_ENDIAN_LITTLE, + CGEN_ENDIAN_BIG +}; + +/* Forward decl. */ + +typedef struct cgen_insn CGEN_INSN; + +/* Opaque pointer version for use by external world. */ + +typedef struct cgen_cpu_desc *CGEN_CPU_DESC; + +/* Attributes. + Attributes are used to describe various random things associated with + an object (ifield, hardware, operand, insn, whatever) and are specified + as name/value pairs. + Integer attributes computed at compile time are currently all that's + supported, though adding string attributes and run-time computation is + straightforward. Integer attribute values are always host int's + (signed or unsigned). For portability, this means 32 bits. + Integer attributes are further categorized as boolean, bitset, integer, + and enum types. Boolean attributes appear frequently enough that they're + recorded in one host int. This limits the maximum number of boolean + attributes to 32, though that's a *lot* of attributes. */ + +/* Type of attribute values. */ + +typedef int CGEN_ATTR_VALUE_TYPE; + +/* Struct to record attribute information. */ + +typedef struct +{ + /* Boolean attributes. */ + unsigned int bool; + /* Non-boolean integer attributes. */ + CGEN_ATTR_VALUE_TYPE nonbool[1]; +} CGEN_ATTR; + +/* Define a structure member for attributes with N non-boolean entries. + There is no maximum number of non-boolean attributes. + There is a maximum of 32 boolean attributes (since they are all recorded + in one host int). */ + +#define CGEN_ATTR_TYPE(n) \ +struct { unsigned int bool; \ + CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } + +/* Return the boolean attributes. */ + +#define CGEN_ATTR_BOOLS(a) ((a)->bool) + +/* Non-boolean attribute numbers are offset by this much. */ + +#define CGEN_ATTR_NBOOL_OFFSET 32 + +/* Given a boolean attribute number, return its mask. */ + +#define CGEN_ATTR_MASK(attr) (1 << (attr)) + +/* Return the value of boolean attribute ATTR in ATTRS. */ + +#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) + +/* Return value of attribute ATTR in ATTR_TABLE for OBJ. + OBJ is a pointer to the entity that has the attributes + (??? not used at present but is reserved for future purposes - eventually + the goal is to allow recording attributes in source form and computing + them lazily at runtime, not sure of the details yet). */ + +#define CGEN_ATTR_VALUE(obj, attr_table, attr) \ +((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ + ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ + : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET])) + +/* Attribute name/value tables. + These are used to assist parsing of descriptions at run-time. */ + +typedef struct +{ + const char * name; + CGEN_ATTR_VALUE_TYPE value; +} CGEN_ATTR_ENTRY; + +/* For each domain (ifld,hw,operand,insn), list of attributes. */ + +typedef struct +{ + const char * name; + const CGEN_ATTR_ENTRY * dfault; + const CGEN_ATTR_ENTRY * vals; +} CGEN_ATTR_TABLE; + +/* Instruction set variants. */ + +typedef struct { + const char *name; + + /* Default instruction size (in bits). + This is used by the assembler when it encounters an unknown insn. */ + unsigned int default_insn_bitsize; + + /* Base instruction size (in bits). + For non-LIW cpus this is generally the length of the smallest insn. + For LIW cpus its wip (work-in-progress). For the m32r its 32. */ + unsigned int base_insn_bitsize; + + /* Minimum/maximum instruction size (in bits). */ + unsigned int min_insn_bitsize; + unsigned int max_insn_bitsize; +} CGEN_ISA; + +/* Machine variants. */ + +typedef struct { + const char *name; + /* The argument to bfd_arch_info->scan. */ + const char *bfd_name; + /* one of enum mach_attr */ + int num; + /* parameter from mach->cpu */ + unsigned int insn_chunk_bitsize; +} CGEN_MACH; + +/* Parse result (also extraction result). + + The result of parsing an insn is stored here. + To generate the actual insn, this is passed to the insert handler. + When printing an insn, the result of extraction is stored here. + To print the insn, this is passed to the print handler. + + It is machine generated so we don't define it here, + but we do need a forward decl for the handler fns. + + There is one member for each possible field in the insn. + The type depends on the field. + Also recorded here is the computed length of the insn for architectures + where it varies. +*/ + +typedef struct cgen_fields CGEN_FIELDS; + +/* Total length of the insn, as recorded in the `fields' struct. */ +/* ??? The field insert handler has lots of opportunities for optimization + if it ever gets inlined. On architectures where insns all have the same + size, may wish to detect that and make this macro a constant - to allow + further optimizations. */ + +#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) + +/* Extraction support for variable length insn sets. */ + +/* When disassembling we don't know the number of bytes to read at the start. + So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest + are read when needed. This struct controls this. It is basically the + disassemble_info stuff, except that we provide a cache for values already + read (since bytes can typically be read several times to fetch multiple + operands that may be in them), and that extraction of fields is needed + in contexts other than disassembly. */ + +typedef struct { + /* A pointer to the disassemble_info struct. + We don't require dis-asm.h so we use void * for the type here. + If NULL, BYTES is full of valid data (VALID == -1). */ + void *dis_info; + /* Points to a working buffer of sufficient size. */ + unsigned char *insn_bytes; + /* Mask of bytes that are valid in INSN_BYTES. */ + unsigned int valid; +} CGEN_EXTRACT_INFO; + +/* Associated with each insn or expression is a set of "handlers" for + performing operations like parsing, printing, etc. These require a bfd_vma + value to be passed around but we don't want all applications to need bfd.h. + So this stuff is only provided if bfd.h has been included. */ + +/* Parse handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + STRP is a pointer to a pointer to the text being parsed. + FIELDS is a pointer to a cgen_fields struct in which the results are placed. + If the expression is successfully parsed, *STRP is updated. + If not it is left alone. + The result is NULL if success or an error message. */ +typedef const char * (cgen_parse_fn) + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + const char **strp_, CGEN_FIELDS *fields_); + +/* Insert handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + FIELDS is a pointer to a cgen_fields struct from which the values + are fetched. + INSNP is a pointer to a buffer in which to place the insn. + PC is the pc value of the insn. + The result is an error message or NULL if success. */ + +#ifdef __BFD_H_SEEN__ +typedef const char * (cgen_insert_fn) + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, + bfd_vma pc_); +#else +typedef const char * (cgen_insert_fn) (); +#endif + +/* Extract handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + The second argument is a pointer to a struct controlling extraction + (only used for variable length insns). + EX_INFO is a pointer to a struct for controlling reading of further + bytes for the insn. + BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). + FIELDS is a pointer to a cgen_fields struct in which the results are placed. + PC is the pc value of the insn. + The result is the length of the insn in bits or zero if not recognized. */ + +#ifdef __BFD_H_SEEN__ +typedef int (cgen_extract_fn) + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, + CGEN_FIELDS *fields_, bfd_vma pc_); +#else +typedef int (cgen_extract_fn) (); +#endif + +/* Print handler. + CD is a cpu table descriptor. + INFO is a pointer to the disassembly info. + Eg: disassemble_info. It's defined as `PTR' so this file can be included + without dis-asm.h. + INSN is a pointer to a struct describing the insn being printed. + FIELDS is a pointer to a cgen_fields struct. + PC is the pc value of the insn. + LEN is the length of the insn, in bits. */ + +#ifdef __BFD_H_SEEN__ +typedef void (cgen_print_fn) + (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, bfd_vma pc_, int len_); +#else +typedef void (cgen_print_fn) (); +#endif + +/* Parse/insert/extract/print handlers. + + Indices into the handler tables. + We could use pointers here instead, but 90% of them are generally identical + and that's a lot of redundant data. Making these unsigned char indices + into tables of pointers saves a bit of space. + Using indices also keeps assembler code out of the disassembler and + vice versa. */ + +struct cgen_opcode_handler +{ + unsigned char parse, insert, extract, print; +}; + +/* Assembler interface. + + The interface to the assembler is intended to be clean in the sense that + libopcodes.a is a standalone entity and could be used with any assembler. + Not that one would necessarily want to do that but rather that it helps + keep a clean interface. The interface will obviously be slanted towards + GAS, but at least it's a start. + ??? Note that one possible user of the assembler besides GAS is GDB. + + Parsing is controlled by the assembler which calls + CGEN_SYM (assemble_insn). If it can parse and build the entire insn + it doesn't call back to the assembler. If it needs/wants to call back + to the assembler, cgen_parse_operand_fn is called which can either + + - return a number to be inserted in the insn + - return a "register" value to be inserted + (the register might not be a register per pe) + - queue the argument and return a marker saying the expression has been + queued (eg: a fix-up) + - return an error message indicating the expression wasn't recognizable + + The result is an error message or NULL for success. + The parsed value is stored in the bfd_vma *. */ + +/* Values for indicating what the caller wants. */ + +enum cgen_parse_operand_type +{ + CGEN_PARSE_OPERAND_INIT, + CGEN_PARSE_OPERAND_INTEGER, + CGEN_PARSE_OPERAND_ADDRESS +}; + +/* Values for indicating what was parsed. */ + +enum cgen_parse_operand_result +{ + CGEN_PARSE_OPERAND_RESULT_NUMBER, + CGEN_PARSE_OPERAND_RESULT_REGISTER, + CGEN_PARSE_OPERAND_RESULT_QUEUED, + CGEN_PARSE_OPERAND_RESULT_ERROR +}; + +#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ +typedef const char * (cgen_parse_operand_fn) + (CGEN_CPU_DESC, + enum cgen_parse_operand_type, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *); +#else +typedef const char * (cgen_parse_operand_fn) (); +#endif + +/* Set the cgen_parse_operand_fn callback. */ + +extern void cgen_set_parse_operand_fn + (CGEN_CPU_DESC, cgen_parse_operand_fn); + +/* Called before trying to match a table entry with the insn. */ + +extern void cgen_init_parse_operand (CGEN_CPU_DESC); + +/* Operand values (keywords, integers, symbols, etc.) */ + +/* Types of assembler elements. */ + +enum cgen_asm_type +{ + CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX +}; + +#ifndef CGEN_ARCH +enum cgen_hw_type { CGEN_HW_MAX }; +#endif + +/* List of hardware elements. */ + +typedef struct +{ + char *name; + enum cgen_hw_type type; + /* There is currently no example where both index specs and value specs + are required, so for now both are clumped under "asm_data". */ + enum cgen_asm_type asm_type; + void *asm_data; +#ifndef CGEN_HW_NBOOL_ATTRS +#define CGEN_HW_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; +#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) +} CGEN_HW_ENTRY; + +/* Return value of attribute ATTR in HW. */ + +#define CGEN_HW_ATTR_VALUE(hw, attr) \ +CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) + +/* Table of hardware elements for selected mach, computed at runtime. + enum cgen_hw_type is an index into this table (specifically `entries'). */ + +typedef struct { + /* Pointer to null terminated table of all compiled in entries. */ + const CGEN_HW_ENTRY *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + /* Array of all entries, initial and run-time added. */ + const CGEN_HW_ENTRY **entries; + /* Number of elements in `entries'. */ + unsigned int num_entries; + /* For now, xrealloc is called each time a new entry is added at runtime. + ??? May wish to keep track of some slop to reduce the number of calls to + xrealloc, except that there's unlikely to be many and not expected to be + in speed critical code. */ +} CGEN_HW_TABLE; + +extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name + (CGEN_CPU_DESC, const char *); +extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num + (CGEN_CPU_DESC, unsigned int); + +/* This struct is used to describe things like register names, etc. */ + +typedef struct cgen_keyword_entry +{ + /* Name (as in register name). */ + char * name; + + /* Value (as in register number). + The value cannot be -1 as that is used to indicate "not found". + IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ + int value; + + /* Attributes. + This should, but technically needn't, appear last. It is a variable sized + array in that one architecture may have 1 nonbool attribute and another + may have more. Having this last means the non-architecture specific code + needn't care. The goal is to eventually record + attributes in their raw form, evaluate them at run-time, and cache the + values, so this worry will go away anyway. */ + /* ??? Moving this last should be done by treating keywords like insn lists + and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ + /* FIXME: Not used yet. */ +#ifndef CGEN_KEYWORD_NBOOL_ATTRS +#define CGEN_KEYWORD_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; + + /* ??? Putting these here means compiled in entries can't be const. + Not a really big deal, but something to consider. */ + /* Next name hash table entry. */ + struct cgen_keyword_entry *next_name; + /* Next value hash table entry. */ + struct cgen_keyword_entry *next_value; +} CGEN_KEYWORD_ENTRY; + +/* Top level struct for describing a set of related keywords + (e.g. register names). + + This struct supports run-time entry of new values, and hashed lookups. */ + +typedef struct cgen_keyword +{ + /* Pointer to initial [compiled in] values. */ + CGEN_KEYWORD_ENTRY *init_entries; + + /* Number of entries in `init_entries'. */ + unsigned int num_init_entries; + + /* Hash table used for name lookup. */ + CGEN_KEYWORD_ENTRY **name_hash_table; + + /* Hash table used for value lookup. */ + CGEN_KEYWORD_ENTRY **value_hash_table; + + /* Number of entries in the hash_tables. */ + unsigned int hash_table_size; + + /* Pointer to null keyword "" entry if present. */ + const CGEN_KEYWORD_ENTRY *null_entry; + + /* String containing non-alphanumeric characters used + in keywords. + At present, the highest number of entries used is 1. */ + char nonalpha_chars[8]; +} CGEN_KEYWORD; + +/* Structure used for searching. */ + +typedef struct +{ + /* Table being searched. */ + const CGEN_KEYWORD *table; + + /* Specification of what is being searched for. */ + const char *spec; + + /* Current index in hash table. */ + unsigned int current_hash; + + /* Current element in current hash chain. */ + CGEN_KEYWORD_ENTRY *current_entry; +} CGEN_KEYWORD_SEARCH; + +/* Lookup a keyword from its name. */ + +const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name + (CGEN_KEYWORD *, const char *); + +/* Lookup a keyword from its value. */ + +const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value + (CGEN_KEYWORD *, int); + +/* Add a keyword. */ + +void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); + +/* Keyword searching. + This can be used to retrieve every keyword, or a subset. */ + +CGEN_KEYWORD_SEARCH cgen_keyword_search_init + (CGEN_KEYWORD *, const char *); +const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next + (CGEN_KEYWORD_SEARCH *); + +/* Operand value support routines. */ + +extern const char *cgen_parse_keyword + (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); +#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ +extern const char *cgen_parse_signed_integer + (CGEN_CPU_DESC, const char **, int, long *); +extern const char *cgen_parse_unsigned_integer + (CGEN_CPU_DESC, const char **, int, unsigned long *); +extern const char *cgen_parse_address + (CGEN_CPU_DESC, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *); +extern const char *cgen_validate_signed_integer + (long, long, long); +extern const char *cgen_validate_unsigned_integer + (unsigned long, unsigned long, unsigned long); +#endif + +/* Operand modes. */ + +/* ??? This duplicates the values in arch.h. Revisit. + These however need the CGEN_ prefix [as does everything in this file]. */ +/* ??? Targets may need to add their own modes so we may wish to move this + to <arch>-opc.h, or add a hook. */ + +enum cgen_mode { + CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ + CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, + CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, + CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, + CGEN_MODE_TARGET_MAX, + CGEN_MODE_INT, CGEN_MODE_UINT, + CGEN_MODE_MAX +}; + +/* FIXME: Until simulator is updated. */ + +#define CGEN_MODE_VM CGEN_MODE_VOID + +/* Operands. */ + +#ifndef CGEN_ARCH +enum cgen_operand_type { CGEN_OPERAND_MAX }; +#endif + +/* "nil" indicator for the operand instance table */ +#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX + +/* A tree of these structs represents the multi-ifield + structure of an operand's hw-index value, if it exists. */ + +struct cgen_ifld; + +typedef struct cgen_maybe_multi_ifield +{ + int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); + n: indexed by array of more cgen_maybe_multi_ifields. */ + union + { + const void *p; + const struct cgen_maybe_multi_ifield * multi; + const struct cgen_ifld * leaf; + } val; +} +CGEN_MAYBE_MULTI_IFLD; + +/* This struct defines each entry in the operand table. */ + +typedef struct +{ + /* Name as it appears in the syntax string. */ + char *name; + + /* Operand type. */ + enum cgen_operand_type type; + + /* The hardware element associated with this operand. */ + enum cgen_hw_type hw_type; + + /* FIXME: We don't yet record ifield definitions, which we should. + When we do it might make sense to delete start/length (since they will + be duplicated in the ifield's definition) and replace them with a + pointer to the ifield entry. */ + + /* Bit position. + This is just a hint, and may be unused in more complex operands. + May be unused for a modifier. */ + unsigned char start; + + /* The number of bits in the operand. + This is just a hint, and may be unused in more complex operands. + May be unused for a modifier. */ + unsigned char length; + + /* The (possibly-multi) ifield used as an index for this operand, if it + is indexed by a field at all. This substitutes / extends the start and + length fields above, but unsure at this time whether they are used + anywhere. */ + CGEN_MAYBE_MULTI_IFLD index_fields; +#if 0 /* ??? Interesting idea but relocs tend to get too complicated, + and ABI dependent, for simple table lookups to work. */ + /* Ideally this would be the internal (external?) reloc type. */ + int reloc_type; +#endif + + /* Attributes. + This should, but technically needn't, appear last. It is a variable sized + array in that one architecture may have 1 nonbool attribute and another + may have more. Having this last means the non-architecture specific code + needn't care, now or tomorrow. The goal is to eventually record + attributes in their raw form, evaluate them at run-time, and cache the + values, so this worry will go away anyway. */ +#ifndef CGEN_OPERAND_NBOOL_ATTRS +#define CGEN_OPERAND_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; +#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) +} CGEN_OPERAND; + +/* Return value of attribute ATTR in OPERAND. */ + +#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ +CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) + +/* Table of operands for selected mach/isa, computed at runtime. + enum cgen_operand_type is an index into this table (specifically + `entries'). */ + +typedef struct { + /* Pointer to null terminated table of all compiled in entries. */ + const CGEN_OPERAND *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + /* Array of all entries, initial and run-time added. */ + const CGEN_OPERAND **entries; + /* Number of elements in `entries'. */ + unsigned int num_entries; + /* For now, xrealloc is called each time a new entry is added at runtime. + ??? May wish to keep track of some slop to reduce the number of calls to + xrealloc, except that there's unlikely to be many and not expected to be + in speed critical code. */ +} CGEN_OPERAND_TABLE; + +extern const CGEN_OPERAND * cgen_operand_lookup_by_name + (CGEN_CPU_DESC, const char *); +extern const CGEN_OPERAND * cgen_operand_lookup_by_num + (CGEN_CPU_DESC, int); + +/* Instruction operand instances. + + For each instruction, a list of the hardware elements that are read and + written are recorded. */ + +/* The type of the instance. */ + +enum cgen_opinst_type { + /* End of table marker. */ + CGEN_OPINST_END = 0, + CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT +}; + +typedef struct +{ + /* Input or output indicator. */ + enum cgen_opinst_type type; + + /* Name of operand. */ + const char *name; + + /* The hardware element referenced. */ + enum cgen_hw_type hw_type; + + /* The mode in which the operand is being used. */ + enum cgen_mode mode; + + /* The operand table entry CGEN_OPERAND_NIL if there is none + (i.e. an explicit hardware reference). */ + enum cgen_operand_type op_type; + + /* If `operand' is "nil", the index (e.g. into array of registers). */ + int index; + + /* Attributes. + ??? This perhaps should be a real attribute struct but there's + no current need, so we save a bit of space and just have a set of + flags. The interface is such that this can easily be made attributes + should it prove useful. */ + unsigned int attrs; +#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) +/* Return value of attribute ATTR in OPINST. */ +#define CGEN_OPINST_ATTR(opinst, attr) \ +((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) +/* Operand is conditionally referenced (read/written). */ +#define CGEN_OPINST_COND_REF 1 +} CGEN_OPINST; + +/* Syntax string. + + Each insn format and subexpression has one of these. + + The syntax "string" consists of characters (n > 0 && n < 128), and operand + values (n >= 128), and is terminated by 0. Operand values are 128 + index + into the operand table. The operand table doesn't exist in C, per se, as + the data is recorded in the parse/insert/extract/print switch statements. */ + +/* This should be at least as large as necessary for any target. */ +#define CGEN_MAX_SYNTAX_ELEMENTS 48 + +/* A target may know its own precise maximum. Assert that it falls below + the above limit. */ +#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS +#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS +#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" +#endif +#endif + +typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; + +typedef struct +{ + CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; +} CGEN_SYNTAX; + +#define CGEN_SYNTAX_STRING(syn) (syn->syntax) +#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) +#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) +#define CGEN_SYNTAX_FIELD(c) ((c) - 128) +#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) + +/* ??? I can't currently think of any case where the mnemonic doesn't come + first [and if one ever doesn't building the hash tables will be tricky]. + However, we treat mnemonics as just another operand of the instruction. + A value of 1 means "this is where the mnemonic appears". 1 isn't + special other than it's a non-printable ASCII char. */ + +#define CGEN_SYNTAX_MNEMONIC 1 +#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) + +/* Instruction fields. + + ??? We currently don't allow adding fields at run-time. + Easy to fix when needed. */ + +typedef struct cgen_ifld { + /* Enum of ifield. */ + int num; +#define CGEN_IFLD_NUM(f) ((f)->num) + + /* Name of the field, distinguishes it from all other fields. */ + const char *name; +#define CGEN_IFLD_NAME(f) ((f)->name) + + /* Default offset, in bits, from the start of the insn to the word + containing the field. */ + int word_offset; +#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) + + /* Default length of the word containing the field. */ + int word_size; +#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) + + /* Default starting bit number. + Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ + int start; +#define CGEN_IFLD_START(f) ((f)->start) + + /* Length of the field, in bits. */ + int length; +#define CGEN_IFLD_LENGTH(f) ((f)->length) + +#ifndef CGEN_IFLD_NBOOL_ATTRS +#define CGEN_IFLD_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; +#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) +} CGEN_IFLD; + +/* Return value of attribute ATTR in IFLD. */ +#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ +CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) + +/* Instruction data. */ + +/* Instruction formats. + + Instructions are grouped by format. Associated with an instruction is its + format. Each insn's opcode table entry contains a format table entry. + ??? There is usually very few formats compared with the number of insns, + so one can reduce the size of the opcode table by recording the format table + as a separate entity. Given that we currently don't, format table entries + are also distinguished by their operands. This increases the size of the + table, but reduces the number of tables. It's all minutiae anyway so it + doesn't really matter [at this point in time]. + + ??? Support for variable length ISA's is wip. */ + +/* Accompanying each iformat description is a list of its fields. */ + +typedef struct { + const CGEN_IFLD *ifld; +#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) +} CGEN_IFMT_IFLD; + +/* This should be at least as large as necessary for any target. */ +#define CGEN_MAX_IFMT_OPERANDS 16 + +/* A target may know its own precise maximum. Assert that it falls below + the above limit. */ +#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS +#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS +#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" +#endif +#endif + + +typedef struct +{ + /* Length that MASK and VALUE have been calculated to + [VALUE is recorded elsewhere]. + Normally it is base_insn_bitsize. On [V]LIW architectures where the base + insn size may be larger than the size of an insn, this field is less than + base_insn_bitsize. */ + unsigned char mask_length; +#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) + + /* Total length of instruction, in bits. */ + unsigned char length; +#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) + + /* Mask to apply to the first MASK_LENGTH bits. + Each insn's value is stored with the insn. + The first step in recognizing an insn for disassembly is + (opcode & mask) == value. */ + CGEN_INSN_INT mask; +#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) + + /* Instruction fields. + +1 for trailing NULL. */ + CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; +#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) +} CGEN_IFMT; + +/* Instruction values. */ + +typedef struct +{ + /* The opcode portion of the base insn. */ + CGEN_INSN_INT base_value; + +#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS + /* Extra opcode values beyond base_value. */ + unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; +#endif +} CGEN_IVALUE; + +/* Instruction opcode table. + This contains the syntax and format data of an instruction. */ + +/* ??? Some ports already have an opcode table yet still need to use the rest + of what cgen_insn has. Plus keeping the opcode data with the operand + instance data can create a pretty big file. So we keep them separately. + Not sure this is a good idea in the long run. */ + +typedef struct +{ + /* Indices into parse/insert/extract/print handler tables. */ + struct cgen_opcode_handler handlers; +#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) + + /* Syntax string. */ + CGEN_SYNTAX syntax; +#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) + + /* Format entry. */ + const CGEN_IFMT *format; +#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) +#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) +#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) +#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) + + /* Instruction opcode value. */ + CGEN_IVALUE value; +#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) +#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) +#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) +} CGEN_OPCODE; + +/* Instruction attributes. + This is made a published type as applications can cache a pointer to + the attributes for speed. */ + +#ifndef CGEN_INSN_NBOOL_ATTRS +#define CGEN_INSN_NBOOL_ATTRS 1 +#endif +typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; + +/* Enum of architecture independent attributes. */ + +#ifndef CGEN_ARCH +/* ??? Numbers here are recorded in two places. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS = 0 +} CGEN_INSN_ATTR; +#endif + +/* This struct defines each entry in the instruction table. */ + +typedef struct +{ + /* Each real instruction is enumerated. */ + /* ??? This may go away in time. */ + int num; +#define CGEN_INSN_NUM(insn) ((insn)->base->num) + + /* Name of entry (that distinguishes it from all other entries). */ + /* ??? If mnemonics have operands, try to print full mnemonic. */ + const char *name; +#define CGEN_INSN_NAME(insn) ((insn)->base->name) + + /* Mnemonic. This is used when parsing and printing the insn. + In the case of insns that have operands on the mnemonics, this is + only the constant part. E.g. for conditional execution of an `add' insn, + where the full mnemonic is addeq, addne, etc., and the condition is + treated as an operand, this is only "add". */ + const char *mnemonic; +#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) + + /* Total length of instruction, in bits. */ + int bitsize; +#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) + +#if 0 /* ??? Disabled for now as there is a problem with embedded newlines + and the table is already pretty big. Should perhaps be moved + to a file of its own. */ + /* Semantics, as RTL. */ + /* ??? Plain text or bytecodes? */ + /* ??? Note that the operand instance table could be computed at run-time + if we parse this and cache the results. Something to eventually do. */ + const char *rtx; +#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) +#endif + + /* Attributes. + This must appear last. It is a variable sized array in that one + architecture may have 1 nonbool attribute and another may have more. + Having this last means the non-architecture specific code needn't + care. The goal is to eventually record attributes in their raw form, + evaluate them at run-time, and cache the values, so this worry will go + away anyway. */ + CGEN_INSN_ATTR_TYPE attrs; +#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) +/* Return value of attribute ATTR in INSN. */ +#define CGEN_INSN_ATTR_VALUE(insn, attr) \ +CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) +} CGEN_IBASE; + +/* Return non-zero if INSN is the "invalid" insn marker. */ + +#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) + +/* Main struct contain instruction information. + BASE is always present, the rest is present only if asked for. */ + +struct cgen_insn +{ + /* ??? May be of use to put a type indicator here. + Then this struct could different info for different classes of insns. */ + /* ??? A speedup can be had by moving `base' into this struct. + Maybe later. */ + const CGEN_IBASE *base; + const CGEN_OPCODE *opcode; + const CGEN_OPINST *opinst; + + /* Regex to disambiguate overloaded opcodes */ + void *rx; +#define CGEN_INSN_RX(insn) ((insn)->rx) +#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) +}; + +/* Instruction lists. + This is used for adding new entries and for creating the hash lists. */ + +typedef struct cgen_insn_list +{ + struct cgen_insn_list *next; + const CGEN_INSN *insn; +} CGEN_INSN_LIST; + +/* Table of instructions. */ + +typedef struct +{ + const CGEN_INSN *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + unsigned int num_init_entries; + CGEN_INSN_LIST *new_entries; +} CGEN_INSN_TABLE; + +/* Return number of instructions. This includes any added at run-time. */ + +extern int cgen_insn_count (CGEN_CPU_DESC); +extern int cgen_macro_insn_count (CGEN_CPU_DESC); + +/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ + +/* Fetch INSN's operand instance table. */ +/* ??? Doesn't handle insns added at runtime. */ +#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) + +/* Return INSN's opcode table entry. */ +#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) + +/* Return INSN's handler data. */ +#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) + +/* Return INSN's syntax. */ +#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) + +/* Return size of base mask in bits. */ +#define CGEN_INSN_MASK_BITSIZE(insn) \ + CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) + +/* Return mask of base part of INSN. */ +#define CGEN_INSN_BASE_MASK(insn) \ + CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) + +/* Return value of base part of INSN. */ +#define CGEN_INSN_BASE_VALUE(insn) \ + CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) + +/* Standard way to test whether INSN is supported by MACH. + MACH is one of enum mach_attr. + The "|1" is because the base mach is always selected. */ +#define CGEN_INSN_MACH_HAS_P(insn, mach) \ +((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) + +/* Macro instructions. + Macro insns aren't real insns, they map to one or more real insns. + E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or + some such. + + Macro insns can expand to nothing (e.g. a nop that is optimized away). + This is useful in multi-insn macros that build a constant in a register. + Of course this isn't the default behaviour and must be explicitly enabled. + + Assembly of macro-insns is relatively straightforward. Disassembly isn't. + However, disassembly of at least some kinds of macro insns is important + in order that the disassembled code preserve the readability of the original + insn. What is attempted here is to disassemble all "simple" macro-insns, + where "simple" is currently defined to mean "expands to one real insn". + + Simple macro-insns are handled specially. They are emitted as ALIAS's + of real insns. This simplifies their handling since there's usually more + of them than any other kind of macro-insn, and proper disassembly of them + falls out for free. */ + +/* For each macro-insn there may be multiple expansion possibilities, + depending on the arguments. This structure is accessed via the `data' + member of CGEN_INSN. */ + +typedef struct cgen_minsn_expansion { + /* Function to do the expansion. + If the expansion fails (e.g. "no match") NULL is returned. + Space for the expansion is obtained with malloc. + It is up to the caller to free it. */ + const char * (* fn) + (const struct cgen_minsn_expansion *, + const char *, const char **, int *, + CGEN_OPERAND **); +#define CGEN_MIEXPN_FN(ex) ((ex)->fn) + + /* Instruction(s) the macro expands to. + The format of STR is defined by FN. + It is typically the assembly code of the real insn, but it could also be + the original Scheme expression or a tokenized form of it (with FN being + an appropriate interpreter). */ + const char * str; +#define CGEN_MIEXPN_STR(ex) ((ex)->str) +} CGEN_MINSN_EXPANSION; + +/* Normal expander. + When supported, this function will convert the input string to another + string and the parser will be invoked recursively. The output string + may contain further macro invocations. */ + +extern const char * cgen_expand_macro_insn + (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, + const char *, const char **, int *, CGEN_OPERAND **); + +/* The assembler insn table is hashed based on some function of the mnemonic + (the actually hashing done is up to the target, but we provide a few + examples like the first letter or a function of the entire mnemonic). */ + +extern CGEN_INSN_LIST * cgen_asm_lookup_insn + (CGEN_CPU_DESC, const char *); +#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) +#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) + +/* The disassembler insn table is hashed based on some function of machine + instruction (the actually hashing done is up to the target). */ + +extern CGEN_INSN_LIST * cgen_dis_lookup_insn + (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); +/* FIXME: delete these two */ +#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) +#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) + +/* The CPU description. + A copy of this is created when the cpu table is "opened". + All global state information is recorded here. + Access macros are provided for "public" members. */ + +typedef struct cgen_cpu_desc +{ + /* Bitmap of selected machine(s) (a la BFD machine number). */ + int machs; + + /* Bitmap of selected isa(s). + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + int isas; + + /* Current endian. */ + enum cgen_endian endian; +#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) + + /* Current insn endian. */ + enum cgen_endian insn_endian; +#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) + + /* Word size (in bits). */ + /* ??? Or maybe maximum word size - might we ever need to allow a cpu table + to be opened for both sparc32/sparc64? + ??? Another alternative is to create a table of selected machs and + lazily fetch the data from there. */ + unsigned int word_bitsize; + + /* Instruction chunk size (in bits), for purposes of endianness + conversion. */ + unsigned int insn_chunk_bitsize; + + /* Indicator if sizes are unknown. + This is used by default_insn_bitsize,base_insn_bitsize if there is a + difference between the selected isa's. */ +#define CGEN_SIZE_UNKNOWN 65535 + + /* Default instruction size (in bits). + This is used by the assembler when it encounters an unknown insn. */ + unsigned int default_insn_bitsize; + + /* Base instruction size (in bits). + For non-LIW cpus this is generally the length of the smallest insn. + For LIW cpus its wip (work-in-progress). For the m32r its 32. */ + unsigned int base_insn_bitsize; + + /* Minimum/maximum instruction size (in bits). */ + unsigned int min_insn_bitsize; + unsigned int max_insn_bitsize; + + /* Instruction set variants. */ + const CGEN_ISA *isa_table; + + /* Machine variants. */ + const CGEN_MACH *mach_table; + + /* Hardware elements. */ + CGEN_HW_TABLE hw_table; + + /* Instruction fields. */ + const CGEN_IFLD *ifld_table; + + /* Operands. */ + CGEN_OPERAND_TABLE operand_table; + + /* Main instruction table. */ + CGEN_INSN_TABLE insn_table; +#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) + + /* Macro instructions are defined separately and are combined with real + insns during hash table computation. */ + CGEN_INSN_TABLE macro_insn_table; + + /* Copy of CGEN_INT_INSN_P. */ + int int_insn_p; + + /* Called to rebuild the tables after something has changed. */ + void (*rebuild_tables) (CGEN_CPU_DESC); + + /* Operand parser callback. */ + cgen_parse_operand_fn * parse_operand_fn; + + /* Parse/insert/extract/print cover fns for operands. */ + const char * (*parse_operand) + (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); +#ifdef __BFD_H_SEEN__ + const char * (*insert_operand) + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, + CGEN_INSN_BYTES_PTR, bfd_vma pc_); + int (*extract_operand) + (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *fields_, bfd_vma pc_); + void (*print_operand) + (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, + void const *attrs_, bfd_vma pc_, int length_); +#else + const char * (*insert_operand) (); + int (*extract_operand) (); + void (*print_operand) (); +#endif +#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) +#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) +#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) +#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) + + /* Size of CGEN_FIELDS struct. */ + unsigned int sizeof_fields; +#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) + + /* Set the bitsize field. */ + void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); +#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) + + /* CGEN_FIELDS accessors. */ + int (*get_int_operand) + (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); + void (*set_int_operand) + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); +#ifdef __BFD_H_SEEN__ + bfd_vma (*get_vma_operand) + (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); + void (*set_vma_operand) + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); +#else + long (*get_vma_operand) (); + void (*set_vma_operand) (); +#endif +#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) +#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) +#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) +#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) + + /* Instruction parse/insert/extract/print handlers. */ + /* FIXME: make these types uppercase. */ + cgen_parse_fn * const *parse_handlers; + cgen_insert_fn * const *insert_handlers; + cgen_extract_fn * const *extract_handlers; + cgen_print_fn * const *print_handlers; +#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) +#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) +#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) +#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) + + /* Return non-zero if insn should be added to hash table. */ + int (* asm_hash_p) (const CGEN_INSN *); + + /* Assembler hash function. */ + unsigned int (* asm_hash) (const char *); + + /* Number of entries in assembler hash table. */ + unsigned int asm_hash_size; + + /* Return non-zero if insn should be added to hash table. */ + int (* dis_hash_p) (const CGEN_INSN *); + + /* Disassembler hash function. */ + unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); + + /* Number of entries in disassembler hash table. */ + unsigned int dis_hash_size; + + /* Assembler instruction hash table. */ + CGEN_INSN_LIST **asm_hash_table; + CGEN_INSN_LIST *asm_hash_table_entries; + + /* Disassembler instruction hash table. */ + CGEN_INSN_LIST **dis_hash_table; + CGEN_INSN_LIST *dis_hash_table_entries; + + /* This field could be turned into a bitfield if room for other flags is needed. */ + unsigned int signed_overflow_ok_p; + +} CGEN_CPU_TABLE; + +/* wip */ +#ifndef CGEN_WORD_ENDIAN +#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) +#endif +#ifndef CGEN_INSN_WORD_ENDIAN +#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) +#endif + +/* Prototypes of major functions. */ +/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. + Not the init fns though, as that would drag in things that mightn't be + used and might not even exist. */ + +/* Argument types to cpu_open. */ + +enum cgen_cpu_open_arg { + CGEN_CPU_OPEN_END, + /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ + CGEN_CPU_OPEN_ISAS, + /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ + CGEN_CPU_OPEN_MACHS, + /* Select machine, arg is mach's bfd name. + Multiple machines can be specified by repeated use. */ + CGEN_CPU_OPEN_BFDMACH, + /* Select endian, arg is CGEN_ENDIAN_*. */ + CGEN_CPU_OPEN_ENDIAN +}; + +/* Open a cpu descriptor table for use. + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); + +/* Cover fn to handle simple case. */ + +extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) + (const char *mach_name_, enum cgen_endian endian_); + +/* Close it. */ + +extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); + +/* Initialize the opcode table for use. + Called by init_asm/init_dis. */ + +extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); + +/* build the insn selection regex. + called by init_opcode_table */ + +extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); + +/* Initialize the ibld table for use. + Called by init_asm/init_dis. */ + +extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); + +/* Initialize an cpu table for assembler or disassembler use. + These must be called immediately after cpu_open. */ + +extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); +extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); + +/* Initialize the operand instance table for use. */ + +extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); + +/* Assemble an instruction. */ + +extern const CGEN_INSN * CGEN_SYM (assemble_insn) + (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, + CGEN_INSN_BYTES_PTR, char **); + +extern const CGEN_KEYWORD CGEN_SYM (operand_mach); +extern int CGEN_SYM (get_mach) (const char *); + +/* Operand index computation. */ +extern const CGEN_INSN * cgen_lookup_insn + (CGEN_CPU_DESC, const CGEN_INSN * insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, CGEN_FIELDS *fields_, int alias_p_); +extern void cgen_get_insn_operands + (CGEN_CPU_DESC, const CGEN_INSN * insn_, + const CGEN_FIELDS *fields_, int *indices_); +extern const CGEN_INSN * cgen_lookup_get_insn_operands + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, int *indices_, CGEN_FIELDS *fields_); + +/* Cover fns to bfd_get/set. */ + +extern CGEN_INSN_INT cgen_get_insn_value + (CGEN_CPU_DESC, unsigned char *, int); +extern void cgen_put_insn_value + (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); + +/* Read in a cpu description file. + ??? For future concerns, including adding instructions to the assembler/ + disassembler at run-time. */ + +extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); + +/* Allow signed overflow of instruction fields. */ +extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); + +/* Generate an error message if a signed field in an instruction overflows. */ +extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); + +/* Will an error message be generated if a signed field in an instruction overflows ? */ +extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); + +#endif /* CGEN_H */ diff --git a/include/opcode/convex.h b/include/opcode/convex.h new file mode 100644 index 000000000..ccf556829 --- /dev/null +++ b/include/opcode/convex.h @@ -0,0 +1,1707 @@ +/* Information for instruction disassembly on the Convex. + Copyright 1989, 1993, 2002 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define xxx 0 +#define rrr 1 +#define rr 2 +#define rxr 3 +#define r 4 +#define nops 5 +#define nr 6 +#define pcrel 7 +#define lr 8 +#define rxl 9 +#define rlr 10 +#define rrl 11 +#define iml 12 +#define imr 13 +#define a1r 14 +#define a1l 15 +#define a2r 16 +#define a2l 17 +#define a3 18 +#define a4 19 +#define a5 20 +#define V 1 +#define S 2 +#define VM 3 +#define A 4 +#define VL 5 +#define VS 6 +#define VLS 7 +#define PSW 8 +/* Prevent an error during "make depend". */ +#if !defined (PC) +#define PC 9 +#endif +#define ITR 10 +#define VV 11 +#define ITSR 12 +#define TOC 13 +#define CIR 14 +#define TTR 15 +#define VMU 16 +#define VML 17 +#define ICR 18 +#define TCPU 19 +#define CPUID 20 +#define TID 21 + +const char *op[] = { + "", + "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7", + "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7", + "vm", + "sp\0a1\0a2\0a3\0a4\0a5\0ap\0fp", + "vl", + "vs", + "vls", + "psw", + "pc", + "itr", + "vv", + "itsr", + "toc", + "cir", + "ttr", + "vmu", + "vml", + "icr", + "tcpu", + "cpuid", + "tid", +}; + +const struct formstr format0[] = { + {0,0,rrr,V,S,S}, /* mov */ + {0,0,rrr,S,S,V}, /* mov */ + {1,1,rrr,V,V,V}, /* merg.t */ + {2,1,rrr,V,V,V}, /* mask.t */ + {1,2,rrr,V,S,V}, /* merg.f */ + {2,2,rrr,V,S,V}, /* mask.f */ + {1,1,rrr,V,S,V}, /* merg.t */ + {2,1,rrr,V,S,V}, /* mask.t */ + {3,3,rrr,V,V,V}, /* mul.s */ + {3,4,rrr,V,V,V}, /* mul.d */ + {4,3,rrr,V,V,V}, /* div.s */ + {4,4,rrr,V,V,V}, /* div.d */ + {3,3,rrr,V,S,V}, /* mul.s */ + {3,4,rrr,V,S,V}, /* mul.d */ + {4,3,rrr,V,S,V}, /* div.s */ + {4,4,rrr,V,S,V}, /* div.d */ + {5,0,rrr,V,V,V}, /* and */ + {6,0,rrr,V,V,V}, /* or */ + {7,0,rrr,V,V,V}, /* xor */ + {8,0,rrr,V,V,V}, /* shf */ + {5,0,rrr,V,S,V}, /* and */ + {6,0,rrr,V,S,V}, /* or */ + {7,0,rrr,V,S,V}, /* xor */ + {8,0,rrr,V,S,V}, /* shf */ + {9,3,rrr,V,V,V}, /* add.s */ + {9,4,rrr,V,V,V}, /* add.d */ + {10,3,rrr,V,V,V}, /* sub.s */ + {10,4,rrr,V,V,V}, /* sub.d */ + {9,3,rrr,V,S,V}, /* add.s */ + {9,4,rrr,V,S,V}, /* add.d */ + {10,3,rrr,V,S,V}, /* sub.s */ + {10,4,rrr,V,S,V}, /* sub.d */ + {9,5,rrr,V,V,V}, /* add.b */ + {9,6,rrr,V,V,V}, /* add.h */ + {9,7,rrr,V,V,V}, /* add.w */ + {9,8,rrr,V,V,V}, /* add.l */ + {9,5,rrr,V,S,V}, /* add.b */ + {9,6,rrr,V,S,V}, /* add.h */ + {9,7,rrr,V,S,V}, /* add.w */ + {9,8,rrr,V,S,V}, /* add.l */ + {10,5,rrr,V,V,V}, /* sub.b */ + {10,6,rrr,V,V,V}, /* sub.h */ + {10,7,rrr,V,V,V}, /* sub.w */ + {10,8,rrr,V,V,V}, /* sub.l */ + {10,5,rrr,V,S,V}, /* sub.b */ + {10,6,rrr,V,S,V}, /* sub.h */ + {10,7,rrr,V,S,V}, /* sub.w */ + {10,8,rrr,V,S,V}, /* sub.l */ + {3,5,rrr,V,V,V}, /* mul.b */ + {3,6,rrr,V,V,V}, /* mul.h */ + {3,7,rrr,V,V,V}, /* mul.w */ + {3,8,rrr,V,V,V}, /* mul.l */ + {3,5,rrr,V,S,V}, /* mul.b */ + {3,6,rrr,V,S,V}, /* mul.h */ + {3,7,rrr,V,S,V}, /* mul.w */ + {3,8,rrr,V,S,V}, /* mul.l */ + {4,5,rrr,V,V,V}, /* div.b */ + {4,6,rrr,V,V,V}, /* div.h */ + {4,7,rrr,V,V,V}, /* div.w */ + {4,8,rrr,V,V,V}, /* div.l */ + {4,5,rrr,V,S,V}, /* div.b */ + {4,6,rrr,V,S,V}, /* div.h */ + {4,7,rrr,V,S,V}, /* div.w */ + {4,8,rrr,V,S,V}, /* div.l */ +}; + +const struct formstr format1[] = { + {11,0,xxx,0,0,0}, /* exit */ + {12,0,a3,0,0,0}, /* jmp */ + {13,2,a3,0,0,0}, /* jmpi.f */ + {13,1,a3,0,0,0}, /* jmpi.t */ + {14,2,a3,0,0,0}, /* jmpa.f */ + {14,1,a3,0,0,0}, /* jmpa.t */ + {15,2,a3,0,0,0}, /* jmps.f */ + {15,1,a3,0,0,0}, /* jmps.t */ + {16,0,a3,0,0,0}, /* tac */ + {17,0,a1r,A,0,0}, /* ldea */ + {18,8,a1l,VLS,0,0}, /* ld.l */ + {18,9,a1l,VM,0,0}, /* ld.x */ + {19,0,a3,0,0,0}, /* tas */ + {20,0,a3,0,0,0}, /* pshea */ + {21,8,a2l,VLS,0,0}, /* st.l */ + {21,9,a2l,VM,0,0}, /* st.x */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {22,0,a3,0,0,0}, /* call */ + {23,0,a3,0,0,0}, /* calls */ + {24,0,a3,0,0,0}, /* callq */ + {25,0,a1r,A,0,0}, /* pfork */ + {26,5,a2r,S,0,0}, /* ste.b */ + {26,6,a2r,S,0,0}, /* ste.h */ + {26,7,a2r,S,0,0}, /* ste.w */ + {26,8,a2r,S,0,0}, /* ste.l */ + {18,5,a1r,A,0,0}, /* ld.b */ + {18,6,a1r,A,0,0}, /* ld.h */ + {18,7,a1r,A,0,0}, /* ld.w */ + {27,7,a1r,A,0,0}, /* incr.w */ + {21,5,a2r,A,0,0}, /* st.b */ + {21,6,a2r,A,0,0}, /* st.h */ + {21,7,a2r,A,0,0}, /* st.w */ + {27,8,a1r,S,0,0}, /* incr.l */ + {18,5,a1r,S,0,0}, /* ld.b */ + {18,6,a1r,S,0,0}, /* ld.h */ + {18,7,a1r,S,0,0}, /* ld.w */ + {18,8,a1r,S,0,0}, /* ld.l */ + {21,5,a2r,S,0,0}, /* st.b */ + {21,6,a2r,S,0,0}, /* st.h */ + {21,7,a2r,S,0,0}, /* st.w */ + {21,8,a2r,S,0,0}, /* st.l */ + {18,5,a1r,V,0,0}, /* ld.b */ + {18,6,a1r,V,0,0}, /* ld.h */ + {18,7,a1r,V,0,0}, /* ld.w */ + {18,8,a1r,V,0,0}, /* ld.l */ + {21,5,a2r,V,0,0}, /* st.b */ + {21,6,a2r,V,0,0}, /* st.h */ + {21,7,a2r,V,0,0}, /* st.w */ + {21,8,a2r,V,0,0}, /* st.l */ +}; + +const struct formstr format2[] = { + {28,5,rr,A,A,0}, /* cvtw.b */ + {28,6,rr,A,A,0}, /* cvtw.h */ + {29,7,rr,A,A,0}, /* cvtb.w */ + {30,7,rr,A,A,0}, /* cvth.w */ + {28,5,rr,S,S,0}, /* cvtw.b */ + {28,6,rr,S,S,0}, /* cvtw.h */ + {29,7,rr,S,S,0}, /* cvtb.w */ + {30,7,rr,S,S,0}, /* cvth.w */ + {28,3,rr,S,S,0}, /* cvtw.s */ + {31,7,rr,S,S,0}, /* cvts.w */ + {32,3,rr,S,S,0}, /* cvtd.s */ + {31,4,rr,S,S,0}, /* cvts.d */ + {31,8,rr,S,S,0}, /* cvts.l */ + {32,8,rr,S,S,0}, /* cvtd.l */ + {33,3,rr,S,S,0}, /* cvtl.s */ + {33,4,rr,S,S,0}, /* cvtl.d */ + {34,0,rr,A,A,0}, /* ldpa */ + {8,0,nr,A,0,0}, /* shf */ + {18,6,nr,A,0,0}, /* ld.h */ + {18,7,nr,A,0,0}, /* ld.w */ + {33,7,rr,S,S,0}, /* cvtl.w */ + {28,8,rr,S,S,0}, /* cvtw.l */ + {35,1,rr,S,S,0}, /* plc.t */ + {36,0,rr,S,S,0}, /* tzc */ + {37,6,rr,A,A,0}, /* eq.h */ + {37,7,rr,A,A,0}, /* eq.w */ + {37,6,nr,A,0,0}, /* eq.h */ + {37,7,nr,A,0,0}, /* eq.w */ + {37,5,rr,S,S,0}, /* eq.b */ + {37,6,rr,S,S,0}, /* eq.h */ + {37,7,rr,S,S,0}, /* eq.w */ + {37,8,rr,S,S,0}, /* eq.l */ + {38,6,rr,A,A,0}, /* leu.h */ + {38,7,rr,A,A,0}, /* leu.w */ + {38,6,nr,A,0,0}, /* leu.h */ + {38,7,nr,A,0,0}, /* leu.w */ + {38,5,rr,S,S,0}, /* leu.b */ + {38,6,rr,S,S,0}, /* leu.h */ + {38,7,rr,S,S,0}, /* leu.w */ + {38,8,rr,S,S,0}, /* leu.l */ + {39,6,rr,A,A,0}, /* ltu.h */ + {39,7,rr,A,A,0}, /* ltu.w */ + {39,6,nr,A,0,0}, /* ltu.h */ + {39,7,nr,A,0,0}, /* ltu.w */ + {39,5,rr,S,S,0}, /* ltu.b */ + {39,6,rr,S,S,0}, /* ltu.h */ + {39,7,rr,S,S,0}, /* ltu.w */ + {39,8,rr,S,S,0}, /* ltu.l */ + {40,6,rr,A,A,0}, /* le.h */ + {40,7,rr,A,A,0}, /* le.w */ + {40,6,nr,A,0,0}, /* le.h */ + {40,7,nr,A,0,0}, /* le.w */ + {40,5,rr,S,S,0}, /* le.b */ + {40,6,rr,S,S,0}, /* le.h */ + {40,7,rr,S,S,0}, /* le.w */ + {40,8,rr,S,S,0}, /* le.l */ + {41,6,rr,A,A,0}, /* lt.h */ + {41,7,rr,A,A,0}, /* lt.w */ + {41,6,nr,A,0,0}, /* lt.h */ + {41,7,nr,A,0,0}, /* lt.w */ + {41,5,rr,S,S,0}, /* lt.b */ + {41,6,rr,S,S,0}, /* lt.h */ + {41,7,rr,S,S,0}, /* lt.w */ + {41,8,rr,S,S,0}, /* lt.l */ + {9,7,rr,S,A,0}, /* add.w */ + {8,0,rr,A,A,0}, /* shf */ + {0,0,rr,A,A,0}, /* mov */ + {0,0,rr,S,A,0}, /* mov */ + {0,7,rr,S,S,0}, /* mov.w */ + {8,0,rr,S,S,0}, /* shf */ + {0,0,rr,S,S,0}, /* mov */ + {0,0,rr,A,S,0}, /* mov */ + {5,0,rr,A,A,0}, /* and */ + {6,0,rr,A,A,0}, /* or */ + {7,0,rr,A,A,0}, /* xor */ + {42,0,rr,A,A,0}, /* not */ + {5,0,rr,S,S,0}, /* and */ + {6,0,rr,S,S,0}, /* or */ + {7,0,rr,S,S,0}, /* xor */ + {42,0,rr,S,S,0}, /* not */ + {40,3,rr,S,S,0}, /* le.s */ + {40,4,rr,S,S,0}, /* le.d */ + {41,3,rr,S,S,0}, /* lt.s */ + {41,4,rr,S,S,0}, /* lt.d */ + {9,3,rr,S,S,0}, /* add.s */ + {9,4,rr,S,S,0}, /* add.d */ + {10,3,rr,S,S,0}, /* sub.s */ + {10,4,rr,S,S,0}, /* sub.d */ + {37,3,rr,S,S,0}, /* eq.s */ + {37,4,rr,S,S,0}, /* eq.d */ + {43,6,rr,A,A,0}, /* neg.h */ + {43,7,rr,A,A,0}, /* neg.w */ + {3,3,rr,S,S,0}, /* mul.s */ + {3,4,rr,S,S,0}, /* mul.d */ + {4,3,rr,S,S,0}, /* div.s */ + {4,4,rr,S,S,0}, /* div.d */ + {9,6,rr,A,A,0}, /* add.h */ + {9,7,rr,A,A,0}, /* add.w */ + {9,6,nr,A,0,0}, /* add.h */ + {9,7,nr,A,0,0}, /* add.w */ + {9,5,rr,S,S,0}, /* add.b */ + {9,6,rr,S,S,0}, /* add.h */ + {9,7,rr,S,S,0}, /* add.w */ + {9,8,rr,S,S,0}, /* add.l */ + {10,6,rr,A,A,0}, /* sub.h */ + {10,7,rr,A,A,0}, /* sub.w */ + {10,6,nr,A,0,0}, /* sub.h */ + {10,7,nr,A,0,0}, /* sub.w */ + {10,5,rr,S,S,0}, /* sub.b */ + {10,6,rr,S,S,0}, /* sub.h */ + {10,7,rr,S,S,0}, /* sub.w */ + {10,8,rr,S,S,0}, /* sub.l */ + {3,6,rr,A,A,0}, /* mul.h */ + {3,7,rr,A,A,0}, /* mul.w */ + {3,6,nr,A,0,0}, /* mul.h */ + {3,7,nr,A,0,0}, /* mul.w */ + {3,5,rr,S,S,0}, /* mul.b */ + {3,6,rr,S,S,0}, /* mul.h */ + {3,7,rr,S,S,0}, /* mul.w */ + {3,8,rr,S,S,0}, /* mul.l */ + {4,6,rr,A,A,0}, /* div.h */ + {4,7,rr,A,A,0}, /* div.w */ + {4,6,nr,A,0,0}, /* div.h */ + {4,7,nr,A,0,0}, /* div.w */ + {4,5,rr,S,S,0}, /* div.b */ + {4,6,rr,S,S,0}, /* div.h */ + {4,7,rr,S,S,0}, /* div.w */ + {4,8,rr,S,S,0}, /* div.l */ +}; + +const struct formstr format3[] = { + {32,3,rr,V,V,0}, /* cvtd.s */ + {31,4,rr,V,V,0}, /* cvts.d */ + {33,4,rr,V,V,0}, /* cvtl.d */ + {32,8,rr,V,V,0}, /* cvtd.l */ + {0,0,rrl,S,S,VM}, /* mov */ + {0,0,rlr,S,VM,S}, /* mov */ + {0,0,0,0,0,0}, + {44,0,rr,S,S,0}, /* lop */ + {36,0,rr,V,V,0}, /* tzc */ + {44,0,rr,V,V,0}, /* lop */ + {0,0,0,0,0,0}, + {42,0,rr,V,V,0}, /* not */ + {8,0,rr,S,V,0}, /* shf */ + {35,1,rr,V,V,0}, /* plc.t */ + {45,2,rr,V,V,0}, /* cprs.f */ + {45,1,rr,V,V,0}, /* cprs.t */ + {37,3,rr,V,V,0}, /* eq.s */ + {37,4,rr,V,V,0}, /* eq.d */ + {43,3,rr,V,V,0}, /* neg.s */ + {43,4,rr,V,V,0}, /* neg.d */ + {37,3,rr,S,V,0}, /* eq.s */ + {37,4,rr,S,V,0}, /* eq.d */ + {43,3,rr,S,S,0}, /* neg.s */ + {43,4,rr,S,S,0}, /* neg.d */ + {40,3,rr,V,V,0}, /* le.s */ + {40,4,rr,V,V,0}, /* le.d */ + {41,3,rr,V,V,0}, /* lt.s */ + {41,4,rr,V,V,0}, /* lt.d */ + {40,3,rr,S,V,0}, /* le.s */ + {40,4,rr,S,V,0}, /* le.d */ + {41,3,rr,S,V,0}, /* lt.s */ + {41,4,rr,S,V,0}, /* lt.d */ + {37,5,rr,V,V,0}, /* eq.b */ + {37,6,rr,V,V,0}, /* eq.h */ + {37,7,rr,V,V,0}, /* eq.w */ + {37,8,rr,V,V,0}, /* eq.l */ + {37,5,rr,S,V,0}, /* eq.b */ + {37,6,rr,S,V,0}, /* eq.h */ + {37,7,rr,S,V,0}, /* eq.w */ + {37,8,rr,S,V,0}, /* eq.l */ + {40,5,rr,V,V,0}, /* le.b */ + {40,6,rr,V,V,0}, /* le.h */ + {40,7,rr,V,V,0}, /* le.w */ + {40,8,rr,V,V,0}, /* le.l */ + {40,5,rr,S,V,0}, /* le.b */ + {40,6,rr,S,V,0}, /* le.h */ + {40,7,rr,S,V,0}, /* le.w */ + {40,8,rr,S,V,0}, /* le.l */ + {41,5,rr,V,V,0}, /* lt.b */ + {41,6,rr,V,V,0}, /* lt.h */ + {41,7,rr,V,V,0}, /* lt.w */ + {41,8,rr,V,V,0}, /* lt.l */ + {41,5,rr,S,V,0}, /* lt.b */ + {41,6,rr,S,V,0}, /* lt.h */ + {41,7,rr,S,V,0}, /* lt.w */ + {41,8,rr,S,V,0}, /* lt.l */ + {43,5,rr,V,V,0}, /* neg.b */ + {43,6,rr,V,V,0}, /* neg.h */ + {43,7,rr,V,V,0}, /* neg.w */ + {43,8,rr,V,V,0}, /* neg.l */ + {43,5,rr,S,S,0}, /* neg.b */ + {43,6,rr,S,S,0}, /* neg.h */ + {43,7,rr,S,S,0}, /* neg.w */ + {43,8,rr,S,S,0}, /* neg.l */ +}; + +const struct formstr format4[] = { + {46,0,nops,0,0,0}, /* nop */ + {47,0,pcrel,0,0,0}, /* br */ + {48,2,pcrel,0,0,0}, /* bri.f */ + {48,1,pcrel,0,0,0}, /* bri.t */ + {49,2,pcrel,0,0,0}, /* bra.f */ + {49,1,pcrel,0,0,0}, /* bra.t */ + {50,2,pcrel,0,0,0}, /* brs.f */ + {50,1,pcrel,0,0,0}, /* brs.t */ +}; + +const struct formstr format5[] = { + {51,5,rr,V,V,0}, /* ldvi.b */ + {51,6,rr,V,V,0}, /* ldvi.h */ + {51,7,rr,V,V,0}, /* ldvi.w */ + {51,8,rr,V,V,0}, /* ldvi.l */ + {28,3,rr,V,V,0}, /* cvtw.s */ + {31,7,rr,V,V,0}, /* cvts.w */ + {28,8,rr,V,V,0}, /* cvtw.l */ + {33,7,rr,V,V,0}, /* cvtl.w */ + {52,5,rxr,V,V,0}, /* stvi.b */ + {52,6,rxr,V,V,0}, /* stvi.h */ + {52,7,rxr,V,V,0}, /* stvi.w */ + {52,8,rxr,V,V,0}, /* stvi.l */ + {52,5,rxr,S,V,0}, /* stvi.b */ + {52,6,rxr,S,V,0}, /* stvi.h */ + {52,7,rxr,S,V,0}, /* stvi.w */ + {52,8,rxr,S,V,0}, /* stvi.l */ +}; + +const struct formstr format6[] = { + {53,0,r,A,0,0}, /* ldsdr */ + {54,0,r,A,0,0}, /* ldkdr */ + {55,3,r,S,0,0}, /* ln.s */ + {55,4,r,S,0,0}, /* ln.d */ + {56,0,nops,0,0,0}, /* patu */ + {57,0,r,A,0,0}, /* pate */ + {58,0,nops,0,0,0}, /* pich */ + {59,0,nops,0,0,0}, /* plch */ + {0,0,lr,PSW,A,0}, /* mov */ + {0,0,rxl,A,PSW,0}, /* mov */ + {0,0,lr,PC,A,0}, /* mov */ + {60,0,r,S,0,0}, /* idle */ + {0,0,lr,ITR,S,0}, /* mov */ + {0,0,rxl,S,ITR,0}, /* mov */ + {0,0,0,0,0,0}, + {0,0,rxl,S,ITSR,0}, /* mov */ + {61,0,nops,0,0,0}, /* rtnq */ + {62,0,nops,0,0,0}, /* cfork */ + {63,0,nops,0,0,0}, /* rtn */ + {64,0,nops,0,0,0}, /* wfork */ + {65,0,nops,0,0,0}, /* join */ + {66,0,nops,0,0,0}, /* rtnc */ + {67,3,r,S,0,0}, /* exp.s */ + {67,4,r,S,0,0}, /* exp.d */ + {68,3,r,S,0,0}, /* sin.s */ + {68,4,r,S,0,0}, /* sin.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {69,3,r,S,0,0}, /* cos.s */ + {69,4,r,S,0,0}, /* cos.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {70,7,r,A,0,0}, /* psh.w */ + {0,0,0,0,0,0}, + {71,7,r,A,0,0}, /* pop.w */ + {0,0,0,0,0,0}, + {70,7,r,S,0,0}, /* psh.w */ + {70,8,r,S,0,0}, /* psh.l */ + {71,7,r,S,0,0}, /* pop.w */ + {71,8,r,S,0,0}, /* pop.l */ + {72,0,nops,0,0,0}, /* eni */ + {73,0,nops,0,0,0}, /* dsi */ + {74,0,nops,0,0,0}, /* bkpt */ + {75,0,nops,0,0,0}, /* msync */ + {76,0,r,S,0,0}, /* mski */ + {77,0,r,S,0,0}, /* xmti */ + {0,0,rxl,S,VV,0}, /* mov */ + {78,0,nops,0,0,0}, /* tstvv */ + {0,0,lr,VS,A,0}, /* mov */ + {0,0,rxl,A,VS,0}, /* mov */ + {0,0,lr,VL,A,0}, /* mov */ + {0,0,rxl,A,VL,0}, /* mov */ + {0,7,lr,VS,S,0}, /* mov.w */ + {0,7,rxl,S,VS,0}, /* mov.w */ + {0,7,lr,VL,S,0}, /* mov.w */ + {0,7,rxl,S,VL,0}, /* mov.w */ + {79,0,r,A,0,0}, /* diag */ + {80,0,nops,0,0,0}, /* pbkpt */ + {81,3,r,S,0,0}, /* sqrt.s */ + {81,4,r,S,0,0}, /* sqrt.d */ + {82,0,nops,0,0,0}, /* casr */ + {0,0,0,0,0,0}, + {83,3,r,S,0,0}, /* atan.s */ + {83,4,r,S,0,0}, /* atan.d */ +}; + +const struct formstr format7[] = { + {84,5,r,V,0,0}, /* sum.b */ + {84,6,r,V,0,0}, /* sum.h */ + {84,7,r,V,0,0}, /* sum.w */ + {84,8,r,V,0,0}, /* sum.l */ + {85,0,r,V,0,0}, /* all */ + {86,0,r,V,0,0}, /* any */ + {87,0,r,V,0,0}, /* parity */ + {0,0,0,0,0,0}, + {88,5,r,V,0,0}, /* max.b */ + {88,6,r,V,0,0}, /* max.h */ + {88,7,r,V,0,0}, /* max.w */ + {88,8,r,V,0,0}, /* max.l */ + {89,5,r,V,0,0}, /* min.b */ + {89,6,r,V,0,0}, /* min.h */ + {89,7,r,V,0,0}, /* min.w */ + {89,8,r,V,0,0}, /* min.l */ + {84,3,r,V,0,0}, /* sum.s */ + {84,4,r,V,0,0}, /* sum.d */ + {90,3,r,V,0,0}, /* prod.s */ + {90,4,r,V,0,0}, /* prod.d */ + {88,3,r,V,0,0}, /* max.s */ + {88,4,r,V,0,0}, /* max.d */ + {89,3,r,V,0,0}, /* min.s */ + {89,4,r,V,0,0}, /* min.d */ + {90,5,r,V,0,0}, /* prod.b */ + {90,6,r,V,0,0}, /* prod.h */ + {90,7,r,V,0,0}, /* prod.w */ + {90,8,r,V,0,0}, /* prod.l */ + {35,2,lr,VM,S,0}, /* plc.f */ + {35,1,lr,VM,S,0}, /* plc.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr formatx[] = { + {0,0,0,0,0,0}, +}; + +const struct formstr format1a[] = { + {91,0,imr,A,0,0}, /* halt */ + {92,0,a4,0,0,0}, /* sysc */ + {18,6,imr,A,0,0}, /* ld.h */ + {18,7,imr,A,0,0}, /* ld.w */ + {5,0,imr,A,0,0}, /* and */ + {6,0,imr,A,0,0}, /* or */ + {7,0,imr,A,0,0}, /* xor */ + {8,0,imr,A,0,0}, /* shf */ + {9,6,imr,A,0,0}, /* add.h */ + {9,7,imr,A,0,0}, /* add.w */ + {10,6,imr,A,0,0}, /* sub.h */ + {10,7,imr,A,0,0}, /* sub.w */ + {3,6,imr,A,0,0}, /* mul.h */ + {3,7,imr,A,0,0}, /* mul.w */ + {4,6,imr,A,0,0}, /* div.h */ + {4,7,imr,A,0,0}, /* div.w */ + {18,7,iml,VL,0,0}, /* ld.w */ + {18,7,iml,VS,0,0}, /* ld.w */ + {0,0,0,0,0,0}, + {8,7,imr,S,0,0}, /* shf.w */ + {93,0,a5,0,0,0}, /* trap */ + {0,0,0,0,0,0}, + {37,6,imr,A,0,0}, /* eq.h */ + {37,7,imr,A,0,0}, /* eq.w */ + {38,6,imr,A,0,0}, /* leu.h */ + {38,7,imr,A,0,0}, /* leu.w */ + {39,6,imr,A,0,0}, /* ltu.h */ + {39,7,imr,A,0,0}, /* ltu.w */ + {40,6,imr,A,0,0}, /* le.h */ + {40,7,imr,A,0,0}, /* le.w */ + {41,6,imr,A,0,0}, /* lt.h */ + {41,7,imr,A,0,0}, /* lt.w */ +}; + +const struct formstr format1b[] = { + {18,4,imr,S,0,0}, /* ld.d */ + {18,10,imr,S,0,0}, /* ld.u */ + {18,8,imr,S,0,0}, /* ld.l */ + {18,7,imr,S,0,0}, /* ld.w */ + {5,0,imr,S,0,0}, /* and */ + {6,0,imr,S,0,0}, /* or */ + {7,0,imr,S,0,0}, /* xor */ + {8,0,imr,S,0,0}, /* shf */ + {9,6,imr,S,0,0}, /* add.h */ + {9,7,imr,S,0,0}, /* add.w */ + {10,6,imr,S,0,0}, /* sub.h */ + {10,7,imr,S,0,0}, /* sub.w */ + {3,6,imr,S,0,0}, /* mul.h */ + {3,7,imr,S,0,0}, /* mul.w */ + {4,6,imr,S,0,0}, /* div.h */ + {4,7,imr,S,0,0}, /* div.w */ + {9,3,imr,S,0,0}, /* add.s */ + {10,3,imr,S,0,0}, /* sub.s */ + {3,3,imr,S,0,0}, /* mul.s */ + {4,3,imr,S,0,0}, /* div.s */ + {40,3,imr,S,0,0}, /* le.s */ + {41,3,imr,S,0,0}, /* lt.s */ + {37,6,imr,S,0,0}, /* eq.h */ + {37,7,imr,S,0,0}, /* eq.w */ + {38,6,imr,S,0,0}, /* leu.h */ + {38,7,imr,S,0,0}, /* leu.w */ + {39,6,imr,S,0,0}, /* ltu.h */ + {39,7,imr,S,0,0}, /* ltu.w */ + {40,6,imr,S,0,0}, /* le.h */ + {40,7,imr,S,0,0}, /* le.w */ + {41,6,imr,S,0,0}, /* lt.h */ + {41,7,imr,S,0,0}, /* lt.w */ +}; + +const struct formstr e0_format0[] = { + {10,3,rrr,S,V,V}, /* sub.s */ + {10,4,rrr,S,V,V}, /* sub.d */ + {4,3,rrr,S,V,V}, /* div.s */ + {4,4,rrr,S,V,V}, /* div.d */ + {10,11,rrr,S,V,V}, /* sub.s.f */ + {10,12,rrr,S,V,V}, /* sub.d.f */ + {4,11,rrr,S,V,V}, /* div.s.f */ + {4,12,rrr,S,V,V}, /* div.d.f */ + {3,11,rrr,V,V,V}, /* mul.s.f */ + {3,12,rrr,V,V,V}, /* mul.d.f */ + {4,11,rrr,V,V,V}, /* div.s.f */ + {4,12,rrr,V,V,V}, /* div.d.f */ + {3,11,rrr,V,S,V}, /* mul.s.f */ + {3,12,rrr,V,S,V}, /* mul.d.f */ + {4,11,rrr,V,S,V}, /* div.s.f */ + {4,12,rrr,V,S,V}, /* div.d.f */ + {5,2,rrr,V,V,V}, /* and.f */ + {6,2,rrr,V,V,V}, /* or.f */ + {7,2,rrr,V,V,V}, /* xor.f */ + {8,2,rrr,V,V,V}, /* shf.f */ + {5,2,rrr,V,S,V}, /* and.f */ + {6,2,rrr,V,S,V}, /* or.f */ + {7,2,rrr,V,S,V}, /* xor.f */ + {8,2,rrr,V,S,V}, /* shf.f */ + {9,11,rrr,V,V,V}, /* add.s.f */ + {9,12,rrr,V,V,V}, /* add.d.f */ + {10,11,rrr,V,V,V}, /* sub.s.f */ + {10,12,rrr,V,V,V}, /* sub.d.f */ + {9,11,rrr,V,S,V}, /* add.s.f */ + {9,12,rrr,V,S,V}, /* add.d.f */ + {10,11,rrr,V,S,V}, /* sub.s.f */ + {10,12,rrr,V,S,V}, /* sub.d.f */ + {9,13,rrr,V,V,V}, /* add.b.f */ + {9,14,rrr,V,V,V}, /* add.h.f */ + {9,15,rrr,V,V,V}, /* add.w.f */ + {9,16,rrr,V,V,V}, /* add.l.f */ + {9,13,rrr,V,S,V}, /* add.b.f */ + {9,14,rrr,V,S,V}, /* add.h.f */ + {9,15,rrr,V,S,V}, /* add.w.f */ + {9,16,rrr,V,S,V}, /* add.l.f */ + {10,13,rrr,V,V,V}, /* sub.b.f */ + {10,14,rrr,V,V,V}, /* sub.h.f */ + {10,15,rrr,V,V,V}, /* sub.w.f */ + {10,16,rrr,V,V,V}, /* sub.l.f */ + {10,13,rrr,V,S,V}, /* sub.b.f */ + {10,14,rrr,V,S,V}, /* sub.h.f */ + {10,15,rrr,V,S,V}, /* sub.w.f */ + {10,16,rrr,V,S,V}, /* sub.l.f */ + {3,13,rrr,V,V,V}, /* mul.b.f */ + {3,14,rrr,V,V,V}, /* mul.h.f */ + {3,15,rrr,V,V,V}, /* mul.w.f */ + {3,16,rrr,V,V,V}, /* mul.l.f */ + {3,13,rrr,V,S,V}, /* mul.b.f */ + {3,14,rrr,V,S,V}, /* mul.h.f */ + {3,15,rrr,V,S,V}, /* mul.w.f */ + {3,16,rrr,V,S,V}, /* mul.l.f */ + {4,13,rrr,V,V,V}, /* div.b.f */ + {4,14,rrr,V,V,V}, /* div.h.f */ + {4,15,rrr,V,V,V}, /* div.w.f */ + {4,16,rrr,V,V,V}, /* div.l.f */ + {4,13,rrr,V,S,V}, /* div.b.f */ + {4,14,rrr,V,S,V}, /* div.h.f */ + {4,15,rrr,V,S,V}, /* div.w.f */ + {4,16,rrr,V,S,V}, /* div.l.f */ +}; + +const struct formstr e0_format1[] = { + {0,0,0,0,0,0}, + {94,0,a3,0,0,0}, /* tst */ + {95,0,a3,0,0,0}, /* lck */ + {96,0,a3,0,0,0}, /* ulk */ + {17,0,a1r,S,0,0}, /* ldea */ + {97,0,a1r,A,0,0}, /* spawn */ + {98,0,a1r,A,0,0}, /* ldcmr */ + {99,0,a2r,A,0,0}, /* stcmr */ + {100,0,a1r,A,0,0}, /* popr */ + {101,0,a2r,A,0,0}, /* pshr */ + {102,7,a1r,A,0,0}, /* rcvr.w */ + {103,7,a2r,A,0,0}, /* matm.w */ + {104,7,a2r,A,0,0}, /* sndr.w */ + {104,8,a2r,S,0,0}, /* sndr.l */ + {102,8,a1r,S,0,0}, /* rcvr.l */ + {103,8,a2r,S,0,0}, /* matm.l */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {105,7,a2r,A,0,0}, /* putr.w */ + {105,8,a2r,S,0,0}, /* putr.l */ + {106,7,a1r,A,0,0}, /* getr.w */ + {106,8,a1r,S,0,0}, /* getr.l */ + {26,13,a2r,S,0,0}, /* ste.b.f */ + {26,14,a2r,S,0,0}, /* ste.h.f */ + {26,15,a2r,S,0,0}, /* ste.w.f */ + {26,16,a2r,S,0,0}, /* ste.l.f */ + {107,7,a2r,A,0,0}, /* matr.w */ + {108,7,a2r,A,0,0}, /* mat.w */ + {109,7,a1r,A,0,0}, /* get.w */ + {110,7,a1r,A,0,0}, /* rcv.w */ + {0,0,0,0,0,0}, + {111,7,a1r,A,0,0}, /* inc.w */ + {112,7,a2r,A,0,0}, /* put.w */ + {113,7,a2r,A,0,0}, /* snd.w */ + {107,8,a2r,S,0,0}, /* matr.l */ + {108,8,a2r,S,0,0}, /* mat.l */ + {109,8,a1r,S,0,0}, /* get.l */ + {110,8,a1r,S,0,0}, /* rcv.l */ + {0,0,0,0,0,0}, + {111,8,a1r,S,0,0}, /* inc.l */ + {112,8,a2r,S,0,0}, /* put.l */ + {113,8,a2r,S,0,0}, /* snd.l */ + {18,13,a1r,V,0,0}, /* ld.b.f */ + {18,14,a1r,V,0,0}, /* ld.h.f */ + {18,15,a1r,V,0,0}, /* ld.w.f */ + {18,16,a1r,V,0,0}, /* ld.l.f */ + {21,13,a2r,V,0,0}, /* st.b.f */ + {21,14,a2r,V,0,0}, /* st.h.f */ + {21,15,a2r,V,0,0}, /* st.w.f */ + {21,16,a2r,V,0,0}, /* st.l.f */ +}; + +const struct formstr e0_format2[] = { + {28,5,rr,V,V,0}, /* cvtw.b */ + {28,6,rr,V,V,0}, /* cvtw.h */ + {29,7,rr,V,V,0}, /* cvtb.w */ + {30,7,rr,V,V,0}, /* cvth.w */ + {28,13,rr,V,V,0}, /* cvtw.b.f */ + {28,14,rr,V,V,0}, /* cvtw.h.f */ + {29,15,rr,V,V,0}, /* cvtb.w.f */ + {30,15,rr,V,V,0}, /* cvth.w.f */ + {31,8,rr,V,V,0}, /* cvts.l */ + {32,7,rr,V,V,0}, /* cvtd.w */ + {33,3,rr,V,V,0}, /* cvtl.s */ + {28,4,rr,V,V,0}, /* cvtw.d */ + {31,16,rr,V,V,0}, /* cvts.l.f */ + {32,15,rr,V,V,0}, /* cvtd.w.f */ + {33,11,rr,V,V,0}, /* cvtl.s.f */ + {28,12,rr,V,V,0}, /* cvtw.d.f */ + {114,0,rr,S,S,0}, /* enal */ + {8,7,rr,S,S,0}, /* shf.w */ + {115,0,rr,S,S,0}, /* enag */ + {0,0,0,0,0,0}, + {28,4,rr,S,S,0}, /* cvtw.d */ + {32,7,rr,S,S,0}, /* cvtd.w */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {116,3,rr,S,S,0}, /* frint.s */ + {116,4,rr,S,S,0}, /* frint.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {116,3,rr,V,V,0}, /* frint.s */ + {116,4,rr,V,V,0}, /* frint.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {116,11,rr,V,V,0}, /* frint.s.f */ + {116,12,rr,V,V,0}, /* frint.d.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {81,3,rr,V,V,0}, /* sqrt.s */ + {81,4,rr,V,V,0}, /* sqrt.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {81,11,rr,V,V,0}, /* sqrt.s.f */ + {81,12,rr,V,V,0}, /* sqrt.d.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e0_format3[] = { + {32,11,rr,V,V,0}, /* cvtd.s.f */ + {31,12,rr,V,V,0}, /* cvts.d.f */ + {33,12,rr,V,V,0}, /* cvtl.d.f */ + {32,16,rr,V,V,0}, /* cvtd.l.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {36,2,rr,V,V,0}, /* tzc.f */ + {44,2,rr,V,V,0}, /* lop.f */ + {117,2,rr,V,V,0}, /* xpnd.f */ + {42,2,rr,V,V,0}, /* not.f */ + {8,2,rr,S,V,0}, /* shf.f */ + {35,17,rr,V,V,0}, /* plc.t.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {37,11,rr,V,V,0}, /* eq.s.f */ + {37,12,rr,V,V,0}, /* eq.d.f */ + {43,11,rr,V,V,0}, /* neg.s.f */ + {43,12,rr,V,V,0}, /* neg.d.f */ + {37,11,rr,S,V,0}, /* eq.s.f */ + {37,12,rr,S,V,0}, /* eq.d.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {40,11,rr,V,V,0}, /* le.s.f */ + {40,12,rr,V,V,0}, /* le.d.f */ + {41,11,rr,V,V,0}, /* lt.s.f */ + {41,12,rr,V,V,0}, /* lt.d.f */ + {40,11,rr,S,V,0}, /* le.s.f */ + {40,12,rr,S,V,0}, /* le.d.f */ + {41,11,rr,S,V,0}, /* lt.s.f */ + {41,12,rr,S,V,0}, /* lt.d.f */ + {37,13,rr,V,V,0}, /* eq.b.f */ + {37,14,rr,V,V,0}, /* eq.h.f */ + {37,15,rr,V,V,0}, /* eq.w.f */ + {37,16,rr,V,V,0}, /* eq.l.f */ + {37,13,rr,S,V,0}, /* eq.b.f */ + {37,14,rr,S,V,0}, /* eq.h.f */ + {37,15,rr,S,V,0}, /* eq.w.f */ + {37,16,rr,S,V,0}, /* eq.l.f */ + {40,13,rr,V,V,0}, /* le.b.f */ + {40,14,rr,V,V,0}, /* le.h.f */ + {40,15,rr,V,V,0}, /* le.w.f */ + {40,16,rr,V,V,0}, /* le.l.f */ + {40,13,rr,S,V,0}, /* le.b.f */ + {40,14,rr,S,V,0}, /* le.h.f */ + {40,15,rr,S,V,0}, /* le.w.f */ + {40,16,rr,S,V,0}, /* le.l.f */ + {41,13,rr,V,V,0}, /* lt.b.f */ + {41,14,rr,V,V,0}, /* lt.h.f */ + {41,15,rr,V,V,0}, /* lt.w.f */ + {41,16,rr,V,V,0}, /* lt.l.f */ + {41,13,rr,S,V,0}, /* lt.b.f */ + {41,14,rr,S,V,0}, /* lt.h.f */ + {41,15,rr,S,V,0}, /* lt.w.f */ + {41,16,rr,S,V,0}, /* lt.l.f */ + {43,13,rr,V,V,0}, /* neg.b.f */ + {43,14,rr,V,V,0}, /* neg.h.f */ + {43,15,rr,V,V,0}, /* neg.w.f */ + {43,16,rr,V,V,0}, /* neg.l.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e0_format4[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e0_format5[] = { + {51,13,rr,V,V,0}, /* ldvi.b.f */ + {51,14,rr,V,V,0}, /* ldvi.h.f */ + {51,15,rr,V,V,0}, /* ldvi.w.f */ + {51,16,rr,V,V,0}, /* ldvi.l.f */ + {28,11,rr,V,V,0}, /* cvtw.s.f */ + {31,15,rr,V,V,0}, /* cvts.w.f */ + {28,16,rr,V,V,0}, /* cvtw.l.f */ + {33,15,rr,V,V,0}, /* cvtl.w.f */ + {52,13,rxr,V,V,0}, /* stvi.b.f */ + {52,14,rxr,V,V,0}, /* stvi.h.f */ + {52,15,rxr,V,V,0}, /* stvi.w.f */ + {52,16,rxr,V,V,0}, /* stvi.l.f */ + {52,13,rxr,S,V,0}, /* stvi.b.f */ + {52,14,rxr,S,V,0}, /* stvi.h.f */ + {52,15,rxr,S,V,0}, /* stvi.w.f */ + {52,16,rxr,S,V,0}, /* stvi.l.f */ +}; + +const struct formstr e0_format6[] = { + {0,0,rxl,S,CIR,0}, /* mov */ + {0,0,lr,CIR,S,0}, /* mov */ + {0,0,lr,TOC,S,0}, /* mov */ + {0,0,lr,CPUID,S,0}, /* mov */ + {0,0,rxl,S,TTR,0}, /* mov */ + {0,0,lr,TTR,S,0}, /* mov */ + {118,0,nops,0,0,0}, /* ctrsl */ + {119,0,nops,0,0,0}, /* ctrsg */ + {0,0,rxl,S,VMU,0}, /* mov */ + {0,0,lr,VMU,S,0}, /* mov */ + {0,0,rxl,S,VML,0}, /* mov */ + {0,0,lr,VML,S,0}, /* mov */ + {0,0,rxl,S,ICR,0}, /* mov */ + {0,0,lr,ICR,S,0}, /* mov */ + {0,0,rxl,S,TCPU,0}, /* mov */ + {0,0,lr,TCPU,S,0}, /* mov */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {120,0,nops,0,0,0}, /* stop */ + {0,0,0,0,0,0}, + {0,0,rxl,S,TID,0}, /* mov */ + {0,0,lr,TID,S,0}, /* mov */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e0_format7[] = { + {84,13,r,V,0,0}, /* sum.b.f */ + {84,14,r,V,0,0}, /* sum.h.f */ + {84,15,r,V,0,0}, /* sum.w.f */ + {84,16,r,V,0,0}, /* sum.l.f */ + {85,2,r,V,0,0}, /* all.f */ + {86,2,r,V,0,0}, /* any.f */ + {87,2,r,V,0,0}, /* parity.f */ + {0,0,0,0,0,0}, + {88,13,r,V,0,0}, /* max.b.f */ + {88,14,r,V,0,0}, /* max.h.f */ + {88,15,r,V,0,0}, /* max.w.f */ + {88,16,r,V,0,0}, /* max.l.f */ + {89,13,r,V,0,0}, /* min.b.f */ + {89,14,r,V,0,0}, /* min.h.f */ + {89,15,r,V,0,0}, /* min.w.f */ + {89,16,r,V,0,0}, /* min.l.f */ + {84,11,r,V,0,0}, /* sum.s.f */ + {84,12,r,V,0,0}, /* sum.d.f */ + {90,11,r,V,0,0}, /* prod.s.f */ + {90,12,r,V,0,0}, /* prod.d.f */ + {88,11,r,V,0,0}, /* max.s.f */ + {88,12,r,V,0,0}, /* max.d.f */ + {89,11,r,V,0,0}, /* min.s.f */ + {89,12,r,V,0,0}, /* min.d.f */ + {90,13,r,V,0,0}, /* prod.b.f */ + {90,14,r,V,0,0}, /* prod.h.f */ + {90,15,r,V,0,0}, /* prod.w.f */ + {90,16,r,V,0,0}, /* prod.l.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format0[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {10,18,rrr,S,V,V}, /* sub.s.t */ + {10,19,rrr,S,V,V}, /* sub.d.t */ + {4,18,rrr,S,V,V}, /* div.s.t */ + {4,19,rrr,S,V,V}, /* div.d.t */ + {3,18,rrr,V,V,V}, /* mul.s.t */ + {3,19,rrr,V,V,V}, /* mul.d.t */ + {4,18,rrr,V,V,V}, /* div.s.t */ + {4,19,rrr,V,V,V}, /* div.d.t */ + {3,18,rrr,V,S,V}, /* mul.s.t */ + {3,19,rrr,V,S,V}, /* mul.d.t */ + {4,18,rrr,V,S,V}, /* div.s.t */ + {4,19,rrr,V,S,V}, /* div.d.t */ + {5,1,rrr,V,V,V}, /* and.t */ + {6,1,rrr,V,V,V}, /* or.t */ + {7,1,rrr,V,V,V}, /* xor.t */ + {8,1,rrr,V,V,V}, /* shf.t */ + {5,1,rrr,V,S,V}, /* and.t */ + {6,1,rrr,V,S,V}, /* or.t */ + {7,1,rrr,V,S,V}, /* xor.t */ + {8,1,rrr,V,S,V}, /* shf.t */ + {9,18,rrr,V,V,V}, /* add.s.t */ + {9,19,rrr,V,V,V}, /* add.d.t */ + {10,18,rrr,V,V,V}, /* sub.s.t */ + {10,19,rrr,V,V,V}, /* sub.d.t */ + {9,18,rrr,V,S,V}, /* add.s.t */ + {9,19,rrr,V,S,V}, /* add.d.t */ + {10,18,rrr,V,S,V}, /* sub.s.t */ + {10,19,rrr,V,S,V}, /* sub.d.t */ + {9,20,rrr,V,V,V}, /* add.b.t */ + {9,21,rrr,V,V,V}, /* add.h.t */ + {9,22,rrr,V,V,V}, /* add.w.t */ + {9,23,rrr,V,V,V}, /* add.l.t */ + {9,20,rrr,V,S,V}, /* add.b.t */ + {9,21,rrr,V,S,V}, /* add.h.t */ + {9,22,rrr,V,S,V}, /* add.w.t */ + {9,23,rrr,V,S,V}, /* add.l.t */ + {10,20,rrr,V,V,V}, /* sub.b.t */ + {10,21,rrr,V,V,V}, /* sub.h.t */ + {10,22,rrr,V,V,V}, /* sub.w.t */ + {10,23,rrr,V,V,V}, /* sub.l.t */ + {10,20,rrr,V,S,V}, /* sub.b.t */ + {10,21,rrr,V,S,V}, /* sub.h.t */ + {10,22,rrr,V,S,V}, /* sub.w.t */ + {10,23,rrr,V,S,V}, /* sub.l.t */ + {3,20,rrr,V,V,V}, /* mul.b.t */ + {3,21,rrr,V,V,V}, /* mul.h.t */ + {3,22,rrr,V,V,V}, /* mul.w.t */ + {3,23,rrr,V,V,V}, /* mul.l.t */ + {3,20,rrr,V,S,V}, /* mul.b.t */ + {3,21,rrr,V,S,V}, /* mul.h.t */ + {3,22,rrr,V,S,V}, /* mul.w.t */ + {3,23,rrr,V,S,V}, /* mul.l.t */ + {4,20,rrr,V,V,V}, /* div.b.t */ + {4,21,rrr,V,V,V}, /* div.h.t */ + {4,22,rrr,V,V,V}, /* div.w.t */ + {4,23,rrr,V,V,V}, /* div.l.t */ + {4,20,rrr,V,S,V}, /* div.b.t */ + {4,21,rrr,V,S,V}, /* div.h.t */ + {4,22,rrr,V,S,V}, /* div.w.t */ + {4,23,rrr,V,S,V}, /* div.l.t */ +}; + +const struct formstr e1_format1[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {26,20,a2r,S,0,0}, /* ste.b.t */ + {26,21,a2r,S,0,0}, /* ste.h.t */ + {26,22,a2r,S,0,0}, /* ste.w.t */ + {26,23,a2r,S,0,0}, /* ste.l.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {18,20,a1r,V,0,0}, /* ld.b.t */ + {18,21,a1r,V,0,0}, /* ld.h.t */ + {18,22,a1r,V,0,0}, /* ld.w.t */ + {18,23,a1r,V,0,0}, /* ld.l.t */ + {21,20,a2r,V,0,0}, /* st.b.t */ + {21,21,a2r,V,0,0}, /* st.h.t */ + {21,22,a2r,V,0,0}, /* st.w.t */ + {21,23,a2r,V,0,0}, /* st.l.t */ +}; + +const struct formstr e1_format2[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {28,20,rr,V,V,0}, /* cvtw.b.t */ + {28,21,rr,V,V,0}, /* cvtw.h.t */ + {29,22,rr,V,V,0}, /* cvtb.w.t */ + {30,22,rr,V,V,0}, /* cvth.w.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {31,23,rr,V,V,0}, /* cvts.l.t */ + {32,22,rr,V,V,0}, /* cvtd.w.t */ + {33,18,rr,V,V,0}, /* cvtl.s.t */ + {28,19,rr,V,V,0}, /* cvtw.d.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {116,18,rr,V,V,0}, /* frint.s.t */ + {116,19,rr,V,V,0}, /* frint.d.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {81,18,rr,V,V,0}, /* sqrt.s.t */ + {81,19,rr,V,V,0}, /* sqrt.d.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format3[] = { + {32,18,rr,V,V,0}, /* cvtd.s.t */ + {31,19,rr,V,V,0}, /* cvts.d.t */ + {33,19,rr,V,V,0}, /* cvtl.d.t */ + {32,23,rr,V,V,0}, /* cvtd.l.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {36,1,rr,V,V,0}, /* tzc.t */ + {44,1,rr,V,V,0}, /* lop.t */ + {117,1,rr,V,V,0}, /* xpnd.t */ + {42,1,rr,V,V,0}, /* not.t */ + {8,1,rr,S,V,0}, /* shf.t */ + {35,24,rr,V,V,0}, /* plc.t.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {37,18,rr,V,V,0}, /* eq.s.t */ + {37,19,rr,V,V,0}, /* eq.d.t */ + {43,18,rr,V,V,0}, /* neg.s.t */ + {43,19,rr,V,V,0}, /* neg.d.t */ + {37,18,rr,S,V,0}, /* eq.s.t */ + {37,19,rr,S,V,0}, /* eq.d.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {40,18,rr,V,V,0}, /* le.s.t */ + {40,19,rr,V,V,0}, /* le.d.t */ + {41,18,rr,V,V,0}, /* lt.s.t */ + {41,19,rr,V,V,0}, /* lt.d.t */ + {40,18,rr,S,V,0}, /* le.s.t */ + {40,19,rr,S,V,0}, /* le.d.t */ + {41,18,rr,S,V,0}, /* lt.s.t */ + {41,19,rr,S,V,0}, /* lt.d.t */ + {37,20,rr,V,V,0}, /* eq.b.t */ + {37,21,rr,V,V,0}, /* eq.h.t */ + {37,22,rr,V,V,0}, /* eq.w.t */ + {37,23,rr,V,V,0}, /* eq.l.t */ + {37,20,rr,S,V,0}, /* eq.b.t */ + {37,21,rr,S,V,0}, /* eq.h.t */ + {37,22,rr,S,V,0}, /* eq.w.t */ + {37,23,rr,S,V,0}, /* eq.l.t */ + {40,20,rr,V,V,0}, /* le.b.t */ + {40,21,rr,V,V,0}, /* le.h.t */ + {40,22,rr,V,V,0}, /* le.w.t */ + {40,23,rr,V,V,0}, /* le.l.t */ + {40,20,rr,S,V,0}, /* le.b.t */ + {40,21,rr,S,V,0}, /* le.h.t */ + {40,22,rr,S,V,0}, /* le.w.t */ + {40,23,rr,S,V,0}, /* le.l.t */ + {41,20,rr,V,V,0}, /* lt.b.t */ + {41,21,rr,V,V,0}, /* lt.h.t */ + {41,22,rr,V,V,0}, /* lt.w.t */ + {41,23,rr,V,V,0}, /* lt.l.t */ + {41,20,rr,S,V,0}, /* lt.b.t */ + {41,21,rr,S,V,0}, /* lt.h.t */ + {41,22,rr,S,V,0}, /* lt.w.t */ + {41,23,rr,S,V,0}, /* lt.l.t */ + {43,20,rr,V,V,0}, /* neg.b.t */ + {43,21,rr,V,V,0}, /* neg.h.t */ + {43,22,rr,V,V,0}, /* neg.w.t */ + {43,23,rr,V,V,0}, /* neg.l.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format4[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format5[] = { + {51,20,rr,V,V,0}, /* ldvi.b.t */ + {51,21,rr,V,V,0}, /* ldvi.h.t */ + {51,22,rr,V,V,0}, /* ldvi.w.t */ + {51,23,rr,V,V,0}, /* ldvi.l.t */ + {28,18,rr,V,V,0}, /* cvtw.s.t */ + {31,22,rr,V,V,0}, /* cvts.w.t */ + {28,23,rr,V,V,0}, /* cvtw.l.t */ + {33,22,rr,V,V,0}, /* cvtl.w.t */ + {52,20,rxr,V,V,0}, /* stvi.b.t */ + {52,21,rxr,V,V,0}, /* stvi.h.t */ + {52,22,rxr,V,V,0}, /* stvi.w.t */ + {52,23,rxr,V,V,0}, /* stvi.l.t */ + {52,20,rxr,S,V,0}, /* stvi.b.t */ + {52,21,rxr,S,V,0}, /* stvi.h.t */ + {52,22,rxr,S,V,0}, /* stvi.w.t */ + {52,23,rxr,S,V,0}, /* stvi.l.t */ +}; + +const struct formstr e1_format6[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format7[] = { + {84,20,r,V,0,0}, /* sum.b.t */ + {84,21,r,V,0,0}, /* sum.h.t */ + {84,22,r,V,0,0}, /* sum.w.t */ + {84,23,r,V,0,0}, /* sum.l.t */ + {85,1,r,V,0,0}, /* all.t */ + {86,1,r,V,0,0}, /* any.t */ + {87,1,r,V,0,0}, /* parity.t */ + {0,0,0,0,0,0}, + {88,20,r,V,0,0}, /* max.b.t */ + {88,21,r,V,0,0}, /* max.h.t */ + {88,22,r,V,0,0}, /* max.w.t */ + {88,23,r,V,0,0}, /* max.l.t */ + {89,20,r,V,0,0}, /* min.b.t */ + {89,21,r,V,0,0}, /* min.h.t */ + {89,22,r,V,0,0}, /* min.w.t */ + {89,23,r,V,0,0}, /* min.l.t */ + {84,18,r,V,0,0}, /* sum.s.t */ + {84,19,r,V,0,0}, /* sum.d.t */ + {90,18,r,V,0,0}, /* prod.s.t */ + {90,19,r,V,0,0}, /* prod.d.t */ + {88,18,r,V,0,0}, /* max.s.t */ + {88,19,r,V,0,0}, /* max.d.t */ + {89,18,r,V,0,0}, /* min.s.t */ + {89,19,r,V,0,0}, /* min.d.t */ + {90,20,r,V,0,0}, /* prod.b.t */ + {90,21,r,V,0,0}, /* prod.h.t */ + {90,22,r,V,0,0}, /* prod.w.t */ + {90,23,r,V,0,0}, /* prod.l.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +char *lop[] = { + "mov", /* 0 */ + "merg", /* 1 */ + "mask", /* 2 */ + "mul", /* 3 */ + "div", /* 4 */ + "and", /* 5 */ + "or", /* 6 */ + "xor", /* 7 */ + "shf", /* 8 */ + "add", /* 9 */ + "sub", /* 10 */ + "exit", /* 11 */ + "jmp", /* 12 */ + "jmpi", /* 13 */ + "jmpa", /* 14 */ + "jmps", /* 15 */ + "tac", /* 16 */ + "ldea", /* 17 */ + "ld", /* 18 */ + "tas", /* 19 */ + "pshea", /* 20 */ + "st", /* 21 */ + "call", /* 22 */ + "calls", /* 23 */ + "callq", /* 24 */ + "pfork", /* 25 */ + "ste", /* 26 */ + "incr", /* 27 */ + "cvtw", /* 28 */ + "cvtb", /* 29 */ + "cvth", /* 30 */ + "cvts", /* 31 */ + "cvtd", /* 32 */ + "cvtl", /* 33 */ + "ldpa", /* 34 */ + "plc", /* 35 */ + "tzc", /* 36 */ + "eq", /* 37 */ + "leu", /* 38 */ + "ltu", /* 39 */ + "le", /* 40 */ + "lt", /* 41 */ + "not", /* 42 */ + "neg", /* 43 */ + "lop", /* 44 */ + "cprs", /* 45 */ + "nop", /* 46 */ + "br", /* 47 */ + "bri", /* 48 */ + "bra", /* 49 */ + "brs", /* 50 */ + "ldvi", /* 51 */ + "stvi", /* 52 */ + "ldsdr", /* 53 */ + "ldkdr", /* 54 */ + "ln", /* 55 */ + "patu", /* 56 */ + "pate", /* 57 */ + "pich", /* 58 */ + "plch", /* 59 */ + "idle", /* 60 */ + "rtnq", /* 61 */ + "cfork", /* 62 */ + "rtn", /* 63 */ + "wfork", /* 64 */ + "join", /* 65 */ + "rtnc", /* 66 */ + "exp", /* 67 */ + "sin", /* 68 */ + "cos", /* 69 */ + "psh", /* 70 */ + "pop", /* 71 */ + "eni", /* 72 */ + "dsi", /* 73 */ + "bkpt", /* 74 */ + "msync", /* 75 */ + "mski", /* 76 */ + "xmti", /* 77 */ + "tstvv", /* 78 */ + "diag", /* 79 */ + "pbkpt", /* 80 */ + "sqrt", /* 81 */ + "casr", /* 82 */ + "atan", /* 83 */ + "sum", /* 84 */ + "all", /* 85 */ + "any", /* 86 */ + "parity", /* 87 */ + "max", /* 88 */ + "min", /* 89 */ + "prod", /* 90 */ + "halt", /* 91 */ + "sysc", /* 92 */ + "trap", /* 93 */ + "tst", /* 94 */ + "lck", /* 95 */ + "ulk", /* 96 */ + "spawn", /* 97 */ + "ldcmr", /* 98 */ + "stcmr", /* 99 */ + "popr", /* 100 */ + "pshr", /* 101 */ + "rcvr", /* 102 */ + "matm", /* 103 */ + "sndr", /* 104 */ + "putr", /* 105 */ + "getr", /* 106 */ + "matr", /* 107 */ + "mat", /* 108 */ + "get", /* 109 */ + "rcv", /* 110 */ + "inc", /* 111 */ + "put", /* 112 */ + "snd", /* 113 */ + "enal", /* 114 */ + "enag", /* 115 */ + "frint", /* 116 */ + "xpnd", /* 117 */ + "ctrsl", /* 118 */ + "ctrsg", /* 119 */ + "stop", /* 120 */ +}; + +char *rop[] = { + "", /* 0 */ + ".t", /* 1 */ + ".f", /* 2 */ + ".s", /* 3 */ + ".d", /* 4 */ + ".b", /* 5 */ + ".h", /* 6 */ + ".w", /* 7 */ + ".l", /* 8 */ + ".x", /* 9 */ + ".u", /* 10 */ + ".s.f", /* 11 */ + ".d.f", /* 12 */ + ".b.f", /* 13 */ + ".h.f", /* 14 */ + ".w.f", /* 15 */ + ".l.f", /* 16 */ + ".t.f", /* 17 */ + ".s.t", /* 18 */ + ".d.t", /* 19 */ + ".b.t", /* 20 */ + ".h.t", /* 21 */ + ".w.t", /* 22 */ + ".l.t", /* 23 */ + ".t.t", /* 24 */ +}; diff --git a/include/opcode/cris.h b/include/opcode/cris.h new file mode 100644 index 000000000..1f10034c3 --- /dev/null +++ b/include/opcode/cris.h @@ -0,0 +1,300 @@ +/* cris.h -- Header file for CRIS opcode and register tables. + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Originally written for GAS 1.38.1 by Mikael Asker. + Updated, BFDized and GNUified by Hans-Peter Nilsson. + +This file is part of GAS, GDB and the GNU binutils. + +GAS, GDB, and GNU binutils is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2, or (at your +option) any later version. + +GAS, GDB, and GNU binutils are distributed in the hope that they will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef __CRIS_H_INCLUDED_ +#define __CRIS_H_INCLUDED_ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + + +/* Registers. */ +#define MAX_REG (15) +#define REG_SP (14) +#define REG_PC (15) + +/* CPU version control of disassembly and assembly of instructions. + May affect how the instruction is assembled, at least the size of + immediate operands. */ +enum cris_insn_version_usage +{ + /* Any version. */ + cris_ver_version_all=0, + + /* Indeterminate (intended for disassembly only, or obsolete). */ + cris_ver_warning, + + /* Simulator only (reserved). */ + cris_ver_sim, + + /* Only for v0..3 (Etrax 1..4). */ + cris_ver_v0_3, + + /* Only for v3 or higher (ETRAX 4 and beyond). */ + cris_ver_v3p, + + /* Only for v8 (Etrax 100). */ + cris_ver_v8, + + /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */ + cris_ver_v8p, + + /* Only for v10 or higher (ETRAX 100 LX). + Of course some or all these of may change to cris_ver_v10p if/when + there's a new revision. */ + cris_ver_v10p +}; + + +/* Special registers. */ +struct cris_spec_reg +{ + const char *const name; + unsigned int number; + + /* The size of the register. */ + unsigned int reg_size; + + /* What CPU version the special register of that name is implemented + in. If cris_ver_warning, emit an unimplemented-warning. */ + enum cris_insn_version_usage applicable_version; + + /* There might be a specific warning for using a special register + here. */ + const char *const warning; +}; +extern const struct cris_spec_reg cris_spec_regs[]; + +/* Opcode-dependent constants. */ +#define AUTOINCR_BIT (0x04) + +/* Prefixes. */ +#define BDAP_QUICK_OPCODE (0x0100) +#define BDAP_QUICK_Z_BITS (0x0e00) + +#define BIAP_OPCODE (0x0540) +#define BIAP_Z_BITS (0x0a80) + +#define DIP_OPCODE (0x0970) +#define DIP_Z_BITS (0xf280) + +#define BDAP_INDIR_LOW (0x40) +#define BDAP_INDIR_LOW_Z (0x80) +#define BDAP_INDIR_HIGH (0x09) +#define BDAP_INDIR_HIGH_Z (0x02) + +#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW) +#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z) +#define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC) +#define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT) + +/* No prefix must have this code for its "match" bits in the + opcode-table. "BCC .+2" will do nicely. */ +#define NO_CRIS_PREFIX 0 + +/* Definitions for condition codes. */ +#define CC_CC 0x0 +#define CC_HS 0x0 +#define CC_CS 0x1 +#define CC_LO 0x1 +#define CC_NE 0x2 +#define CC_EQ 0x3 +#define CC_VC 0x4 +#define CC_VS 0x5 +#define CC_PL 0x6 +#define CC_MI 0x7 +#define CC_LS 0x8 +#define CC_HI 0x9 +#define CC_GE 0xA +#define CC_LT 0xB +#define CC_GT 0xC +#define CC_LE 0xD +#define CC_A 0xE +#define CC_EXT 0xF + +/* A table of strings "cc", "cs"... indexed with condition code + values as above. */ +extern const char *const cris_cc_strings[]; + +/* Bcc quick. */ +#define BRANCH_QUICK_LOW (0) +#define BRANCH_QUICK_HIGH (0) +#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW) +#define BRANCH_QUICK_Z_BITS (0x0F00) + +/* BA quick. */ +#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10) +#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW) + +/* Bcc [PC+]. */ +#define BRANCH_PC_LOW (0xFF) +#define BRANCH_INCR_HIGH (0x0D) +#define BA_PC_INCR_OPCODE \ + ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW) + +/* Jump. */ +/* Note that old versions generated special register 8 (in high bits) + and not-that-old versions recognized it as a jump-instruction. + That opcode now belongs to JUMPU. */ +#define JUMP_INDIR_OPCODE (0x0930) +#define JUMP_INDIR_Z_BITS (0xf2c0) +#define JUMP_PC_INCR_OPCODE \ + (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC) +#define ADD_PC_INCR_OPCODE \ + (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC) + +/* Nop. */ +#define NOP_OPCODE (0x050F) +#define NOP_Z_BITS (0xFAF0) + +/* Structure of an opcode table entry. */ +enum cris_imm_oprnd_size_type +{ + /* No size is applicable. */ + SIZE_NONE, + + /* Always 32 bits. */ + SIZE_FIX_32, + + /* Indicated by size of special register. */ + SIZE_SPEC_REG, + + /* Indicated by size field. */ + SIZE_FIELD +}; + +/* For GDB. FIXME: Is this the best way to handle opcode + interpretation? */ +enum cris_op_type +{ + cris_not_implemented_op = 0, + cris_abs_op, + cris_addi_op, + cris_asr_op, + cris_asrq_op, + cris_ax_ei_setf_op, + cris_bdap_prefix, + cris_biap_prefix, + cris_break_op, + cris_btst_nop_op, + cris_clearf_di_op, + cris_dip_prefix, + cris_dstep_logshift_mstep_neg_not_op, + cris_eight_bit_offset_branch_op, + cris_move_mem_to_reg_movem_op, + cris_move_reg_to_mem_movem_op, + cris_move_to_preg_op, + cris_muls_op, + cris_mulu_op, + cris_none_reg_mode_add_sub_cmp_and_or_move_op, + cris_none_reg_mode_clear_test_op, + cris_none_reg_mode_jump_op, + cris_none_reg_mode_move_from_preg_op, + cris_quick_mode_add_sub_op, + cris_quick_mode_and_cmp_move_or_op, + cris_quick_mode_bdap_prefix, + cris_reg_mode_add_sub_cmp_and_or_move_op, + cris_reg_mode_clear_op, + cris_reg_mode_jump_op, + cris_reg_mode_move_from_preg_op, + cris_reg_mode_test_op, + cris_scc_op, + cris_sixteen_bit_offset_branch_op, + cris_three_operand_add_sub_cmp_and_or_op, + cris_three_operand_bound_op, + cris_two_operand_bound_op, + cris_xor_op +}; + +struct cris_opcode +{ + /* The name of the insn. */ + const char *name; + + /* Bits that must be 1 for a match. */ + unsigned int match; + + /* Bits that must be 0 for a match. */ + unsigned int lose; + + /* See the table in "opcodes/cris-opc.c". */ + const char *args; + + /* Nonzero if this is a delayed branch instruction. */ + char delayed; + + /* Size of immediate operands. */ + enum cris_imm_oprnd_size_type imm_oprnd_size; + + /* Indicates which version this insn was first implemented in. */ + enum cris_insn_version_usage applicable_version; + + /* What kind of operation this is. */ + enum cris_op_type op; +}; +extern const struct cris_opcode cris_opcodes[]; + + +/* These macros are for the target-specific flags in disassemble_info + used at disassembly. */ + +/* This insn accesses memory. This flag is more trustworthy than + checking insn_type for "dis_dref" which does not work for + e.g. "JSR [foo]". */ +#define CRIS_DIS_FLAG_MEMREF (1 << 0) + +/* The "target" field holds a register number. */ +#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1) + +/* The "target2" field holds a register number; add it to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2) + +/* Yet another add-on: the register in "target2" must be multiplied + by 2 before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3) + +/* Yet another add-on: the register in "target2" must be multiplied + by 4 (mutually exclusive with .._MULT2). */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4) + +/* The register in "target2" is an indirect memory reference (of the + register there), add to "target". Assumed size is dword (mutually + exclusive with .._MULT[24]). */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5) + +/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte"; + sign-extended before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6) + +/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word"; + sign-extended before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7) + +#endif /* __CRIS_H_INCLUDED_ */ + +/* + * Local variables: + * eval: (c-set-style "gnu") + * indent-tabs-mode: t + * End: + */ diff --git a/include/opcode/crx.h b/include/opcode/crx.h new file mode 100644 index 000000000..1e0d5733a --- /dev/null +++ b/include/opcode/crx.h @@ -0,0 +1,395 @@ +/* crx.h -- Header file for CRX opcode and register tables. + Copyright 2004 Free Software Foundation, Inc. + Contributed by Tomer Levi, NSC, Israel. + Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. + Updates, BFDizing, GNUifying and ELF support by Tomer Levi. + + This file is part of GAS, GDB and the GNU binutils. + + GAS, GDB, and GNU binutils is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GAS, GDB, and GNU binutils are distributed in the hope that they will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _CRX_H_ +#define _CRX_H_ + +/* CRX core/debug Registers : + The enums are used as indices to CRX registers table (crx_regtab). + Therefore, order MUST be preserved. */ + +typedef enum + { + /* 32-bit general purpose registers. */ + r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, + r10, r11, r12, r13, r14, r15, ra, sp, + /* 32-bit user registers. */ + u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, + u10, u11, u12, u13, u14, u15, ura, usp, + /* hi and lo registers. */ + hi, lo, + /* hi and lo user registers. */ + uhi, ulo, + /* Processor Status Register. */ + psr, + /* Configuration Register. */ + cfg, + /* Coprocessor Configuration Register. */ + cpcfg, + /* Cashe Configuration Register. */ + ccfg, + /* Interrupt Base Register. */ + intbase, + /* Interrupt Stack Pointer Register. */ + isp, + /* Coprocessor Enable Register. */ + cen, + /* Program Counter Register. */ + pc, + /* Not a register. */ + nullregister, + MAX_REG + } +reg; + +/* CRX Coprocessor registers and special registers : + The enums are used as indices to CRX coprocessor registers table + (crx_copregtab). Therefore, order MUST be preserved. */ + +typedef enum + { + /* Coprocessor registers. */ + c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, + c9, c10, c11, c12, c13, c14, c15, + /* Coprocessor special registers. */ + cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, + cs9, cs10, cs11, cs12, cs13, cs14, cs15, + /* Not a Coprocessor register. */ + nullcopregister, + MAX_COPREG + } +copreg; + +/* CRX Register types. */ + +typedef enum + { + CRX_PC_REGTYPE, /* pc type */ + CRX_R_REGTYPE, /* r<N> */ + CRX_U_REGTYPE, /* u<N> */ + CRX_C_REGTYPE, /* c<N> */ + CRX_CS_REGTYPE, /* cs<N> */ + CRX_MTPR_REGTYPE, /* mtpr */ + CRX_CFG_REGTYPE /* *hi|lo, *cfg, psr */ + } +reg_type; + +/* CRX argument types : + The argument types correspond to instructions operands + + Argument types : + r - register + c - constant + d - displacement + ic - immediate + icr - index register + rbase - register base + s - star ('*') + copr - coprocessor register + copsr - coprocessor special register. */ + +typedef enum + { + arg_r, arg_c, arg_cr, arg_dc, arg_dcr, arg_sc, + arg_ic, arg_icr, arg_rbase, arg_copr, arg_copsr, + /* Not an argument. */ + nullargs + } +argtype; + +/* CRX operand types : + The operand types correspond to instructions operands + + Operand Types : + cst4 - 4-bit encoded constant + iN - N-bit immediate field + d, dispsN - N-bit immediate signed displacement + dispuN - N-bit immediate unsigned displacement + absN - N-bit absolute address + rbase - 4-bit genaral-purpose register specifier + regr - 4-bit genaral-purpose register specifier + regr8 - 8-bit register address space + copregr - coprocessor register + copsregr - coprocessor special register + scl2 - 2-bit scaling factor for memory index + ridx - register index. */ + +typedef enum + { + dummy, cst4, disps9, + i3, i4, i5, i8, i12, i16, i32, + d5, d9, d17, d25, d33, + abs16, abs32, + rbase, rbase_cst4, + rbase_dispu8, rbase_dispu12, rbase_dispu16, rbase_dispu28, rbase_dispu32, + rbase_ridx_scl2_dispu6, rbase_ridx_scl2_dispu22, + regr, regr8, copregr,copregr8,copsregr, + /* Not an operand. */ + nulloperand, + /* Maximum supported operand. */ + MAX_OPRD + } +operand_type; + +/* CRX instruction types. */ + +#define ARITH_INS 1 +#define LD_STOR_INS 2 +#define BRANCH_INS 3 +#define ARITH_BYTE_INS 4 +#define CMPBR_INS 5 +#define SHIFT_INS 6 +#define BRANCH_NEQ_INS 7 +#define LD_STOR_INS_INC 8 +#define STOR_IMM_INS 9 +#define CSTBIT_INS 10 +#define SYS_INS 11 +#define JMP_INS 12 +#define MUL_INS 13 +#define DIV_INS 14 +#define COP_BRANCH_INS 15 +#define COP_REG_INS 16 +#define DCR_BRANCH_INS 17 +#define MMC_INS 18 +#define MMU_INS 19 + +/* Maximum value supported for instruction types. */ +#define CRX_INS_MAX (1 << 5) +/* Mask to record an instruction type. */ +#define CRX_INS_MASK (CRX_INS_MAX - 1) +/* Return instruction type, given instruction's attributes. */ +#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) + +/* Indicates whether this instruction has a register list as parameter. */ +#define REG_LIST CRX_INS_MAX +/* The operands in binary and assembly are placed in reverse order. + load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ +#define REVERSE_MATCH (REG_LIST << 1) + +/* Kind of displacement map used DISPU[BWD]4. */ +#define DISPUB4 (REVERSE_MATCH << 1) +#define DISPUW4 (DISPUB4 << 1) +#define DISPUD4 (DISPUW4 << 1) +#define CST4MAP (DISPUB4 | DISPUW4 | DISPUD4) + +/* Printing formats, where the instruction prefix isn't consecutive. */ +#define FMT_1 (DISPUD4 << 1) /* 0xF0F00000 */ +#define FMT_2 (FMT_1 << 1) /* 0xFFF0FF00 */ +#define FMT_3 (FMT_2 << 1) /* 0xFFF00F00 */ +#define FMT_4 (FMT_3 << 1) /* 0xFFF0F000 */ +#define FMT_5 (FMT_4 << 1) /* 0xFFF0FFF0 */ +#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) + +#define RELAXABLE (FMT_5 << 1) + +/* Maximum operands per instruction. */ +#define MAX_OPERANDS 5 +/* Maximum words per instruction. */ +#define MAX_WORDS 3 +/* Maximum register name length. */ +#define MAX_REGNAME_LEN 10 +/* Maximum instruction length. */ +#define MAX_INST_LEN 256 + +/* Single operand description. */ + +typedef struct + { + /* Operand type. */ + operand_type op_type; + /* Operand location within the opcode. */ + unsigned int shift; + } +operand_desc; + +/* Instruction data structure used in instruction table. */ + +typedef struct + { + /* Name. */ + const char *mnemonic; + /* Size (in words). */ + unsigned int size; + /* Constant prefix (matched by the disassembler). */ + unsigned long match; + /* Match size (in bits). */ + int match_bits; + /* Attributes. */ + unsigned int flags; + /* Operands (always last, so unreferenced operands are initialized). */ + operand_desc operands[MAX_OPERANDS]; + } +inst; + +/* Data structure for a single instruction's arguments (Operands). */ + +typedef struct + { + /* Register or base register. */ + reg r; + /* Index register. */ + reg i_r; + /* Coprocessor register. */ + copreg cr; + /* Constant/immediate/absolute value. */ + unsigned long int constant; + /* Scaled index mode. */ + unsigned int scale; + /* Argument type. */ + argtype type; + /* Size of the argument (in bits) required to represent. */ + int size; + /* Indicates whether a constant is positive or negative. */ + int signflag; + } +argument; + +/* Internal structure to hold the various entities + corresponding to the current assembling instruction. */ + +typedef struct + { + /* Number of arguments. */ + int nargs; + /* The argument data structure for storing args (operands). */ + argument arg[MAX_OPERANDS]; +/* The following fields are required only by CRX-assembler. */ +#ifdef TC_CRX + /* Expression used for setting the fixups (if any). */ + expressionS exp; + bfd_reloc_code_real_type rtype; +#endif /* TC_CRX */ + /* Instruction size (in bytes). */ + int size; + } +ins; + +/* Structure to hold information about predefined operands. */ + +typedef struct + { + /* Size (in bits). */ + unsigned int bit_size; + /* Argument type. */ + argtype arg_type; + } +operand_entry; + +/* Structure to hold trap handler information. */ + +typedef struct + { + /* Trap name. */ + char *name; + /* Index in dispatch table. */ + unsigned int entry; + } +trap_entry; + +/* Structure to hold information about predefined registers. */ + +typedef struct + { + /* Name (string representation). */ + char *name; + /* Value (enum representation). */ + union + { + /* Register. */ + reg reg_val; + /* Coprocessor register. */ + copreg copreg_val; + } value; + /* Register image. */ + int image; + /* Register type. */ + reg_type type; + } +reg_entry; + +/* Structure to hold a cst4 operand mapping. */ + +typedef struct + { + /* The binary value which is written to the object file. */ + int binary; + /* The value which is mapped. */ + int value; + } +cst4_entry; + +/* CRX opcode table. */ +extern const inst crx_instruction[]; +extern const int crx_num_opcodes; +#define NUMOPCODES crx_num_opcodes + +/* CRX operands table. */ +extern const operand_entry crx_optab[]; + +/* CRX registers table. */ +extern const reg_entry crx_regtab[]; +extern const int crx_num_regs; +#define NUMREGS crx_num_regs + +/* CRX coprocessor registers table. */ +extern const reg_entry crx_copregtab[]; +extern const int crx_num_copregs; +#define NUMCOPREGS crx_num_copregs + +/* CRX trap/interrupt table. */ +extern const trap_entry crx_traps[]; +extern const int crx_num_traps; +#define NUMTRAPS crx_num_traps + +/* cst4 operand mapping. */ +extern const cst4_entry cst4_map[]; +extern const int cst4_maps; + +/* Current instruction we're assembling. */ +extern const inst *instruction; + +/* A macro for representing the instruction "constant" opcode, that is, + the FIXED part of the instruction. The "constant" opcode is represented + as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) + over that range. */ +#define BIN(OPC,SHIFT) (OPC << SHIFT) + +/* Is the current instruction type is TYPE ? */ +#define IS_INSN_TYPE(TYPE) \ + (CRX_INS_TYPE(instruction->flags) == TYPE) + +/* Is the current instruction mnemonic is MNEMONIC ? */ +#define IS_INSN_MNEMONIC(MNEMONIC) \ + (strcmp(instruction->mnemonic,MNEMONIC) == 0) + +/* Does the current instruction has register list ? */ +#define INST_HAS_REG_LIST \ + (instruction->flags & REG_LIST) + +/* Long long type handling. */ +/* Replace all appearances of 'long long int' with LONGLONG. */ +typedef long long int LONGLONG; +typedef unsigned long long ULONGLONG; +/* A mask for the upper 31 bits of a 64 bits type. */ +#define UPPER31_MASK 0xFFFFFFFE00000000LL + +#endif /* _CRX_H_ */ diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h new file mode 100644 index 000000000..74d9006f1 --- /dev/null +++ b/include/opcode/d10v.h @@ -0,0 +1,208 @@ +/* d10v.h -- Header file for D10V opcode table + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + Written by Martin Hunt (hunt@cygnus.com), Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef D10V_H +#define D10V_H + +/* Format Specifier */ +#define FM00 0 +#define FM01 0x40000000 +#define FM10 0x80000000 +#define FM11 0xC0000000 + +#define NOP 0x5e00 +#define OPCODE_DIVS 0x14002800 + +/* The opcode table is an array of struct d10v_opcode. */ + +struct d10v_opcode +{ + /* The opcode name. */ + const char *name; + + /* the opcode format */ + int format; + + /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ +#define SHORT_OPCODE 1 +#define LONG_OPCODE 8 +#define SHORT_2 1 /* short with 2 operands */ +#define SHORT_B 3 /* short with 8-bit branch */ +#define LONG_B 8 /* long with 16-bit branch */ +#define LONG_L 10 /* long with 3 operands */ +#define LONG_R 12 /* reserved */ + + /* just a placeholder for variable-length instructions */ + /* for example, "bra" will be a fake for "bra.s" and bra.l" */ + /* which will immediately follow in the opcode table. */ +#define OPCODE_FAKE 32 + + /* the number of cycles */ + int cycles; + + /* the execution unit(s) used */ + int unit; +#define EITHER 0 +#define IU 1 +#define MU 2 +#define BOTH 3 + + /* execution type; parallel or sequential */ + /* this field is used to decide if two instructions */ + /* can be executed in parallel */ + int exec_type; +#define PARONLY 1 /* parallel only */ +#define SEQ 2 /* must be sequential */ +#define PAR 4 /* may be parallel */ +#define BRANCH_LINK 8 /* subroutine call. must be aligned */ +#define RMEM 16 /* reads memory */ +#define WMEM 32 /* writes memory */ +#define RF0 64 /* reads f0 */ +#define WF0 128 /* modifies f0 */ +#define WCAR 256 /* write Carry */ +#define BRANCH 512 /* branch, no link */ +#define ALONE 1024 /* short but pack with a NOP if on asm line alone */ + + /* the opcode */ + long opcode; + + /* mask. if( (i & mask) == opcode ) then match */ + long mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct d10v_opcode d10v_opcodes[]; +extern const int d10v_num_opcodes; + +/* The operands table is an array of struct d10v_operand. */ +struct d10v_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the d10v_opcodes table. */ + +extern const struct d10v_operand d10v_operands[]; + +/* Values defined for the flags field of a struct d10v_operand. */ + +/* the operand must be an even number */ +#define OPERAND_EVEN (1) + +/* the operand must be an odd number */ +#define OPERAND_ODD (2) + +/* this is the destination register; it will be modified */ +/* this is used by the optimizer */ +#define OPERAND_DEST (4) + +/* number or symbol */ +#define OPERAND_NUM (8) + +/* address or label */ +#define OPERAND_ADDR (0x10) + +/* register */ +#define OPERAND_REG (0x20) + +/* postincrement + */ +#define OPERAND_PLUS (0x40) + +/* postdecrement - */ +#define OPERAND_MINUS (0x80) + +/* @ */ +#define OPERAND_ATSIGN (0x100) + +/* @( */ +#define OPERAND_ATPAR (0x200) + +/* accumulator 0 */ +#define OPERAND_ACC0 (0x400) + +/* accumulator 1 */ +#define OPERAND_ACC1 (0x800) + +/* f0 / f1 flag register */ +#define OPERAND_FFLAG (0x1000) + +/* c flag register */ +#define OPERAND_CFLAG (0x2000) + +/* control register */ +#define OPERAND_CONTROL (0x4000) + +/* predecrement mode '@-sp' */ +#define OPERAND_ATMINUS (0x8000) + +/* signed number */ +#define OPERAND_SIGNED (0x10000) + +/* special accumulator shifts need a 4-bit number */ +/* 1 <= x <= 16 */ +#define OPERAND_SHIFT (0x20000) + +/* general purpose register */ +#define OPERAND_GPR (0x40000) + +/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ +/* needed for rac/rachi */ +#define RESTRICTED_NUM3 (0x80000) + +/* Pre-decrement is only supported for SP. */ +#define OPERAND_SP (0x100000) + +/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and + unlike OPERAND_SP, this flag doesn't prevent the instruction from + matching, it only fails validation later on. */ +#define OPERAND_NOSP (0x200000) + +/* Structure to hold information about predefined registers. */ +struct pd_reg +{ + char *name; /* name to recognize */ + char *pname; /* name to print for this register */ + int value; +}; + +extern const struct pd_reg d10v_predefined_registers[]; +int d10v_reg_name_cnt (void); + +/* an expressionS only has one register type, so we fake it */ +/* by setting high bits to indicate type */ +#define REGISTER_MASK 0xFF + +#endif /* D10V_H */ diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h new file mode 100644 index 000000000..809bdeb7d --- /dev/null +++ b/include/opcode/d30v.h @@ -0,0 +1,286 @@ +/* d30v.h -- Header file for D30V opcode table + Copyright 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef D30V_H +#define D30V_H + +#define NOP 0x00F00000 + +/* Structure to hold information about predefined registers. */ +struct pd_reg +{ + char *name; /* name to recognize */ + char *pname; /* name to print for this register */ + int value; +}; + +extern const struct pd_reg pre_defined_registers[]; +int reg_name_cnt (void); + +/* the number of control registers */ +#define MAX_CONTROL_REG 64 + +/* define the format specifiers */ +#define FM00 0 +#define FM01 0x80000000 +#define FM10 0x8000000000000000LL +#define FM11 0x8000000080000000LL + +/* define the opcode classes */ +#define BRA 0 +#define LOGIC 1 +#define IMEM 2 +#define IALU1 4 +#define IALU2 5 + +/* define the execution condition codes */ +#define ECC_AL 0 /* ALways (default) */ +#define ECC_TX 1 /* F0=True, F1=Don't care */ +#define ECC_FX 2 /* F0=False, F1=Don't care */ +#define ECC_XT 3 /* F0=Don't care, F1=True */ +#define ECC_XF 4 /* F0=Don't care, F1=False */ +#define ECC_TT 5 /* F0=True, F1=True */ +#define ECC_TF 6 /* F0=True, F1=False */ +#define ECC_RESERVED 7 /* reserved */ +#define ECC_MAX ECC_RESERVED + +extern const char *d30v_ecc_names[]; + +/* condition code table for CMP and CMPU */ +extern const char *d30v_cc_names[]; + +/* The opcode table is an array of struct d30v_opcode. */ +struct d30v_opcode +{ + /* The opcode name. */ + const char *name; + + /* the opcode */ + int op1; /* first part, "IALU1" for example */ + int op2; /* the rest of the opcode */ + + /* opcode format(s). These numbers correspond to entries */ + /* in the d30v_format_table */ + unsigned char format[4]; + +#define SHORT_M 1 +#define SHORT_M2 5 /* for ld2w and st2w */ +#define SHORT_A 9 +#define SHORT_B1 11 +#define SHORT_B2 12 +#define SHORT_B2r 13 +#define SHORT_B3 14 +#define SHORT_B3r 16 +#define SHORT_B3b 18 +#define SHORT_B3br 20 +#define SHORT_D1r 22 +#define SHORT_D2 24 +#define SHORT_D2r 26 +#define SHORT_D2Br 28 +#define SHORT_U 30 /* unary SHORT_A. ABS for example */ +#define SHORT_F 31 /* SHORT_A with flag registers */ +#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ +#define SHORT_T 35 /* for trap instruction */ +#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ +#define SHORT_CMP 38 /* special form for CMPcc */ +#define SHORT_CMPU 40 /* special form for CMPUcc */ +#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ +#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ +#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ +#define SHORT_MODINC 48 +#define SHORT_MODDEC 49 +#define SHORT_C1 50 +#define SHORT_C2 51 +#define SHORT_UF 52 +#define SHORT_A2 53 +#define SHORT_NONE 55 /* no operands */ +#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ +#define LONG 57 +#define LONG_U 58 /* unary LONG */ +#define LONG_Ur 59 /* LONG pc-relative */ +#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ +#define LONG_M 61 /* Memory long for ldb, stb */ +#define LONG_M2 62 /* Memory long for ld2w, st2w */ +#define LONG_2 63 /* LONG with 2 operands; jmptnz */ +#define LONG_2r 64 /* LONG with 2 operands; bratnz */ +#define LONG_2b 65 /* LONG_2 with modifier of 3 */ +#define LONG_2br 66 /* LONG_2r with modifier of 3 */ +#define LONG_D 67 /* for DJMPI */ +#define LONG_Dr 68 /* for DBRAI */ +#define LONG_Dbr 69 /* for repeati */ + + /* the execution unit(s) used */ + int unit; +#define EITHER 0 +#define IU 1 +#define MU 2 +#define EITHER_BUT_PREFER_MU 3 + + /* this field is used to decide if two instructions */ + /* can be executed in parallel */ + long flags_used; + long flags_set; +#define FLAG_0 (1L<<0) +#define FLAG_1 (1L<<1) +#define FLAG_2 (1L<<2) +#define FLAG_3 (1L<<3) +#define FLAG_4 (1L<<4) /* S (saturation) */ +#define FLAG_5 (1L<<5) /* V (overflow) */ +#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ +#define FLAG_7 (1L<<7) /* C (carry/borrow) */ +#define FLAG_SM (1L<<8) /* SM (stack mode) */ +#define FLAG_RP (1L<<9) /* RP (repeat enable) */ +#define FLAG_CONTROL (1L<<10) /* control registers */ +#define FLAG_A0 (1L<<11) /* A0 */ +#define FLAG_A1 (1L<<12) /* A1 */ +#define FLAG_JMP (1L<<13) /* instruction is a branch */ +#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ +#define FLAG_MEM (1L<<15) /* reads/writes memory */ +#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation + New meaning: operation cannot be + combined in parallel with ADD/SUBppp. */ +#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ +#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ +#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ +#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ +#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ +#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) +#define FLAG_C FLAG_7 +#define FLAG_ALL (FLAG_0 | \ + FLAG_1 | \ + FLAG_2 | \ + FLAG_3 | \ + FLAG_4 | \ + FLAG_5 | \ + FLAG_6 | \ + FLAG_7 | \ + FLAG_SM | \ + FLAG_RP | \ + FLAG_CONTROL) + + int reloc_flag; +#define RELOC_PCREL 1 +#define RELOC_ABS 2 +}; + +extern const struct d30v_opcode d30v_opcode_table[]; +extern const int d30v_num_opcodes; + +/* The operands table is an array of struct d30v_operand. */ +struct d30v_operand +{ + /* the length of the field */ + int length; + + /* The number of significant bits in the operand. */ + int bits; + + /* position relative to Ra */ + int position; + + /* syntax flags. */ + long flags; +}; +extern const struct d30v_operand d30v_operand_table[]; + +/* Values defined for the flags field of a struct d30v_operand. */ + +/* this is the destination register; it will be modified */ +/* this is used by the optimizer */ +#define OPERAND_DEST (1) + +/* number or symbol */ +#define OPERAND_NUM (2) + +/* address or label */ +#define OPERAND_ADDR (4) + +/* register */ +#define OPERAND_REG (8) + +/* postincrement + */ +#define OPERAND_PLUS (0x10) + +/* postdecrement - */ +#define OPERAND_MINUS (0x20) + +/* signed number */ +#define OPERAND_SIGNED (0x40) + +/* this operand must be shifted left by 3 */ +#define OPERAND_SHIFT (0x80) + +/* flag register */ +#define OPERAND_FLAG (0x100) + +/* control register */ +#define OPERAND_CONTROL (0x200) + +/* accumulator */ +#define OPERAND_ACC (0x400) + +/* @ */ +#define OPERAND_ATSIGN (0x800) + +/* @( */ +#define OPERAND_ATPAR (0x1000) + +/* predecrement mode '@-sp' */ +#define OPERAND_ATMINUS (0x2000) + +/* this operand changes the instruction name */ +/* for example, CPMcc, CMPUcc */ +#define OPERAND_NAME (0x4000) + +/* fake operand for mvtsys and mvfsys */ +#define OPERAND_SPECIAL (0x8000) + +/* let the optimizer know that two registers are affected */ +#define OPERAND_2REG (0x10000) + +/* This operand is pc-relative. Note that repeati can have two immediate + operands, one of which is pcrel, the other (the IMM6U one) is not. */ +#define OPERAND_PCREL (0x20000) + +/* The format table is an array of struct d30v_format. */ +struct d30v_format +{ + int form; /* SHORT_A, LONG, etc */ + int modifier; /* two bit modifier following opcode */ + unsigned char operands[5]; +}; +extern const struct d30v_format d30v_format_table[]; + + +/* an instruction is defined by an opcode and a format */ +/* for example, "add" has one opcode, but three different */ +/* formats, 2 SHORT_A forms and a LONG form. */ +struct d30v_insn +{ + struct d30v_opcode *op; /* pointer to an entry in the opcode table */ + struct d30v_format *form; /* pointer to an entry in the format table */ + int ecc; /* execution condition code */ +}; + +/* an expressionS only has one register type, so we fake it */ +/* by setting high bits to indicate type */ +#define REGISTER_MASK 0xFF + +#endif /* D30V_H */ diff --git a/include/opcode/dlx.h b/include/opcode/dlx.h new file mode 100644 index 000000000..e1b249f85 --- /dev/null +++ b/include/opcode/dlx.h @@ -0,0 +1,282 @@ +/* Table of opcodes for the DLX microprocess. + Copyright 2002 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Initially created by Kuang Hwa Lin, 2002. */ + +/* Following are the function codes for the Special OP (ALU). */ +#define ALUOP 0x00000000 +#define SPECIALOP 0x00000000 + +#define NOPF 0x00000000 +#define SLLF 0x00000004 +#define SRLF 0x00000006 +#define SRAF 0x00000007 + +#define SEQUF 0x00000010 +#define SNEUF 0x00000011 +#define SLTUF 0x00000012 +#define SGTUF 0x00000013 +#define SLEUF 0x00000014 +#define SGEUF 0x00000015 + +#define ADDF 0x00000020 +#define ADDUF 0x00000021 +#define SUBF 0x00000022 +#define SUBUF 0x00000023 +#define ANDF 0x00000024 +#define ORF 0x00000025 +#define XORF 0x00000026 + +#define SEQF 0x00000028 +#define SNEF 0x00000029 +#define SLTF 0x0000002A +#define SGTF 0x0000002B +#define SLEF 0x0000002C +#define SGEF 0x0000002D + /* Following special functions was not mentioned in the + Hennessy's book but was implemented in the RTL. */ +#define MVTSF 0x00000030 +#define MVFSF 0x00000031 +#define BSWAPF 0x00000032 +#define LUTF 0x00000033 +/* Following special functions was mentioned in the + Hennessy's book but was not implemented in the RTL. */ +#define MULTF 0x00000005 +#define MULTUF 0x00000006 +#define DIVF 0x00000007 +#define DIVUF 0x00000008 + + +/* Following are the rest of the OPcodes: + JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26) + ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26) + ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26) + RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26) + BREAKOP= (0x014 << 26) + SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26) + SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26) + LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26) + LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26) + LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26), + SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26) + SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26) + SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */ +#define JOP 0x08000000 +#define JALOP 0x0c000000 +#define BEQOP 0x10000000 +#define BNEOP 0x14000000 + +#define ADDIOP 0x20000000 +#define ADDUIOP 0x24000000 +#define SUBIOP 0x28000000 +#define SUBUIOP 0x2c000000 +#define ANDIOP 0x30000000 +#define ORIOP 0x34000000 +#define XORIOP 0x38000000 +#define LHIOP 0x3c000000 +#define RFEOP 0x40000000 +#define TRAPOP 0x44000000 +#define JROP 0x48000000 +#define JALROP 0x4c000000 +#define BREAKOP 0x50000000 + +#define SEQIOP 0x60000000 +#define SNEIOP 0x64000000 +#define SLTIOP 0x68000000 +#define SGTIOP 0x6c000000 +#define SLEIOP 0x70000000 +#define SGEIOP 0x74000000 + +#define LBOP 0x80000000 +#define LHOP 0x84000000 +#define LWOP 0x8c000000 +#define LBUOP 0x90000000 +#define LHUOP 0x94000000 +#define LDSTBU +#define LDSTHU +#define SBOP 0xa0000000 +#define SHOP 0xa4000000 +#define SWOP 0xac000000 +#define LDST + +#define SEQUIOP 0xc0000000 +#define SNEUIOP 0xc4000000 +#define SLTUIOP 0xc8000000 +#define SGTUIOP 0xcc000000 +#define SLEUIOP 0xd0000000 +#define SGEUIOP 0xd4000000 + +#define SLLIOP 0xd8000000 +#define SRLIOP 0xdc000000 +#define SRAIOP 0xe0000000 + +/* Following 3 ops was added to provide the MP atonmic operation. */ +#define LSBUOP 0x98000000 +#define LSHUOP 0x9c000000 +#define LSWOP 0xb0000000 + +/* Following opcode was defined in the Hennessy's book as + "normal" opcode but was implemented in the RTL as special + functions. */ +#if 0 +#define MVTSOP 0x50000000 +#define MVFSOP 0x54000000 +#endif + +struct dlx_opcode +{ + /* Name of the instruction. */ + char *name; + + /* Opcode word. */ + unsigned long opcode; + + /* A string of characters which describe the operands. + Valid characters are: + , Itself. The character appears in the assembly code. + a rs1 The register number is in bits 21-25 of the instruction. + b rs2/rd The register number is in bits 16-20 of the instruction. + c rd. The register number is in bits 11-15 of the instruction. + f FUNC bits 0-10 of the instruction. + i An immediate operand is in bits 0-16 of the instruction. 0 extended + I An immediate operand is in bits 0-16 of the instruction. sign extended + d An 16 bit PC relative displacement. + D An immediate operand is in bits 0-25 of the instruction. + N No opperands needed, for nops. + P it can be a register or a 16 bit operand. */ + char *args; +}; + +static const struct dlx_opcode dlx_opcodes[] = + { + /* Arithmetic and Logic R-TYPE instructions. */ + { "nop", (ALUOP|NOPF), "N" }, /* NOP */ + { "add", (ALUOP|ADDF), "c,a,b" }, /* Add */ + { "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */ + { "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */ + { "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */ + { "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */ + { "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */ + { "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */ + { "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */ + { "and", (ALUOP|ANDF), "c,a,b" }, /* AND */ + { "or", (ALUOP|ORF), "c,a,b" }, /* OR */ + { "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */ + { "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */ + { "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */ + { "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */ + { "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */ + { "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */ + { "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */ + { "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */ + { "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */ + { "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */ + { "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */ + { "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */ + { "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */ + { "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */ + { "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/ + { "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */ + { "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */ + { "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */ + { "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */ + { "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */ + + /* Arithmetic and Logical Immediate I-TYPE instructions. */ + { "addi", ADDIOP, "b,a,I" }, /* Add Immediate */ + { "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */ + { "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */ + { "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */ + { "andi", ANDIOP, "b,a,i" }, /* AND Immediate */ + { "ori", ORIOP, "b,a,i" }, /* OR Immediate */ + { "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */ + { "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */ + { "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */ + { "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/ + { "seqi", SEQIOP, "b,a,i" }, /* Set if equal */ + { "snei", SNEIOP, "b,a,i" }, /* Set if not equal */ + { "slti", SLTIOP, "b,a,i" }, /* Set if less */ + { "sgti", SGTIOP, "b,a,i" }, /* Set if greater */ + { "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */ + { "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */ + { "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */ + { "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */ + { "sltui", SLTUIOP, "b,a,i" }, /* Set if less */ + { "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */ + { "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */ + { "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */ + /* Macros for I type instructions. */ + { "mov", ADDIOP, "b,P" }, /* a move macro */ + { "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */ + +#if 0 + /* Move special. */ + { "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */ + { "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */ +#endif + + /* Load high Immediate I-TYPE instruction. */ + { "lhi", LHIOP, "b,i" }, /* Load High Immediate */ + { "lui", LHIOP, "b,i" }, /* Load High Immediate */ + { "sethi", LHIOP, "b,i" }, /* Load High Immediate */ + + /* LOAD/STORE BYTE 8 bits I-TYPE. */ + { "lb", LBOP, "b,a,I" }, /* Load Byte */ + { "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */ + { "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */ + { "sb", SBOP, "b,a,I" }, /* Store Byte */ + + /* LOAD/STORE HALFWORD 16 bits. */ + { "lh", LHOP, "b,a,I" }, /* Load Halfword */ + { "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */ + { "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */ + { "sh", SHOP, "b,a,I" }, /* Store Halfword */ + + /* LOAD/STORE WORD 32 bits. */ + { "lw", LWOP, "b,a,I" }, /* Load Word */ + { "sw", SWOP, "b,a,I" }, /* Store Word */ + { "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */ + + /* Branch PC-relative, 16 bits offset. */ + { "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */ + { "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */ + { "beq", BEQOP, "a,d" }, /* Branch if a == 0 */ + { "bne", BNEOP, "a,d" }, /* Branch if a != 0 */ + + /* Jumps Trap and RFE J-TYPE. */ + { "j", JOP, "D" }, /* Jump, PC-relative 26 bits */ + { "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */ + { "break", BREAKOP, "D" }, /* break to OS */ + { "trap" , TRAPOP, "D" }, /* TRAP to OS */ + { "rfe", RFEOP, "N" }, /* Return From Exception */ + /* Macros. */ + { "call", JOP, "D" }, /* Jump, PC-relative 26 bits */ + + /* Jumps Trap and RFE I-TYPE. */ + { "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ + { "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */ + /* Macros. */ + { "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ + + { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. + This lets code examine entry i + 1 without + checking if we've run off the end of the table. */ + }; + +const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1); diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h new file mode 100644 index 000000000..fe1097fd2 --- /dev/null +++ b/include/opcode/h8300.h @@ -0,0 +1,1892 @@ +/* Opcode table for the H8/300 + Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2003, 2004 + Free Software Foundation, Inc. + Written by Steve Chamberlain <sac@cygnus.com>. + + This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* Instructions are stored as a sequence of nibbles. + If the nibble has value 15 or less than the representation is complete. + Otherwise, we record what it contains with several flags. */ + +typedef int op_type; + +enum h8_flags +{ + L_2 = 0x10, + L_3 = 0x20, + /* 3 bit constant, zero not accepted. */ + L_3NZ = 0x30, + L_4 = 0x40, + L_5 = 0x50, + L_8 = 0x60, + L_8U = 0x70, + L_16 = 0x80, + L_16U = 0x90, + L_24 = 0xA0, + L_32 = 0xB0, + L_P = 0xC0, + + /* Mask to isolate the L_x size bits. */ + SIZE = 0xF0, + + REG = 0x0100, + ABS = 0x0200, + MEMIND = 0x0300, + IMM = 0x0400, + DISP = 0x0500, + IND = 0x0600, + POSTINC = 0x0700, + POSTDEC = 0x0800, + PREINC = 0x0900, + PREDEC = 0x0A00, + PCREL = 0x0B00, + KBIT = 0x0C00, + DBIT = 0x0D00, + CONST_2 = 0x0E00, + CONST_4 = 0x0F00, + CONST_8 = 0x1000, + CONST_16 = 0x1100, + INDEXB = 0x1200, + INDEXW = 0x1300, + INDEXL = 0x1400, + PCIDXB = 0x1500, + PCIDXW = 0x1600, + PCIDXL = 0x1700, + VECIND = 0x1800, + LOWREG = 0x1900, + DATA = 0x2000, + + /* Synonyms. */ + INC = POSTINC, + DEC = PREDEC, + /* Control Registers. */ + CCR = 0x4000, + EXR = 0x4100, + MACH = 0x4200, + MACL = 0x4300, + RESERV1 = 0x4400, + RESERV2 = 0x4500, + VBR = 0x4600, + SBR = 0x4700, + MACREG = 0x4800, + CCR_EXR = 0x4900, + VBR_SBR = 0x4A00, + CC_EX_VB_SB = 0x4B00, + RESERV3 = 0x4C00, + RESERV4 = 0x4D00, + RESERV5 = 0x4E00, + RESERV6 = 0x4F00, + + /* Mask to isolate the addressing mode bits (REG .. PREDEC). */ + MODE = 0x7F00, + + CTRL = 0x4000, + + NO_SYMBOLS = 0x8000, + SRC = 0x10000, + DST = 0x20000, + OP3 = 0x40000, + MEMRELAX = 0x80000, /* Move insn which may relax. */ + + DISPREG = 0x100000, + IGNORE = 0x200000, + ABSJMP = 0x400000, + + B00 = 0x800000, /* Bit 0 must be low. */ + B01 = 0x1000000, /* Bit 0 must be high. */ + B10 = 0x2000000, /* Bit 1 must be low. */ + B11 = 0x4000000, /* Bit 1 must be high. */ + B20 = 0x8000000, /* Bit 2 must be low. */ + B21 = 0x10000000, /* Bit 2 must be high. */ + B30 = 0x20000000, /* Bit 3 must be low. */ + B31 = 0x40000000, /* Bit 3 must be high. */ + E = 0x80000000, /* End of nibble sequence. */ + + /* Immediates smaller than 8 bits are always unsigned. */ + IMM3 = IMM | L_3, + IMM4 = IMM | L_4, + IMM5 = IMM | L_5, + IMM3NZ = IMM | L_3NZ, + IMM2 = IMM | L_2, + + IMM8 = IMM | SRC | L_8, + IMM8U = IMM | SRC | L_8U, + IMM16 = IMM | SRC | L_16, + IMM16U = IMM | SRC | L_16U, + IMM32 = IMM | SRC | L_32, + + IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, + IMM4_NS = IMM4 | NO_SYMBOLS, + IMM8U_NS = IMM8U | NO_SYMBOLS, + IMM16U_NS = IMM16U | NO_SYMBOLS, + + RD8 = DST | L_8 | REG, + RD16 = DST | L_16 | REG, + RD32 = DST | L_32 | REG, + R3_8 = OP3 | L_8 | REG, + R3_16 = OP3 | L_16 | REG, + R3_32 = OP3 | L_32 | REG, + RS8 = SRC | L_8 | REG, + RS16 = SRC | L_16 | REG, + RS32 = SRC | L_32 | REG, + + RSP = SRC | L_P | REG, + RDP = DST | L_P | REG, + + PCREL8 = PCREL | L_8, + PCREL16 = PCREL | L_16, + + OP3PCREL8 = OP3 | PCREL | L_8, + OP3PCREL16 = OP3 | PCREL | L_16, + + INDEXB16 = INDEXB | L_16, + INDEXW16 = INDEXW | L_16, + INDEXL16 = INDEXL | L_16, + INDEXB16D = INDEXB | L_16 | DST, + INDEXW16D = INDEXW | L_16 | DST, + INDEXL16D = INDEXL | L_16 | DST, + + INDEXB32 = INDEXB | L_32, + INDEXW32 = INDEXW | L_32, + INDEXL32 = INDEXL | L_32, + INDEXB32D = INDEXB | L_32 | DST, + INDEXW32D = INDEXW | L_32 | DST, + INDEXL32D = INDEXL | L_32 | DST, + + DISP2SRC = DISP | L_2 | SRC, + DISP16SRC = DISP | L_16 | SRC, + DISP32SRC = DISP | L_32 | SRC, + + DISP2DST = DISP | L_2 | DST, + DISP16DST = DISP | L_16 | DST, + DISP32DST = DISP | L_32 | DST, + + DSTDISPREG = DST | DISPREG, + SRCDISPREG = SRC | DISPREG, + + ABS8SRC = SRC | ABS | L_8, + ABS16SRC = SRC | ABS | L_16U, + ABS24SRC = SRC | ABS | L_24, + ABS32SRC = SRC | ABS | L_32, + + ABS8DST = DST | ABS | L_8, + ABS16DST = DST | ABS | L_16U, + ABS24DST = DST | ABS | L_24, + ABS32DST = DST | ABS | L_32, + + ABS8OP3 = OP3 | ABS | L_8, + ABS16OP3 = OP3 | ABS | L_16U, + ABS24OP3 = OP3 | ABS | L_24, + ABS32OP3 = OP3 | ABS | L_32, + + RDDEC = DST | DEC, + RSINC = SRC | INC, + RDINC = DST | INC, + + RSPOSTINC = SRC | POSTINC, + RDPOSTINC = DST | POSTINC, + RSPREINC = SRC | PREINC, + RDPREINC = DST | PREINC, + RSPOSTDEC = SRC | POSTDEC, + RDPOSTDEC = DST | POSTDEC, + RSPREDEC = SRC | PREDEC, + RDPREDEC = DST | PREDEC, + + RSIND = SRC | IND, + RDIND = DST | IND, + R3_IND = OP3 | IND, + +#define MS32 (SRC | L_32 | MACREG) +#define MD32 (DST | L_32 | MACREG) + +#if 1 + OR8 = RS8, /* ??? OR as in One Register. */ + OR16 = RS16, + OR32 = RS32, +#else + OR8 = RD8, + OR16 = RD16, + OR32 = RD32 +#endif +}; + +enum ctrlreg +{ + C_CCR = 0, + C_EXR = 1, + C_MACH = 2, + C_MACL = 3, + C_VBR = 6, + C_SBR = 7 +}; + +enum {MAX_CODE_NIBBLES = 33}; + +struct code +{ + op_type nib[MAX_CODE_NIBBLES]; +}; + +struct arg +{ + op_type nib[3]; +}; + +/* Availability of instructions on processor models. */ +enum h8_model +{ + AV_H8, + AV_H8H, + AV_H8S, + AV_H8SX +}; + +struct h8_opcode +{ + int how; + enum h8_model available; + int time; + char *name; + struct arg args; + struct code data; +}; + +#ifdef DEFINE_TABLE + +#define DATA2 DATA, DATA +#define DATA3 DATA, DATA, DATA +#define DATA5 DATA, DATA, DATA, DATA, DATA +#define DATA7 DATA, DATA, DATA, DATA, DATA, DATA, DATA + +#define IMM8LIST IMM8, DATA +#define IMM16LIST IMM16, DATA3 +#define IMM16ULIST IMM16U, DATA3 +#define IMM24LIST IMM24, DATA5 +#define IMM32LIST IMM32, DATA7 + +#define DISP16LIST DISP | L_16, DATA3 +#define DISP24LIST DISP | L_24, DATA5 +#define DISP32LIST DISP | L_32, DATA7 + +#define ABS8LIST ABS | L_8, DATA +#define ABS16LIST ABS | L_16U, DATA3 +#define ABS24LIST ABS | L_24, DATA5 +#define ABS32LIST ABS | L_32, DATA7 + +#define DSTABS8LIST DST | ABS | L_8, DATA +#define DSTABS16LIST DST | ABS | L_16U, DATA3 +#define DSTABS24LIST DST | ABS | L_24, DATA5 +#define DSTABS32LIST DST | ABS | L_32, DATA7 + +#define OP3ABS8LIST OP3 | ABS | L_8, DATA +#define OP3ABS16LIST OP3 | ABS | L_16, DATA3 +#define OP3ABS24LIST OP3 | ABS | L_24, DATA5 +#define OP3ABS32LIST OP3 | ABS | L_32, DATA7 + +#define DSTDISP16LIST DST | DISP | L_16, DATA3 +#define DSTDISP24LIST DST | DISP | L_24, DATA5 +#define DSTDISP32LIST DST | DISP | L_32, DATA7 + +#define A16LIST L_16, DATA3 +#define A24LIST L_24, DATA5 +#define A32LIST L_32, DATA7 + +/* Extended Operand Prefixes: */ + +#define PREFIX_010 0x0, 0x1, 0x0 +#define PREFIX_015 0x0, 0x1, 0x5 +#define PREFIX_017 0x0, 0x1, 0x7 + +#define PREFIX_0100 0x0, 0x1, 0x0, 0x0 +#define PREFIX_010_D2 0x0, 0x1, 0x0, B30 | B21 | DISP2SRC +#define PREFIX_0101 0x0, 0x1, 0x0, 0x1 +#define PREFIX_0102 0x0, 0x1, 0x0, 0x2 +#define PREFIX_0103 0x0, 0x1, 0x0, 0x3 +#define PREFIX_0104 0x0, 0x1, 0x0, 0x4 +#define PREFIX_0105 0x0, 0x1, 0x0, 0x5 +#define PREFIX_0106 0x0, 0x1, 0x0, 0x6 +#define PREFIX_0107 0x0, 0x1, 0x0, 0x7 +#define PREFIX_0108 0x0, 0x1, 0x0, 0x8 +#define PREFIX_0109 0x0, 0x1, 0x0, 0x9 +#define PREFIX_010A 0x0, 0x1, 0x0, 0xa +#define PREFIX_010D 0x0, 0x1, 0x0, 0xd +#define PREFIX_010E 0x0, 0x1, 0x0, 0xe + +#define PREFIX_0150 0x0, 0x1, 0x5, 0x0 +#define PREFIX_015_D2 0x0, 0x1, 0x5, B30 | B21 | DISP2SRC +#define PREFIX_0151 0x0, 0x1, 0x5, 0x1 +#define PREFIX_0152 0x0, 0x1, 0x5, 0x2 +#define PREFIX_0153 0x0, 0x1, 0x5, 0x3 +#define PREFIX_0154 0x0, 0x1, 0x5, 0x4 +#define PREFIX_0155 0x0, 0x1, 0x5, 0x5 +#define PREFIX_0156 0x0, 0x1, 0x5, 0x6 +#define PREFIX_0157 0x0, 0x1, 0x5, 0x7 +#define PREFIX_0158 0x0, 0x1, 0x5, 0x8 +#define PREFIX_0159 0x0, 0x1, 0x5, 0x9 +#define PREFIX_015A 0x0, 0x1, 0x5, 0xa +#define PREFIX_015D 0x0, 0x1, 0x5, 0xd +#define PREFIX_015E 0x0, 0x1, 0x5, 0xe +#define PREFIX_015F 0x0, 0x1, 0x5, 0xf + +#define PREFIX_0170 0x0, 0x1, 0x7, 0x0 +#define PREFIX_017_D2S 0x0, 0x1, 0x7, B30 | B21 | DISP2SRC +#define PREFIX_017_D2D 0x0, 0x1, 0x7, B30 | B21 | DISP2DST +#define PREFIX_0171 0x0, 0x1, 0x7, 0x1 +#define PREFIX_0172 0x0, 0x1, 0x7, 0x2 +#define PREFIX_0173 0x0, 0x1, 0x7, 0x3 +#define PREFIX_0174 0x0, 0x1, 0x7, 0x4 +#define PREFIX_0175 0x0, 0x1, 0x7, 0x5 +#define PREFIX_0176 0x0, 0x1, 0x7, 0x6 +#define PREFIX_0177 0x0, 0x1, 0x7, 0x7 +#define PREFIX_0178 0x0, 0x1, 0x7, 0x8 +#define PREFIX_0179 0x0, 0x1, 0x7, 0x9 +#define PREFIX_017A 0x0, 0x1, 0x7, 0xa +#define PREFIX_017D 0x0, 0x1, 0x7, 0xd +#define PREFIX_017E 0x0, 0x1, 0x7, 0xe +#define PREFIX_017F 0x0, 0x1, 0x7, 0xf + +#define PREFIX_6A15 0x6, 0xa, 0x1, 0x5 +#define PREFIX_6A35 0x6, 0xa, 0x3, 0x5 +#define PREFIX_6B15 0x6, 0xb, 0x1, 0x5 +#define PREFIX_6B35 0x6, 0xb, 0x3, 0x5 + +#define PREFIX_78R4 0x7, 0x8, B31 | DISPREG, 0x4 +#define PREFIX_78R5 0x7, 0x8, B31 | DISPREG, 0x5 +#define PREFIX_78R6 0x7, 0x8, B31 | DISPREG, 0x6 +#define PREFIX_78R7 0x7, 0x8, B31 | DISPREG, 0x7 + +#define PREFIX_78R4W 0x7, 0x8, B30 | DISPREG, 0x4 +#define PREFIX_78R5W 0x7, 0x8, B30 | DISPREG, 0x5 +#define PREFIX_78R6W 0x7, 0x8, B30 | DISPREG, 0x6 +#define PREFIX_78R7W 0x7, 0x8, B30 | DISPREG, 0x7 + +#define PREFIX_78R4WD 0x7, 0x8, B30 | DSTDISPREG, 0x4 +#define PREFIX_78R5WD 0x7, 0x8, B30 | DSTDISPREG, 0x5 +#define PREFIX_78R6WD 0x7, 0x8, B30 | DSTDISPREG, 0x6 +#define PREFIX_78R7WD 0x7, 0x8, B30 | DSTDISPREG, 0x7 + +#define PREFIX_7974 0x7, 0x9, 0x7, 0x4 +#define PREFIX_7A74 0x7, 0xa, 0x7, 0x4 +#define PREFIX_7A7C 0x7, 0xa, 0x7, 0xc + + +/* Source standard fragment: */ +#define FROM_IND 0, RSIND +#define FROM_POSTINC 8, RSPOSTINC +#define FROM_POSTDEC 10, RSPOSTDEC +#define FROM_PREINC 9, RSPREINC +#define FROM_PREDEC 11, RSPREDEC +#define FROM_DISP2 B30 | B20 | DISP2SRC, DISPREG +#define FROM_DISP16 12, B30 | DISPREG +#define FROM_DISP32 12, B31 | DISPREG +#define FROM_DISP16B 13, B30 | DISPREG +#define FROM_DISP16W 14, B30 | DISPREG +#define FROM_DISP16L 15, B30 | DISPREG +#define FROM_DISP32B 13, B31 | DISPREG +#define FROM_DISP32W 14, B31 | DISPREG +#define FROM_DISP32L 15, B31 | DISPREG +#define FROM_ABS16 4, B30 | IGNORE +#define FROM_ABS32 4, B31 | IGNORE + +/* Destination standard fragment: */ +#define TO_IND 0, RDIND +#define TO_IND_MOV 0, RDIND | B30 +#define TO_POSTINC 8, RDPOSTINC +#define TO_POSTINC_MOV 8, RDPOSTINC | B30 +#define TO_POSTDEC 10, RDPOSTDEC +#define TO_POSTDEC_MOV 10, RDPOSTDEC | B30 +#define TO_PREINC 9, RDPREINC +#define TO_PREINC_MOV 9, RDPREINC | B30 +#define TO_PREDEC 11, RDPREDEC +#define TO_PREDEC_MOV 11, RDPREDEC | B30 +#define TO_DISP2 B30 | B20 | DISP2DST, DSTDISPREG +#define TO_DISP2_MOV B30 | B20 | DISP2DST, DSTDISPREG | B30 +#define TO_DISP16 12, B30 | DSTDISPREG +#define TO_DISP32 12, B31 | DSTDISPREG +#define TO_DISP16B 13, B30 | DSTDISPREG +#define TO_DISP16W 14, B30 | DSTDISPREG +#define TO_DISP16L 15, B30 | DSTDISPREG +#define TO_DISP32B 13, B31 | DSTDISPREG +#define TO_DISP32W 14, B31 | DSTDISPREG +#define TO_DISP32L 15, B31 | DSTDISPREG +#define TO_ABS16 4, B30 | IGNORE +#define TO_ABS32 4, B31 | IGNORE + +/* Source fragment for three-word instruction: */ +#define TFROM_IND 6, 9, B30 | RSIND, 12 +#define TFROM_DISP2 6, 9, B30 | DISPREG, 12 +#define TFROM_ABS16 6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST +#define TFROM_ABS32 6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST +#define TFROM_POSTINC 6, 13, B30 | RSPOSTINC, 12 +#define TFROM_PREINC 6, 13, B30 | RSPREINC, 12 +#define TFROM_POSTDEC 6, 13, B30 | RSPOSTDEC, 12 +#define TFROM_PREDEC 6, 13, B30 | RSPREDEC, 12 +#define TFROM_DISP16 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP16B 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16W 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16L 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32B 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP32W 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP32L 6, 11, 2, 12, DISP32LIST +#define TFROM_ABS16W 6, 11, 1, 12, ABS16LIST +#define TFROM_ABS32W 6, 11, 3, 12, ABS32LIST + +/* Source fragment for three-word instruction: */ +#define TFROM_IND_B 6, 8, B30 | RSIND, 12 +#define TFROM_ABS16_B 6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST +#define TFROM_ABS32_B 6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST + +#define TFROM_DISP2_B 6, 8, B30 | DISPREG, 12 +#define TFROM_POSTINC_B 6, 12, B30 | RSPOSTINC, 12 +#define TFROM_PREINC_B 6, 12, B30 | RSPREINC, 12 +#define TFROM_POSTDEC_B 6, 12, B30 | RSPOSTDEC, 12 +#define TFROM_PREDEC_B 6, 12, B30 | RSPREDEC, 12 +#define TFROM_DISP16_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP16B_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16W_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16L_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32B_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP32W_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP32L_B 6, 10, 2, 12, DISP32LIST + +#define TFROM_ABS16W_B 6, 10, 1, 12, ABS16LIST +#define TFROM_ABS32W_B 6, 10, 3, 12, ABS32LIST + +/* Extended Operand Class Expanders: */ + +#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, DSTABS32LIST, E}}} + +#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, SRC_SUFFIX, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, SRC_SUFFIX, DSTABS32LIST, E}}} + +#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, 0, RDIND, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 8, RDPOSTINC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 9, RDPREINC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, 11, RDPREDEC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, 4, B30 | IGNORE, IMM8LIST, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, 4, B31 | IGNORE, IMM8LIST, DSTABS32LIST, E}}} + +#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, LIST, 0, RDIND, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, LIST, 8, RDPOSTINC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, LIST, 9, RDPREINC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, LIST, 11, RDPREDEC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, LIST, 4, B30 | IGNORE, DATA2, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, LIST, 4, B31 | IGNORE, DATA2, DSTABS32LIST, E}}} + +#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ + {CODE, AV_H8, 4, NAME, {{SRC, RDIND, E}}, {{ 6, OP1, B31 | RDIND, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3, 6, OP3, B31 | RDPOSTINC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1, 6, OP3, B31 | RDPOSTDEC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 2, 6, OP3, B31 | RDPREINC, SRC, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, RDPREDEC, E}}, {{ 6, OP3, B31 | RDPREDEC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} + +#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ + {CODE, AV_H8, 4, NAME, {{RSIND, DST, E}}, {{ 6, OP1, B30 | RSIND, DST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{RSPOSTINC, DST, E}}, {{ 6, OP3, B30 | RSPOSTINC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2, 6, OP3, B30 | RSPOSTDEC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, 1, 6, OP3, B30 | RSPREINC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, 3, 6, OP3, B30 | RSPREDEC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{7, 8, B30 | DISPREG, 2, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{7, 8, B30 | DISPREG, 3, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8, 4, NAME, {{ABS16SRC, DST, E}}, {{ 6, OP2, 0, DST, RELAX16 | ABS16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{ABS32SRC, DST, E}}, {{ 6, OP2, 2, DST, MEMRELAX | ABS32LIST, E}}} + +/* Expansion macros for two-word (plus data) instructions. */ + +/* Expansion from one source to "standard" destinations. */ +#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} + +/* Expansion from one destination to "standard" sources. */ +#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, FROM_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, FROM_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, FROM_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}} + +/* Expansion from immediate source to "standard" destinations. */ +#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}} + +/* Expansion from abs/disp source to "standard" destinations. */ +#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, DSTLIST, TO_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, DSTLIST, TO_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, DSTLIST, TO_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} + +/* Expansion from ind source to "standard" destinations. */ +#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}} + +/* Expansion macros for three word (plus data) instructions. */ + +#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}} + +#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, INFIX, 0, RDIND, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, INFIX, 4, B30 | IGNORE, OPCODE, B30 | IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, INFIX, 4, B31 | IGNORE, OPCODE, B30 | IGNORE, DSTABS32LIST, E}}} + + +#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 6, NAME, RSIND, PREFIX_0104, TFROM_IND, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104, TFROM_POSTINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106, TFROM_POSTDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC, PREFIX_0105, TFROM_PREINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC, PREFIX_0107, TFROM_PREDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC, PREFIX_010_D2, TFROM_DISP2, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104, TFROM_DISP16, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4, TFROM_DISP32, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16, PREFIX_0105, TFROM_DISP16B, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16, PREFIX_0106, TFROM_DISP16W, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16, PREFIX_0107, TFROM_DISP16L, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32, PREFIX_78R5, TFROM_DISP32B, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32, PREFIX_78R6, TFROM_DISP32W, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32, PREFIX_78R7, TFROM_DISP32L, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC, PREFIX_0104, TFROM_ABS16, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC, PREFIX_0104, TFROM_ABS32, OPCODE) + + +#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154, TFROM_POSTINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156, TFROM_POSTDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0155, TFROM_PREINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0157, TFROM_PREDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_015_D2, TFROM_DISP2, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154, TFROM_DISP16, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0155, TFROM_DISP16B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0156, TFROM_DISP16W, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0157, TFROM_DISP16L, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L, OPCODE) + +#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174, TFROM_POSTINC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176, TFROM_POSTDEC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0175, TFROM_PREINC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0177, TFROM_PREDEC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_017_D2S, TFROM_DISP2_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174, TFROM_DISP16_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0175, TFROM_DISP16B_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0176, TFROM_DISP16W_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0177, TFROM_DISP16L_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L_B, OPCODE) + + +/* Use the expansion macros to fill out the opcode table. */ + +#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, OP2, RS8, IGNORE, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, OP2, RS8, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}} + +#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, OP1, OP2, IGNORE, RD8, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \ + {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, RD8, E}}, {{0x7, 0xe, ABS8LIST, OP1, OP2, IGNORE, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8, E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8, E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}} + +#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6A15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6A35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND, E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}} + +#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, OP1, OP2, RS16, IGNORE, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \ + {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}} + +#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, IGNORE, OP1, OP2, IGNORE, RD16, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}} + +#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6B15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6B35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}} + +#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}} + +#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND, E}}, {{PREFIX_0109, TO_IND, OPCODE, B30 | RS32, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \ + {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}} + +#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32, E}}, {{PREFIX_010A, FROM_IND, OPCODE, B30 | RD32, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}} + + +#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174, 0x6, 0xc, B30 | RDPOSTINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC, E}}, {{PREFIX_0175, 0x6, 0xc, B30 | RDPREINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC, E}}, {{PREFIX_0177, 0x6, 0xc, B30 | RDPREDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST, E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | B20 | IGNORE, DSTABS16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | B20 | IGNORE, DSTABS32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8, 2, NAME, {{RS8, RD8, E}}, {{OP2, OP3, RS8, RD8, E}}}, \ + EXPAND_FROM_REG8 (CODE, NAME, OP2, OP3, OP4), \ + EXPAND_TO_REG8 (CODE, NAME, OP2, OP3, OP4), \ + EXPAND_FROM_IND8 (CODE, NAME, OP4), \ + EXPAND_STD_MATRIX_B (CODE, NAME, OP4), \ + EXPAND_FROM_ABS16_B (CODE, NAME, OP4), \ + EXPAND_FROM_ABS32_B (CODE, NAME, OP4) + +#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8H, 6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \ + EXPAND_FROM_IMM16_W (CODE, NAME, OP3), \ + EXPAND_FROM_REG16 (CODE, NAME, OP1, OP2, OP3), \ + EXPAND_TO_REG16 (CODE, NAME, OP1, OP2, OP3), \ + EXPAND_FROM_IND16 (CODE, NAME, OP3), \ + EXPAND_STD_MATRIX_W (CODE, NAME, OP3), \ + EXPAND_FROM_ABS16_W (CODE, NAME, OP3), \ + EXPAND_FROM_ABS32_W (CODE, NAME, OP3) + +#define EXPAND_TWOOP_L(CODE, NAME, OP1) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \ + {CODE, AV_H8H, 6, NAME, {{IMM32, RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST, E}}}, \ + EXPAND_FROM_IMM16_L (CODE, NAME, OP1), \ + EXPAND_FROM_IMM32_L (CODE, NAME, OP1), \ + EXPAND_FROM_REG32 (CODE, NAME, OP1), \ + EXPAND_TO_REG32 (CODE, NAME, OP1), \ + EXPAND_STD_MATRIX_L (CODE, NAME, OP1) + + +/* Old expanders: */ + +#define BITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + {code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \ + {code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \ + {code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \ + {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \ + {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}} + +#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + {code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}} + +#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ + BITOP(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) + +#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ + BITOP_B(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) + +#define WTWOP(code, name, op1, op2) \ + {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}} + +#define BRANCH(code, name, op) \ + {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \ + {code, AV_H8, 4, name, {{PCREL8, E}}, {{0x4, op, PCREL8, DATA | B00, E}}} + + +#define UNOP(code, name, op1, op2) \ + {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}} + +#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{OR8, E}}, {{ OP1, OP2, OP3, OR8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B30 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, E}}, {{ 7, 15, ABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 10, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 10, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8H, 2, NAME, {{OR16, E}}, {{ OP1, OP2, OP3, OR16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B31 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 11, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 11, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8H, 2, NAME, {{OR32, E}}, {{ OP1, OP2, OP3, B30 | OR32, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{PREFIX, 4, 6, 9, B30 | RSIND, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B31 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B31 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B31 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B30 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST, E}}, {{ 7, 15, DSTABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 10, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 10, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B31 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 11, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 11, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT | RD32, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{PREFIX, 4, 6, 9, B30 | RDIND, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}} + +#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST +#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC + +#define O(op, size) (op * 4 + size) +#define OP_SIZE(HOW) (HOW % 4) +#define OP_KIND(HOW) (HOW / 4) + +enum h8_asm_codes +{ + O_RECOMPILE = 0, + O_ADD, + O_ADDX, + O_AND, + O_BAND, + O_BRA, + O_BRAB, + O_BRAW, + O_BRAL, + O_BRAS, + O_BRABC, + O_BRABS, + O_BSRBC, + O_BSRBS, + O_BRN, + O_BHI, + O_BLS, + O_BCC, + O_BCS, + O_BNE, + O_BVC, + O_BVS, + O_BPL, + O_BMI, + O_BGE, + O_BLT, + O_BGT, + O_BLE, + O_ANDC, + O_BEQ, + O_BCLR, + O_BCLREQ, + O_BCLRNE, + O_BSETEQ, + O_BSETNE, + O_BFLD, + O_BFST, + O_BIAND, + O_BILD, + O_BIOR, + O_BIXOR, + O_BIST, + O_BISTZ, + O_BLD, + O_BNOT, + O_BOR, + O_BSET, + O_BSR, + O_BXOR, + O_CMP, + O_DAA, + O_DAS, + O_DEC, + O_DIVU, + O_DIVS, + O_DIVXU, + O_DIVXS, + O_INC, + O_LDC, + O_MOV, + O_MOVAB, + O_MOVAW, + O_MOVAL, + O_MOVMD, + O_MOVSD, + O_OR, + O_ROTL, + O_ROTR, + O_ROTXL, + O_ROTXR, + O_BPT, + O_SHAL, + O_SHAR, + O_SHLL, + O_SHLR, + O_SUB, + O_SUBS, + O_TRAPA, + O_XOR, + O_XORC, + O_BST, + O_BSTZ, + O_BTST, + O_EEPMOV, + O_EXTS, + O_EXTU, + O_JMP, + O_JSR, + O_MULU, + O_MULUU, + O_MULS, + O_MULSU, + O_MULXU, + O_MULXS, + O_NOP, + O_NOT, + O_ORC, + O_RTE, + O_RTEL, + O_STC, + O_SUBX, + O_NEG, + O_RTS, + O_RTSL, + O_SLEEP, + O_ILL, + O_ADDS, + O_SYSCALL, + O_TAS, + O_CLRMAC, + O_LDMAC, + O_MAC, + O_LDM, + O_STM, + O_STMAC, + O_LAST, + /* Change made for System Call processing. */ + O_SYS_CREAT, + O_SYS_OPEN, + O_SYS_READ, + O_SYS_WRITE, + O_SYS_LSEEK, + O_SYS_CLOSE, + O_SYS_STAT, + O_SYS_FSTAT, +/* Space reserved for future file I/O system calls. */ + O_SYS_CMDLINE + /* End of System Call specific Changes. */ +}; + +enum h8_size +{ + SB = 0, + SW = 1, + SL = 2, + SN = 3 +}; + + +/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences. + Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */ + +struct h8_opcode h8_opcodes[] = +{ + {O (O_ADD, SB), AV_H8, 2, "add.b", {{IMM8, RD8, E}}, {{0x8, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0), + + {O (O_ADD, SW), AV_H8, 6, "add.w", {{RS16, RD16, E}}, {{0x0, 0x9, RS16, RD16, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1), + + {O (O_ADD, SL), AV_H8H, 6, "add.l", {{RS32, RD32, E}}, {{0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1), + + {O (O_ADDS, SL), AV_H8, 2, "adds", {{KBIT, RDP, E}}, {{0x0, 0xB,KBIT, RDP, E}}}, + + {O (O_ADDX, SB), AV_H8, 2, "addx", {{IMM8, RD8, E}}, {{0x9, RD8, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8, 2, "addx", {{RS8, RD8, E}}, {{0x0, 0xe, RS8, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x1, RD16, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x0, 0x9, RS16, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x1, RD32, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_AND, SB), AV_H8, 2, "and.b", {{IMM8, RD8, E}}, {{0xe, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0), + + {O (O_AND, SW), AV_H8, 2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6), + + {O (O_AND, SL), AV_H8H, 2, "and.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6), + + {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}}, + {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}}, + + BRANCH (O (O_BRA, SB), "bra", 0x0), + + {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8, E}}, {{0x5, 0x9, LOWREG | L_8 | B30, 0x5, E}}}, + {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}}, + {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}}, + + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + + {O (O_BRAS, SB), AV_H8SX, 0, "bra/s", {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}}, + + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + + BRANCH (O (O_BRA, SB), "bt", 0x0), + BRANCH (O (O_BRN, SB), "brn", 0x1), + BRANCH (O (O_BRN, SB), "bf", 0x1), + BRANCH (O (O_BHI, SB), "bhi", 0x2), + BRANCH (O (O_BLS, SB), "bls", 0x3), + BRANCH (O (O_BCC, SB), "bcc", 0x4), + BRANCH (O (O_BCC, SB), "bhs", 0x4), + BRANCH (O (O_BCS, SB), "bcs", 0x5), + BRANCH (O (O_BCS, SB), "blo", 0x5), + BRANCH (O (O_BNE, SB), "bne", 0x6), + BRANCH (O (O_BEQ, SB), "beq", 0x7), + BRANCH (O (O_BVC, SB), "bvc", 0x8), + BRANCH (O (O_BVS, SB), "bvs", 0x9), + BRANCH (O (O_BPL, SB), "bpl", 0xA), + BRANCH (O (O_BMI, SB), "bmi", 0xB), + BRANCH (O (O_BGE, SB), "bge", 0xC), + BRANCH (O (O_BLT, SB), "blt", 0xD), + BRANCH (O (O_BGT, SB), "bgt", 0xE), + BRANCH (O (O_BLE, SB), "ble", 0xF), + + EBITOP (O (O_BCLR, SB), IMM3 | B30, "bclr", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BAND, SB), IMM3 | B30, "band", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BILD, SB), IMM3 | B31, "bild", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIOR, SB), IMM3 | B31, "bior", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIST, SB), IMM3 | B31, "bist", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BLD, SB), IMM3 | B30, "bld", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + EBITOP (O (O_BNOT, SB), IMM3 | B30, "bnot", 0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BOR, SB), IMM3 | B30, "bor", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + EBITOP (O (O_BSET, SB), IMM3 | B30, "bset", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BST, SB), IMM3 | B30, "bst", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + EBITOP (O (O_BTST, SB), IMM3 | B30, "btst", 0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BXOR, SB), IMM3 | B30, "bxor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + + EBITOP_B (O (O_BCLREQ, SB), IMM3 | B30, "bclr/eq", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + EBITOP_B (O (O_BCLRNE, SB), IMM3 | B30, "bclr/ne", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), + EBITOP_B (O (O_BSETEQ, SB), IMM3 | B30, "bset/eq", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + EBITOP_B (O (O_BSETNE, SB), IMM3 | B30, "bset/ne", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), + BITOP_B (O (O_BISTZ, SB), IMM3 | B31, "bistz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + BITOP_B (O (O_BSTZ, SB), IMM3 | B30, "bstz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND, R3_8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST, R3_8}}, {{0x7, 0xE, DSTABS8LIST, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0xF, R3_8, IMM8LIST, E}}}, + + /* Because the assembler treats SRC, DST and OP3 as ordinals, + I must designate the second argument, an immediate value, as DST. + May God have mercy on my soul. */ + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}}, {{0x7, 0xD, B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}}, {{0x7, 0xF, OP3ABS8LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + + {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL8, E}}, {{0x5, 0x5, PCREL8, DATA, E}}}, + {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}}, + {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8, E}}, {{0x5, 0xd, B30 | LOWREG | L_8, 0x5, E}}}, + {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16, E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}}, + {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32, E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}}, + + {O (O_CMP, SB), AV_H8, 2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00), + + {O (O_CMP, SW), AV_H8, 2, "cmp.w", {{RS16, RD16, E}}, {{0x1, 0xd, RS16, RD16, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2), + + {O (O_CMP, SL), AV_H8H, 6, "cmp.l", {{RS32, RD32, E}}, {{0x1, 0xf, B31 | RS32, B30 | RD32, E}}}, + {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2), + + UNOP (O (O_DAA, SB), "daa", 0x0, 0xF), + UNOP (O (O_DAS, SB), "das", 0x1, 0xF), + UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA), + + {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16, E}}}, + {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, + + {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}}, + {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, + + {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}}, + {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, + + {O (O_DIVXS, SB), AV_H8SX, 0, "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVXS, SB), AV_H8H, 13, "divxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8, RD16, E}}}, + {O (O_DIVXS, SW), AV_H8SX, 0, "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVXS, SW), AV_H8H, 21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}}, + + {O (O_DIVXU, SB), AV_H8SX, 0, "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVXU, SB), AV_H8, 13, "divxu.b", {{RS8, RD16, E}}, {{0x5, 0x1, RS8, RD16, E}}}, + {O (O_DIVXU, SW), AV_H8SX, 0, "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVXU, SW), AV_H8H, 21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3, RS16, B30 | RD32, E}}}, + + {O (O_EEPMOV, SB), AV_H8, 4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}}, + {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}}, + + EXPAND_UNOP_STD_W (O (O_EXTS, SW), "exts.w", PREFIX_015, 0x1, 0x7, 0xd), + EXPAND_UNOP_STD_L (O (O_EXTS, SL), "exts.l", PREFIX_010, 0x1, 0x7, 0xf), + EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0), + EXPAND_UNOP_STD_W (O (O_EXTU, SW), "extu.w", PREFIX_015, 0x1, 0x7, 0x5), + EXPAND_UNOP_STD_L (O (O_EXTU, SL), "extu.l", PREFIX_010, 0x1, 0x7, 0x7), + EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0), + + UNOP (O (O_INC, SB), "inc", 0x0, 0xA), + + {O (O_INC, SW), AV_H8H, 2, "inc.w", {{DBIT, RD16, E}}, {{0x0, 0xB, 0x5 | DBIT, RD16, E}}}, + {O (O_INC, SL), AV_H8H, 2, "inc.l", {{DBIT, RD32, E}}, {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, + + {O (O_JMP, SN), AV_H8, 4, "jmp", {{RSIND, E}}, {{0x5, 0x9, B30 | RSIND, 0x0, E}}}, + {O (O_JMP, SN), AV_H8, 6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}}, + + {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, + + {O (O_JMP, SN), AV_H8, 8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}}, + {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}}, + + {O (O_JSR, SN), AV_H8, 6, "jsr", {{RSIND, E}}, {{0x5, 0xD, B30 | RSIND, 0x0, E}}}, + {O (O_JSR, SN), AV_H8, 8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}}, + + {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, + + {O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}}, + {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}}, + + {O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}}, + {O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}}, + {O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}}, + {O (O_LDC, SB), AV_H8S, 2, "ldc", {{RS8, EXR | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSIND, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSPOSTINC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + + {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}}, + + + {O (O_MOV, SB), AV_H8, 2, "mov.b", {{IMM8, RD8, E}}, {{0xF, RD8, IMM8LIST, E}}}, + {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}}, + {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}}, + MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8), + + {O (O_MOV, SB), AV_H8, 2, "mov.b", {{RS8, RD8, E}}, {{0x0, 0xC, RS8, RD8, E}}}, + MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), + {O (O_MOV, SB), AV_H8, 4, "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}}, + MOVTO_REG_BW (O (O_MOV, SB), "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), + {O (O_MOV, SB), AV_H8, 4, "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST, E}}}, + + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC, FROM_ABS32, ABS32LIST), + + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16, E}}}, + {O (O_MOV, SW), AV_H8, 4, "mov.w", {{IMM16, RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}}, + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}}, + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}}, + + MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS), + MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST), + + {O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}}, + MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0), + MOVTO_REG_BW (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0), + + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC, FROM_ABS32, ABS32LIST), + + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, + + MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS), + MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST), + + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}}, + {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{IMM32, RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST, E}}}, + + MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST), + + {O (O_MOV, SL), AV_H8H, 2, "mov.l", {{RS32, RD32, E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}}, + + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDIND, E}}, {{PREFIX_0100, 0x6, 0x9, B31 | RDIND, B30 | RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103, 0x6, 0xd, B31 | RDPOSTINC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101, 0x6, 0xd, B31 | RDPOSTDEC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC, E}}, {{PREFIX_0102, 0x6, 0xd, B31 | RDPREINC, RS32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS16DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0x8, RS32, DSTABS16LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS32DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTABS32LIST, E}}}, + + {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{RSIND, RD32, E}}, {{PREFIX_0100, 0x6, 0x9, B30 | RSIND, RD32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100, 0x6, 0xd, B30 | RSPOSTINC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102, 0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC, RD32, E}}, {{PREFIX_0101, 0x6, 0xd, B30 | RSPREINC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x0, RD32, SRC | ABS16LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS32SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x2, RD32, SRC | MEMRELAX | ABS32LIST, E}}}, + + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST), + +#define DO_MOVA1(TYPE, OP0, OP1) \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, DISP16LIST, E}}}, \ +\ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, DISP32LIST, E}}} + +#define DO_MOVA2(TYPE, OP0, OP1, OP2) \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, DISP16LIST, E}}}, \ +\ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, DISP32LIST, E}}} + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, DISP16LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, DISP32LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, DISP16LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, DISP32LIST, E}}}, + + DO_MOVA1 (RDIND, 0x0, B30 | RDIND), + DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC), + DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC), + DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC), + DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC), + DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG), + DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (ABS16DST, 0x4, 0x0, DSTABS16LIST), + DO_MOVA2 (ABS32DST, 0x4, 0x8, DSTABS32LIST), + + {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}}, + {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}}, + + {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}}, {{0x7, 0xb, 0x9, 0x4, E}}}, + {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}}, {{0x7, 0xb, 0xa, 0x4, E}}}, + {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}}, {{0x7, 0xb, 0xb, 0x4, E}}}, + {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}}, + + {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}}, + {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}}, + {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULXS, SB), AV_H8SX, 0, "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULXS, SB), AV_H8H, 20, "mulxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8, RD16, E}}}, + {O (O_MULXS, SW), AV_H8SX, 0, "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULXS, SW), AV_H8H, 20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}}, + + {O (O_MULXU, SB), AV_H8SX, 0, "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULXU, SB), AV_H8, 14, "mulxu.b", {{RS8, RD16, E}}, {{0x5, 0x0, RS8, RD16, E}}}, + {O (O_MULXU, SW), AV_H8SX, 0, "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULXU, SW), AV_H8H, 14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2, RS16, B30 | RD32, E}}}, + + EXPAND_UNOP_STD_B (O (O_NEG, SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8), + EXPAND_UNOP_STD_W (O (O_NEG, SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9), + EXPAND_UNOP_STD_L (O (O_NEG, SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb), + + {O (O_NOP, SN), AV_H8, 2, "nop", {{E}}, {{0x0, 0x0, 0x0, 0x0, E}}}, + + EXPAND_UNOP_STD_B (O (O_NOT, SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0), + EXPAND_UNOP_STD_W (O (O_NOT, SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1), + EXPAND_UNOP_STD_L (O (O_NOT, SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3), + + {O (O_OR, SB), AV_H8, 2, "or.b", {{IMM8, RD8, E}}, {{0xc, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0), + + {O (O_OR, SW), AV_H8, 2, "or.w", {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4), + + {O (O_OR, SL), AV_H8H, 2, "or.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4), + + {O (O_ORC, SB), AV_H8, 2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}}, + {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}}, + + {O (O_MOV, SW), AV_H8, 6, "pop.w", {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "pop.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}}, + {O (O_MOV, SW), AV_H8, 6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}}, + + EXPAND_UNOP_STD_B (O (O_ROTL, SB), "rotl.b", PREFIX_017, 0x1, 0x2, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc), + EXPAND_UNOP_STD_W (O (O_ROTL, SW), "rotl.w", PREFIX_015, 0x1, 0x2, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd), + EXPAND_UNOP_STD_L (O (O_ROTL, SL), "rotl.l", PREFIX_010, 0x1, 0x2, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_ROTR, SB), "rotr.b", PREFIX_017, 0x1, 0x3, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc), + EXPAND_UNOP_STD_W (O (O_ROTR, SW), "rotr.w", PREFIX_015, 0x1, 0x3, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd), + EXPAND_UNOP_STD_L (O (O_ROTR, SL), "rotr.l", PREFIX_010, 0x1, 0x3, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_ROTXL, SB), "rotxl.b", PREFIX_017, 0x1, 0x2, 0x0), + EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4), + EXPAND_UNOP_STD_W (O (O_ROTXL, SW), "rotxl.w", PREFIX_015, 0x1, 0x2, 0x1), + EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5), + EXPAND_UNOP_STD_L (O (O_ROTXL, SL), "rotxl.l", PREFIX_010, 0x1, 0x2, 0x3), + EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30), + EXPAND_UNOP_STD_B (O (O_ROTXR, SB), "rotxr.b", PREFIX_017, 0x1, 0x3, 0x0), + EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4), + EXPAND_UNOP_STD_W (O (O_ROTXR, SW), "rotxr.w", PREFIX_015, 0x1, 0x3, 0x1), + EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5), + EXPAND_UNOP_STD_L (O (O_ROTXR, SL), "rotxr.l", PREFIX_010, 0x1, 0x3, 0x3), + EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30), + + + {O (O_BPT, SN), AV_H8, 10, "bpt", {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}}, + {O (O_RTE, SN), AV_H8, 10, "rte", {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}}, + {O (O_RTS, SN), AV_H8, 8, "rts", {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}}, + {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}}, + {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}}, + + EXPAND_UNOP_STD_B (O (O_SHAL, SB), "shal.b", PREFIX_017, 0x1, 0x0, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc), + EXPAND_UNOP_STD_W (O (O_SHAL, SW), "shal.w", PREFIX_015, 0x1, 0x0, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd), + EXPAND_UNOP_STD_L (O (O_SHAL, SL), "shal.l", PREFIX_010, 0x1, 0x0, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_SHAR, SB), "shar.b", PREFIX_017, 0x1, 0x1, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc), + EXPAND_UNOP_STD_W (O (O_SHAR, SW), "shar.w", PREFIX_015, 0x1, 0x1, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd), + EXPAND_UNOP_STD_L (O (O_SHAR, SL), "shar.l", PREFIX_010, 0x1, 0x1, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30), + + EXPAND_UNOP_STD_B (O (O_SHLL, SB), "shll.b", PREFIX_017, 0x1, 0x0, 0x0), + + {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x0, RD8, E}}}, + + EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4), + EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa), + {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}}, + + EXPAND_UNOP_STD_W (O (O_SHLL, SW), "shll.w", PREFIX_015, 0x1, 0x0, 0x1), + + {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x1, RD16, E}}}, + + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5), + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2), + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6), + {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}}, + + EXPAND_UNOP_STD_L (O (O_SHLL, SL), "shll.l", PREFIX_010, 0x1, 0x0, 0x3), + + {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31), + {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_STD_B (O (O_SHLR, SB), "shlr.b", PREFIX_017, 0x1, 0x1, 0x0), + + {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x0, RD8, E}}}, + + EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4), + EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa), + {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}}, + + EXPAND_UNOP_STD_W (O (O_SHLR, SW), "shlr.w", PREFIX_015, 0x1, 0x1, 0x1), + + {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x1, RD16, E}}}, + + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5), + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2), + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6), + {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}, + + EXPAND_UNOP_STD_L (O (O_SHLR, SL), "shlr.l", PREFIX_010, 0x1, 0x1, 0x3), + + {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31), + {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}}, + + {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}}, + + {O (O_STC, SB), AV_H8, 2, "stc", {{CCR | SRC, RD8, E}}, {{0x0, 0x2, B30 | CCR | SRC, RD8, E}}}, + {O (O_STC, SB), AV_H8S, 2, "stc", {{EXR | SRC, RD8, E}}, {{0x0, 0x2, B30 | EXR | SRC, RD8, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, + {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}}, + + + EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01), + + {O (O_SUB, SW), AV_H8, 2, "sub.w", {{RS16, RD16, E}}, {{0x1, 0x9, RS16, RD16, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3), + + {O (O_SUB, SL), AV_H8H, 6, "sub.l", {{RS32, RD32, E}}, {{0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3), + + {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}}, + + {O (O_SUBX, SB), AV_H8, 2, "subx", {{IMM8, RD8, E}}, {{0xb, RD8, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8, 2, "subx", {{RS8, RD8, E}}, {{0x1, 0xe, RS8, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x3, RD16, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x1, 0x9, RS16, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x3, RD32, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2, E}}, {{0x5, 0x7, IMM2, IGNORE, E}}}, + {O (O_TAS, SB), AV_H8H, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}}, + + {O (O_XOR, SB), AV_H8, 2, "xor.b", {{IMM8, RD8, E}}, {{0xd, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0), + + {O (O_XOR, SW), AV_H8, 2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5), + + {O (O_XOR, SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5), + + {O (O_XORC, SB), AV_H8, 2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}}, + {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}}, + + {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}}, + {O (O_MAC, SW), AV_H8S, 2, "mac", {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}}, + {O (O_LDMAC, SL), AV_H8S, 2, "ldmac", {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}}, + {O (O_STMAC, SL), AV_H8S, 2, "stmac", {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}}, + {O (O_LDM, SL), AV_H8H, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}}, + {O (O_STM, SL), AV_H8H, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}}, + {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}} +}; +#else +extern const struct h8_opcode h8_opcodes[]; +#endif + diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h new file mode 100644 index 000000000..8234664a6 --- /dev/null +++ b/include/opcode/hppa.h @@ -0,0 +1,874 @@ +/* Table of opcodes for the PA-RISC. + Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, + 2001, 2002 + Free Software Foundation, Inc. + + Contributed by the Center for Software Science at the + University of Utah (pa-gdb-bugs@cs.utah.edu). + +This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + +/* + * Structure of an opcode table entry. + */ + +/* There are two kinds of delay slot nullification: normal which is + * controled by the nullification bit, and conditional, which depends + * on the direction of the branch and its success or failure. + * + * NONE is unfortunately #defined in the hiux system include files. + * #undef it away. + */ +#undef NONE +struct pa_opcode +{ + const char *name; + unsigned long int match; /* Bits that must be set... */ + unsigned long int mask; /* ... in these bits. */ + char *args; + enum pa_arch arch; + char flags; +}; + +/* Enable/disable strict syntax checking. Not currently used, but will + be necessary for PA2.0 support in the future. */ +#define FLAG_STRICT 0x1 + +/* + All hppa opcodes are 32 bits. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character for each operand of + the instruction. Characters used as a prefix allow any second character to + be used without conflicting with the main operand characters. + + Bit positions in this description follow HP usage of lsb = 31, + "at" is lsb of field. + + In the args field, the following characters must match exactly: + + '+,() ' + + In the args field, the following characters are unused: + + ' " - / 34 6789:; ' + '@ C M [\] ' + '` e g } ' + + Here are all the characters: + + ' !"#$%&'()*+-,./0123456789:;<=>?' + '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_' + '`abcdefghijklmnopqrstuvwxyz{|}~ ' + +Kinds of operands: + x integer register field at 15. + b integer register field at 10. + t integer register field at 31. + a integer register field at 10 and 15 (for PERMH) + 5 5 bit immediate at 15. + s 2 bit space specifier at 17. + S 3 bit space specifier at 18. + V 5 bit immediate value at 31 + i 11 bit immediate value at 31 + j 14 bit immediate value at 31 + k 21 bit immediate value at 31 + l 16 bit immediate value at 31 (wide mode only, unusual encoding). + n nullification for branch instructions + N nullification for spop and copr instructions + w 12 bit branch displacement + W 17 bit branch displacement (PC relative) + X 22 bit branch displacement (PC relative) + z 17 bit branch displacement (just a number, not an address) + +Also these: + + . 2 bit shift amount at 25 + * 4 bit shift amount at 25 + p 5 bit shift count at 26 (to support the SHD instruction) encoded as + 31-p + ~ 6 bit shift count at 20,22:26 encoded as 63-~. + P 5 bit bit position at 26 + q 6 bit bit position at 20,22:26 + T 5 bit field length at 31 (encoded as 32-T) + % 6 bit field length at 23,27:31 (variable extract/deposit) + | 6 bit field length at 19,27:31 (fixed extract/deposit) + A 13 bit immediate at 18 (to support the BREAK instruction) + ^ like b, but describes a control register + ! sar (cr11) register + D 26 bit immediate at 31 (to support the DIAG instruction) + $ 9 bit immediate at 28 (to support POPBTS) + + v 3 bit Special Function Unit identifier at 25 + O 20 bit Special Function Unit operation split between 15 bits at 20 + and 5 bits at 31 + o 15 bit Special Function Unit operation at 20 + 2 22 bit Special Function Unit operation split between 17 bits at 20 + and 5 bits at 31 + 1 15 bit Special Function Unit operation split between 10 bits at 20 + and 5 bits at 31 + 0 10 bit Special Function Unit operation split between 5 bits at 20 + and 5 bits at 31 + u 3 bit coprocessor unit identifier at 25 + F Source Floating Point Operand Format Completer encoded 2 bits at 20 + I Source Floating Point Operand Format Completer encoded 1 bits at 20 + (for 0xe format FP instructions) + G Destination Floating Point Operand Format Completer encoded 2 bits at 18 + H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' + (very similar to 'F') + + r 5 bit immediate value at 31 (for the break instruction) + (very similar to V above, except the value is unsigned instead of + low_sign_ext) + R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions) + (same as r above, except the value is in a different location) + U 10 bit immediate value at 15 (for SSM, RSM on pa2.0) + Q 5 bit immediate value at 10 (a bit position specified in + the bb instruction. It's the same as r above, except the + value is in a different location) + B 5 bit immediate value at 10 (a bit position specified in + the bb instruction. Similar to Q, but 64 bit handling is + different. + Z %r1 -- implicit target of addil instruction. + L ,%r2 completer for new syntax branch + { Source format completer for fcnv + _ Destination format completer for fcnv + h cbit for fcmp + = gfx tests for ftest + d 14 bit offset for single precision FP long load/store. + # 14 bit offset for double precision FP load long/store. + J Yet another 14 bit offset for load/store with ma,mb completers. + K Yet another 14 bit offset for load/store with ma,mb completers. + y 16 bit offset for word aligned load/store (PA2.0 wide). + & 16 bit offset for dword aligned load/store (PA2.0 wide). + < 16 bit offset for load/store with ma,mb completers (PA2.0 wide). + > 16 bit offset for load/store with ma,mb completers (PA2.0 wide). + Y %sr0,%r31 -- implicit target of be,l instruction. + @ implicit immediate value of 0 + +Completer operands all have 'c' as the prefix: + + cx indexed load completer. + cX indexed load completer. Like cx, but emits a space after + in disassembler. + cm short load and store completer. + cM short load and store completer. Like cm, but emits a space + after in disassembler. + cq long load and store completer (like cm, but inserted into a + different location in the target instruction). + cs store bytes short completer. + cA store bytes short completer. Like cs, but emits a space + after in disassembler. + ce long load/store completer for LDW/STW with a different encoding than the + others + cc load cache control hint + cd load and clear cache control hint + cC store cache control hint + co ordered access + + cp branch link and push completer + cP branch pop completer + cl branch link completer + cg branch gate completer + + cw read/write completer for PROBE + cW wide completer for MFCTL + cL local processor completer for cache control + cZ System Control Completer (to support LPA, LHA, etc.) + + ci correction completer for DCOR + ca add completer + cy 32 bit add carry completer + cY 64 bit add carry completer + cv signed overflow trap completer + ct trap on condition completer for ADDI, SUB + cT trap on condition completer for UADDCM + cb 32 bit borrow completer for SUB + cB 64 bit borrow completer for SUB + + ch left/right half completer + cH signed/unsigned saturation completer + cS signed/unsigned completer at 21 + cz zero/sign extension completer. + c* permutation completer + +Condition operands all have '?' as the prefix: + + ?f Floating point compare conditions (encoded as 5 bits at 31) + + ?a add conditions + ?A 64 bit add conditions + ?@ add branch conditions followed by nullify + ?d non-negated add branch conditions + ?D negated add branch conditions + ?w wide mode non-negated add branch conditions + ?W wide mode negated add branch conditions + + ?s compare/subtract conditions + ?S 64 bit compare/subtract conditions + ?t non-negated compare and branch conditions + ?n 32 bit compare and branch conditions followed by nullify + ?N 64 bit compare and branch conditions followed by nullify + ?Q 64 bit compare and branch conditions for CMPIB instruction + + ?l logical conditions + ?L 64 bit logical conditions + + ?b branch on bit conditions + ?B 64 bit branch on bit conditions + + ?x shift/extract/deposit conditions + ?X 64 bit shift/extract/deposit conditions + ?y shift/extract/deposit conditions followed by nullify for conditional + branches + + ?u unit conditions + ?U 64 bit unit conditions + +Floating point registers all have 'f' as a prefix: + + ft target register at 31 + fT target register with L/R halves at 31 + fa operand 1 register at 10 + fA operand 1 register with L/R halves at 10 + fX Same as fA, except prints a space before register during disasm + fb operand 2 register at 15 + fB operand 2 register with L/R halves at 15 + fC operand 3 register with L/R halves at 16:18,21:23 + fe Like fT, but encoding is different. + fE Same as fe, except prints a space before register during disasm. + fx target register at 15 (only for PA 2.0 long format FLDD/FSTD). + +Float registers for fmpyadd and fmpysub: + + fi mult operand 1 register at 10 + fj mult operand 2 register at 15 + fk mult target register at 20 + fl add/sub operand register at 25 + fm add/sub target register at 31 + +*/ + + +#if 0 +/* List of characters not to put a space after. Note that + "," is included, as the "spopN" operations use literal + commas in their completer sections. */ +static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}"; +#endif + +/* The order of the opcodes in this table is significant: + + * The assembler requires that all instances of the same mnemonic must be + consecutive. If they aren't, the assembler will bomb at runtime. + + * The disassembler should not care about the order of the opcodes. */ + +static const struct pa_opcode pa_opcodes[] = +{ + +/* Pseudo-instructions. */ + +{ "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */ +{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ + +{ "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, +{ "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, +{ "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +{ "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT}, +{ "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT}, +{ "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT}, +{ "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, +{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT}, +{ "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +{ "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */ +{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */ +{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */ + +/* Loads and Stores for integer registers. */ + +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(b)", pa10, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(b)", pa20, FLAG_STRICT}, +{ "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldwa", 0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa10, FLAG_STRICT}, +{ "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa10, FLAG_STRICT}, +{ "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldda", 0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(b),t", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(b)", pa10, 0}, + +/* Immediate instructions. */ +{ "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0}, +{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0}, + +/* Branching instructions. */ +{ "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT}, +{ "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT}, +{ "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */ +{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0}, +{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0}, +{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0}, +{ "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT}, +{ "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0}, +{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0}, +{ "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0}, +{ "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, +{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, +{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, +{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, +{ "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT}, + +/* Computation Instructions. */ + +{ "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT}, +{ "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT}, +{ "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT}, +{ "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT}, +{ "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0}, +{ "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT}, +{ "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT}, +{ "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT}, +{ "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT}, +{ "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0}, + +/* Subword Operation Instructions. */ + +{ "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT}, +{ "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT}, +{ "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT}, +{ "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT}, + + +/* Extract and Deposit Instructions. */ + +{ "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT}, +{ "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT}, +{ "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT}, +{ "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT}, +{ "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0}, +{ "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0}, +{ "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT}, +{ "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT}, +{ "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT}, +{ "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT}, +{ "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT}, +{ "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT}, +{ "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT}, +{ "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT}, +{ "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT}, +{ "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT}, +{ "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0}, +{ "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0}, + +/* System Control Instructions. */ + +{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0}, +{ "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT}, +{ "rfi", 0x00000c00, 0xffffffff, "", pa10, 0}, +{ "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0}, +{ "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10, 0}, +{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0}, +{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0}, +{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, +{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT}, +{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0}, +{ "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT}, +{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0}, +{ "sync", 0x00000400, 0xffffffff, "", pa10, 0}, +{ "syncdma", 0x00100400, 0xffffffff, "", pa10, 0}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT}, +{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10, 0}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, +{ "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, +{ "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, + +/* These may be specific to certain versions of the PA. Joel claimed + they were 72000 (7200?) specific. However, I'm almost certain the + mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, +{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, +{ "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, +{ "tocdis", 0x14401620, 0xffffffff, "", pa10, 0}, +{ "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, +{ "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, + +/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either + the Timex FPU or the Mustang ERS (not sure which) manual. */ +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(b)", pa11, 0}, + +/* Floating Point Coprocessor Instructions. */ + +{ "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc001380, "cxccx(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000000, "cJd(b),fe", pa20, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq#(b),fx", pa20, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000000, "cJfe,y(b)", pa20w, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000000, "cJfe,d(b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqfx,#(b)", pa20, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(b),fT", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(b),ft", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, +{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0}, +{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0}, +{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0}, +{ "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0}, +{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT}, +{ "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT}, +{ "ftest", 0x30002420, 0xffffffff, "", pa10, 0}, +{ "fid", 0x30000000, 0xffffffff, "", pa11, 0}, + +/* Performance Monitor Instructions. */ + +{ "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT}, +{ "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT}, + +/* Assist Instructions. */ + +{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0}, +{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0}, +{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, +{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, +{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, 0}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa20, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, + +/* More pseudo instructions which must follow the main table. */ +{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, +{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, + +}; + +#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) + +/* SKV 12/18/92. Added some denotations for various operands. */ + +#define PA_IMM11_AT_31 'i' +#define PA_IMM14_AT_31 'j' +#define PA_IMM21_AT_31 'k' +#define PA_DISP12 'w' +#define PA_DISP17 'W' + +#define N_HPPA_OPERAND_FORMATS 5 diff --git a/include/opcode/i370.h b/include/opcode/i370.h new file mode 100644 index 000000000..e317f2364 --- /dev/null +++ b/include/opcode/i370.h @@ -0,0 +1,265 @@ +/* i370.h -- Header file for S/390 opcode table + Copyright 1994, 1995, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef I370_H +#define I370_H + +/* The opcode table is an array of struct i370_opcode. */ +typedef union +{ + unsigned int i[2]; + unsigned short s[4]; + unsigned char b[8]; +} i370_insn_t; + +struct i370_opcode +{ + /* The opcode name. */ + const char *name; + + /* the length of the instruction */ + char len; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + i370_insn_t opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + i370_insn_t mask; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The defined values + are listed below. */ + unsigned long flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct i370_opcode i370_opcodes[]; +extern const int i370_num_opcodes; + +/* Values defined for the flags field of a struct i370_opcode. */ + +/* Opcode is defined for the original 360 architecture. */ +#define I370_OPCODE_360 (0x01) + +/* Opcode is defined for the 370 architecture. */ +#define I370_OPCODE_370 (0x02) + +/* Opcode is defined for the 370-XA architecture. */ +#define I370_OPCODE_370_XA (0x04) + +/* Opcode is defined for the ESA/370 architecture. */ +#define I370_OPCODE_ESA370 (0x08) + +/* Opcode is defined for the ESA/390 architecture. */ +#define I370_OPCODE_ESA390 (0x10) + +/* Opcode is defined for the ESA/390 w/ BFP facility. */ +#define I370_OPCODE_ESA390_BF (0x20) + +/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ +#define I370_OPCODE_ESA390_BS (0x40) + +/* Opcode is defined for the ESA/390 w/ checksum facility. */ +#define I370_OPCODE_ESA390_CK (0x80) + +/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ +#define I370_OPCODE_ESA390_CM (0x100) + +/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ +#define I370_OPCODE_ESA390_FX (0x200) + +/* Opcode is defined for the ESA/390 w/ HFP facility. */ +#define I370_OPCODE_ESA390_HX (0x400) + +/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ +#define I370_OPCODE_ESA390_IR (0x800) + +/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ +#define I370_OPCODE_ESA390_MI (0x1000) + +/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ +#define I370_OPCODE_ESA390_PC (0x2000) + +/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ +#define I370_OPCODE_ESA390_PL (0x4000) + +/* Opcode is defined for the ESA/390 w/ square-root facility. */ +#define I370_OPCODE_ESA390_QR (0x8000) + +/* Opcode is defined for the ESA/390 w/ resume-program facility. */ +#define I370_OPCODE_ESA390_RP (0x10000) + +/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ +#define I370_OPCODE_ESA390_SA (0x20000) + +/* Opcode is defined for the ESA/390 w/ subspace group facility. */ +#define I370_OPCODE_ESA390_SG (0x40000) + +/* Opcode is defined for the ESA/390 w/ string facility. */ +#define I370_OPCODE_ESA390_SR (0x80000) + +/* Opcode is defined for the ESA/390 w/ trap facility. */ +#define I370_OPCODE_ESA390_TR (0x100000) + +#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) + + +/* The operands table is an array of struct i370_operand. */ + +struct i370_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + i370_insn_t (*insert) + (i370_insn_t instruction, long op, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & I370_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) (i370_insn_t instruction, int *invalid); + + /* One bit syntax flags. */ + unsigned long flags; + + /* name -- handy for debugging, otherwise pointless */ + char * name; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the i370_opcodes table. */ + +extern const struct i370_operand i370_operands[]; + +/* Values defined for the flags field of a struct i370_operand. */ + +/* This operand should be wrapped in parentheses rather than + separated from the previous by a comma. This is used for S, RS and + SS form instructions which want their operands to look like + reg,displacement(basereg) */ +#define I370_OPERAND_SBASE (0x01) + +/* This operand is a base register. It may or may not appear next + to an index register, i.e. either of the two forms + reg,displacement(basereg) + reg,displacement(index,basereg) */ +#define I370_OPERAND_BASE (0x02) + +/* This pair of operands should be wrapped in parentheses rather than + separated from the last by a comma. This is used for the RX form + instructions which want their operands to look like + reg,displacement(index,basereg) */ +#define I370_OPERAND_INDEX (0x04) + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define I370_OPERAND_GPR (0x08) + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define I370_OPERAND_FPR (0x10) + +/* This operand is a displacement. */ +#define I370_OPERAND_RELATIVE (0x20) + +/* This operand is a length, such as that in SS form instructions. */ +#define I370_OPERAND_LENGTH (0x40) + +/* This operand is optional, and is zero if omitted. This is used for + the optional B2 field in the shift-left, shift-right instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ +#define I370_OPERAND_OPTIONAL (0x80) + + +/* Define some misc macros. We keep them with the operands table + for simplicity. The macro table is an array of struct i370_macro. */ + +struct i370_macro +{ + /* The macro name. */ + const char *name; + + /* The number of operands the macro takes. */ + unsigned int operands; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct i370_opcode flags field. */ + unsigned long flags; + + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char *format; +}; + +extern const struct i370_macro i370_macros[]; +extern const int i370_num_macros; + + +#endif /* I370_H */ diff --git a/include/opcode/i386.h b/include/opcode/i386.h new file mode 100644 index 000000000..96bf149d5 --- /dev/null +++ b/include/opcode/i386.h @@ -0,0 +1,1612 @@ +/* opcode/i386.h -- Intel 80386 opcode table + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002, 2003, 2004 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived + ix86 Unix assemblers, generate floating point instructions with + reversed source and destination registers in certain cases. + Unfortunately, gcc and possibly many other programs use this + reversed syntax, so we're stuck with it. + + eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but + `fsub %st,%st(3)' results in st(3) = st - st(3), rather than + the expected st(3) = st(3) - st + + This happens with all the non-commutative arithmetic floating point + operations with two register operands, where the source register is + %st, and destination register is %st(i). See FloatDR below. + + The affected opcode map is dceX, dcfX, deeX, defX. */ + +#ifndef SYSV386_COMPAT +/* Set non-zero for broken, compatible instructions. Set to zero for + non-broken opcodes at your peril. gcc generates SystemV/386 + compatible instructions. */ +#define SYSV386_COMPAT 1 +#endif +#ifndef OLDGCC_COMPAT +/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could + generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands + reversed. */ +#define OLDGCC_COMPAT SYSV386_COMPAT +#endif + +static const template i386_optab[] = +{ + +#define X None +#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) +#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) +#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) +#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf) +#define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) +#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf) +#define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf) +#define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf) +#define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) +#define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) +#define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) +#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) +#define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) +#define sldx_Suf (No_bSuf|No_wSuf|No_qSuf) +#define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) +#define bwlq_Suf (No_sSuf|No_xSuf) +#define FP (NoSuf|IgnoreSize) +#define l_FP (l_Suf|IgnoreSize) +#define x_FP (x_Suf|IgnoreSize) +#define sl_FP (sl_Suf|IgnoreSize) +#if SYSV386_COMPAT +/* Someone forgot that the FloatR bit reverses the operation when not + equal to the FloatD bit. ie. Changing only FloatD results in the + destination being swapped *and* the direction being reversed. */ +#define FloatDR FloatD +#else +#define FloatDR (FloatD|FloatR) +#endif + +/* Move instructions. */ +#define MOV_AX_DISP32 0xa0 +/* In the 64bit mode the short form mov immediate is redefined to have + 64bit displacement value. */ +{ "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, +{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +/* In the 64bit mode the short form mov immediate is redefined to have + 64bit displacement value. */ +{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } }, +{ "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } }, +{ "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, +/* The segment register moves accept WordReg so that a segment register + can be copied to a 32 bit register, and vice versa, without using a + size prefix. When moving to a 32 bit register, the upper 16 bits + are set to an implementation defined value (on the Pentium Pro, + the implementation defined value is zero). */ +{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } }, +{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } }, +{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } }, +{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } }, +/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit + mode they are 64bit.*/ +{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, +{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, +{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, +{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, +{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, + +/* Move with sign extend. */ +/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid + conflict with the "movs" string move instruction. */ +{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, +{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, +{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} }, +{"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, +{"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, +{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, +/* Intel Syntax next 5 insns */ +{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, +{"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, +{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, +{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, + +/* Move with zero extend. */ +{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, +/* These instructions are not particulary usefull, since the zero extend + 32->64 is implicit, but we can encode them. */ +{"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, +{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, +/* Intel Syntax next 4 insns */ +{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, +/* These instructions are not particulary usefull, since the zero extend + 32->64 is implicit, but we can encode them. */ +{"movzx", 2, 0x0fb6, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, +{"movzx", 2, 0x0fb7, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, + +/* Push instructions. */ +{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, +{"push", 1, 0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +/* In 64bit mode, the operand size is implicitly 64bit. */ +{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, +{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, +{"push", 1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, + +{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, + +/* Pop instructions. */ +{"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, +#define POP_SEG_SHORT 0x07 +{"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +/* In 64bit mode, the operand size is implicitly 64bit. */ +{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, +{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, +{"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, + +{"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, + +/* Exchange instructions. + xchg commutes: we allow both operand orders. + + In the 64bit code, xchg eax, eax is reused for new nop instruction. */ +#if 0 /* While the two entries that are disabled generate shorter code + for xchg eax, reg (on x86_64), the special case xchg eax, eax + does not get handled correctly - it degenerates into nop, but + that way the side effect of zero-extending eax to rax is lost. */ +{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } }, +{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } }, +#else +{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, +{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, +{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } }, +{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } }, +#endif +{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, + +/* In/out from ports. */ +/* XXX should reject %rax */ +{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, +{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, +{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, +{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, +{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, +{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, +{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, +{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, + +/* Load effective address. */ +{"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, + +/* Load segment registers from memory. */ +{"lds", 2, 0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"les", 2, 0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, + +/* Flags register instructions. */ +{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, +{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, +{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, +{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, +{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, +{"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} }, +{"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} }, +{"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, +{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, +{"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, +{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, +{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, + +/* Arithmetic. */ +{"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} }, +{"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} }, +{"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, +{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +/* clr with 1 operand is really xor with 2 operands. */ +{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, + +{"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"aaa", 0, 0x37, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"aas", 0, 0x3f, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8S, 0, 0} }, +{"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8S, 0, 0} }, + +/* Conversion insns. */ +/* Intel naming */ +{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, +{"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, +{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, +{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, +{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, +{"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, +/* AT&T naming */ +{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, +{"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, +{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, +{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, +{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, +{"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, + +/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are + expanding 64-bit multiplies, and *cannot* be selected to accomplish + 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) + These multiplies can only be selected with single operand forms. */ +{"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, +{"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} }, +/* imul with 2 operands mimics imul with 3 by putting the register in + both i.rm.reg & i.rm.regmem fields. regKludge enables this + transformation. */ +{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, +{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} }, + +{"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, +{"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, + +{"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, +{"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, +{"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, + +{"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, +{"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, +{"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, + +/* Control transfer instructions. */ +{"call", 1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, +{"call", 1, 0xe8, X, Cpu64, wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} }, +{"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} }, +/* Intel Syntax */ +{"call", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +/* Intel Syntax */ +{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, {WordMem, 0, 0} }, +{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} }, +{"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, + +#define JUMP_PC_RELATIVE 0xeb +{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp,0, 0} }, +{"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} }, +/* Intel Syntax. */ +{"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +/* Intel Syntax. */ +{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} }, +{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +{"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, + +{"ret", 0, 0xc3, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, +{"ret", 1, 0xc2, X, CpuNo64,wl_Suf|DefaultSize, { Imm16, 0, 0} }, +{"ret", 0, 0xc3, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"ret", 1, 0xc2, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, +{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, +{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, +{"enter", 2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, +{"enter", 2, 0xc8, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm16, Imm8, 0} }, +{"leave", 0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"leave", 0, 0xc9, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { 0, 0, 0} }, + +/* Conditional jumps. */ +{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, + +/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ +{"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} }, +{"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, +{"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, +{"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} }, + +/* The loop instructions also use the address size prefix to select + %cx rather than %ecx for the loop count, so the `w' form of these + instructions emit an address size prefix rather than a data size + prefix. */ +{"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, +{"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, +{"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, +{"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, +{"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, + +/* Set byte on flag instructions. */ +{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, + +/* String manipulation. */ +{"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, +{"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, +{"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, +{"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, +{"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, +{"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, +{"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, +{"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, +{"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, +{"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, +{"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, +{"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, +{"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, +{"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, +{"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, +{"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, +{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, +{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, + +/* Bit manipulation. */ +{"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, + +/* Interrupts & op. sys insns. */ +/* See gas/config/tc-i386.c for conversion of 'int $3' into the special + int 3 insn. */ +#define INT_OPCODE 0xcd +#define INT3_OPCODE 0xcc +{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, +{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, +{"into", 0, 0xce, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, +/* i386sl, i486sl, later 486, and Pentium. */ +{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, + +{"bound", 2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm, { WordReg, WordMem, 0} }, + +{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, +/* nop is actually 'xchgl %eax, %eax'. */ +{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, + +/* Protection control. */ +{"arpl", 2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, +{"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"lgdt", 1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"lgdt", 1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, +{"lidt", 1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"lidt", 1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, +{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, + +{"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, +{"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm, { LLongMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, + +{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, + +/* Floating point instructions. */ + +/* load */ +{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +/* Intel Syntax */ +{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, +{"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +/* Intel Syntax */ +{"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} }, + +/* store (no pop) */ +{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +/* store (with pop) */ +{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +/* Intel Syntax */ +{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, +{"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +/* Intel Syntax */ +{"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} }, + +/* exchange %st<n> with %st0 */ +{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +/* alias for fxch %st(1) */ +{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, + +/* comparison (without pop) */ +{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +/* alias for fcom %st(1) */ +{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, +{"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +/* comparison (with pop) */ +{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +/* alias for fcomp %st(1) */ +{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, +{"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, + +/* unordered comparison (with pop) */ +{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, +/* alias for fucom %st(1) */ +{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, +{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, +/* alias for fucomp %st(1) */ +{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, +{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, + +{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, +{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, + +/* load constants into %st0 */ +{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, +{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, +{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, +{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, +{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, +{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, +{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, + +/* Arithmetic. */ + +/* add */ +{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, +/* alias for fadd %st(i), %st */ +{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +/* alias for faddp */ +{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, +#endif +{"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +/* alias for faddp %st, %st(1) */ +{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, +{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, + +/* subtract */ +{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +/* alias for fsubp */ +{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, +#endif +{"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +#if SYSV386_COMPAT +{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT +{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +#endif +#else +{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, +#endif + +/* subtract reverse */ +{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +/* alias for fsubrp */ +{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, +#endif +{"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +#if SYSV386_COMPAT +{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT +{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +#endif +#else +{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, +#endif + +/* multiply */ +{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, +{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +/* alias for fmulp */ +{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, +#endif +{"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, +{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, + +/* divide */ +{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +/* alias for fdivp */ +{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, +#endif +{"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +#if SYSV386_COMPAT +{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT +{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +#endif +#else +{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, +#endif + +/* divide reverse */ +{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +/* alias for fdivrp */ +{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, +#endif +{"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +#if SYSV386_COMPAT +{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT +{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +#endif +#else +{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, +#endif + +{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, +{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, +{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, +{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, +{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, +{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, +{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, +{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, +{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, +{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, +{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, +{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, +{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, +{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, +{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, +{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, +{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, +{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, + +/* processor control */ +{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, +{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, +{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} }, +{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, +{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, +{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} }, +{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, +{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, +{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} }, +{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, +{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, +{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, +{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, +/* Short forms of fldenv, fstenv use data size prefix. */ +{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, +{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, +{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, + +{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +/* P6:free st(i), pop st */ +{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, +{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, +#define FWAIT_OPCODE 0x9b +{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, + +/* Opcode prefixes; we allow them as separate insns too. */ + +#define ADDR_PREFIX_OPCODE 0x67 +{"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +#define DATA_PREFIX_OPCODE 0x66 +{"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +#define LOCK_PREFIX_OPCODE 0xf0 +{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +#define CS_PREFIX_OPCODE 0x2e +{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +#define DS_PREFIX_OPCODE 0x3e +{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +#define ES_PREFIX_OPCODE 0x26 +{"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, +#define FS_PREFIX_OPCODE 0x64 +{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, +#define GS_PREFIX_OPCODE 0x65 +{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, +#define SS_PREFIX_OPCODE 0x36 +{"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, +#define REPNE_PREFIX_OPCODE 0xf2 +#define REPE_PREFIX_OPCODE 0xf3 +{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, + +/* 486 extensions. */ + +{"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } }, +{"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, +{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, +{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} }, + +/* 586 and late 486 extensions. */ +{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, + +/* Pentium extensions. */ +{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, +{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, +{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, +{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} }, + +/* Pentium II/Pentium Pro extensions. */ +{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, +{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, +{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, +{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, +{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, +/* official undefined instr. */ +{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, +/* alias for ud2 */ +{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, +/* 2nd. official undefined instr. */ +{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, + +{"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, + +{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, + +{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, +{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, +{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, +{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, +{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, + +/* Pentium4 extensions. */ + +{"movnti", 2, 0x0fc3, X, CpuP4, FP|Modrm, { WordReg, WordMem, 0 } }, +{"clflush", 1, 0x0fae, 7, CpuP4, FP|Modrm, { ByteMem, 0, 0 } }, +{"lfence", 0, 0x0fae, 0xe8, CpuP4, FP|ImmExt, { 0, 0, 0 } }, +{"mfence", 0, 0x0fae, 0xf0, CpuP4, FP|ImmExt, { 0, 0, 0 } }, +{"pause", 0, 0xf390, X, CpuP4, FP, { 0, 0, 0 } }, + +/* MMX/SSE2 instructions. */ + +{"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } }, +{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, +{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg32|LLongMem, RegXMM, 0 } }, +{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg32|LLongMem, 0 } }, +/* Real MMX instructions. */ +{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, +{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, +{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, +/* In the 64bit mode the short form mov immediate is redefined to have + 64bit displacement value. */ +{"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, +{"movq", 2, 0xf30f7e,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movq", 2, 0x660fd6,X,CpuSSE2,FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, +{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, +{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, +/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit + mode they are 64bit.*/ +{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, +{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, +{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddb", 2, 0x660ffc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddw", 2, 0x660ffd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddd", 2, 0x660ffe,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddq", 2, 0x0fd4, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"paddq", 2, 0x660fd4,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsb", 2, 0x660fec,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsw", 2, 0x660fed,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusb", 2, 0x660fdc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusw", 2, 0x660fdd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pand", 2, 0x660fdb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pandn", 2, 0x660fdf,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhw", 2, 0x660fe5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmullw", 2, 0x660fd5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"por", 2, 0x660feb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x660ff1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psllw", 2, 0x660f71,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pslld", 2, 0x660ff2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"pslld", 2, 0x660f72,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllq", 2, 0x660ff3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psllq", 2, 0x660f73,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psraw", 2, 0x660fe1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psraw", 2, 0x660f71,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrad", 2, 0x660fe2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrad", 2, 0x660f72,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlw", 2, 0x660fd1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlw", 2, 0x660f71,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrld", 2, 0x660fd2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrld", 2, 0x660f72,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlq", 2, 0x660fd3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlq", 2, 0x660f73,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubb", 2, 0x660ff8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubw", 2, 0x660ff9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubd", 2, 0x660ffa,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubq", 2, 0x0ffb, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"psubq", 2, 0x660ffb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsb", 2, 0x660fe8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsw", 2, 0x660fe9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusb", 2, 0x660fd8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusw", 2, 0x660fd9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pxor", 2, 0x660fef,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, + +/* PIII Katmai New Instructions / SIMD instructions. */ + +{"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, +{"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, +{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, +{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, +{"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, +{"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, +{"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, +{"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } }, +{"movntdq", 2, 0x660fe7, X, CpuSSE2,FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, +{"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pextrw", 3, 0x0fc5, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, +{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } }, +{"pinsrw", 3, 0x0fc4, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, +{"pinsrw", 3, 0x660fc4, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, +{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxsw", 2, 0x660fee, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxub", 2, 0x660fde, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmovmskb", 2, 0x0fd7, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, +{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, +{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, +{"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"psadbw", 2, 0x660ff6, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, +{"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"sfence", 0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt, { 0, 0, 0 } }, +{"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, +{"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, + +/* SSE-2 instructions. */ + +{"addpd", 2, 0x660f58, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addsd", 2, 0xf20f58, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"andnpd", 2, 0x660f55, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andpd", 2, 0x660f54, X, CpuSSE2, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +/* Intel mode string compare. */ +{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, +{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, +{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, +{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, +{"divpd", 2, 0x660f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divsd", 2, 0xf20f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"maxpd", 2, 0x660f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxsd", 2, 0xf20f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"minpd", 2, 0x660f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minsd", 2, 0xf20f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"movapd", 2, 0x660f28, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movapd", 2, 0x660f29, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhpd", 2, 0x660f16, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhpd", 2, 0x660f17, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlpd", 2, 0x660f12, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, +{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +/* Intel mode string move. */ +{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, +{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, +{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, +{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movupd", 2, 0x660f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulpd", 2, 0x660f59, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulsd", 2, 0xf20f59, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"orpd", 2, 0x660f56, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"shufpd", 3, 0x660fc6, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtpd", 2, 0x660f51, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"subpd", 2, 0x660f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subsd", 2, 0xf20f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"ucomisd", 2, 0x660f2e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"unpckhpd", 2, 0x660f15, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklpd", 2, 0x660f14, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorpd", 2, 0x660f57, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, +{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, +{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movdqa", 2, 0x660f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movdqa", 2, 0x660f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movdqu", 2, 0xf30f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movdqu", 2, 0xf30f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegMMX, 0 } }, +{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, FP|Modrm, { RegMMX|InvMem, RegXMM, 0 } }, +{"pmuludq", 2, 0x0ff4, X, CpuSSE2, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmuludq", 2, 0x660ff4, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"pshufd", 3, 0x660f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pshufhw", 3, 0xf30f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pshuflw", 3, 0xf20f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pslldq", 2, 0x660f73, 7, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrldq", 2, 0x660f73, 3, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, +{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, + +/* Prescott New Instructions. */ + +{"addsubpd", 2, 0x660fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addsubps", 2, 0xf20fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +/* Intel Syntax */ +{"fisttpq", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"haddpd", 2, 0x660f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"haddps", 2, 0xf20f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"hsubpd", 2, 0x660f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"hsubps", 2, 0xf20f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"lddqu", 2, 0xf20ff0, X, CpuPNI, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"monitor", 0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { 0, 0, 0} }, +/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */ +{"monitor", 3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { Reg32, Reg32, Reg32} }, +{"movddup", 2, 0xf20f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movshdup", 2, 0xf30f16, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movsldup", 2, 0xf30f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mwait", 0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { 0, 0, 0} }, +/* Need to ensure only "mwait %eax,%ecx" is accepted. */ +{"mwait", 2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { Reg32, Reg32, 0} }, + +/* AMD 3DNow! instructions. */ + +{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, +{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, +{"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } }, +{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, + +/* AMD extensions. */ +{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, +{"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, +{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, + +/* VIA PadLock extensions. */ +{"xstorerng", 0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"xcryptecb", 0, 0xf30fa7c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"xcryptcbc", 0, 0xf30fa7d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"xcryptcfb", 0, 0xf30fa7e0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"xcryptofb", 0, 0xf30fa7e8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"montmul", 0, 0xf30fa6c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"xsha1", 0, 0xf30fa6c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"xsha256", 0, 0xf30fa6d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +/* Alias for xstorerng. */ +{"xstore", 0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, + +/* sentinel */ +{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } +}; +#undef X +#undef NoSuf +#undef b_Suf +#undef w_Suf +#undef l_Suf +#undef q_Suf +#undef x_Suf +#undef bw_Suf +#undef bl_Suf +#undef wl_Suf +#undef wlq_Suf +#undef sl_Suf +#undef bwl_Suf +#undef bwlq_Suf +#undef FP +#undef l_FP +#undef x_FP +#undef sl_FP + +#define MAX_MNEM_SIZE 16 /* For parsing insn mnemonics from input. */ + +/* 386 register table. */ + +static const reg_entry i386_regtab[] = +{ + /* Make %st first as we test for it. */ + {"st", FloatReg|FloatAcc, 0, 0}, + /* 8 bit regs */ +#define REGNAM_AL 1 /* Entry in i386_regtab. */ + {"al", Reg8|Acc, 0, 0}, + {"cl", Reg8|ShiftCount, 0, 1}, + {"dl", Reg8, 0, 2}, + {"bl", Reg8, 0, 3}, + {"ah", Reg8, 0, 4}, + {"ch", Reg8, 0, 5}, + {"dh", Reg8, 0, 6}, + {"bh", Reg8, 0, 7}, + {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */ + {"cxl", Reg8, RegRex64, 1}, + {"dxl", Reg8, RegRex64, 2}, + {"bxl", Reg8, RegRex64, 3}, + {"spl", Reg8, RegRex64, 4}, + {"bpl", Reg8, RegRex64, 5}, + {"sil", Reg8, RegRex64, 6}, + {"dil", Reg8, RegRex64, 7}, + {"r8b", Reg8, RegRex64|RegRex, 0}, + {"r9b", Reg8, RegRex64|RegRex, 1}, + {"r10b", Reg8, RegRex64|RegRex, 2}, + {"r11b", Reg8, RegRex64|RegRex, 3}, + {"r12b", Reg8, RegRex64|RegRex, 4}, + {"r13b", Reg8, RegRex64|RegRex, 5}, + {"r14b", Reg8, RegRex64|RegRex, 6}, + {"r15b", Reg8, RegRex64|RegRex, 7}, + /* 16 bit regs */ +#define REGNAM_AX 25 + {"ax", Reg16|Acc, 0, 0}, + {"cx", Reg16, 0, 1}, + {"dx", Reg16|InOutPortReg, 0, 2}, + {"bx", Reg16|BaseIndex, 0, 3}, + {"sp", Reg16, 0, 4}, + {"bp", Reg16|BaseIndex, 0, 5}, + {"si", Reg16|BaseIndex, 0, 6}, + {"di", Reg16|BaseIndex, 0, 7}, + {"r8w", Reg16, RegRex, 0}, + {"r9w", Reg16, RegRex, 1}, + {"r10w", Reg16, RegRex, 2}, + {"r11w", Reg16, RegRex, 3}, + {"r12w", Reg16, RegRex, 4}, + {"r13w", Reg16, RegRex, 5}, + {"r14w", Reg16, RegRex, 6}, + {"r15w", Reg16, RegRex, 7}, + /* 32 bit regs */ +#define REGNAM_EAX 41 + {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot. */ + {"ecx", Reg32|BaseIndex, 0, 1}, + {"edx", Reg32|BaseIndex, 0, 2}, + {"ebx", Reg32|BaseIndex, 0, 3}, + {"esp", Reg32, 0, 4}, + {"ebp", Reg32|BaseIndex, 0, 5}, + {"esi", Reg32|BaseIndex, 0, 6}, + {"edi", Reg32|BaseIndex, 0, 7}, + {"r8d", Reg32|BaseIndex, RegRex, 0}, + {"r9d", Reg32|BaseIndex, RegRex, 1}, + {"r10d", Reg32|BaseIndex, RegRex, 2}, + {"r11d", Reg32|BaseIndex, RegRex, 3}, + {"r12d", Reg32|BaseIndex, RegRex, 4}, + {"r13d", Reg32|BaseIndex, RegRex, 5}, + {"r14d", Reg32|BaseIndex, RegRex, 6}, + {"r15d", Reg32|BaseIndex, RegRex, 7}, + {"rax", Reg64|BaseIndex|Acc, 0, 0}, + {"rcx", Reg64|BaseIndex, 0, 1}, + {"rdx", Reg64|BaseIndex, 0, 2}, + {"rbx", Reg64|BaseIndex, 0, 3}, + {"rsp", Reg64, 0, 4}, + {"rbp", Reg64|BaseIndex, 0, 5}, + {"rsi", Reg64|BaseIndex, 0, 6}, + {"rdi", Reg64|BaseIndex, 0, 7}, + {"r8", Reg64|BaseIndex, RegRex, 0}, + {"r9", Reg64|BaseIndex, RegRex, 1}, + {"r10", Reg64|BaseIndex, RegRex, 2}, + {"r11", Reg64|BaseIndex, RegRex, 3}, + {"r12", Reg64|BaseIndex, RegRex, 4}, + {"r13", Reg64|BaseIndex, RegRex, 5}, + {"r14", Reg64|BaseIndex, RegRex, 6}, + {"r15", Reg64|BaseIndex, RegRex, 7}, + /* Segment registers. */ + {"es", SReg2, 0, 0}, + {"cs", SReg2, 0, 1}, + {"ss", SReg2, 0, 2}, + {"ds", SReg2, 0, 3}, + {"fs", SReg3, 0, 4}, + {"gs", SReg3, 0, 5}, + /* Control registers. */ + {"cr0", Control, 0, 0}, + {"cr1", Control, 0, 1}, + {"cr2", Control, 0, 2}, + {"cr3", Control, 0, 3}, + {"cr4", Control, 0, 4}, + {"cr5", Control, 0, 5}, + {"cr6", Control, 0, 6}, + {"cr7", Control, 0, 7}, + {"cr8", Control, RegRex, 0}, + {"cr9", Control, RegRex, 1}, + {"cr10", Control, RegRex, 2}, + {"cr11", Control, RegRex, 3}, + {"cr12", Control, RegRex, 4}, + {"cr13", Control, RegRex, 5}, + {"cr14", Control, RegRex, 6}, + {"cr15", Control, RegRex, 7}, + /* Debug registers. */ + {"db0", Debug, 0, 0}, + {"db1", Debug, 0, 1}, + {"db2", Debug, 0, 2}, + {"db3", Debug, 0, 3}, + {"db4", Debug, 0, 4}, + {"db5", Debug, 0, 5}, + {"db6", Debug, 0, 6}, + {"db7", Debug, 0, 7}, + {"db8", Debug, RegRex, 0}, + {"db9", Debug, RegRex, 1}, + {"db10", Debug, RegRex, 2}, + {"db11", Debug, RegRex, 3}, + {"db12", Debug, RegRex, 4}, + {"db13", Debug, RegRex, 5}, + {"db14", Debug, RegRex, 6}, + {"db15", Debug, RegRex, 7}, + {"dr0", Debug, 0, 0}, + {"dr1", Debug, 0, 1}, + {"dr2", Debug, 0, 2}, + {"dr3", Debug, 0, 3}, + {"dr4", Debug, 0, 4}, + {"dr5", Debug, 0, 5}, + {"dr6", Debug, 0, 6}, + {"dr7", Debug, 0, 7}, + {"dr8", Debug, RegRex, 0}, + {"dr9", Debug, RegRex, 1}, + {"dr10", Debug, RegRex, 2}, + {"dr11", Debug, RegRex, 3}, + {"dr12", Debug, RegRex, 4}, + {"dr13", Debug, RegRex, 5}, + {"dr14", Debug, RegRex, 6}, + {"dr15", Debug, RegRex, 7}, + /* Test registers. */ + {"tr0", Test, 0, 0}, + {"tr1", Test, 0, 1}, + {"tr2", Test, 0, 2}, + {"tr3", Test, 0, 3}, + {"tr4", Test, 0, 4}, + {"tr5", Test, 0, 5}, + {"tr6", Test, 0, 6}, + {"tr7", Test, 0, 7}, + /* MMX and simd registers. */ + {"mm0", RegMMX, 0, 0}, + {"mm1", RegMMX, 0, 1}, + {"mm2", RegMMX, 0, 2}, + {"mm3", RegMMX, 0, 3}, + {"mm4", RegMMX, 0, 4}, + {"mm5", RegMMX, 0, 5}, + {"mm6", RegMMX, 0, 6}, + {"mm7", RegMMX, 0, 7}, + {"xmm0", RegXMM, 0, 0}, + {"xmm1", RegXMM, 0, 1}, + {"xmm2", RegXMM, 0, 2}, + {"xmm3", RegXMM, 0, 3}, + {"xmm4", RegXMM, 0, 4}, + {"xmm5", RegXMM, 0, 5}, + {"xmm6", RegXMM, 0, 6}, + {"xmm7", RegXMM, 0, 7}, + {"xmm8", RegXMM, RegRex, 0}, + {"xmm9", RegXMM, RegRex, 1}, + {"xmm10", RegXMM, RegRex, 2}, + {"xmm11", RegXMM, RegRex, 3}, + {"xmm12", RegXMM, RegRex, 4}, + {"xmm13", RegXMM, RegRex, 5}, + {"xmm14", RegXMM, RegRex, 6}, + {"xmm15", RegXMM, RegRex, 7}, + /* No type will make this register rejected for all purposes except + for addressing. This saves creating one extra type for RIP. */ + {"rip", BaseIndex, 0, 0} +}; + +static const reg_entry i386_float_regtab[] = +{ + {"st(0)", FloatReg|FloatAcc, 0, 0}, + {"st(1)", FloatReg, 0, 1}, + {"st(2)", FloatReg, 0, 2}, + {"st(3)", FloatReg, 0, 3}, + {"st(4)", FloatReg, 0, 4}, + {"st(5)", FloatReg, 0, 5}, + {"st(6)", FloatReg, 0, 6}, + {"st(7)", FloatReg, 0, 7} +}; + +#define MAX_REG_NAME_SIZE 8 /* For parsing register names from input. */ + +/* Segment stuff. */ +static const seg_entry cs = { "cs", 0x2e }; +static const seg_entry ds = { "ds", 0x3e }; +static const seg_entry ss = { "ss", 0x36 }; +static const seg_entry es = { "es", 0x26 }; +static const seg_entry fs = { "fs", 0x64 }; +static const seg_entry gs = { "gs", 0x65 }; + diff --git a/include/opcode/i860.h b/include/opcode/i860.h new file mode 100644 index 000000000..b46a5e5a4 --- /dev/null +++ b/include/opcode/i860.h @@ -0,0 +1,507 @@ +/* Table of opcodes for the i860. + Copyright 1989, 1991, 2000, 2003 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* Structure of an opcode table entry. */ +struct i860_opcode +{ + /* The opcode name. */ + const char *name; + + /* Bits that must be set. */ + unsigned long match; + + /* Bits that must not be set. */ + unsigned long lose; + + const char *args; + + /* Nonzero if this is a possible expand-instruction. */ + char expand; +}; + + +enum expand_type +{ + E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY +}; + + +/* All i860 opcodes are 32 bits, except for the pseudo-instructions + and the operations utilizing a 32-bit address expression, an + unsigned 32-bit constant, or a signed 32-bit constant. + These opcodes are expanded into a two-instruction sequence for + any situation where the immediate operand does not fit in 32 bits. + In the case of the add and subtract operations the expansion is + to a three-instruction sequence (ex: orh, or, adds). In cases + where the address is to be relocated, the instruction is + expanded to handle the worse case, this could be optimized at + the final link if the actual address were known. + + The pseudoinstructions are: mov, fmov, pmov, nop, and fnop. + These instructions are implemented as a one or two instruction + sequence of other operations. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character + for each operand of the instruction. + +Kinds of operands: + # Number used by optimizer. It is ignored. + 1 src1 integer register. + 2 src2 integer register. + d dest register. + c ctrlreg control register. + i 16 bit immediate. + I 16 bit immediate, aligned 2^0. (ld.b) + J 16 bit immediate, aligned 2^1. (ld.s) + K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l) + L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d) + M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q) + 5 5 bit immediate. + l lbroff 26 bit PC relative immediate. + r sbroff 16 bit PC relative immediate. + s split 16 bit immediate. + S split 16 bit immediate, aligned 2^0. (st.b) + T split 16 bit immediate, aligned 2^1. (st.s) + U split 16 bit immediate, aligned 2^2. (st.l) + e src1 floating point register. + f src2 floating point register. + g dest floating point register. */ + + +/* The order of the opcodes in this table is significant. The assembler + requires that all instances of the same mnemonic must be consecutive. + If they aren't, the assembler will not function properly. + + The order of opcodes does not affect the disassembler. */ + +static const struct i860_opcode i860_opcodes[] = +{ +/* REG-Format Instructions. */ +{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ +{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ +{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ +{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */ +{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */ +{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */ +{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */ + +{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */ +{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */ +{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */ +{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */ + +{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */ + +{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */ +{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */ +{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */ +{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */ +{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */ +{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */ +{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */ +{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */ +{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */ +{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */ +{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */ +{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */ + +{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */ +{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */ +{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */ +{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */ +{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */ +{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */ +{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */ +{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */ +{ "pfld.q", 0x60000004, 0x9c000003, "1(2),g", XP_ONLY }, /* pfld.q isrc1(isrc2),fdest */ +{ "pfld.q", 0x64000004, 0x98000003, "L(2),g", XP_ONLY }, /* pfld.q #const(isrc2),fdest */ +{ "pfld.q", 0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY }, /* pfld.q isrc1(isrc2)++,fdest */ +{ "pfld.q", 0x64000005, 0x98000002, "L(2)++,g", XP_ONLY }, /* pfld.q #const(isrc2)++,fdest */ + +{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */ +{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */ +{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */ +{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */ +{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ +{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ + +{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */ +{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */ + +{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */ +{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */ +{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */ +{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */ +{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */ +{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */ +{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */ +{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */ + +{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */ +{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */ +{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */ +{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */ +{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */ +{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */ +{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */ + +{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */ +{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */ +{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */ +{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */ + +{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */ + +{ "flush", 0x34000004, 0xc81f0003, "L(2)", E_ADDR }, /* flush #const(isrc2) */ +{ "flush", 0x34000005, 0xc81f0002, "L(2)++", E_ADDR }, /* flush #const(isrc2)++ */ + +{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */ +{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */ +{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */ +{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */ +{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */ +{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */ +{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */ +{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */ +{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */ +{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */ +{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */ +{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */ + +{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */ +{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */ +{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */ +{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */ +{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */ +{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */ + +/* Core Escape Instruction Format */ +{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */ +{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */ +{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */ +{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */ +{ "ldio.l", 0x4c000408, 0xb00003f7, "2,d", XP_ONLY }, /* ldio.l isrc2,idest */ +{ "ldio.s", 0x4c000208, 0xb00005f7, "2,d", XP_ONLY }, /* ldio.s isrc2,idest */ +{ "ldio.b", 0x4c000008, 0xb00007f7, "2,d", XP_ONLY }, /* ldio.b isrc2,idest */ +{ "stio.l", 0x4c000409, 0xb00003f6, "1,2", XP_ONLY }, /* stio.l isrc1ni,isrc2 */ +{ "stio.s", 0x4c000209, 0xb00005f6, "1,2", XP_ONLY }, /* stio.s isrc1ni,isrc2 */ +{ "stio.b", 0x4c000009, 0xb00007f6, "1,2", XP_ONLY }, /* stio.b isrc1ni,isrc2 */ +{ "ldint.l", 0x4c00040a, 0xb00003f5, "2,d", XP_ONLY }, /* ldint.l isrc2,idest */ +{ "ldint.s", 0x4c00020a, 0xb00005f5, "2,d", XP_ONLY }, /* ldint.s isrc2,idest */ +{ "ldint.b", 0x4c00000a, 0xb00007f5, "2,d", XP_ONLY }, /* ldint.b isrc2,idest */ +{ "scyc.b", 0x4c00000b, 0xb00007f4, "2", XP_ONLY }, /* scyc.b isrc2 */ + +/* CTRL-Format Instructions */ +{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */ +{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */ +{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */ +{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */ +{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ +{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ + +/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */ +{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 }, +{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 }, +{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 }, +{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 }, +{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 }, +{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 }, +{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 }, +{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 }, +{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 }, +{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 }, +{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 }, +{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 }, +{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 }, +{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 }, +{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 }, +{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 }, +{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 }, +{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 }, +{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 }, +{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 }, +{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 }, +{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 }, +{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 }, +{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 }, +{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 }, +{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 }, +{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 }, +{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 }, +{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 }, +{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 }, +{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 }, +{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 }, +{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 }, +{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 }, +{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 }, +{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 }, +{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 }, +{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 }, +{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 }, +{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 }, +{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 }, +{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 }, +{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 }, +{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 }, +{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 }, +{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 }, +{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 }, +{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */ +{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 }, +{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 }, +{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 }, +{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 }, +{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 }, +{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 }, +{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 }, +{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 }, +{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 }, +{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 }, +{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 }, +{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 }, +{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 }, +{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 }, +{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 }, +{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 }, +{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 }, +{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 }, +{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 }, +{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 }, +{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 }, +{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 }, +{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 }, +{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 }, +{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 }, +{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 }, +{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 }, +{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 }, +{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 }, +{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 }, +{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 }, +{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 }, +{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 }, +{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 }, +{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 }, +{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 }, +{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 }, +{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 }, +{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 }, +{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 }, +{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 }, +{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 }, +{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 }, +{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 }, +{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 }, +{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 }, +{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 }, +{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */ +{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 }, +{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 }, +{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 }, +{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 }, +{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 }, +{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 }, +{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 }, +{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 }, +{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 }, +{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 }, +{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 }, +{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 }, +{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 }, +{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 }, +{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 }, +{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 }, +{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 }, +{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 }, +{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 }, +{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 }, +{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 }, +{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 }, +{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 }, +{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 }, +{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 }, +{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 }, +{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 }, +{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 }, +{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 }, +{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 }, +{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 }, +{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 }, +{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 }, +{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 }, +{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 }, +{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 }, +{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 }, +{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 }, +{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 }, +{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 }, +{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 }, +{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 }, +{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 }, +{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 }, +{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */ +{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 }, +{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 }, +{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 }, +{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 }, +{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 }, +{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 }, +{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 }, +{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 }, +{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 }, +{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 }, +{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 }, +{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 }, +{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 }, +{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 }, +{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 }, +{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 }, +{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 }, +{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 }, +{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 }, +{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 }, +{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 }, +{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 }, +{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 }, +{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 }, +{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 }, +{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 }, +{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 }, +{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 }, +{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 }, +{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 }, +{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 }, +{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 }, +{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 }, +{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 }, +{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 }, +{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 }, +{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 }, +{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 }, +{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 }, +{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 }, +{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 }, +{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 }, +{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 }, +{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 }, +{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 }, + +{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */ +{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */ +{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +/* Opcode pfgt has R bit cleared; pfle has R bit set. */ +{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +/* Opcode pfgt has R bit cleared; pfle has R bit set. */ +{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ +{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ +{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */ +{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */ +{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */ +{ "fzchks", 0x480001df, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */ +{ "pfzchks", 0x480005df, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */ +{ "faddp", 0x480001d0, 0xb400042f, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */ +{ "pfaddp", 0x480005d0, 0xb400002f, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */ +{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */ +{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */ +{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */ +{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */ + +/* Floating point pseudo-instructions. */ +{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ +{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ +{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */ +{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */ +{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */ +{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ +{ 0, 0, 0, 0, 0 }, + +}; + +#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0])) + + diff --git a/include/opcode/i960.h b/include/opcode/i960.h new file mode 100644 index 000000000..33b56e635 --- /dev/null +++ b/include/opcode/i960.h @@ -0,0 +1,525 @@ +/* Basic 80960 instruction formats. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + The 'COJ' instructions are actually COBR instructions with the 'b' in + the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary: + if the displacement will not fit in 13 bits, the assembler will replace them + with the corresponding compare and branch instructions. + + All of the 'MEMn' instructions are the same format; the 'n' in the name + indicates the default index scale factor (the size of the datum operated on). + + The FBRA formats are not actually an instruction format. They are the + "convenience directives" for branching on floating-point comparisons, + each of which generates 2 instructions (a 'bno' and one other branch). + + The CALLJ format is not actually an instruction format. It indicates that + the instruction generated (a CTRL-format 'call') should have its relocation + specially flagged for link-time replacement with a 'bal' or 'calls' if + appropriate. */ + +#define CTRL 0 +#define COBR 1 +#define COJ 2 +#define REG 3 +#define MEM1 4 +#define MEM2 5 +#define MEM4 6 +#define MEM8 7 +#define MEM12 8 +#define MEM16 9 +#define FBRA 10 +#define CALLJ 11 + +/* Masks for the mode bits in REG format instructions */ +#define M1 0x0800 +#define M2 0x1000 +#define M3 0x2000 + +/* Generate the 12-bit opcode for a REG format instruction by placing the + * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits + * 7-10. + */ + +#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7) + +/* Generate a template for a REG format instruction: place the opcode bits + * in the appropriate fields and OR in mode bits for the operands that will not + * be used. I.e., + * set m1=1, if src1 will not be used + * set m2=1, if src2 will not be used + * set m3=1, if dst will not be used + * + * Setting the "unused" mode bits to 1 speeds up instruction execution(!). + * The information is also useful to us because some 1-operand REG instructions + * use the src1 field, others the dst field; and some 2-operand REG instructions + * use src1/src2, others src1/dst. The set mode bits enable us to distinguish. + */ +#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */ +#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */ +#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */ +#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */ +#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */ +#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */ + +/* DESCRIPTOR BYTES FOR REGISTER OPERANDS + * + * Interpret names as follows: + * R: global or local register only + * RS: global, local, or (if target allows) special-function register only + * RL: global or local register, or integer literal + * RSL: global, local, or (if target allows) special-function register; + * or integer literal + * F: global, local, or floating-point register + * FL: global, local, or floating-point register; or literal (including + * floating point) + * + * A number appended to a name indicates that registers must be aligned, + * as follows: + * 2: register number must be multiple of 2 + * 4: register number must be multiple of 4 + */ + +#define SFR 0x10 /* Mask for the "sfr-OK" bit */ +#define LIT 0x08 /* Mask for the "literal-OK" bit */ +#define FP 0x04 /* Mask for "floating-point-OK" bit */ + +/* This macro ors the bits together. Note that 'align' is a mask + * for the low 0, 1, or 2 bits of the register number, as appropriate. + */ +#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr ) + +#define R OP( 0, 0, 0, 0 ) +#define RS OP( 0, 0, 0, SFR ) +#define RL OP( 0, LIT, 0, 0 ) +#define RSL OP( 0, LIT, 0, SFR ) +#define F OP( 0, 0, FP, 0 ) +#define FL OP( 0, LIT, FP, 0 ) +#define R2 OP( 1, 0, 0, 0 ) +#define RL2 OP( 1, LIT, 0, 0 ) +#define F2 OP( 1, 0, FP, 0 ) +#define FL2 OP( 1, LIT, FP, 0 ) +#define R4 OP( 3, 0, 0, 0 ) +#define RL4 OP( 3, LIT, 0, 0 ) +#define F4 OP( 3, 0, FP, 0 ) +#define FL4 OP( 3, LIT, FP, 0 ) + +#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */ + +/* Macros to extract info from the register operand descriptor byte 'od'. + */ +#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */ +#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */ +#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */ +#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0) + /* TRUE if reg #n is properly aligned */ +#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/ + +/* Description of a single i80960 instruction */ +struct i960_opcode { + long opcode; /* 32 bits, constant fields filled in, rest zeroed */ + char *name; /* Assembler mnemonic */ + short iclass; /* Class: see #defines below */ + char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */ + char num_ops; /* Number of operands */ + char operand[3];/* Operand descriptors; same order as assembler instr */ +}; + +/* Classes of 960 intructions: + * - each instruction falls into one class. + * - each target architecture supports one or more classes. + * + * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass(). + */ +#define I_BASE 0x01 /* 80960 base instruction set */ +#define I_CX 0x02 /* 80960Cx instruction */ +#define I_DEC 0x04 /* Decimal instruction */ +#define I_FP 0x08 /* Floating point instruction */ +#define I_KX 0x10 /* 80960Kx instruction */ +#define I_MIL 0x20 /* Military instruction */ +#define I_CASIM 0x40 /* CA simulator instruction */ +#define I_CX2 0x80 /* Cx/Jx/Hx instructions */ +#define I_JX 0x100 /* Jx/Hx instruction */ +#define I_HX 0x200 /* Hx instructions */ + +/****************************************************************************** + * + * TABLE OF i960 INSTRUCTION DESCRIPTIONS + * + ******************************************************************************/ + +const struct i960_opcode i960_opcodes[] = { + + /* if a CTRL instruction has an operand, it's always a displacement */ + + /* callj default=='call' */ + { 0x09000000, "callj", I_BASE, CALLJ, 1, { 0, 0, 0 } }, + { 0x08000000, "b", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x09000000, "call", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x0a000000, "ret", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x0b000000, "bal", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x10000000, "bno", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bf same as bno */ + { 0x10000000, "bf", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bru same as bno */ + { 0x10000000, "bru", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x11000000, "bg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brg same as bg */ + { 0x11000000, "brg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x12000000, "be", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bre same as be */ + { 0x12000000, "bre", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x13000000, "bge", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brge same as bge */ + { 0x13000000, "brge", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x14000000, "bl", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brl same as bl */ + { 0x14000000, "brl", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x15000000, "bne", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brlg same as bne */ + { 0x15000000, "brlg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x16000000, "ble", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brle same as ble */ + { 0x16000000, "brle", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x17000000, "bo", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bt same as bo */ + { 0x17000000, "bt", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bro same as bo */ + { 0x17000000, "bro", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x18000000, "faultno", I_BASE, CTRL, 0, { 0, 0, 0 } }, + /* faultf same as faultno */ + { 0x18000000, "faultf", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x19000000, "faultg", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1a000000, "faulte", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1b000000, "faultge", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1c000000, "faultl", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1d000000, "faultne", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1e000000, "faultle", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1f000000, "faulto", I_BASE, CTRL, 0, { 0, 0, 0 } }, + /* faultt syn for faulto */ + { 0x1f000000, "faultt", I_BASE, CTRL, 0, { 0, 0, 0 } }, + + { 0x01000000, "syscall", I_CASIM,CTRL, 0, { 0, 0, 0 } }, + + /* If a COBR (or COJ) has 3 operands, the last one is always a + * displacement and does not appear explicitly in the table. + */ + + { 0x20000000, "testno", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x21000000, "testg", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x22000000, "teste", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x23000000, "testge", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x24000000, "testl", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x25000000, "testne", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x26000000, "testle", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x27000000, "testo", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x38000000, "cmpibno", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x39000000, "cmpibg", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3a000000, "cmpibe", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3b000000, "cmpibge", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3c000000, "cmpibl", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3d000000, "cmpibne", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3e000000, "cmpible", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3f000000, "cmpibo", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x31000000, "cmpojg", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x32000000, "cmpoje", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x33000000, "cmpojge", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x34000000, "cmpojl", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x35000000, "cmpojne", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x36000000, "cmpojle", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x38000000, "cmpijno", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x39000000, "cmpijg", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3a000000, "cmpije", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3b000000, "cmpijge", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3c000000, "cmpijl", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3d000000, "cmpijne", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3e000000, "cmpijle", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3f000000, "cmpijo", I_BASE, COJ, 3, { RL, RS, 0 } }, + + { 0x80000000, "ldob", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x82000000, "stob", I_BASE, MEM1, 2, { R, M, 0 } }, + { 0x84000000, "bx", I_BASE, MEM1, 1, { M, 0, 0 } }, + { 0x85000000, "balx", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x86000000, "callx", I_BASE, MEM1, 1, { M, 0, 0 } }, + { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } }, + { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } }, + { 0x8c000000, "lda", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x90000000, "ld", I_BASE, MEM4, 2, { M, R, 0 } }, + { 0x92000000, "st", I_BASE, MEM4, 2, { R, M, 0 } }, + { 0x98000000, "ldl", I_BASE, MEM8, 2, { M, R2, 0 } }, + { 0x9a000000, "stl", I_BASE, MEM8, 2, { R2, M, 0 } }, + { 0xa0000000, "ldt", I_BASE, MEM12, 2, { M, R4, 0 } }, + { 0xa2000000, "stt", I_BASE, MEM12, 2, { R4, M, 0 } }, + { 0xb0000000, "ldq", I_BASE, MEM16, 2, { M, R4, 0 } }, + { 0xb2000000, "stq", I_BASE, MEM16, 2, { R4, M, 0 } }, + { 0xc0000000, "ldib", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0xc2000000, "stib", I_BASE, MEM1, 2, { R, M, 0 } }, + { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } }, + { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } }, + + { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x58a), "not", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_3(0x58b), "ornot", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58c), "clrbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58d), "notor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58e), "nand", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58f), "alterbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x590), "addo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x591), "addi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x592), "subo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x593), "subi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x598), "shro", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59a), "shrdi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59b), "shri", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59c), "shlo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59d), "rotate", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59e), "shli", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2(0x5a0), "cmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a1), "cmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a2), "concmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a3), "concmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_3(0x5a4), "cmpinco", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a5), "cmpinci", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2(0x5ac), "scanbyte", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5ae), "chkbit", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_3(0x5b0), "addc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5b2), "subc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x5cc), "mov", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_2D(0x5dc), "movl", I_BASE, REG, 2, { RL2,R2, 0 } }, + { R_2D(0x5ec), "movt", I_BASE, REG, 2, { RL4,R4, 0 } }, + { R_2D(0x5fc), "movq", I_BASE, REG, 2, { RL4,R4, 0 } }, + { R_3(0x610), "atmod", I_BASE, REG, 3, { RS, RSL,R } }, + { R_3(0x612), "atadd", I_BASE, REG, 3, { RS, RSL,RS } }, + { R_2D(0x640), "spanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_2D(0x641), "scanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_3(0x645), "modac", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x650), "modify", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_3(0x651), "extract", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_3(0x654), "modtc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x655), "modpc", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_1(0x660), "calls", I_BASE, REG, 1, { RSL, 0, 0 } }, + { R_0(0x66b), "mark", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66c), "fmark", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66d), "flushreg", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66f), "syncf", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_3(0x670), "emul", I_BASE, REG, 3, { RSL,RSL,R2 } }, + { R_3(0x671), "ediv", I_BASE, REG, 3, { RSL,RL2,RS } }, + { R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } }, + { R_3(0x701), "mulo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x708), "remo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x70b), "divo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x741), "muli", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x748), "remi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x749), "modi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x74b), "divi", I_BASE, REG, 3, { RSL,RSL,RS } }, + + /* Floating-point instructions */ + + { R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } }, + { R_2D(0x675), "cvtilr", I_FP, REG, 2, { RL, F, 0 } }, + { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } }, + { R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } }, + { R_3(0x680), "atanr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x681), "logepr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x682), "logr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x683), "remr", I_FP, REG, 3, { FL, FL, F } }, + { R_2(0x684), "cmpor", I_FP, REG, 2, { FL, FL, 0 } }, + { R_2(0x685), "cmpr", I_FP, REG, 2, { FL, FL, 0 } }, + { R_2D(0x688), "sqrtr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x689), "expr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68a), "logbnr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68b), "roundr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68c), "sinr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68d), "cosr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68e), "tanr", I_FP, REG, 2, { FL, F, 0 } }, + { R_1(0x68f), "classr", I_FP, REG, 1, { FL, 0, 0 } }, + { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } }, + { R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } }, + { R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69a), "logbnrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69b), "roundrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69c), "sinrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69d), "cosrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69e), "tanrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_1(0x69f), "classrl", I_FP, REG, 1, { FL2, 0, 0 } }, + { R_2D(0x6c0), "cvtri", I_FP, REG, 2, { FL, R, 0 } }, + { R_2D(0x6c1), "cvtril", I_FP, REG, 2, { FL, R2, 0 } }, + { R_2D(0x6c2), "cvtzri", I_FP, REG, 2, { FL, R, 0 } }, + { R_2D(0x6c3), "cvtzril", I_FP, REG, 2, { FL, R2, 0 } }, + { R_2D(0x6c9), "movr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x6d9), "movrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x6e1), "movre", I_FP, REG, 2, { FL4,F4, 0 } }, + { R_3(0x6e2), "cpysre", I_FP, REG, 3, { FL4,FL4,F4 } }, + { R_3(0x6e3), "cpyrsre", I_FP, REG, 3, { FL4,FL4,F4 } }, + { R_3(0x78b), "divr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78c), "mulr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78d), "subr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78f), "addr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x79b), "divrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79c), "mulrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79d), "subrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79f), "addrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + + /* These are the floating point branch instructions. Each actually + * generates 2 branch instructions: the first a CTRL instruction with + * the indicated opcode, and the second a 'bno'. + */ + + { 0x12000000, "brue", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x11000000, "brug", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x13000000, "bruge", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x14000000, "brul", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x16000000, "brule", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x15000000, "brulg", I_FP, FBRA, 1, { 0, 0, 0 } }, + + + /* Decimal instructions */ + + { R_3(0x642), "daddc", I_DEC, REG, 3, { RSL,RSL,RS } }, + { R_3(0x643), "dsubc", I_DEC, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x644), "dmovt", I_DEC, REG, 2, { RSL,RS, 0 } }, + + + /* KX extensions */ + + { R_2(0x600), "synmov", I_KX, REG, 2, { R, R, 0 } }, + { R_2(0x601), "synmovl", I_KX, REG, 2, { R, R, 0 } }, + { R_2(0x602), "synmovq", I_KX, REG, 2, { R, R, 0 } }, + { R_2D(0x615), "synld", I_KX, REG, 2, { R, R, 0 } }, + + + /* MC extensions */ + + { R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } }, + { R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } }, + { R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } }, + { R_2D(0x613), "inspacc", I_MIL, REG, 2, { R, R, 0 } }, + { R_2D(0x614), "ldphy", I_MIL, REG, 2, { R, R, 0 } }, + { R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } }, + { R_2D(0x646), "condrec", I_MIL, REG, 2, { R, R, 0 } }, + { R_2D(0x656), "receive", I_MIL, REG, 2, { R, R, 0 } }, + { R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } }, + { R_1(0x663), "sendserv", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x664), "resumprcs", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x665), "schedprcs", I_MIL, REG, 1, { R, 0, 0 } }, + { R_0(0x666), "saveprcs", I_MIL, REG, 0, { 0, 0, 0 } }, + { R_1(0x668), "condwait", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x669), "wait", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x66a), "signal", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1D(0x673), "ldtime", I_MIL, REG, 1, { R2, 0, 0 } }, + + + /* CX extensions */ + + { R_3(0x5d8), "eshro", I_CX2, REG, 3, { RSL,RSL,RS } }, + { R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } }, + { R_3(0x631), "udma", I_CX, REG, 0, { 0, 0, 0 } }, + { R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } }, + + + /* Jx extensions. */ + { R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } }, + + { R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } }, + + { R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } }, + { R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } }, + { R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } }, + { R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } }, + { R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } }, + + /* Hx extensions. */ + { 0xac000000, "dcinva", I_HX, MEM1, 1, { M, 0, 0 } }, + + /* END OF TABLE */ + + { 0, NULL, 0, 0, 0, { 0, 0, 0 } } +}; + + /* end of i960-opcode.h */ diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h new file mode 100644 index 000000000..0d33fc61b --- /dev/null +++ b/include/opcode/ia64.h @@ -0,0 +1,392 @@ +/* ia64.h -- Header file for ia64 opcode table + Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ + +#ifndef opcode_ia64_h +#define opcode_ia64_h + +#include <sys/types.h> + +#include "bfd.h" + + +typedef BFD_HOST_U_64_BIT ia64_insn; + +enum ia64_insn_type + { + IA64_TYPE_NIL = 0, /* illegal type */ + IA64_TYPE_A, /* integer alu (I- or M-unit) */ + IA64_TYPE_I, /* non-alu integer (I-unit) */ + IA64_TYPE_M, /* memory (M-unit) */ + IA64_TYPE_B, /* branch (B-unit) */ + IA64_TYPE_F, /* floating-point (F-unit) */ + IA64_TYPE_X, /* long encoding (X-unit) */ + IA64_TYPE_DYN, /* Dynamic opcode */ + IA64_NUM_TYPES + }; + +enum ia64_unit + { + IA64_UNIT_NIL = 0, /* illegal unit */ + IA64_UNIT_I, /* integer unit */ + IA64_UNIT_M, /* memory unit */ + IA64_UNIT_B, /* branching unit */ + IA64_UNIT_F, /* floating-point unit */ + IA64_UNIT_L, /* long "unit" */ + IA64_UNIT_X, /* may be integer or branch unit */ + IA64_NUM_UNITS + }; + +/* Changes to this enumeration must be propagated to the operand table in + bfd/cpu-ia64-opc.c + */ +enum ia64_opnd + { + IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ + + /* constants */ + IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ + IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ + IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ + IA64_OPND_C1, /* the constant 1 */ + IA64_OPND_C8, /* the constant 8 */ + IA64_OPND_C16, /* the constant 16 */ + IA64_OPND_GR0, /* gr0 */ + IA64_OPND_IP, /* instruction pointer (ip) */ + IA64_OPND_PR, /* predicate register (pr) */ + IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ + IA64_OPND_PSR, /* processor status register (psr) */ + IA64_OPND_PSR_L, /* processor status register L (psr.l) */ + IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ + + /* register operands: */ + IA64_OPND_AR3, /* third application register # (bits 20-26) */ + IA64_OPND_B1, /* branch register # (bits 6-8) */ + IA64_OPND_B2, /* branch register # (bits 13-15) */ + IA64_OPND_CR3, /* third control register # (bits 20-26) */ + IA64_OPND_F1, /* first floating-point register # */ + IA64_OPND_F2, /* second floating-point register # */ + IA64_OPND_F3, /* third floating-point register # */ + IA64_OPND_F4, /* fourth floating-point register # */ + IA64_OPND_P1, /* first predicate # */ + IA64_OPND_P2, /* second predicate # */ + IA64_OPND_R1, /* first register # */ + IA64_OPND_R2, /* second register # */ + IA64_OPND_R3, /* third register # */ + IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ + + /* indirect operands: */ + IA64_OPND_CPUID_R3, /* cpuid[reg] */ + IA64_OPND_DBR_R3, /* dbr[reg] */ + IA64_OPND_DTR_R3, /* dtr[reg] */ + IA64_OPND_ITR_R3, /* itr[reg] */ + IA64_OPND_IBR_R3, /* ibr[reg] */ + IA64_OPND_MR3, /* memory at addr of third register # */ + IA64_OPND_MSR_R3, /* msr[reg] */ + IA64_OPND_PKR_R3, /* pkr[reg] */ + IA64_OPND_PMC_R3, /* pmc[reg] */ + IA64_OPND_PMD_R3, /* pmd[reg] */ + IA64_OPND_RR_R3, /* rr[reg] */ + + /* immediate operands: */ + IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ + IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ + IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ + IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ + IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ + IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ + IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ + IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ + IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ + IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ + IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ + IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ + IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ + IA64_OPND_SOF, /* 8-bit stack frame size */ + IA64_OPND_SOL, /* 8-bit size of locals */ + IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ + IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ + IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ + IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ + IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ + IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ + IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ + IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ + IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ + IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ + IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ + IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ + IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ + IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ + IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ + IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ + IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ + IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ + IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ + IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ + IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ + IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ + IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ + IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ + IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ + IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ + IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ + IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ + IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ + IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ + + IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ + }; + +enum ia64_dependency_mode +{ + IA64_DV_RAW, + IA64_DV_WAW, + IA64_DV_WAR, +}; + +enum ia64_dependency_semantics +{ + IA64_DVS_NONE, + IA64_DVS_IMPLIED, + IA64_DVS_IMPLIEDF, + IA64_DVS_DATA, + IA64_DVS_INSTR, + IA64_DVS_SPECIFIC, + IA64_DVS_STOP, + IA64_DVS_OTHER, +}; + +enum ia64_resource_specifier +{ + IA64_RS_ANY, + IA64_RS_AR_K, + IA64_RS_AR_UNAT, + IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ + IA64_RS_ARb, /* 48-63, 112-127 */ + IA64_RS_BR, + IA64_RS_CFM, + IA64_RS_CPUID, + IA64_RS_CR_IRR, + IA64_RS_CR_LRR, + IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */ + IA64_RS_DBR, + IA64_RS_FR, + IA64_RS_FRb, + IA64_RS_GR0, + IA64_RS_GR, + IA64_RS_IBR, + IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ + IA64_RS_MSR, + IA64_RS_PKR, + IA64_RS_PMC, + IA64_RS_PMD, + IA64_RS_PR, /* non-rotating, 1-15 */ + IA64_RS_PRr, /* rotating, 16-62 */ + IA64_RS_PR63, + IA64_RS_RR, + + IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ + IA64_RS_CRX, /* CRs not in RS_CR */ + IA64_RS_PSR, /* PSR bits */ + IA64_RS_RSE, /* implementation-specific RSE resources */ + IA64_RS_AR_FPSR, +}; + +enum ia64_rse_resource +{ + IA64_RSE_N_STACKED_PHYS, + IA64_RSE_BOF, + IA64_RSE_STORE_REG, + IA64_RSE_LOAD_REG, + IA64_RSE_BSPLOAD, + IA64_RSE_RNATBITINDEX, + IA64_RSE_CFLE, + IA64_RSE_NDIRTY, +}; + +/* Information about a given resource dependency */ +struct ia64_dependency +{ + /* Name of the resource */ + const char *name; + /* Does this dependency need further specification? */ + enum ia64_resource_specifier specifier; + /* Mode of dependency */ + enum ia64_dependency_mode mode; + /* Dependency semantics */ + enum ia64_dependency_semantics semantics; + /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ +#define REG_NONE (-1) + int regindex; + /* Special info on semantics */ + const char *info; +}; + +/* Two arrays of indexes into the ia64_dependency table. + chks are dependencies to check for conflicts when an opcode is + encountered; regs are dependencies to register (mark as used) when an + opcode is used. chks correspond to readers (RAW) or writers (WAW or + WAR) of a resource, while regs correspond to writers (RAW or WAW) and + readers (WAR) of a resource. */ +struct ia64_opcode_dependency +{ + int nchks; + const unsigned short *chks; + int nregs; + const unsigned short *regs; +}; + +/* encode/extract the note/index for a dependency */ +#define RDEP(N,X) (((N)<<11)|(X)) +#define NOTE(X) (((X)>>11)&0x1F) +#define DEP(X) ((X)&0x7FF) + +/* A template descriptor describes the execution units that are active + for each of the three slots. It also specifies the location of + instruction group boundaries that may be present between two slots. */ +struct ia64_templ_desc + { + int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ + enum ia64_unit exec_unit[3]; + const char *name; + }; + +/* The opcode table is an array of struct ia64_opcode. */ + +struct ia64_opcode + { + /* The opcode name. */ + const char *name; + + /* The type of the instruction: */ + enum ia64_insn_type type; + + /* Number of output operands: */ + int num_outputs; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + ia64_insn opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + ia64_insn mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + enum ia64_opnd operands[5]; + + /* One bit flags for the opcode. These are primarily used to + indicate specific processors and environments support the + instructions. The defined values are listed below. */ + unsigned int flags; + + /* Used by ia64_find_next_opcode (). */ + short ent_index; + + /* Opcode dependencies. */ + const struct ia64_opcode_dependency *dependencies; + }; + +/* Values defined for the flags field of a struct ia64_opcode. */ + +#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ +#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ +#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ +#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ +#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ +#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ +#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ +#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ +#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ +#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ +#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ + +/* A macro to extract the major opcode from an instruction. */ +#define IA64_OP(i) (((i) >> 37) & 0xf) + +enum ia64_operand_class + { + IA64_OPND_CLASS_CST, /* constant */ + IA64_OPND_CLASS_REG, /* register */ + IA64_OPND_CLASS_IND, /* indirect register */ + IA64_OPND_CLASS_ABS, /* absolute value */ + IA64_OPND_CLASS_REL, /* IP-relative value */ + }; + +/* The operands table is an array of struct ia64_operand. */ + +struct ia64_operand +{ + enum ia64_operand_class class; + + /* Set VALUE as the operand bits for the operand of type SELF in the + instruction pointed to by CODE. If an error occurs, *CODE is not + modified and the returned string describes the cause of the + error. If no error occurs, NULL is returned. */ + const char *(*insert) (const struct ia64_operand *self, ia64_insn value, + ia64_insn *code); + + /* Extract the operand bits for an operand of type SELF from + instruction CODE store them in *VALUE. If an error occurs, the + cause of the error is described by the string returned. If no + error occurs, NULL is returned. */ + const char *(*extract) (const struct ia64_operand *self, ia64_insn code, + ia64_insn *value); + + /* A string whose meaning depends on the operand class. */ + + const char *str; + + struct bit_field + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + } + field[4]; /* no operand has more than this many bit-fields */ + + unsigned int flags; + + const char *desc; /* brief description */ +}; + +/* Values defined for the flags field of a struct ia64_operand. */ + +/* Disassemble as signed decimal (instead of hex): */ +#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) +/* Disassemble as unsigned decimal (instead of hex): */ +#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) + +extern const struct ia64_templ_desc ia64_templ_desc[16]; + +/* The tables are sorted by major opcode number and are otherwise in + the order in which the disassembler should consider instructions. */ +extern struct ia64_opcode ia64_opcodes_a[]; +extern struct ia64_opcode ia64_opcodes_i[]; +extern struct ia64_opcode ia64_opcodes_m[]; +extern struct ia64_opcode ia64_opcodes_b[]; +extern struct ia64_opcode ia64_opcodes_f[]; +extern struct ia64_opcode ia64_opcodes_d[]; + + +extern struct ia64_opcode *ia64_find_opcode (const char *name); +extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent); + +extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn, + enum ia64_insn_type type); + +extern void ia64_free_opcode (struct ia64_opcode *ent); +extern const struct ia64_dependency *ia64_find_dependency (int index); + +/* To avoid circular library dependencies, this array is implemented + in bfd/cpu-ia64-opc.c: */ +extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; + +#endif /* opcode_ia64_h */ diff --git a/include/opcode/m68hc11.h b/include/opcode/m68hc11.h new file mode 100644 index 000000000..648c23b56 --- /dev/null +++ b/include/opcode/m68hc11.h @@ -0,0 +1,427 @@ +/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table + Copyright 1999, 2000, 2002, 2003 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _OPCODE_M68HC11_H +#define _OPCODE_M68HC11_H + +/* Flags for the definition of the 68HC11 & 68HC12 CCR. */ +#define M6811_S_BIT 0x80 /* Stop disable */ +#define M6811_X_BIT 0x40 /* X-interrupt mask */ +#define M6811_H_BIT 0x20 /* Half carry flag */ +#define M6811_I_BIT 0x10 /* I-interrupt mask */ +#define M6811_N_BIT 0x08 /* Negative */ +#define M6811_Z_BIT 0x04 /* Zero */ +#define M6811_V_BIT 0x02 /* Overflow */ +#define M6811_C_BIT 0x01 /* Carry */ + +/* 68HC11 register address offsets (range 0..0x3F or 0..64). + The absolute address of the I/O register depends on the setting + of the M6811_INIT register. At init time, the I/O registers are + mapped at 0x1000. Address of registers is then: + + 0x1000 + M6811_xxx +*/ +#define M6811_PORTA 0x00 /* Port A register */ +#define M6811__RES1 0x01 /* Unused/Reserved */ +#define M6811_PIOC 0x02 /* Parallel I/O Control register */ +#define M6811_PORTC 0x03 /* Port C register */ +#define M6811_PORTB 0x04 /* Port B register */ +#define M6811_PORTCL 0x05 /* Alternate latched port C */ +#define M6811__RES6 0x06 /* Unused/Reserved */ +#define M6811_DDRC 0x07 /* Data direction register for port C */ +#define M6811_PORTD 0x08 /* Port D register */ +#define M6811_DDRD 0x09 /* Data direction register for port D */ +#define M6811_PORTE 0x0A /* Port E input register */ +#define M6811_CFORC 0x0B /* Compare Force Register */ +#define M6811_OC1M 0x0C /* OC1 Action Mask register */ +#define M6811_OC1D 0x0D /* OC1 Action Data register */ +#define M6811_TCTN 0x0E /* Timer Counter Register */ +#define M6811_TCTN_H 0x0E /* " " " High part */ +#define M6811_TCTN_L 0x0F /* " " " Low part */ +#define M6811_TIC1 0x10 /* Input capture 1 register */ +#define M6811_TIC1_H 0x10 /* " " " High part */ +#define M6811_TIC1_L 0x11 /* " " " Low part */ +#define M6811_TIC2 0x12 /* Input capture 2 register */ +#define M6811_TIC2_H 0x12 /* " " " High part */ +#define M6811_TIC2_L 0x13 /* " " " Low part */ +#define M6811_TIC3 0x14 /* Input capture 3 register */ +#define M6811_TIC3_H 0x14 /* " " " High part */ +#define M6811_TIC3_L 0x15 /* " " " Low part */ +#define M6811_TOC1 0x16 /* Output Compare 1 register */ +#define M6811_TOC1_H 0x16 /* " " " High part */ +#define M6811_TOC1_L 0x17 /* " " " Low part */ +#define M6811_TOC2 0x18 /* Output Compare 2 register */ +#define M6811_TOC2_H 0x18 /* " " " High part */ +#define M6811_TOC2_L 0x19 /* " " " Low part */ +#define M6811_TOC3 0x1A /* Output Compare 3 register */ +#define M6811_TOC3_H 0x1A /* " " " High part */ +#define M6811_TOC3_L 0x1B /* " " " Low part */ +#define M6811_TOC4 0x1C /* Output Compare 4 register */ +#define M6811_TOC4_H 0x1C /* " " " High part */ +#define M6811_TOC4_L 0x1D /* " " " Low part */ +#define M6811_TOC5 0x1E /* Output Compare 5 register */ +#define M6811_TOC5_H 0x1E /* " " " High part */ +#define M6811_TOC5_L 0x1F /* " " " Low part */ +#define M6811_TCTL1 0x20 /* Timer Control register 1 */ +#define M6811_TCTL2 0x21 /* Timer Control register 2 */ +#define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */ +#define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */ +#define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */ +#define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */ +#define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */ +#define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */ +#define M6811_SPCR 0x28 /* SPI Control register */ +#define M6811_SPSR 0x29 /* SPI Status register */ +#define M6811_SPDR 0x2A /* SPI Data register */ +#define M6811_BAUD 0x2B /* SCI Baud register */ +#define M6811_SCCR1 0x2C /* SCI Control register 1 */ +#define M6811_SCCR2 0x2D /* SCI Control register 2 */ +#define M6811_SCSR 0x2E /* SCI Status register */ +#define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */ +#define M6811_ADCTL 0x30 /* A/D Control register */ +#define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */ +#define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */ +#define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */ +#define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */ +#define M6811__RES35 0x35 +#define M6811__RES36 0x36 +#define M6811__RES37 0x37 +#define M6811__RES38 0x38 +#define M6811_OPTION 0x39 /* System Configuration Options */ +#define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */ +#define M6811_PPROG 0x3B /* EEPROM Programming Control Register */ +#define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */ +#define M6811_INIT 0x3D /* Ram and I/O mapping register */ +#define M6811_TEST1 0x3E /* Factory test control register */ +#define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */ + + +/* Flags of the CONFIG register (in EEPROM). */ +#define M6811_NOSEC 0x08 /* Security mode disable */ +#define M6811_NOCOP 0x04 /* COP system disable */ +#define M6811_ROMON 0x02 /* Enable on-chip rom */ +#define M6811_EEON 0x01 /* Enable on-chip eeprom */ + +/* Flags of the PPROG register. */ +#define M6811_BYTE 0x10 /* Byte mode */ +#define M6811_ROW 0x08 /* Row mode */ +#define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */ +#define M6811_EELAT 0x02 /* EEPROM Latch Control */ +#define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */ + +/* Flags of the PIOC register. */ +#define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */ +#define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */ +#define M6811_CWOM 0x20 /* Port C Wire OR mode */ +#define M6811_HNDS 0x10 /* Handshake mode */ +#define M6811_OIN 0x08 /* Output or Input handshaking */ +#define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */ +#define M6811_EGA 0x02 /* Active Edge for Strobe A */ +#define M6811_INVB 0x01 /* Invert Strobe B */ + +/* Flags of the SCCR1 register. */ +#define M6811_R8 0x80 /* Receive Data bit 8 */ +#define M6811_T8 0x40 /* Transmit data bit 8 */ +#define M6811__SCCR1_5 0x20 /* Unused */ +#define M6811_M 0x10 /* SCI Character length */ +#define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */ + +/* Flags of the SCCR2 register. */ +#define M6811_TIE 0x80 /* Transmit Interrupt enable */ +#define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */ +#define M6811_RIE 0x20 /* Receive Interrupt Enable */ +#define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */ +#define M6811_TE 0x08 /* Transmit Enable */ +#define M6811_RE 0x04 /* Receive Enable */ +#define M6811_RWU 0x02 /* Receiver Wake Up */ +#define M6811_SBK 0x01 /* Send Break */ + +/* Flags of the SCSR register. */ +#define M6811_TDRE 0x80 /* Transmit Data Register Empty */ +#define M6811_TC 0x40 /* Transmit Complete */ +#define M6811_RDRF 0x20 /* Receive Data Register Full */ +#define M6811_IDLE 0x10 /* Idle Line Detect */ +#define M6811_OR 0x08 /* Overrun Error */ +#define M6811_NF 0x04 /* Noise Flag */ +#define M6811_FE 0x02 /* Framing Error */ +#define M6811__SCSR_0 0x01 /* Unused */ + +/* Flags of the BAUD register. */ +#define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */ +#define M6811__BAUD_6 0x40 /* Not used */ +#define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */ +#define M6811_SCP0 0x10 +#define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */ +#define M6811_SCR2 0x04 /* SCI Baud rate select */ +#define M6811_SCR1 0x02 +#define M6811_SCR0 0x01 + +#define M6811_BAUD_DIV_1 (0) +#define M6811_BAUD_DIV_3 (M6811_SCP0) +#define M6811_BAUD_DIV_4 (M6811_SCP1) +#define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0) + +/* Flags of the SPCR register. */ +#define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */ +#define M6811_SPE 0x40 /* Serial Peripheral System Enable */ +#define M6811_DWOM 0x20 /* Port D Wire-OR mode option */ +#define M6811_MSTR 0x10 /* Master Mode Select */ +#define M6811_CPOL 0x08 /* Clock Polarity */ +#define M6811_CPHA 0x04 /* Clock Phase */ +#define M6811_SPR1 0x02 /* SPI Clock Rate Select */ +#define M6811_SPR0 0x01 + +/* Flags of the SPSR register. */ +#define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ +#define M6811_WCOL 0x40 /* Write Collision */ +#define M6811_MODF 0x10 /* Mode Fault */ + +/* Flags of the ADCTL register. */ +#define M6811_CCF 0x80 /* Conversions Complete Flag */ +#define M6811_SCAN 0x20 /* Continuous Scan Control */ +#define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */ +#define M6811_CD 0x08 /* Channel Select D */ +#define M6811_CC 0x04 /* C */ +#define M6811_CB 0x02 /* B */ +#define M6811_CA 0x01 /* A */ + +/* Flags of the CFORC register. */ +#define M6811_FOC1 0x80 /* Force Output Compare 1 */ +#define M6811_FOC2 0x40 /* 2 */ +#define M6811_FOC3 0x20 /* 3 */ +#define M6811_FOC4 0x10 /* 4 */ +#define M6811_FOC5 0x08 /* 5 */ + +/* Flags of the OC1M register. */ +#define M6811_OC1M7 0x80 /* Output Compare 7 */ +#define M6811_OC1M6 0x40 /* 6 */ +#define M6811_OC1M5 0x20 /* 5 */ +#define M6811_OC1M4 0x10 /* 4 */ +#define M6811_OC1M3 0x08 /* 3 */ + +/* Flags of the OC1D register. */ +#define M6811_OC1D7 0x80 +#define M6811_OC1D6 0x40 +#define M6811_OC1D5 0x20 +#define M6811_OC1D4 0x10 +#define M6811_OC1D3 0x08 + +/* Flags of the TCTL1 register. */ +#define M6811_OM2 0x80 /* Output Mode 2 */ +#define M6811_OL2 0x40 /* Output Level 2 */ +#define M6811_OM3 0x20 +#define M6811_OL3 0x10 +#define M6811_OM4 0x08 +#define M6811_OL4 0x04 +#define M6811_OM5 0x02 +#define M6811_OL5 0x01 + +/* Flags of the TCTL2 register. */ +#define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */ +#define M6811_EDG1A 0x10 +#define M6811_EDG2B 0x08 /* Input 2 */ +#define M6811_EDG2A 0x04 +#define M6811_EDG3B 0x02 /* Input 3 */ +#define M6811_EDG3A 0x01 + +/* Flags of the TMSK1 register. */ +#define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */ +#define M6811_OC2I 0x40 /* 2 */ +#define M6811_OC3I 0x20 /* 3 */ +#define M6811_OC4I 0x10 /* 4 */ +#define M6811_OC5I 0x08 /* 5 */ +#define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */ +#define M6811_IC2I 0x02 /* 2 */ +#define M6811_IC3I 0x01 /* 3 */ + +/* Flags of the TFLG1 register. */ +#define M6811_OC1F 0x80 /* Output Compare 1 Flag */ +#define M6811_OC2F 0x40 /* 2 */ +#define M6811_OC3F 0x20 /* 3 */ +#define M6811_OC4F 0x10 /* 4 */ +#define M6811_OC5F 0x08 /* 5 */ +#define M6811_IC1F 0x04 /* Input Capture 1 Flag */ +#define M6811_IC2F 0x02 /* 2 */ +#define M6811_IC3F 0x01 /* 3 */ + +/* Flags of Timer Interrupt Mask Register 2 (TMSK2). */ +#define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */ +#define M6811_RTII 0x40 /* RTI Interrupt Enable */ +#define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */ +#define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */ +#define M6811_PR1 0x02 /* Timer prescaler */ +#define M6811_PR0 0x01 /* Timer prescaler */ +#define M6811_TPR_1 0x00 /* " " prescale div 1 */ +#define M6811_TPR_4 0x01 /* " " prescale div 4 */ +#define M6811_TPR_8 0x02 /* " " prescale div 8 */ +#define M6811_TPR_16 0x03 /* " " prescale div 16 */ + +/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */ +#define M6811_TOF 0x80 /* Timer overflow bit */ +#define M6811_RTIF 0x40 /* Read time interrupt flag */ +#define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */ +#define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */ + +/* Flags of Pulse Accumulator Control Register (PACTL). */ +#define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */ +#define M6811_PAEN 0x40 /* Pulse accumulator system enable */ +#define M6811_PAMOD 0x20 /* Pulse accumulator mode */ +#define M6811_PEDGE 0x10 /* Pulse accumulator edge control */ +#define M6811_RTR1 0x02 /* RTI Interrupt rates select */ +#define M6811_RTR0 0x01 /* " " " " */ + +/* Flags of the Options register. */ +#define M6811_ADPU 0x80 /* A/D Powerup */ +#define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */ +#define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */ +#define M6811_DLY 0x10 /* Stop exit turn on delay */ +#define M6811_CME 0x08 /* Clock Monitor enable */ +#define M6811_CR1 0x02 /* COP timer rate select */ +#define M6811_CR0 0x01 /* COP timer rate select */ + +/* Flags of the HPRIO register. */ +#define M6811_RBOOT 0x80 /* Read Bootstrap ROM */ +#define M6811_SMOD 0x40 /* Special Mode */ +#define M6811_MDA 0x20 /* Mode Select A */ +#define M6811_IRV 0x10 /* Internal Read Visibility */ +#define M6811_PSEL3 0x08 /* Priority Select */ +#define M6811_PSEL2 0x04 +#define M6811_PSEL1 0x02 +#define M6811_PSEL0 0x01 + +/* Some insns used by gas to turn relative branches into absolute ones. */ +#define M6811_BRA 0x20 +#define M6811_JMP 0x7e +#define M6811_BSR 0x8d +#define M6811_JSR 0xbd +#define M6812_JMP 0x06 +#define M6812_BSR 0x07 +#define M6812_JSR 0x16 + +/* Instruction code pages. Code page 1 is the default. */ +/*#define M6811_OPCODE_PAGE1 0x00*/ +#define M6811_OPCODE_PAGE2 0x18 +#define M6811_OPCODE_PAGE3 0x1A +#define M6811_OPCODE_PAGE4 0xCD + + +/* 68HC11 operands formats as stored in the m6811_opcode table. These + flags do not correspond to anything in the 68HC11 or 68HC12. + They are only used by GAS to recognize operands. */ +#define M6811_OP_NONE 0 /* No operand */ +#define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: *<val-8bits> */ +#define M6811_OP_IMM8 0x0002 /* 8 bits immediat: #<val-8bits> */ +#define M6811_OP_IMM16 0x0004 /* 16 bits immediat: #<val-16bits> */ +#define M6811_OP_IND16 0x0008 /* Indirect abs: <val-16> */ +#define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */ +#define M6812_OP_REG 0x0020 /* Register operand 1 */ +#define M6812_OP_REG_2 0x0040 /* Register operand 2 */ + +#define M6811_OP_IX 0x0080 /* Indirect IX: <val-8>,x */ +#define M6811_OP_IY 0x0100 /* Indirect IY: <val-8>,y */ +#define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */ +#define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */ +#define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ +#define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ +#define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ +#define M6812_OP_PAGE 0x4000 /* Page number */ +#define M6811_OP_MASK 0x07FFF +#define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */ +#define M6811_OP_BITMASK 0x00010000 /* Bitmask: #<val-8> */ +#define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: <val-8> */ +#define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: <val-16> */ +#define M6811_OP_PAGE1 0x0000 +#define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */ +#define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */ +#define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */ +#define M6811_MAX_OPERANDS 3 /* Max operands: brset <dst> <mask> <b> */ + +#define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */ +#define M6812_ACC_IND 0x00800000 /* [D,r] */ +#define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */ +#define M6812_PRE_DEC 0x02000000 /* n,-r */ +#define M6812_POST_INC 0x04000000 /* n,r+ */ +#define M6812_POST_DEC 0x08000000 /* n,r- */ +#define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */ +#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ +#define M6812_OP_IDX_P2 0x40000000 + +/* Markers to identify some instructions. */ +#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ +#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ +#define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */ + +#define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */ +#define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */ +#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ +#define M6812_OP_TBCC_MARKER 0x01000000 + +#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ + +#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ +#define M6811_OP_LOW_ADDR 0x02000000 + +#define M68HC12_BANK_VIRT 0x010000 +#define M68HC12_BANK_MASK 0x00003fff +#define M68HC12_BANK_BASE 0x00008000 +#define M68HC12_BANK_SHIFT 14 +#define M68HC12_BANK_PAGE_MASK 0x0ff + + +/* CPU identification. */ +#define cpu6811 0x01 +#define cpu6812 0x02 +#define cpu6812s 0x04 + +/* The opcode table is an array of struct m68hc11_opcode. */ +struct m68hc11_opcode { + const char* name; /* Op-code name */ + long format; + unsigned char size; + unsigned char opcode; + unsigned char cycles_low; + unsigned char cycles_high; + unsigned char set_flags_mask; + unsigned char clr_flags_mask; + unsigned char chg_flags_mask; + unsigned char arch; +}; + +/* Alias definition for 68HC12. */ +struct m68hc12_opcode_alias +{ + const char* name; + const char* translation; + unsigned char size; + unsigned char code1; + unsigned char code2; +}; + +/* The opcode table. The table contains all the opcodes (all pages). + You can't rely on the order. */ +extern const struct m68hc11_opcode m68hc11_opcodes[]; +extern const int m68hc11_num_opcodes; + +/* Alias table for 68HC12. It translates some 68HC11 insn which are not + implemented in 68HC12 but have equivalent translations. */ +extern const struct m68hc12_opcode_alias m68hc12_alias[]; +extern const int m68hc12_num_alias; + +#endif /* _OPCODE_M68HC11_H */ diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h new file mode 100644 index 000000000..014495b97 --- /dev/null +++ b/include/opcode/m68k.h @@ -0,0 +1,381 @@ +/* Opcode table header for m680[01234]0/m6888[12]/m68851. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, + 2003, 2004 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 1, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* These are used as bit flags for the arch field in the m68k_opcode + structure. */ +#define _m68k_undef 0 +#define m68000 0x001 +#define m68008 m68000 /* Synonym for -m68000. otherwise unused. */ +#define m68010 0x002 +#define m68020 0x004 +#define m68030 0x008 +#define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences; + gas will deal with the few differences. */ +#define m68040 0x010 +/* There is no 68050. */ +#define m68060 0x020 +#define m68881 0x040 +#define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ +#define m68851 0x080 +#define cpu32 0x100 /* e.g., 68332 */ + +#define mcfmac 0x200 /* ColdFire MAC. */ +#define mcfemac 0x400 /* ColdFire EMAC. */ +#define cfloat 0x800 /* ColdFire FPU. */ +#define mcfhwdiv 0x1000 /* ColdFire hardware divide. */ + +#define mcfisa_a 0x2000 /* ColdFire ISA_A. */ +#define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */ +#define mcfisa_b 0x8000 /* ColdFire ISA_B. */ +#define mcfusp 0x10000 /* ColdFire USP instructions. */ + +#define mcf5200 0x20000 +#define mcf5206e 0x40000 +#define mcf521x 0x80000 +#define mcf5249 0x100000 +#define mcf528x 0x200000 +#define mcf5307 0x400000 +#define mcf5407 0x800000 +#define mcf5470 0x1000000 +#define mcf5480 0x2000000 + + /* Handy aliases. */ +#define m68040up (m68040 | m68060) +#define m68030up (m68030 | m68040up) +#define m68020up (m68020 | m68030up) +#define m68010up (m68010 | cpu32 | m68020up) +#define m68000up (m68000 | m68010up) + +#define mfloat (m68881 | m68882 | m68040 | m68060) +#define mmmu (m68851 | m68030 | m68040 | m68060) + +/* The structure used to hold information for an opcode. */ + +struct m68k_opcode +{ + /* The opcode name. */ + const char *name; + /* The pseudo-size of the instruction(in bytes). Used to determine + number of bytes necessary to disassemble the instruction. */ + unsigned int size; + /* The opcode itself. */ + unsigned long opcode; + /* The mask used by the disassembler. */ + unsigned long match; + /* The arguments. */ + const char *args; + /* The architectures which support this opcode. */ + unsigned int arch; +}; + +/* The structure used to hold information for an opcode alias. */ + +struct m68k_opcode_alias +{ + /* The alias name. */ + const char *alias; + /* The instruction for which this is an alias. */ + const char *primary; +}; + +/* We store four bytes of opcode for all opcodes because that is the + most any of them need. The actual length of an instruction is + always at least 2 bytes, and is as much longer as necessary to hold + the operands it has. + + The match field is a mask saying which bits must match particular + opcode in order for an instruction to be an instance of that + opcode. + + The args field is a string containing two characters for each + operand of the instruction. The first specifies the kind of + operand; the second, the place it is stored. */ + +/* Kinds of operands: + Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+- + + D data register only. Stored as 3 bits. + A address register only. Stored as 3 bits. + a address register indirect only. Stored as 3 bits. + R either kind of register. Stored as 4 bits. + r either kind of register indirect only. Stored as 4 bits. + At the moment, used only for cas2 instruction. + F floating point coprocessor register only. Stored as 3 bits. + O an offset (or width): immediate data 0-31 or data register. + Stored as 6 bits in special format for BF... insns. + + autoincrement only. Stored as 3 bits (number of the address register). + - autodecrement only. Stored as 3 bits (number of the address register). + Q quick immediate data. Stored as 3 bits. + This matches an immediate operand only when value is in range 1 .. 8. + M moveq immediate data. Stored as 8 bits. + This matches an immediate operand only when value is in range -128..127 + T trap vector immediate data. Stored as 4 bits. + + k K-factor for fmove.p instruction. Stored as a 7-bit constant or + a three bit register offset, depending on the field type. + + # immediate data. Stored in special places (b, w or l) + which say how many bits to store. + ^ immediate data for floating point instructions. Special places + are offset by 2 bytes from '#'... + B pc-relative address, converted to an offset + that is treated as immediate data. + d displacement and register. Stores the register as 3 bits + and stores the displacement in the entire second word. + + C the CCR. No need to store it; this is just for filtering validity. + S the SR. No need to store, just as with CCR. + U the USP. No need to store, just as with CCR. + E the MAC ACC. No need to store, just as with CCR. + e the EMAC ACC[0123]. + G the MAC/EMAC MACSR. No need to store, just as with CCR. + g the EMAC ACCEXT{01,23}. + H the MASK. No need to store, just as with CCR. + i the MAC/EMAC scale factor. + + I Coprocessor ID. Not printed if 1. The Coprocessor ID is always + extracted from the 'd' field of word one, which means that an extended + coprocessor opcode can be skipped using the 'i' place, if needed. + + s System Control register for the floating point coprocessor. + + J Misc register for movec instruction, stored in 'j' format. + Possible values: + 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] + 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] + 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] + 0x003 TC MMU Translation Control [60, 40] + 0x004 ITT0 Instruction Transparent + Translation reg 0 [60, 40] + 0x005 ITT1 Instruction Transparent + Translation reg 1 [60, 40] + 0x006 DTT0 Data Transparent + Translation reg 0 [60, 40] + 0x007 DTT1 Data Transparent + Translation reg 1 [60, 40] + 0x008 BUSCR Bus Control Register [60] + 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] + 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] + 0x802 CAAR Cache Address Register [ 30, 20] + 0x803 MSP Master Stack Pointer [ 40, 30, 20] + 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] + 0x805 MMUSR MMU Status reg [ 40] + 0x806 URP User Root Pointer [60, 40] + 0x807 SRP Supervisor Root Pointer [60, 40] + 0x808 PCR Processor Configuration reg [60] + 0xC00 ROMBAR ROM Base Address Register [520X] + 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] + 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] + 0xC0F MBAR0 RAM Base Address Register 0 [520X] + 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] + 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] + + L Register list of the type d0-d7/a0-a7 etc. + (New! Improved! Can also hold fp0-fp7, as well!) + The assembler tries to see if the registers match the insn by + looking at where the insn wants them stored. + + l Register list like L, but with all the bits reversed. + Used for going the other way. . . + + c cache identifier which may be "nc" for no cache, "ic" + for instruction cache, "dc" for data cache, or "bc" + for both caches. Used in cinv and cpush. Always + stored in position "d". + + u Any register, with ``upper'' or ``lower'' specification. Used + in the mac instructions with size word. + + The remainder are all stored as 6 bits using an address mode and a + register number; they differ in which addressing modes they match. + + * all (modes 0-6,7.0-4) + ~ alterable memory (modes 2-6,7.0,7.1) + (not 0,1,7.2-4) + % alterable (modes 0-6,7.0,7.1) + (not 7.2-4) + ; data (modes 0,2-6,7.0-4) + (not 1) + @ data, but not immediate (modes 0,2-6,7.0-3) + (not 1,7.4) + ! control (modes 2,5,6,7.0-3) + (not 0,1,3,4,7.4) + & alterable control (modes 2,5,6,7.0,7.1) + (not 0,1,3,4,7.2-4) + $ alterable data (modes 0,2-6,7.0,7.1) + (not 1,7.2-4) + ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) + (not 1,3,4,7.2-4) + / control, or data register (modes 0,2,5,6,7.0-3) + (not 1,3,4,7.4) + > *save operands (modes 2,4,5,6,7.0,7.1) + (not 0,1,3,7.2-4) + < *restore operands (modes 2,3,5,6,7.0-3) + (not 0,1,4,7.4) + + coldfire move operands: + m (modes 0-4) + n (modes 5,7.2) + o (modes 6,7.0,7.1,7.3,7.4) + p (modes 0-5) + + coldfire bset/bclr/btst/mulsl/mulul operands: + q (modes 0,2-5) + v (modes 0,2-5,7.0,7.1) + b (modes 0,2-5,7.2) + w (modes 2-5,7.2) + y (modes 2,5) + z (modes 2,5,7.2) + x mov3q immediate operand. + 4 (modes 2,3,4,5) + */ + +/* For the 68851: */ +/* I didn't use much imagination in choosing the + following codes, so many of them aren't very + mnemonic. -rab + + 0 32 bit pmmu register + Possible values: + 000 TC Translation Control Register (68030, 68851) + + 1 16 bit pmmu register + 111 AC Access Control (68851) + + 2 8 bit pmmu register + 100 CAL Current Access Level (68851) + 101 VAL Validate Access Level (68851) + 110 SCC Stack Change Control (68851) + + 3 68030-only pmmu registers (32 bit) + 010 TT0 Transparent Translation reg 0 + (aka Access Control reg 0 -- AC0 -- on 68ec030) + 011 TT1 Transparent Translation reg 1 + (aka Access Control reg 1 -- AC1 -- on 68ec030) + + W wide pmmu registers + Possible values: + 001 DRP Dma Root Pointer (68851) + 010 SRP Supervisor Root Pointer (68030, 68851) + 011 CRP Cpu Root Pointer (68030, 68851) + + f function code register (68030, 68851) + 0 SFC + 1 DFC + + V VAL register only (68851) + + X BADx, BACx (16 bit) + 100 BAD Breakpoint Acknowledge Data (68851) + 101 BAC Breakpoint Acknowledge Control (68851) + + Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) + Z PCSR (68851) + + | memory (modes 2-6, 7.*) + + t address test level (68030 only) + Stored as 3 bits, range 0-7. + Also used for breakpoint instruction now. + +*/ + +/* Places to put an operand, for non-general operands: + Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ + + s source, low bits of first word. + d dest, shifted 9 in first word + 1 second word, shifted 12 + 2 second word, shifted 6 + 3 second word, shifted 0 + 4 third word, shifted 12 + 5 third word, shifted 6 + 6 third word, shifted 0 + 7 second word, shifted 7 + 8 second word, shifted 10 + 9 second word, shifted 5 + D store in both place 1 and place 3; for divul and divsl. + B first word, low byte, for branch displacements + W second word (entire), for branch displacements + L second and third words (entire), for branch displacements + (also overloaded for move16) + b second word, low byte + w second word (entire) [variable word/long branch offset for dbra] + W second word (entire) (must be signed 16 bit value) + l second and third word (entire) + g variable branch offset for bra and similar instructions. + The place to store depends on the magnitude of offset. + t store in both place 7 and place 8; for floating point operations + c branch offset for cpBcc operations. + The place to store is word two if bit six of word one is zero, + and words two and three if bit six of word one is one. + i Increment by two, to skip over coprocessor extended operands. Only + works with the 'I' format. + k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. + Also used for dynamic fmovem instruction. + C floating point coprocessor constant - 7 bits. Also used for static + K-factors... + j Movec register #, stored in 12 low bits of second word. + m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word + and remaining 3 bits of register shifted 9 bits in first word. + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split + with MSB shifted 6 bits in first word and remaining 3 bits of + register shifted 9 bits in first word. No upper/lower + indication is done.) Use with `R' or `u' format. + o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + M For M[S]ACw; 4 bits in low bits of first word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + N For M[S]ACw; 4 bits in low bits of second word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + h shift indicator (scale factor), 1 bit shifted 10 in second word + + Places to put operand, for general operands: + d destination, shifted 6 bits in first word + b source, at low bit of first word, and immediate uses one byte + w source, at low bit of first word, and immediate uses two bytes + l source, at low bit of first word, and immediate uses four bytes + s source, at low bit of first word. + Used sometimes in contexts where immediate is not allowed anyway. + f single precision float, low bit of 1st word, immediate uses 4 bytes + F double precision float, low bit of 1st word, immediate uses 8 bytes + x extended precision float, low bit of 1st word, immediate uses 12 bytes + p packed float, low bit of 1st word, immediate uses 12 bytes + G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) + H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) + F EMAC ACCx + f EMAC ACCy + I MAC/EMAC scale factor + / Like 's', but set 2nd word, bit 5 if trailing_ampersand set + ] first word, bit 10 +*/ + +extern const struct m68k_opcode m68k_opcodes[]; +extern const struct m68k_opcode_alias m68k_opcode_aliases[]; + +extern const int m68k_numopcodes, m68k_numaliases; + +/* end of m68k-opcode.h */ diff --git a/include/opcode/m88k.h b/include/opcode/m88k.h new file mode 100644 index 000000000..6a163bbe9 --- /dev/null +++ b/include/opcode/m88k.h @@ -0,0 +1,453 @@ +/* Table of opcodes for the Motorola M88k family. + Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* + * Disassembler Instruction Table + * + * The first field of the table is the opcode field. If an opcode + * is specified which has any non-opcode bits on, a system error + * will occur when the system attempts the install it into the + * instruction table. The second parameter is a pointer to the + * instruction mnemonic. Each operand is specified by offset, width, + * and type. The offset is the bit number of the least significant + * bit of the operand with bit 0 being the least significant bit of + * the instruction. The width is the number of bits used to specify + * the operand. The type specifies the output format to be used for + * the operand. The valid formats are: register, register indirect, + * hex constant, and bit field specification. The last field is a + * pointer to the next instruction in the linked list. These pointers + * are initialized by init_disasm(). + * + * Revision History + * + * Revision 1.0 11/08/85 Creation date + * 1.1 02/05/86 Updated instruction mnemonic table MD + * 1.2 06/16/86 Updated SIM_FLAGS for floating point + * 1.3 09/20/86 Updated for new encoding + * 05/11/89 R. Trawick adapted from Motorola disassembler + */ + +#include <stdio.h> + +/* Define the number of bits in the primary opcode field of the instruction, + the destination field, the source 1 and source 2 fields. */ + +/* Size of opcode field. */ +#define OP 8 + +/* Size of destination. */ +#define DEST 6 + +/* Size of source1. */ +#define SOURCE1 6 + +/* Size of source2. */ +#define SOURCE2 6 + +/* Number of registers. */ +#define REGs 32 + +/* Type definitions. */ + +typedef unsigned int UINT; +#define WORD long +#define FLAG unsigned +#define STATE short + +/* The next four equates define the priorities that the various classes + * of instructions have regarding writing results back into registers and + * signalling exceptions. */ + +/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */ +#undef PMEM + +/* Integer priority. */ +#define PINT 0 + +/* Floating point priority. */ +#define PFLT 1 + +/* Memory priority. */ +#define PMEM 2 + +/* Not applicable, instruction doesn't write to regs. */ +#define NA 3 + +/* Highest of these priorities. */ +#define HIPRI 3 + +/* The instruction registers are an artificial mechanism to speed up + * simulator execution. In the real processor, an instruction register + * is 32 bits wide. In the simulator, the 32 bit instruction is kept in + * a structure field called rawop, and the instruction is partially decoded, + * and split into various fields and flags which make up the other fields + * of the structure. + * The partial decode is done when the instructions are initially loaded + * into simulator memory. The simulator code memory is not an array of + * 32 bit words, but is an array of instruction register structures. + * Yes this wastes memory, but it executes much quicker. + */ + +struct IR_FIELDS +{ + unsigned op:OP, + dest: DEST, + src1: SOURCE1, + src2: SOURCE2; + int ltncy, + extime, + /* Writeback priority. */ + wb_pri; + /* Immediate size. */ + unsigned imm_flags:2, + /* Register source 1 used. */ + rs1_used:1, + /* Register source 2 used. */ + rs2_used:1, + /* Register source/dest. used. */ + rsd_used:1, + /* Complement. */ + c_flag:1, + /* Upper half word. */ + u_flag:1, + /* Execute next. */ + n_flag:1, + /* Uses writeback slot. */ + wb_flag:1, + /* Dest size. */ + dest_64:1, + /* Source 1 size. */ + s1_64:1, + /* Source 2 size. */ + s2_64:1, + scale_flag:1, + /* Scaled register. */ + brk_flg:1; +}; + +struct mem_segs +{ + /* Pointer (returned by calloc) to segment. */ + struct mem_wrd *seg; + + /* Base load address from file headers. */ + unsigned long baseaddr; + + /* Ending address of segment. */ + unsigned long endaddr; + + /* Segment control flags (none defined). */ + int flags; +}; + +#define MAXSEGS (10) /* max number of segment allowed */ +#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ + +#if 0 +#define BRK_RD (0x01) /* break on memory read */ +#define BRK_WR (0x02) /* break on memory write */ +#define BRK_EXEC (0x04) /* break on execution */ +#define BRK_CNT (0x08) /* break on terminal count */ +#endif + +struct mem_wrd +{ + /* Simulator instruction break down. */ + struct IR_FIELDS opcode; + union { + /* Memory element break down. */ + unsigned long l; + unsigned short s[2]; + unsigned char c[4]; + } mem; +}; + +/* Size of each 32 bit memory model. */ +#define MEMWRDSIZE (sizeof (struct mem_wrd)) + +extern struct mem_segs memory[]; +extern struct PROCESSOR m78000; + +struct PROCESSOR +{ + unsigned WORD + /* Execute instruction pointer. */ + ip, + /* Vector base register. */ + vbr, + /* Processor status register. */ + psr; + + /* Source 1. */ + WORD S1bus, + /* Source 2. */ + S2bus, + /* Destination. */ + Dbus, + /* Data address bus. */ + DAbus, + ALU, + /* Data registers. */ + Regs[REGs], + /* Max clocks before reg is available. */ + time_left[REGs], + /* Writeback priority of reg. */ + wb_pri[REGs], + /* Integer unit control regs. */ + SFU0_regs[REGs], + /* Floating point control regs. */ + SFU1_regs[REGs], + Scoreboard[REGs], + Vbr; + unsigned WORD scoreboard, + Psw, + Tpsw; + /* Waiting for a jump instruction. */ + FLAG jump_pending:1; +}; + +/* Size of immediate field. */ + +#define i26bit 1 +#define i16bit 2 +#define i10bit 3 + +/* Definitions for fields in psr. */ + +#define mode 31 +#define rbo 30 +#define ser 29 +#define carry 28 +#define sf7m 11 +#define sf6m 10 +#define sf5m 9 +#define sf4m 8 +#define sf3m 7 +#define sf2m 6 +#define sf1m 5 +#define mam 4 +#define inm 3 +#define exm 2 +#define trm 1 +#define ovfm 0 + +/* The 1 clock operations. */ + +#define ADDU 1 +#define ADDC 2 +#define ADDUC 3 +#define ADD 4 + +#define SUBU ADD+1 +#define SUBB ADD+2 +#define SUBUB ADD+3 +#define SUB ADD+4 + +#define AND_ ADD+5 +#define OR ADD+6 +#define XOR ADD+7 +#define CMP ADD+8 + +/* Loads. */ + +#define LDAB CMP+1 +#define LDAH CMP+2 +#define LDA CMP+3 +#define LDAD CMP+4 + +#define LDB LDAD+1 +#define LDH LDAD+2 +#define LD LDAD+3 +#define LDD LDAD+4 +#define LDBU LDAD+5 +#define LDHU LDAD+6 + +/* Stores. */ + +#define STB LDHU+1 +#define STH LDHU+2 +#define ST LDHU+3 +#define STD LDHU+4 + +/* Exchange. */ + +#define XMEMBU LDHU+5 +#define XMEM LDHU+6 + +/* Branches. */ + +#define JSR STD+1 +#define BSR STD+2 +#define BR STD+3 +#define JMP STD+4 +#define BB1 STD+5 +#define BB0 STD+6 +#define RTN STD+7 +#define BCND STD+8 + +/* Traps. */ + +#define TB1 BCND+1 +#define TB0 BCND+2 +#define TCND BCND+3 +#define RTE BCND+4 +#define TBND BCND+5 + +/* Misc. */ + +#define MUL TBND + 1 +#define DIV MUL +2 +#define DIVU MUL +3 +#define MASK MUL +4 +#define FF0 MUL +5 +#define FF1 MUL +6 +#define CLR MUL +7 +#define SET MUL +8 +#define EXT MUL +9 +#define EXTU MUL +10 +#define MAK MUL +11 +#define ROT MUL +12 + +/* Control register manipulations. */ + +#define LDCR ROT +1 +#define STCR ROT +2 +#define XCR ROT +3 + +#define FLDCR ROT +4 +#define FSTCR ROT +5 +#define FXCR ROT +6 + +#define NOP XCR +1 + +/* Floating point instructions. */ + +#define FADD NOP +1 +#define FSUB NOP +2 +#define FMUL NOP +3 +#define FDIV NOP +4 +#define FSQRT NOP +5 +#define FCMP NOP +6 +#define FIP NOP +7 +#define FLT NOP +8 +#define INT NOP +9 +#define NINT NOP +10 +#define TRNC NOP +11 +#define FLDC NOP +12 +#define FSTC NOP +13 +#define FXC NOP +14 + +#define UEXT(src,off,wid) \ + ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) + +#define SEXT(src,off,wid) \ + (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) + +#define MAKE(src,off,wid) \ + ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) + +#define opword(n) (unsigned long) (memaddr->mem.l) + +/* Constants and masks. */ + +#define SFU0 0x80000000 +#define SFU1 0x84000000 +#define SFU7 0x9c000000 +#define RRI10 0xf0000000 +#define RRR 0xf4000000 +#define SFUMASK 0xfc00ffe0 +#define RRRMASK 0xfc00ffe0 +#define RRI10MASK 0xfc00fc00 +#define DEFMASK 0xfc000000 +#define CTRL 0x0000f000 +#define CTRLMASK 0xfc00f800 + +/* Operands types. */ + +enum operand_type +{ + HEX = 1, + REG = 2, + CONT = 3, + IND = 3, + BF = 4, + /* Scaled register. */ + REGSC = 5, + /* Control register. */ + CRREG = 6, + /* Floating point control register. */ + FCRREG = 7, + PCREL = 8, + CONDMASK = 9, + /* Extended register. */ + XREG = 10, + /* Decimal. */ + DEC = 11 +}; + +/* Hashing specification. */ + +#define HASHVAL 79 + +/* Structure templates. */ + +typedef struct +{ + unsigned int offset; + unsigned int width; + enum operand_type type; +} OPSPEC; + +struct SIM_FLAGS +{ + int ltncy, /* latency (max number of clocks needed to execute). */ + extime, /* execution time (min number of clocks needed to execute). */ + wb_pri; /* writeback slot priority. */ + unsigned op:OP, /* simulator version of opcode. */ + imm_flags:2, /* 10,16 or 26 bit immediate flags. */ + rs1_used:1, /* register source 1 used. */ + rs2_used:1, /* register source 2 used. */ + rsd_used:1, /* register source/dest used. */ + c_flag:1, /* complement. */ + u_flag:1, /* upper half word. */ + n_flag:1, /* execute next. */ + wb_flag:1, /* uses writeback slot. */ + dest_64:1, /* double precision dest. */ + s1_64:1, /* double precision source 1. */ + s2_64:1, /* double precision source 2. */ + scale_flag:1; /* register is scaled. */ +}; + +typedef struct INSTRUCTAB { + unsigned int opcode; + char *mnemonic; + OPSPEC op1,op2,op3; + struct SIM_FLAGS flgs; +} INSTAB; + + +#define NO_OPERAND {0,0,0} + +extern const INSTAB instructions[]; + +/* + * Local Variables: + * fill-column: 131 + * End: + */ diff --git a/include/opcode/mips.h b/include/opcode/mips.h new file mode 100644 index 000000000..5c3ddfcd7 --- /dev/null +++ b/include/opcode/mips.h @@ -0,0 +1,914 @@ +/* mips.h. Mips opcode list for GDB, the GNU debugger. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + Contributed by Ralph Campbell and OSF + Commented and modified by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _MIPS_H_ +#define _MIPS_H_ + +/* These are bit masks and shift counts to use to access the various + fields of an instruction. To retrieve the X field of an + instruction, use the expression + (i >> OP_SH_X) & OP_MASK_X + To set the same field (to j), use + i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) + + Make sure you use fields that are appropriate for the instruction, + of course. + + The 'i' format uses OP, RS, RT and IMMEDIATE. + + The 'j' format uses OP and TARGET. + + The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. + + The 'b' format uses OP, RS, RT and DELTA. + + The floating point 'i' format uses OP, RS, RT and IMMEDIATE. + + The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. + + A breakpoint instruction uses OP, CODE and SPEC (10 bits of the + breakpoint instruction are not defined; Kane says the breakpoint + code field in BREAK is 20 bits; yet MIPS assemblers and debuggers + only use ten bits). An optional two-operand form of break/sdbbp + allows the lower ten bits to be set too, and MIPS32 and later + architectures allow 20 bits to be set with a signal operand + (using CODE20). + + The syscall instruction uses CODE20. + + The general coprocessor instructions use COPZ. */ + +#define OP_MASK_OP 0x3f +#define OP_SH_OP 26 +#define OP_MASK_RS 0x1f +#define OP_SH_RS 21 +#define OP_MASK_FR 0x1f +#define OP_SH_FR 21 +#define OP_MASK_FMT 0x1f +#define OP_SH_FMT 21 +#define OP_MASK_BCC 0x7 +#define OP_SH_BCC 18 +#define OP_MASK_CODE 0x3ff +#define OP_SH_CODE 16 +#define OP_MASK_CODE2 0x3ff +#define OP_SH_CODE2 6 +#define OP_MASK_RT 0x1f +#define OP_SH_RT 16 +#define OP_MASK_FT 0x1f +#define OP_SH_FT 16 +#define OP_MASK_CACHE 0x1f +#define OP_SH_CACHE 16 +#define OP_MASK_RD 0x1f +#define OP_SH_RD 11 +#define OP_MASK_FS 0x1f +#define OP_SH_FS 11 +#define OP_MASK_PREFX 0x1f +#define OP_SH_PREFX 11 +#define OP_MASK_CCC 0x7 +#define OP_SH_CCC 8 +#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ +#define OP_SH_CODE20 6 +#define OP_MASK_SHAMT 0x1f +#define OP_SH_SHAMT 6 +#define OP_MASK_FD 0x1f +#define OP_SH_FD 6 +#define OP_MASK_TARGET 0x3ffffff +#define OP_SH_TARGET 0 +#define OP_MASK_COPZ 0x1ffffff +#define OP_SH_COPZ 0 +#define OP_MASK_IMMEDIATE 0xffff +#define OP_SH_IMMEDIATE 0 +#define OP_MASK_DELTA 0xffff +#define OP_SH_DELTA 0 +#define OP_MASK_FUNCT 0x3f +#define OP_SH_FUNCT 0 +#define OP_MASK_SPEC 0x3f +#define OP_SH_SPEC 0 +#define OP_SH_LOCC 8 /* FP condition code. */ +#define OP_SH_HICC 18 /* FP condition code. */ +#define OP_MASK_CC 0x7 +#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ +#define OP_MASK_COP1NORM 0x1 /* a single bit. */ +#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ +#define OP_MASK_COP1SPEC 0xf +#define OP_MASK_COP1SCLR 0x4 +#define OP_MASK_COP1CMP 0x3 +#define OP_SH_COP1CMP 4 +#define OP_SH_FORMAT 21 /* FP short format field. */ +#define OP_MASK_FORMAT 0x7 +#define OP_SH_TRUE 16 +#define OP_MASK_TRUE 0x1 +#define OP_SH_GE 17 +#define OP_MASK_GE 0x01 +#define OP_SH_UNSIGNED 16 +#define OP_MASK_UNSIGNED 0x1 +#define OP_SH_HINT 16 +#define OP_MASK_HINT 0x1f +#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ +#define OP_MASK_MMI 0x3f +#define OP_SH_MMISUB 6 +#define OP_MASK_MMISUB 0x1f +#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ +#define OP_SH_PERFREG 1 +#define OP_SH_SEL 0 /* Coprocessor select field. */ +#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ +#define OP_SH_CODE19 6 /* 19 bit wait code. */ +#define OP_MASK_CODE19 0x7ffff +#define OP_SH_ALN 21 +#define OP_MASK_ALN 0x7 +#define OP_SH_VSEL 21 +#define OP_MASK_VSEL 0x1f +#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, + but 0x8-0xf don't select bytes. */ +#define OP_SH_VECBYTE 22 +#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ +#define OP_SH_VECALIGN 21 +#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ +#define OP_SH_INSMSB 11 +#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ +#define OP_SH_EXTMSBD 11 + +#define OP_OP_COP0 0x10 +#define OP_OP_COP1 0x11 +#define OP_OP_COP2 0x12 +#define OP_OP_COP3 0x13 +#define OP_OP_LWC1 0x31 +#define OP_OP_LWC2 0x32 +#define OP_OP_LWC3 0x33 /* a.k.a. pref */ +#define OP_OP_LDC1 0x35 +#define OP_OP_LDC2 0x36 +#define OP_OP_LDC3 0x37 /* a.k.a. ld */ +#define OP_OP_SWC1 0x39 +#define OP_OP_SWC2 0x3a +#define OP_OP_SWC3 0x3b +#define OP_OP_SDC1 0x3d +#define OP_OP_SDC2 0x3e +#define OP_OP_SDC3 0x3f /* a.k.a. sd */ + +/* Values in the 'VSEL' field. */ +#define MDMX_FMTSEL_IMM_QH 0x1d +#define MDMX_FMTSEL_IMM_OB 0x1e +#define MDMX_FMTSEL_VEC_QH 0x15 +#define MDMX_FMTSEL_VEC_OB 0x16 + +/* This structure holds information for a particular instruction. */ + +struct mips_opcode +{ + /* The name of the instruction. */ + const char *name; + /* A string describing the arguments for this instruction. */ + const char *args; + /* The basic opcode for the instruction. When assembling, this + opcode is modified by the arguments to produce the actual opcode + that is used. If pinfo is INSN_MACRO, then this is 0. */ + unsigned long match; + /* If pinfo is not INSN_MACRO, then this is a bit mask for the + relevant portions of the opcode when disassembling. If the + actual opcode anded with the match field equals the opcode field, + then we have found the correct instruction. If pinfo is + INSN_MACRO, then this field is the macro identifier. */ + unsigned long mask; + /* For a macro, this is INSN_MACRO. Otherwise, it is a collection + of bits describing the instruction, notably any relevant hazard + information. */ + unsigned long pinfo; + /* A collection of bits describing the instruction sets of which this + instruction or macro is a member. */ + unsigned long membership; +}; + +/* These are the characters which may appear in the args field of an + instruction. They appear in the order in which the fields appear + when the instruction is used. Commas and parentheses in the args + string are ignored when assembling, and written into the output + when disassembling. + + Each of these characters corresponds to a mask field defined above. + + "<" 5 bit shift amount (OP_*_SHAMT) + ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) + "a" 26 bit target address (OP_*_TARGET) + "b" 5 bit base register (OP_*_RS) + "c" 10 bit breakpoint code (OP_*_CODE) + "d" 5 bit destination register specifier (OP_*_RD) + "h" 5 bit prefx hint (OP_*_PREFX) + "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) + "j" 16 bit signed immediate (OP_*_DELTA) + "k" 5 bit cache opcode in target register position (OP_*_CACHE) + Also used for immediate operands in vr5400 vector insns. + "o" 16 bit signed offset (OP_*_DELTA) + "p" 16 bit PC relative branch target address (OP_*_DELTA) + "q" 10 bit extra breakpoint code (OP_*_CODE2) + "r" 5 bit same register used as both source and target (OP_*_RS) + "s" 5 bit source register specifier (OP_*_RS) + "t" 5 bit target register (OP_*_RT) + "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) + "v" 5 bit same register used as both source and destination (OP_*_RS) + "w" 5 bit same register used as both target and destination (OP_*_RT) + "U" 5 bit same destination register in both OP_*_RD and OP_*_RT + (used by clo and clz) + "C" 25 bit coprocessor function code (OP_*_COPZ) + "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) + "J" 19 bit wait function code (OP_*_CODE19) + "x" accept and ignore register name + "z" must be zero register + "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) + "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). + Enforces: 0 <= pos < 32. + "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 0 < (pos+size) <= 32. + "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 0 < (pos+size) <= 32. + (Also used by "dext" w/ different limits, but limits for + that are checked by the M_DEXT macro.) + "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). + Enforces: 32 <= pos < 64. + "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + + Floating point instructions: + "D" 5 bit destination register (OP_*_FD) + "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) + "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) + "S" 5 bit fs source 1 register (OP_*_FS) + "T" 5 bit ft source 2 register (OP_*_FT) + "R" 5 bit fr source 3 register (OP_*_FR) + "V" 5 bit same register used as floating source and destination (OP_*_FS) + "W" 5 bit same register used as floating target and destination (OP_*_FT) + + Coprocessor instructions: + "E" 5 bit target register (OP_*_RT) + "G" 5 bit destination register (OP_*_RD) + "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) + "P" 5 bit performance-monitor register (OP_*_PERFREG) + "e" 5 bit vector register byte specifier (OP_*_VECBYTE) + "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) + see also "k" above + "+D" Combined destination register ("G") and sel ("H") for CP0 ops, + for pretty-printing in disassembly only. + + Macro instructions: + "A" General 32 bit expression + "I" 32 bit immediate (value placed in imm_expr). + "+I" 32 bit immediate (value placed in imm2_expr). + "F" 64 bit floating point constant in .rdata + "L" 64 bit floating point constant in .lit8 + "f" 32 bit floating point constant + "l" 32 bit floating point constant in .lit4 + + MDMX instruction operands (note that while these use the FP register + fields, they accept both $fN and $vN names for the registers): + "O" MDMX alignment offset (OP_*_ALN) + "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) + "X" MDMX destination register (OP_*_FD) + "Y" MDMX source register (OP_*_FS) + "Z" MDMX source register (OP_*_FT) + + Other: + "()" parens surrounding optional value + "," separates operands + "[]" brackets around index for vector-op scalar operand specifier (vr5400) + "+" Start of extension sequence. + + Characters used so far, for quick reference when adding more: + "%[]<>(),+" + "ABCDEFGHIJKLMNOPQRSTUVWXYZ" + "abcdefhijklopqrstuvwxz" + + Extension character sequences used so far ("+" followed by the + following), for quick reference when adding more: + "ABCDEFGHI" +*/ + +/* These are the bits which may be set in the pinfo field of an + instructions, if it is not equal to INSN_MACRO. */ + +/* Modifies the general purpose register in OP_*_RD. */ +#define INSN_WRITE_GPR_D 0x00000001 +/* Modifies the general purpose register in OP_*_RT. */ +#define INSN_WRITE_GPR_T 0x00000002 +/* Modifies general purpose register 31. */ +#define INSN_WRITE_GPR_31 0x00000004 +/* Modifies the floating point register in OP_*_FD. */ +#define INSN_WRITE_FPR_D 0x00000008 +/* Modifies the floating point register in OP_*_FS. */ +#define INSN_WRITE_FPR_S 0x00000010 +/* Modifies the floating point register in OP_*_FT. */ +#define INSN_WRITE_FPR_T 0x00000020 +/* Reads the general purpose register in OP_*_RS. */ +#define INSN_READ_GPR_S 0x00000040 +/* Reads the general purpose register in OP_*_RT. */ +#define INSN_READ_GPR_T 0x00000080 +/* Reads the floating point register in OP_*_FS. */ +#define INSN_READ_FPR_S 0x00000100 +/* Reads the floating point register in OP_*_FT. */ +#define INSN_READ_FPR_T 0x00000200 +/* Reads the floating point register in OP_*_FR. */ +#define INSN_READ_FPR_R 0x00000400 +/* Modifies coprocessor condition code. */ +#define INSN_WRITE_COND_CODE 0x00000800 +/* Reads coprocessor condition code. */ +#define INSN_READ_COND_CODE 0x00001000 +/* TLB operation. */ +#define INSN_TLB 0x00002000 +/* Reads coprocessor register other than floating point register. */ +#define INSN_COP 0x00004000 +/* Instruction loads value from memory, requiring delay. */ +#define INSN_LOAD_MEMORY_DELAY 0x00008000 +/* Instruction loads value from coprocessor, requiring delay. */ +#define INSN_LOAD_COPROC_DELAY 0x00010000 +/* Instruction has unconditional branch delay slot. */ +#define INSN_UNCOND_BRANCH_DELAY 0x00020000 +/* Instruction has conditional branch delay slot. */ +#define INSN_COND_BRANCH_DELAY 0x00040000 +/* Conditional branch likely: if branch not taken, insn nullified. */ +#define INSN_COND_BRANCH_LIKELY 0x00080000 +/* Moves to coprocessor register, requiring delay. */ +#define INSN_COPROC_MOVE_DELAY 0x00100000 +/* Loads coprocessor register from memory, requiring delay. */ +#define INSN_COPROC_MEMORY_DELAY 0x00200000 +/* Reads the HI register. */ +#define INSN_READ_HI 0x00400000 +/* Reads the LO register. */ +#define INSN_READ_LO 0x00800000 +/* Modifies the HI register. */ +#define INSN_WRITE_HI 0x01000000 +/* Modifies the LO register. */ +#define INSN_WRITE_LO 0x02000000 +/* Takes a trap (easier to keep out of delay slot). */ +#define INSN_TRAP 0x04000000 +/* Instruction stores value into memory. */ +#define INSN_STORE_MEMORY 0x08000000 +/* Instruction uses single precision floating point. */ +#define FP_S 0x10000000 +/* Instruction uses double precision floating point. */ +#define FP_D 0x20000000 +/* Instruction is part of the tx39's integer multiply family. */ +#define INSN_MULT 0x40000000 +/* Instruction synchronize shared memory. */ +#define INSN_SYNC 0x80000000 +/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */ +#define INSN_READ_MDMX_ACC 0 +/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */ +#define INSN_WRITE_MDMX_ACC 0 + +/* Instruction is actually a macro. It should be ignored by the + disassembler, and requires special treatment by the assembler. */ +#define INSN_MACRO 0xffffffff + +/* Masks used to mark instructions to indicate which MIPS ISA level + they were introduced in. ISAs, as defined below, are logical + ORs of these bits, indicating that they support the instructions + defined at the given level. */ + +#define INSN_ISA_MASK 0x00000fff +#define INSN_ISA1 0x00000001 +#define INSN_ISA2 0x00000002 +#define INSN_ISA3 0x00000004 +#define INSN_ISA4 0x00000008 +#define INSN_ISA5 0x00000010 +#define INSN_ISA32 0x00000020 +#define INSN_ISA64 0x00000040 +#define INSN_ISA32R2 0x00000080 +#define INSN_ISA64R2 0x00000100 + +/* Masks used for MIPS-defined ASEs. */ +#define INSN_ASE_MASK 0x0000f000 + +/* MIPS 16 ASE */ +#define INSN_MIPS16 0x00002000 +/* MIPS-3D ASE */ +#define INSN_MIPS3D 0x00004000 +/* MDMX ASE */ +#define INSN_MDMX 0x00008000 + +/* Chip specific instructions. These are bitmasks. */ + +/* MIPS R4650 instruction. */ +#define INSN_4650 0x00010000 +/* LSI R4010 instruction. */ +#define INSN_4010 0x00020000 +/* NEC VR4100 instruction. */ +#define INSN_4100 0x00040000 +/* Toshiba R3900 instruction. */ +#define INSN_3900 0x00080000 +/* MIPS R10000 instruction. */ +#define INSN_10000 0x00100000 +/* Broadcom SB-1 instruction. */ +#define INSN_SB1 0x00200000 +/* NEC VR4111/VR4181 instruction. */ +#define INSN_4111 0x00400000 +/* NEC VR4120 instruction. */ +#define INSN_4120 0x00800000 +/* NEC VR5400 instruction. */ +#define INSN_5400 0x01000000 +/* NEC VR5500 instruction. */ +#define INSN_5500 0x02000000 + +/* MIPS ISA defines, use instead of hardcoding ISA level. */ + +#define ISA_UNKNOWN 0 /* Gas internal use. */ +#define ISA_MIPS1 (INSN_ISA1) +#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) +#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) +#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) +#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) + +#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) +#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) + +#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) +#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) + + +/* CPU defines, use instead of hardcoding processor number. Keep this + in sync with bfd/archures.c in order for machine selection to work. */ +#define CPU_UNKNOWN 0 /* Gas internal use. */ +#define CPU_R3000 3000 +#define CPU_R3900 3900 +#define CPU_R4000 4000 +#define CPU_R4010 4010 +#define CPU_VR4100 4100 +#define CPU_R4111 4111 +#define CPU_VR4120 4120 +#define CPU_R4300 4300 +#define CPU_R4400 4400 +#define CPU_R4600 4600 +#define CPU_R4650 4650 +#define CPU_R5000 5000 +#define CPU_VR5400 5400 +#define CPU_VR5500 5500 +#define CPU_R6000 6000 +#define CPU_RM7000 7000 +#define CPU_R8000 8000 +#define CPU_R10000 10000 +#define CPU_R12000 12000 +#define CPU_MIPS16 16 +#define CPU_MIPS32 32 +#define CPU_MIPS32R2 33 +#define CPU_MIPS5 5 +#define CPU_MIPS64 64 +#define CPU_MIPS64R2 65 +#define CPU_SB1 12310201 /* octal 'SB', 01. */ + +/* Test for membership in an ISA including chip specific ISAs. INSN + is pointer to an element of the opcode table; ISA is the specified + ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to + test, or zero if no CPU specific ISA test is desired. */ + +#define OPCODE_IS_MEMBER(insn, isa, cpu) \ + (((insn)->membership & isa) != 0 \ + || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ + || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ + || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ + && ((insn)->membership & INSN_10000) != 0) \ + || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ + || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ + || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ + || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ + || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ + || 0) /* Please keep this term for easier source merging. */ + +/* This is a list of macro expanded instructions. + + _I appended means immediate + _A appended means address + _AB appended means address with base register + _D appended means 64 bit floating point constant + _S appended means 32 bit floating point constant. */ + +enum +{ + M_ABS, + M_ADD_I, + M_ADDU_I, + M_AND_I, + M_BEQ, + M_BEQ_I, + M_BEQL_I, + M_BGE, + M_BGEL, + M_BGE_I, + M_BGEL_I, + M_BGEU, + M_BGEUL, + M_BGEU_I, + M_BGEUL_I, + M_BGT, + M_BGTL, + M_BGT_I, + M_BGTL_I, + M_BGTU, + M_BGTUL, + M_BGTU_I, + M_BGTUL_I, + M_BLE, + M_BLEL, + M_BLE_I, + M_BLEL_I, + M_BLEU, + M_BLEUL, + M_BLEU_I, + M_BLEUL_I, + M_BLT, + M_BLTL, + M_BLT_I, + M_BLTL_I, + M_BLTU, + M_BLTUL, + M_BLTU_I, + M_BLTUL_I, + M_BNE, + M_BNE_I, + M_BNEL_I, + M_DABS, + M_DADD_I, + M_DADDU_I, + M_DDIV_3, + M_DDIV_3I, + M_DDIVU_3, + M_DDIVU_3I, + M_DEXT, + M_DINS, + M_DIV_3, + M_DIV_3I, + M_DIVU_3, + M_DIVU_3I, + M_DLA_AB, + M_DLCA_AB, + M_DLI, + M_DMUL, + M_DMUL_I, + M_DMULO, + M_DMULO_I, + M_DMULOU, + M_DMULOU_I, + M_DREM_3, + M_DREM_3I, + M_DREMU_3, + M_DREMU_3I, + M_DSUB_I, + M_DSUBU_I, + M_DSUBU_I_2, + M_J_A, + M_JAL_1, + M_JAL_2, + M_JAL_A, + M_L_DOB, + M_L_DAB, + M_LA_AB, + M_LB_A, + M_LB_AB, + M_LBU_A, + M_LBU_AB, + M_LCA_AB, + M_LD_A, + M_LD_OB, + M_LD_AB, + M_LDC1_AB, + M_LDC2_AB, + M_LDC3_AB, + M_LDL_AB, + M_LDR_AB, + M_LH_A, + M_LH_AB, + M_LHU_A, + M_LHU_AB, + M_LI, + M_LI_D, + M_LI_DD, + M_LI_S, + M_LI_SS, + M_LL_AB, + M_LLD_AB, + M_LS_A, + M_LW_A, + M_LW_AB, + M_LWC0_A, + M_LWC0_AB, + M_LWC1_A, + M_LWC1_AB, + M_LWC2_A, + M_LWC2_AB, + M_LWC3_A, + M_LWC3_AB, + M_LWL_A, + M_LWL_AB, + M_LWR_A, + M_LWR_AB, + M_LWU_AB, + M_MOVE, + M_MUL, + M_MUL_I, + M_MULO, + M_MULO_I, + M_MULOU, + M_MULOU_I, + M_NOR_I, + M_OR_I, + M_REM_3, + M_REM_3I, + M_REMU_3, + M_REMU_3I, + M_DROL, + M_ROL, + M_DROL_I, + M_ROL_I, + M_DROR, + M_ROR, + M_DROR_I, + M_ROR_I, + M_S_DA, + M_S_DOB, + M_S_DAB, + M_S_S, + M_SC_AB, + M_SCD_AB, + M_SD_A, + M_SD_OB, + M_SD_AB, + M_SDC1_AB, + M_SDC2_AB, + M_SDC3_AB, + M_SDL_AB, + M_SDR_AB, + M_SEQ, + M_SEQ_I, + M_SGE, + M_SGE_I, + M_SGEU, + M_SGEU_I, + M_SGT, + M_SGT_I, + M_SGTU, + M_SGTU_I, + M_SLE, + M_SLE_I, + M_SLEU, + M_SLEU_I, + M_SLT_I, + M_SLTU_I, + M_SNE, + M_SNE_I, + M_SB_A, + M_SB_AB, + M_SH_A, + M_SH_AB, + M_SW_A, + M_SW_AB, + M_SWC0_A, + M_SWC0_AB, + M_SWC1_A, + M_SWC1_AB, + M_SWC2_A, + M_SWC2_AB, + M_SWC3_A, + M_SWC3_AB, + M_SWL_A, + M_SWL_AB, + M_SWR_A, + M_SWR_AB, + M_SUB_I, + M_SUBU_I, + M_SUBU_I_2, + M_TEQ_I, + M_TGE_I, + M_TGEU_I, + M_TLT_I, + M_TLTU_I, + M_TNE_I, + M_TRUNCWD, + M_TRUNCWS, + M_ULD, + M_ULD_A, + M_ULH, + M_ULH_A, + M_ULHU, + M_ULHU_A, + M_ULW, + M_ULW_A, + M_USH, + M_USH_A, + M_USW, + M_USW_A, + M_USD, + M_USD_A, + M_XOR_I, + M_COP0, + M_COP1, + M_COP2, + M_COP3, + M_NUM_MACROS +}; + + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Many instructions are short hand for other instructions (i.e., The + jal <register> instruction is short for jalr <register>). */ + +extern const struct mips_opcode mips_builtin_opcodes[]; +extern const int bfd_mips_num_builtin_opcodes; +extern struct mips_opcode *mips_opcodes; +extern int bfd_mips_num_opcodes; +#define NUMOPCODES bfd_mips_num_opcodes + + +/* The rest of this file adds definitions for the mips16 TinyRISC + processor. */ + +/* These are the bitmasks and shift counts used for the different + fields in the instruction formats. Other than OP, no masks are + provided for the fixed portions of an instruction, since they are + not needed. + + The I format uses IMM11. + + The RI format uses RX and IMM8. + + The RR format uses RX, and RY. + + The RRI format uses RX, RY, and IMM5. + + The RRR format uses RX, RY, and RZ. + + The RRI_A format uses RX, RY, and IMM4. + + The SHIFT format uses RX, RY, and SHAMT. + + The I8 format uses IMM8. + + The I8_MOVR32 format uses RY and REGR32. + + The IR_MOV32R format uses REG32R and MOV32Z. + + The I64 format uses IMM8. + + The RI64 format uses RY and IMM5. + */ + +#define MIPS16OP_MASK_OP 0x1f +#define MIPS16OP_SH_OP 11 +#define MIPS16OP_MASK_IMM11 0x7ff +#define MIPS16OP_SH_IMM11 0 +#define MIPS16OP_MASK_RX 0x7 +#define MIPS16OP_SH_RX 8 +#define MIPS16OP_MASK_IMM8 0xff +#define MIPS16OP_SH_IMM8 0 +#define MIPS16OP_MASK_RY 0x7 +#define MIPS16OP_SH_RY 5 +#define MIPS16OP_MASK_IMM5 0x1f +#define MIPS16OP_SH_IMM5 0 +#define MIPS16OP_MASK_RZ 0x7 +#define MIPS16OP_SH_RZ 2 +#define MIPS16OP_MASK_IMM4 0xf +#define MIPS16OP_SH_IMM4 0 +#define MIPS16OP_MASK_REGR32 0x1f +#define MIPS16OP_SH_REGR32 0 +#define MIPS16OP_MASK_REG32R 0x1f +#define MIPS16OP_SH_REG32R 3 +#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) +#define MIPS16OP_MASK_MOVE32Z 0x7 +#define MIPS16OP_SH_MOVE32Z 0 +#define MIPS16OP_MASK_IMM6 0x3f +#define MIPS16OP_SH_IMM6 5 + +/* These are the characters which may appears in the args field of an + instruction. They appear in the order in which the fields appear + when the instruction is used. Commas and parentheses in the args + string are ignored when assembling, and written into the output + when disassembling. + + "y" 3 bit register (MIPS16OP_*_RY) + "x" 3 bit register (MIPS16OP_*_RX) + "z" 3 bit register (MIPS16OP_*_RZ) + "Z" 3 bit register (MIPS16OP_*_MOVE32Z) + "v" 3 bit same register as source and destination (MIPS16OP_*_RX) + "w" 3 bit same register as source and destination (MIPS16OP_*_RY) + "0" zero register ($0) + "S" stack pointer ($sp or $29) + "P" program counter + "R" return address register ($ra or $31) + "X" 5 bit MIPS register (MIPS16OP_*_REGR32) + "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) + "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) + "a" 26 bit jump address + "e" 11 bit extension value + "l" register list for entry instruction + "L" register list for exit instruction + + The remaining codes may be extended. Except as otherwise noted, + the full extended operand is a 16 bit signed value. + "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) + ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) + "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) + "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) + "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) + "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) + "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) + "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) + "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) + "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) + "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) + "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) + "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) + "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) + "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) + "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) + "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) + "q" 11 bit branch address (MIPS16OP_*_IMM11) + "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) + "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) + "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) + */ + +/* For the mips16, we use the same opcode table format and a few of + the same flags. However, most of the flags are different. */ + +/* Modifies the register in MIPS16OP_*_RX. */ +#define MIPS16_INSN_WRITE_X 0x00000001 +/* Modifies the register in MIPS16OP_*_RY. */ +#define MIPS16_INSN_WRITE_Y 0x00000002 +/* Modifies the register in MIPS16OP_*_RZ. */ +#define MIPS16_INSN_WRITE_Z 0x00000004 +/* Modifies the T ($24) register. */ +#define MIPS16_INSN_WRITE_T 0x00000008 +/* Modifies the SP ($29) register. */ +#define MIPS16_INSN_WRITE_SP 0x00000010 +/* Modifies the RA ($31) register. */ +#define MIPS16_INSN_WRITE_31 0x00000020 +/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ +#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 +/* Reads the register in MIPS16OP_*_RX. */ +#define MIPS16_INSN_READ_X 0x00000080 +/* Reads the register in MIPS16OP_*_RY. */ +#define MIPS16_INSN_READ_Y 0x00000100 +/* Reads the register in MIPS16OP_*_MOVE32Z. */ +#define MIPS16_INSN_READ_Z 0x00000200 +/* Reads the T ($24) register. */ +#define MIPS16_INSN_READ_T 0x00000400 +/* Reads the SP ($29) register. */ +#define MIPS16_INSN_READ_SP 0x00000800 +/* Reads the RA ($31) register. */ +#define MIPS16_INSN_READ_31 0x00001000 +/* Reads the program counter. */ +#define MIPS16_INSN_READ_PC 0x00002000 +/* Reads the general purpose register in MIPS16OP_*_REGR32. */ +#define MIPS16_INSN_READ_GPR_X 0x00004000 +/* Is a branch insn. */ +#define MIPS16_INSN_BRANCH 0x00010000 + +/* The following flags have the same value for the mips16 opcode + table: + INSN_UNCOND_BRANCH_DELAY + INSN_COND_BRANCH_DELAY + INSN_COND_BRANCH_LIKELY (never used) + INSN_READ_HI + INSN_READ_LO + INSN_WRITE_HI + INSN_WRITE_LO + INSN_TRAP + INSN_ISA3 + */ + +extern const struct mips_opcode mips16_opcodes[]; +extern const int bfd_mips16_num_opcodes; + +#endif /* _MIPS_H_ */ diff --git a/include/opcode/mmix.h b/include/opcode/mmix.h new file mode 100644 index 000000000..d2aef32bd --- /dev/null +++ b/include/opcode/mmix.h @@ -0,0 +1,186 @@ +/* mmix.h -- Header file for MMIX opcode table + Copyright (C) 2001, 2003 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version 2, +or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We could have just a char*[] table indexed by the register number, but + that would not allow for synonyms. The table is terminated with an + entry with a NULL name. */ +struct mmix_spec_reg +{ + const char *name; + unsigned int number; +}; + +/* General indication of the type of instruction. */ +enum mmix_insn_type + { + mmix_type_pseudo, + mmix_type_normal, + mmix_type_branch, + mmix_type_condbranch, + mmix_type_memaccess_octa, + mmix_type_memaccess_tetra, + mmix_type_memaccess_wyde, + mmix_type_memaccess_byte, + mmix_type_memaccess_block, + mmix_type_jsr + }; + +/* Type of operands an instruction takes. Use when parsing assembly code + and disassembling. */ +enum mmix_operands_type + { + mmix_operands_none = 0, + + /* All operands are registers: "$X,$Y,$Z". */ + mmix_operands_regs, + + /* "$X,YZ", like SETH. */ + mmix_operands_reg_yz, + + /* The regular "$X,$Y,$Z|Z". + The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is + assumed. */ + mmix_operands_regs_z_opt, + + /* The regular "$X,$Y,$Z|Z". */ + mmix_operands_regs_z, + + /* "Address"; only JMP. Zero operands allowed unless GNU syntax. */ + mmix_operands_jmp, + + /* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an + integer. */ + mmix_operands_pushgo, + + /* Two registers or a register and a byte, like FLOT, possibly with + rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z". */ + mmix_operands_roundregs_z, + + /* "X,YZ", POP. Unless GNU syntax, zero or one operand is allowed. */ + mmix_operands_pop, + + /* Two registers, possibly with rounding: "$X,$Z" or + "$X,ROUND_MODE,$Z". */ + mmix_operands_roundregs, + + /* "XYZ", like SYNC. */ + mmix_operands_sync, + + /* "X,$Y,$Z|Z", like SYNCD. */ + mmix_operands_x_regs_z, + + /* "$X,Y,$Z|Z", like NEG and NEGU. The Y field is optional, default 0. */ + mmix_operands_neg, + + /* "$X,Address, like GETA or branches. */ + mmix_operands_regaddr, + + /* "$X|X,Address, like PUSHJ. */ + mmix_operands_pushj, + + /* "$X,spec_reg"; GET. */ + mmix_operands_get, + + /* "spec_reg,$Z|Z"; PUT. */ + mmix_operands_put, + + /* Two registers, "$X,$Y". */ + mmix_operands_set, + + /* "$X,0"; SAVE. */ + mmix_operands_save, + + /* "0,$Z"; UNSAVE. */ + mmix_operands_unsave, + + /* "X,Y,Z"; like SWYM or TRAP. Zero (or 1 if GNU syntax) to three + operands, interpreted as 0; XYZ; X, YZ and X, Y, Z. */ + mmix_operands_xyz_opt, + + /* Just "Z", like RESUME. Unless GNU syntax, the operand can be omitted + and will then be assumed zero. */ + mmix_operands_resume, + + /* These are specials to handle that pseudo-directives are specified + like ordinary insns when being mmixal-compatible. They signify the + specific pseudo-directive rather than the operands type. */ + + /* LOC. */ + mmix_operands_loc, + + /* PREFIX. */ + mmix_operands_prefix, + + /* BYTE. */ + mmix_operands_byte, + + /* WYDE. */ + mmix_operands_wyde, + + /* TETRA. */ + mmix_operands_tetra, + + /* OCTA. */ + mmix_operands_octa, + + /* LOCAL. */ + mmix_operands_local, + + /* BSPEC. */ + mmix_operands_bspec, + + /* ESPEC. */ + mmix_operands_espec, + }; + +struct mmix_opcode + { + const char *name; + unsigned long match; + unsigned long lose; + enum mmix_operands_type operands; + + /* This is used by the disassembly function. */ + enum mmix_insn_type type; + }; + +/* Declare the actual tables. */ +extern const struct mmix_opcode mmix_opcodes[]; + +/* This one is terminated with an entry with a NULL name. */ +extern const struct mmix_spec_reg mmix_spec_regs[]; + +/* Some insn values we use when padding and synthesizing address loads. */ +#define IMM_OFFSET_BIT 1 +#define COND_INV_BIT 0x8 +#define PRED_INV_BIT 0x10 + +#define PUSHGO_INSN_BYTE 0xbe +#define GO_INSN_BYTE 0x9e +#define SETL_INSN_BYTE 0xe3 +#define INCML_INSN_BYTE 0xe6 +#define INCMH_INSN_BYTE 0xe5 +#define INCH_INSN_BYTE 0xe4 +#define SWYM_INSN_BYTE 0xfd +#define JMP_INSN_BYTE 0xf0 + +/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable) + global registers. */ +#define MAX_GREGS 223 diff --git a/include/opcode/mn10200.h b/include/opcode/mn10200.h new file mode 100644 index 000000000..42fa94b0c --- /dev/null +++ b/include/opcode/mn10200.h @@ -0,0 +1,110 @@ +/* mn10200.h -- Header file for Matsushita 10200 opcode table + Copyright 1996, 1997 Free Software Foundation, Inc. + Written by Jeff Law, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef MN10200_H +#define MN10200_H + +/* The opcode table is an array of struct mn10200_opcode. */ + +struct mn10200_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* The format of this opcode. */ + unsigned char format; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct mn10200_opcode mn10200_opcodes[]; +extern const int mn10200_num_opcodes; + + +/* The operands table is an array of struct mn10200_operand. */ + +struct mn10200_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the mn10200_opcodes table. */ + +extern const struct mn10200_operand mn10200_operands[]; + +/* Values defined for the flags field of a struct mn10200_operand. */ +#define MN10200_OPERAND_DREG 0x1 + +#define MN10200_OPERAND_AREG 0x2 + +#define MN10200_OPERAND_PSW 0x4 + +#define MN10200_OPERAND_MDR 0x8 + +#define MN10200_OPERAND_SIGNED 0x10 + +#define MN10200_OPERAND_PROMOTE 0x20 + +#define MN10200_OPERAND_PAREN 0x40 + +#define MN10200_OPERAND_REPEATED 0x80 + +#define MN10200_OPERAND_EXTENDED 0x100 + +#define MN10200_OPERAND_NOCHECK 0x200 + +#define MN10200_OPERAND_PCREL 0x400 + +#define MN10200_OPERAND_MEMADDR 0x800 + +#define MN10200_OPERAND_RELAX 0x1000 + +#define FMT_1 1 +#define FMT_2 2 +#define FMT_3 3 +#define FMT_4 4 +#define FMT_5 5 +#define FMT_6 6 +#define FMT_7 7 +#endif /* MN10200_H */ diff --git a/include/opcode/mn10300.h b/include/opcode/mn10300.h new file mode 100644 index 000000000..bd7faa110 --- /dev/null +++ b/include/opcode/mn10300.h @@ -0,0 +1,169 @@ +/* mn10300.h -- Header file for Matsushita 10300 opcode table + Copyright 1996, 1997, 1998, 1999 Free Software Foundation, Inc. + Written by Jeff Law, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef MN10300_H +#define MN10300_H + +/* The opcode table is an array of struct mn10300_opcode. */ + +#define MN10300_MAX_OPERANDS 8 +struct mn10300_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* A bitmask. For each operand, nonzero if it must not have the same + register specification as all other operands with a nonzero bit in + this flag. ie 0x81 would indicate that operands 7 and 0 must not + match. Note that we count operands from left to right as they appear + in the operands specification below. */ + unsigned int no_match_operands; + + /* The format of this opcode. */ + unsigned char format; + + /* Bitmask indicating what cpu variants this opcode is available on. + We assume mn10300 base opcodes are available everywhere, so we only + have to note opcodes which are available on other variants. */ + unsigned int machine; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[MN10300_MAX_OPERANDS]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct mn10300_opcode mn10300_opcodes[]; +extern const int mn10300_num_opcodes; + + +/* The operands table is an array of struct mn10300_operand. */ + +struct mn10300_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the mn10300_opcodes table. */ + +extern const struct mn10300_operand mn10300_operands[]; + +/* Values defined for the flags field of a struct mn10300_operand. */ +#define MN10300_OPERAND_DREG 0x1 + +#define MN10300_OPERAND_AREG 0x2 + +#define MN10300_OPERAND_SP 0x4 + +#define MN10300_OPERAND_PSW 0x8 + +#define MN10300_OPERAND_MDR 0x10 + +#define MN10300_OPERAND_SIGNED 0x20 + +#define MN10300_OPERAND_PROMOTE 0x40 + +#define MN10300_OPERAND_PAREN 0x80 + +#define MN10300_OPERAND_REPEATED 0x100 + +#define MN10300_OPERAND_EXTENDED 0x200 + +#define MN10300_OPERAND_SPLIT 0x400 + +#define MN10300_OPERAND_REG_LIST 0x800 + +#define MN10300_OPERAND_PCREL 0x1000 + +#define MN10300_OPERAND_MEMADDR 0x2000 + +#define MN10300_OPERAND_RELAX 0x4000 + +#define MN10300_OPERAND_USP 0x8000 + +#define MN10300_OPERAND_SSP 0x10000 + +#define MN10300_OPERAND_MSP 0x20000 + +#define MN10300_OPERAND_PC 0x40000 + +#define MN10300_OPERAND_EPSW 0x80000 + +#define MN10300_OPERAND_RREG 0x100000 + +#define MN10300_OPERAND_XRREG 0x200000 + +#define MN10300_OPERAND_PLUS 0x400000 + +#define MN10300_OPERAND_24BIT 0x800000 + +#define MN10300_OPERAND_FSREG 0x1000000 + +#define MN10300_OPERAND_FDREG 0x2000000 + +#define MN10300_OPERAND_FPCR 0x4000000 + +/* Opcode Formats. */ +#define FMT_S0 1 +#define FMT_S1 2 +#define FMT_S2 3 +#define FMT_S4 4 +#define FMT_S6 5 +#define FMT_D0 6 +#define FMT_D1 7 +#define FMT_D2 8 +#define FMT_D4 9 +#define FMT_D5 10 +#define FMT_D6 11 +#define FMT_D7 12 +#define FMT_D8 13 +#define FMT_D9 14 +#define FMT_D10 15 +#define FMT_D3 16 + +/* Variants of the mn10300 which have additional opcodes. */ +#define MN103 300 +#define AM30 300 + +#define AM33 330 +#define AM33_2 332 + +#endif /* MN10300_H */ diff --git a/include/opcode/msp430.h b/include/opcode/msp430.h new file mode 100644 index 000000000..a59ede215 --- /dev/null +++ b/include/opcode/msp430.h @@ -0,0 +1,216 @@ +/* Opcode table for the TI MSP430 microcontrollers + + Copyright 2002, 2004 Free Software Foundation, Inc. + Contributed by Dmitry Diky <diwil@mail.ru> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef __MSP430_H_ +#define __MSP430_H_ + +struct msp430_operand_s +{ + int ol; /* Operand length words. */ + int am; /* Addr mode. */ + int reg; /* Register. */ + int mode; /* Pperand mode. */ +#define OP_REG 0 +#define OP_EXP 1 +#ifndef DASM_SECTION + expressionS exp; +#endif +}; + +#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ + +struct msp430_opcode_s +{ + char *name; + int fmt; + int insn_opnumb; + int bin_opcode; + int bin_mask; +}; + +#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } + +static struct msp430_opcode_s msp430_opcodes[] = +{ + MSP_INSN (and, 1, 2, 0xf000, 0xf000), + MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), + MSP_INSN (xor, 1, 2, 0xe000, 0xf000), + MSP_INSN (setz, 0, 0, 0xd322, 0xffff), + MSP_INSN (setc, 0, 0, 0xd312, 0xffff), + MSP_INSN (eint, 0, 0, 0xd232, 0xffff), + MSP_INSN (setn, 0, 0, 0xd222, 0xffff), + MSP_INSN (bis, 1, 2, 0xd000, 0xf000), + MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), + MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), + MSP_INSN (dint, 0, 0, 0xc232, 0xffff), + MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), + MSP_INSN (bic, 1, 2, 0xc000, 0xf000), + MSP_INSN (bit, 1, 2, 0xb000, 0xf000), + MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), + MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), + MSP_INSN (tst, 0, 1, 0x9300, 0xff30), + MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), + MSP_INSN (decd, 0, 1, 0x8320, 0xff30), + MSP_INSN (dec, 0, 1, 0x8310, 0xff30), + MSP_INSN (sub, 1, 2, 0x8000, 0xf000), + MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), + MSP_INSN (subc, 1, 2, 0x7000, 0xf000), + MSP_INSN (adc, 0, 1, 0x6300, 0xff30), + MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), + MSP_INSN (addc, 1, 2, 0x6000, 0xf000), + MSP_INSN (incd, 0, 1, 0x5320, 0xff30), + MSP_INSN (inc, 0, 1, 0x5310, 0xff30), + MSP_INSN (rla, 0, 2, 0x5000, 0xf000), + MSP_INSN (add, 1, 2, 0x5000, 0xf000), + MSP_INSN (nop, 0, 0, 0x4303, 0xffff), + MSP_INSN (clr, 0, 1, 0x4300, 0xff30), + MSP_INSN (ret, 0, 0, 0x4130, 0xff30), + MSP_INSN (pop, 0, 1, 0x4130, 0xff30), + MSP_INSN (br, 0, 3, 0x4000, 0xf000), + MSP_INSN (mov, 1, 2, 0x4000, 0xf000), + MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), + MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), + MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), + MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), + MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), + MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), + MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), + MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), + MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), + MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), + MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), + MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), + MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), + MSP_INSN (call, 2, 1, 0x1280, 0xffc0), + MSP_INSN (push, 2, 1, 0x1200, 0xff80), + MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), + MSP_INSN (rra, 2, 1, 0x1100, 0xff80), + MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), + MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), + /* Simple polymorphs. */ + MSP_INSN (beq, 4, 0, 0, 0xffff), + MSP_INSN (bne, 4, 1, 0, 0xffff), + MSP_INSN (blt, 4, 2, 0, 0xffff), + MSP_INSN (bltu, 4, 3, 0, 0xffff), + MSP_INSN (bge, 4, 4, 0, 0xffff), + MSP_INSN (bgeu, 4, 5, 0, 0xffff), + MSP_INSN (bltn, 4, 6, 0, 0xffff), + MSP_INSN (jump, 4, 7, 0, 0xffff), + /* Long polymorphs. */ + MSP_INSN (bgt, 5, 0, 0, 0xffff), + MSP_INSN (bgtu, 5, 1, 0, 0xffff), + MSP_INSN (bleu, 5, 2, 0, 0xffff), + MSP_INSN (ble, 5, 3, 0, 0xffff), + + /* End of instruction set. */ + { NULL, 0, 0, 0, 0 } +}; + +/* GCC uses the some condition codes which we'll + implement as new polymorph instructions. + + COND EXPL SHORT JUMP LONG JUMP + =============================================== + eq == jeq jne +4; br lab + ne != jne jeq +4; br lab + + ltn honours no-overflow flag + ltn < jn jn +2; jmp +4; br lab + + lt < jl jge +4; br lab + ltu < jlo lhs +4; br lab + le <= see below + leu <= see below + + gt > see below + gtu > see below + ge >= jge jl +4; br lab + geu >= jhs jlo +4; br lab + =============================================== + + Therefore, new opcodes are (BranchEQ -> beq; and so on...) + beq,bne,blt,bltn,bltu,bge,bgeu + 'u' means unsigned compares + + Also, we add 'jump' instruction: + jump UNCOND -> jmp br lab + + They will have fmt == 4, and insn_opnumb == number of instruction. */ + +struct rcodes_s +{ + char * name; + int index; /* Corresponding insn_opnumb. */ + int sop; /* Opcode if jump length is short. */ + long lpos; /* Label position. */ + long lop0; /* Opcode 1 _word_ (16 bits). */ + long lop1; /* Opcode second word. */ + long lop2; /* Opcode third word. */ +}; + +#define MSP430_RLC(n,i,sop,o1) \ + {#n, i, sop, 2, (o1 + 2), 0x4010, 0} + +static struct rcodes_s msp430_rcodes[] = +{ + MSP430_RLC (beq, 0, 0x2400, 0x2000), + MSP430_RLC (bne, 1, 0x2000, 0x2400), + MSP430_RLC (blt, 2, 0x3800, 0x3400), + MSP430_RLC (bltu, 3, 0x2800, 0x2c00), + MSP430_RLC (bge, 4, 0x3400, 0x3800), + MSP430_RLC (bgeu, 5, 0x2c00, 0x2800), + {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010}, + {"jump", 7, 0x3c00, 1, 0x4010, 0, 0}, + {0,0,0,0,0,0,0} +}; +#undef MSP430_RLC + + +/* More difficult than above and they have format 5. + + COND EXPL SHORT LONG + ================================================================= + gt > jeq +2; jge label jeq +6; jl +4; br label + gtu > jeq +2; jhs label jeq +6; jlo +4; br label + leu <= jeq label; jlo label jeq +2; jhs +4; br label + le <= jeq label; jl label jeq +2; jge +4; br label + ================================================================= */ + +struct hcodes_s +{ + char * name; + int index; /* Corresponding insn_opnumb. */ + int tlab; /* Number of labels in short mode. */ + int op0; /* Opcode for first word of short jump. */ + int op1; /* Opcode for second word of short jump. */ + int lop0; /* Opcodes for long jump mode. */ + int lop1; + int lop2; +}; + +static struct hcodes_s msp430_hcodes[] = +{ + {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 }, + {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 }, + {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 }, + {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 }, + {0,0,0,0,0,0,0,0} +}; + +#endif diff --git a/include/opcode/np1.h b/include/opcode/np1.h new file mode 100644 index 000000000..c3f7e293f --- /dev/null +++ b/include/opcode/np1.h @@ -0,0 +1,422 @@ +/* Print GOULD NPL instructions for GDB, the GNU debugger. + Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc. + +This file is part of GDB. + +GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +struct gld_opcode +{ + char *name; + unsigned long opcode; + unsigned long mask; + char *args; + int length; +}; + +/* We store four bytes of opcode for all opcodes because that + is the most any of them need. The actual length of an instruction + is always at least 2 bytes, and at most four. The length of the + instruction is based on the opcode. + + The mask component is a mask saying which bits must match + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing characters + that are used to format the arguments to the instruction. */ + +/* Kinds of operands: + r Register in first field + R Register in second field + b Base register in first field + B Base register in second field + v Vector register in first field + V Vector register in first field + A Optional address register (base register) + X Optional index register + I Immediate data (16bits signed) + O Offset field (16bits signed) + h Offset field (15bits signed) + d Offset field (14bits signed) + S Shift count field + + any other characters are printed as is... +*/ + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ +struct gld_opcode gld_opcodes[] = +{ +{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 }, +{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 }, +{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 }, +{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, +{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, +{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, +{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 }, +{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 }, +{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 }, +{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 }, +{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 }, +{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 }, +{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 }, +{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 }, +{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 }, +{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 }, +{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 }, + +{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, +{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, +{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, +{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 }, +{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 }, +{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, +{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 }, +{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 }, +{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, +{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, +{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 }, +{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, +{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 }, + +{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 }, +{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 }, +{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 }, +{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 }, +{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 }, +{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 }, +{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 }, +{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 }, +{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 }, +{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 }, +{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 }, + +{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 }, +{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 }, +{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 }, +{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 }, +{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 }, +{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 }, +{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 }, +{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 }, +{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 }, +{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 }, +{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 }, +{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 }, +{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 }, +{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 }, +{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 }, +{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 }, +{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 }, +{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 }, +{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 }, +{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 }, +{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, +{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 }, +{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, +{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 }, +{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 }, +{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 }, +{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 }, +{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 }, +{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 }, + +{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, +{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, +{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, +{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 }, +{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, +{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 }, +{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, +{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, +{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, +{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 }, + +{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 }, +{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 }, +{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 }, +{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 }, +{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 }, +{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 }, + +{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 }, +{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, +{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, +{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, +{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, +{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, +{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, +{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, +{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, +{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, +{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, +{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 }, +{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 }, +{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 }, +{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 }, +{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 }, + +{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 }, +{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 }, +{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 }, +{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 }, +{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 }, + +{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 }, +{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 }, +{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 }, +{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 }, +{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 }, +{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 }, +{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 }, +{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, + +{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, +{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 }, +{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 }, +{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, +{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 }, +{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, +{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 }, +{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 }, +{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, +{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 }, +{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 }, + +{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 }, +{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 }, +{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 }, +{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 }, +{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 }, +{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 }, +{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 }, +{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 }, +{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 }, +{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 }, + +{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, +{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, +{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, +{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, +{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 }, +{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, +{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, +{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, +{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 }, +{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 }, + +{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 }, +{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 }, +{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 }, +{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 }, +{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 }, +{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 }, +{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 }, +{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 }, +{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 }, +{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 }, +{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 }, +{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 }, +{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 }, +{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 }, + +{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, +{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, +{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, +{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, +{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 }, + +{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 }, +{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 }, +{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 }, +{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 }, +{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 }, + +{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 }, +{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 }, +{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 }, +{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 }, +{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 }, +{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 }, +{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 }, +{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 }, +{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 }, +{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 }, +{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 }, +{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 }, +{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 }, + +{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 }, +{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 }, +{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 }, +{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 }, +{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 }, +{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 }, +{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 }, +{ "exr", 0xf8070000, 0xfc0f0000, "", 4 }, +{ "halt", 0x00000000, 0xfc0f0000, "", 2 }, +{ "wait", 0x00010000, 0xfc0f0000, "", 2 }, +{ "nop", 0x00020000, 0xfc0f0000, "", 2 }, +{ "eiae", 0x00030000, 0xfc0f0000, "", 2 }, +{ "efae", 0x000d0000, 0xfc0f0000, "", 2 }, +{ "diae", 0x000e0000, 0xfc0f0000, "", 2 }, +{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 }, +{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 }, +{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 }, +{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 }, +{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 }, +{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 }, +{ "attnio", 0x00050000, 0xfc0f0000, "", 2 }, +{ "fudit", 0x28080000, 0xfc0f0000, "", 2 }, +{ "break", 0x28090000, 0xfc0f0000, "", 2 }, +{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 }, +{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 }, +{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 }, +{ "block", 0x04060000, 0xfc0f0000, "", 2 }, +{ "unblock", 0x04070000, 0xfc0f0000, "", 2 }, +{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 }, +{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 }, +{ "fq", 0x04080000, 0xfc0f0000, "r", 2 }, +{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 }, +{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 }, +{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 }, +{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 }, +{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 }, +{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 }, +{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 }, +{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 }, +{ "grun", 0x0c040000, 0xfc0f0000, "", 2 }, +{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, +{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, + +{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 }, +{ "trver", 0x28070000, 0xfc0f0000, "r", 2 }, +{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 }, + +{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 }, +{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 }, +{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 }, +{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 }, +{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 }, +{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 }, +{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 }, +{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 }, +{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 }, +}; + +int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); + +struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / + sizeof(gld_opcodes[0]); diff --git a/include/opcode/ns32k.h b/include/opcode/ns32k.h new file mode 100644 index 000000000..68a0dbaa4 --- /dev/null +++ b/include/opcode/ns32k.h @@ -0,0 +1,487 @@ +/* ns32k-opcode.h -- Opcode table for National Semi 32k processor + Copyright 1987, 1991, 1994, 2002 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler. + +GAS is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#ifdef SEQUENT_COMPATABILITY +#define DEF_MODEC 20 +#define DEF_MODEL 21 +#endif + +#ifndef DEF_MODEC +#define DEF_MODEC 20 +#endif + +#ifndef DEF_MODEL +#define DEF_MODEL 20 +#endif +/* + After deciding the instruction entry (via hash.c) the instruction parser + will try to match the operands after the instruction to the required set + given in the entry operandfield. Every operand will result in a change in + the opcode or the addition of data to the opcode. + The operands in the source instruction are checked for inconsistent + semantics. + + F : 32 bit float general form + L : 64 bit float " + B : byte " + W : word " + D : double-word " + A : double-word gen-address-form ie no regs, no immediate + I : integer writeable gen int except immediate (A + reg) + Z : floating writeable gen float except immediate (Z + freg) + d : displacement + b : displacement - pc relative addressing acb + p : displacement - pc relative addressing br bcond bsr cxp + q : quick + i : immediate (8 bits) + This is not a standard ns32k operandtype, it is used to build + instructions like svc arg1,arg2 + Svc is the instruction SuperVisorCall and is sometimes used to + call OS-routines from usermode. Some args might be handy! + r : register number (3 bits) + O : setcfg instruction optionslist + C : cinv instruction optionslist + S : stringinstruction optionslist + U : registerlist save,enter + u : registerlist restore,exit + M : mmu register + P : cpu register + g : 3:rd operand of inss or exts instruction + G : 4:th operand of inss or exts instruction + Those operands are encoded in the same byte. + This byte is placed last in the instruction. + f : operand of sfsr + H : sequent-hack for bsr (Warning) + +column 1 instructions + 2 number of bits in opcode. + 3 number of bits in opcode explicitly + determined by the instruction type. + 4 opcodeseed, the number we build our opcode + from. + 5 operandtypes, used by operandparser. + 6 size in bytes of immediate +*/ +struct ns32k_opcode { + const char *name; + unsigned char opcode_id_size; /* not used by the assembler */ + unsigned char opcode_size; + unsigned long opcode_seed; + const char *operands; + unsigned char im_size; /* not used by dissassembler */ + const char *default_args; /* default to those args when none given */ + char default_modec; /* default to this addr-mode when ambigous + ie when the argument of a general addr-mode + is a plain constant */ + char default_model; /* is a plain label */ +}; + +#ifdef comment +/* This section was from the gdb version of this file. */ + +#ifndef ns32k_opcodeT +#define ns32k_opcodeT int +#endif /* no ns32k_opcodeT */ + +struct not_wot /* ns32k opcode table: wot to do with this */ + /* particular opcode */ +{ + int obits; /* number of opcode bits */ + int ibits; /* number of instruction bits */ + ns32k_opcodeT code; /* op-code (may be > 8 bits!) */ + const char *args; /* how to compile said opcode */ +}; + +struct not /* ns32k opcode text */ +{ + const char *name; /* opcode name: lowercase string [key] */ + struct not_wot detail; /* rest of opcode table [datum] */ +}; + +/* Instructions look like this: + + basic instruction--1, 2, or 3 bytes + index byte for operand A, if operand A is indexed--1 byte + index byte for operand B, if operand B is indexed--1 byte + addressing extension for operand A + addressing extension for operand B + implied operands + + Operand A is the operand listed first in the following opcode table. + Operand B is the operand listed second in the following opcode table. + All instructions have at most 2 general operands, so this is enough. + The implied operands are associated with operands other than A and B. + + Each operand has a digit and a letter. + + The digit gives the position in the assembly language. The letter, + one of the following, tells us what kind of operand it is. */ + +/* F : 32 bit float + * L : 64 bit float + * B : byte + * W : word + * D : double-word + * I : integer not immediate + * Z : floating not immediate + * d : displacement + * q : quick + * i : immediate (8 bits) + * r : register number (3 bits) + * p : displacement - pc relative addressing +*/ + + +#endif /* comment */ + +static const struct ns32k_opcode ns32k_opcodes[]= +{ + { "absf", 14,24, 0x35be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "absl", 14,24, 0x34be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "absb", 14,24, 0x304e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "absw", 14,24, 0x314e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "absd", 14,24, 0x334e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "acbb", 7,16, 0x4c, "2I1q3p", 1, "", DEF_MODEC,DEF_MODEL }, + { "acbw", 7,16, 0x4d, "2I1q3p", 2, "", DEF_MODEC,DEF_MODEL }, + { "acbd", 7,16, 0x4f, "2I1q3p", 4, "", DEF_MODEC,DEF_MODEL }, + { "addf", 14,24, 0x01be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "addl", 14,24, 0x00be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "addb", 6,16, 0x00, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addw", 6,16, 0x01, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addd", 6,16, 0x03, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addcb", 6,16, 0x10, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addcw", 6,16, 0x11, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addcd", 6,16, 0x13, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addpb", 14,24, 0x3c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addpw", 14,24, 0x3d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addpd", 14,24, 0x3f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addqb", 7,16, 0x0c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "addqw", 7,16, 0x0d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "addqd", 7,16, 0x0f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "addr", 6,16, 0x27, "1A2I", 4, "", 21,21 }, + { "adjspb", 11,16, 0x057c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "adjspw", 11,16, 0x057d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "adjspd", 11,16, 0x057f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "andb", 6,16, 0x28, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "andw", 6,16, 0x29, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "andd", 6,16, 0x2b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "ashb", 14,24, 0x044e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ashw", 14,24, 0x054e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ashd", 14,24, 0x074e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "beq", 8,8, 0x0a, "1p", 0, "", 21,21 }, + { "bne", 8,8, 0x1a, "1p", 0, "", 21,21 }, + { "bcs", 8,8, 0x2a, "1p", 0, "", 21,21 }, + { "bcc", 8,8, 0x3a, "1p", 0, "", 21,21 }, + { "bhi", 8,8, 0x4a, "1p", 0, "", 21,21 }, + { "bls", 8,8, 0x5a, "1p", 0, "", 21,21 }, + { "bgt", 8,8, 0x6a, "1p", 0, "", 21,21 }, + { "ble", 8,8, 0x7a, "1p", 0, "", 21,21 }, + { "bfs", 8,8, 0x8a, "1p", 0, "", 21,21 }, + { "bfc", 8,8, 0x9a, "1p", 0, "", 21,21 }, + { "blo", 8,8, 0xaa, "1p", 0, "", 21,21 }, + { "bhs", 8,8, 0xba, "1p", 0, "", 21,21 }, + { "blt", 8,8, 0xca, "1p", 0, "", 21,21 }, + { "bge", 8,8, 0xda, "1p", 0, "", 21,21 }, + { "but", 8,8, 0xea, "1p", 0, "", 21,21 }, + { "buf", 8,8, 0xfa, "1p", 0, "", 21,21 }, + { "bicb", 6,16, 0x08, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "bicw", 6,16, 0x09, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "bicd", 6,16, 0x0b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "bicpsrb", 11,16, 0x17c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "bicpsrw", 11,16, 0x17d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "bispsrb", 11,16, 0x37c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "bispsrw", 11,16, 0x37d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "bpt", 8,8, 0xf2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "br", 8,8, 0xea, "1p", 0, "", 21,21 }, +#ifdef SEQUENT_COMPATABILITY + { "bsr", 8,8, 0x02, "1H", 0, "", 21,21 }, +#else + { "bsr", 8,8, 0x02, "1p", 0, "", 21,21 }, +#endif + { "caseb", 11,16, 0x77c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "casew", 11,16, 0x77d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "cased", 11,16, 0x77f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "cbitb", 14,24, 0x084e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "cbitw", 14,24, 0x094e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "cbitd", 14,24, 0x0b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "cbitib", 14,24, 0x0c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "cbitiw", 14,24, 0x0d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "cbitid", 14,24, 0x0f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "checkb", 11,24, 0x0ee, "2A3B1r", 1, "", DEF_MODEC,DEF_MODEL }, + { "checkw", 11,24, 0x1ee, "2A3W1r", 2, "", DEF_MODEC,DEF_MODEL }, + { "checkd", 11,24, 0x3ee, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "cinv", 14,24, 0x271e, "2D1C", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpf", 14,24, 0x09be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpl", 14,24, 0x08be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "cmpb", 6,16, 0x04, "1B2B", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpw", 6,16, 0x05, "1W2W", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpd", 6,16, 0x07, "1D2D", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpmb", 14,24, 0x04ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpmw", 14,24, 0x05ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpmd", 14,24, 0x07ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpqb", 7,16, 0x1c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpqw", 7,16, 0x1d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpqd", 7,16, 0x1f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpsb", 16,24, 0x040e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpsw", 16,24, 0x050e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpsd", 16,24, 0x070e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpst", 16,24, 0x840e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "comb", 14,24, 0x344e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "comw", 14,24, 0x354e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "comd", 14,24, 0x374e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "cvtp", 11,24, 0x036e, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "cxp", 8,8, 0x22, "1p", 0, "", 21,21 }, + { "cxpd", 11,16, 0x07f, "1A", 4, "", DEF_MODEC,DEF_MODEL }, + { "deib", 14,24, 0x2cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "deiw", 14,24, 0x2dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "deid", 14,24, 0x2fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "dia", 8,8, 0xc2, "", 1, "", DEF_MODEC,DEF_MODEL }, + { "divf", 14,24, 0x21be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "divl", 14,24, 0x20be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "divb", 14,24, 0x3cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "divw", 14,24, 0x3dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "divd", 14,24, 0x3fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "enter", 8,8, 0x82, "1U2d", 0, "", DEF_MODEC,DEF_MODEL }, + { "exit", 8,8, 0x92, "1u", 0, "", DEF_MODEC,DEF_MODEL }, + { "extb", 11,24, 0x02e, "2I3B1r4d", 1, "", DEF_MODEC,DEF_MODEL }, + { "extw", 11,24, 0x12e, "2I3W1r4d", 2, "", DEF_MODEC,DEF_MODEL }, + { "extd", 11,24, 0x32e, "2I3D1r4d", 4, "", DEF_MODEC,DEF_MODEL }, + { "extsb", 14,24, 0x0cce, "1I2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, + { "extsw", 14,24, 0x0dce, "1I2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, + { "extsd", 14,24, 0x0fce, "1I2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, + { "ffsb", 14,24, 0x046e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ffsw", 14,24, 0x056e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ffsd", 14,24, 0x076e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "flag", 8,8, 0xd2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "floorfb", 14,24, 0x3c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorfw", 14,24, 0x3d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorfd", 14,24, 0x3f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorlb", 14,24, 0x383e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "floorlw", 14,24, 0x393e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "floorld", 14,24, 0x3b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "ibitb", 14,24, 0x384e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ibitw", 14,24, 0x394e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ibitd", 14,24, 0x3b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "indexb", 11,24, 0x42e, "2B3B1r", 1, "", DEF_MODEC,DEF_MODEL }, + { "indexw", 11,24, 0x52e, "2W3W1r", 2, "", DEF_MODEC,DEF_MODEL }, + { "indexd", 11,24, 0x72e, "2D3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "insb", 11,24, 0x0ae, "2B3I1r4d", 1, "", DEF_MODEC,DEF_MODEL }, + { "insw", 11,24, 0x1ae, "2W3I1r4d", 2, "", DEF_MODEC,DEF_MODEL }, + { "insd", 11,24, 0x3ae, "2D3I1r4d", 4, "", DEF_MODEC,DEF_MODEL }, + { "inssb", 14,24, 0x08ce, "1B2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, + { "inssw", 14,24, 0x09ce, "1W2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, + { "inssd", 14,24, 0x0bce, "1D2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, + { "jsr", 11,16, 0x67f, "1A", 4, "", 21,21 }, + { "jump", 11,16, 0x27f, "1A", 4, "", 21,21 }, + { "lfsr", 19,24, 0x00f3e,"1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "lmr", 15,24, 0x0b1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL }, + { "lprb", 7,16, 0x6c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL }, + { "lprw", 7,16, 0x6d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL }, + { "lprd", 7,16, 0x6f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL }, + { "lshb", 14,24, 0x144e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "lshw", 14,24, 0x154e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "lshd", 14,24, 0x174e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "meib", 14,24, 0x24ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "meiw", 14,24, 0x25ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "meid", 14,24, 0x27ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "modb", 14,24, 0x38ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "modw", 14,24, 0x39ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "modd", 14,24, 0x3bce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "movf", 14,24, 0x05be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movl", 14,24, 0x04be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "movb", 6,16, 0x14, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movw", 6,16, 0x15, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movd", 6,16, 0x17, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "movbf", 14,24, 0x043e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, + { "movwf", 14,24, 0x053e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, + { "movdf", 14,24, 0x073e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movbl", 14,24, 0x003e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, + { "movwl", 14,24, 0x013e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, + { "movdl", 14,24, 0x033e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movfl", 14,24, 0x1b3e, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movlf", 14,24, 0x163e, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "movmb", 14,24, 0x00ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, + { "movmw", 14,24, 0x01ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, + { "movmd", 14,24, 0x03ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, + { "movqb", 7,16, 0x5c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "movqw", 7,16, 0x5d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "movqd", 7,16, 0x5f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "movsb", 16,24, 0x000e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsw", 16,24, 0x010e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsd", 16,24, 0x030e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movst", 16,24, 0x800e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsub", 14,24, 0x0cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "movsuw", 14,24, 0x0dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "movsud", 14,24, 0x0fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "movusb", 14,24, 0x1cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "movusw", 14,24, 0x1dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "movusd", 14,24, 0x1fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "movxbd", 14,24, 0x1cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movxwd", 14,24, 0x1dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movxbw", 14,24, 0x10ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movzbd", 14,24, 0x18ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movzwd", 14,24, 0x19ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movzbw", 14,24, 0x14ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "mulf", 14,24, 0x31be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "mull", 14,24, 0x30be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "mulb", 14,24, 0x20ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "mulw", 14,24, 0x21ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "muld", 14,24, 0x23ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "negf", 14,24, 0x15be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "negl", 14,24, 0x14be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "negb", 14,24, 0x204e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "negw", 14,24, 0x214e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "negd", 14,24, 0x234e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "nop", 8,8, 0xa2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "notb", 14,24, 0x244e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "notw", 14,24, 0x254e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "notd", 14,24, 0x274e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "orb", 6,16, 0x18, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "orw", 6,16, 0x19, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ord", 6,16, 0x1b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "quob", 14,24, 0x30ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "quow", 14,24, 0x31ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "quod", 14,24, 0x33ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "rdval", 19,24, 0x0031e,"1A", 4, "", DEF_MODEC,DEF_MODEL }, + { "remb", 14,24, 0x34ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "remw", 14,24, 0x35ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "remd", 14,24, 0x37ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "restore", 8,8, 0x72, "1u", 0, "", DEF_MODEC,DEF_MODEL }, + { "ret", 8,8, 0x12, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "reti", 8,8, 0x52, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "rett", 8,8, 0x42, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "rotb", 14,24, 0x004e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "rotw", 14,24, 0x014e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "rotd", 14,24, 0x034e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "roundfb", 14,24, 0x243e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundfw", 14,24, 0x253e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundfd", 14,24, 0x273e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundlb", 14,24, 0x203e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "roundlw", 14,24, 0x213e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "roundld", 14,24, 0x233e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "rxp", 8,8, 0x32, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqb", 11,16, 0x3c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqw", 11,16, 0x3d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqd", 11,16, 0x3f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sneb", 11,16, 0xbc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "snew", 11,16, 0xbd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sned", 11,16, 0xbf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsb", 11,16, 0x13c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsw", 11,16, 0x13d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsd", 11,16, 0x13f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccb", 11,16, 0x1bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccw", 11,16, 0x1bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccd", 11,16, 0x1bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "shib", 11,16, 0x23c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "shiw", 11,16, 0x23d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "shid", 11,16, 0x23f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsb", 11,16, 0x2bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsw", 11,16, 0x2bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsd", 11,16, 0x2bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtb", 11,16, 0x33c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtw", 11,16, 0x33d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtd", 11,16, 0x33f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sleb", 11,16, 0x3bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slew", 11,16, 0x3bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sled", 11,16, 0x3bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsb", 11,16, 0x43c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsw", 11,16, 0x43d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsd", 11,16, 0x43f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcb", 11,16, 0x4bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcw", 11,16, 0x4bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcd", 11,16, 0x4bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "slob", 11,16, 0x53c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slow", 11,16, 0x53d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "slod", 11,16, 0x53f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsb", 11,16, 0x5bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsw", 11,16, 0x5bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsd", 11,16, 0x5bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltb", 11,16, 0x63c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltw", 11,16, 0x63d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltd", 11,16, 0x63f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgeb", 11,16, 0x6bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgew", 11,16, 0x6bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sged", 11,16, 0x6bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutb", 11,16, 0x73c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutw", 11,16, 0x73d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutd", 11,16, 0x73f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufb", 11,16, 0x7bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufw", 11,16, 0x7bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufd", 11,16, 0x7bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "save", 8,8, 0x62, "1U", 0, "", DEF_MODEC,DEF_MODEL }, + { "sbitb", 14,24, 0x184e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "sbitw", 14,24, 0x194e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "sbitd", 14,24, 0x1b4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "sbitib", 14,24, 0x1c4e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "sbitiw", 14,24, 0x1d4e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "sbitid", 14,24, 0x1f4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "setcfg", 15,24, 0x0b0e, "1O", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsr", 14,24, 0x373e, "1f", 0, "", DEF_MODEC,DEF_MODEL }, + { "skpsb", 16,24, 0x0c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpsw", 16,24, 0x0d0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpsd", 16,24, 0x0f0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpst", 16,24, 0x8c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "smr", 15,24, 0x0f1e, "2I1M", 4, "", DEF_MODEC,DEF_MODEL }, + { "sprb", 7,16, 0x2c, "2I1P", 1, "", DEF_MODEC,DEF_MODEL }, + { "sprw", 7,16, 0x2d, "2I1P", 2, "", DEF_MODEC,DEF_MODEL }, + { "sprd", 7,16, 0x2f, "2I1P", 4, "", DEF_MODEC,DEF_MODEL }, + { "subf", 14,24, 0x11be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "subl", 14,24, 0x10be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "subb", 6,16, 0x20, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subw", 6,16, 0x21, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subd", 6,16, 0x23, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "subcb", 6,16, 0x30, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subcw", 6,16, 0x31, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subcd", 6,16, 0x33, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "subpb", 14,24, 0x2c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subpw", 14,24, 0x2d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subpd", 14,24, 0x2f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, +#ifdef NS32K_SVC_IMMED_OPERANDS + { "svc", 8,8, 0xe2, "2i1i", 1, "", DEF_MODEC,DEF_MODEL }, /* not really, but some unix uses it */ +#else + { "svc", 8,8, 0xe2, "", 0, "", DEF_MODEC,DEF_MODEL }, +#endif + { "tbitb", 6,16, 0x34, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "tbitw", 6,16, 0x35, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "tbitd", 6,16, 0x37, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfb", 14,24, 0x2c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfw", 14,24, 0x2d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfd", 14,24, 0x2f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "trunclb", 14,24, 0x283e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "trunclw", 14,24, 0x293e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "truncld", 14,24, 0x2b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "wait", 8,8, 0xb2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "wrval", 19,24, 0x0071e,"1A", 0, "", DEF_MODEC,DEF_MODEL }, + { "xorb", 6,16, 0x38, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "xorw", 6,16, 0x39, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "xord", 6,16, 0x3b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "dotf", 14,24, 0x0dfe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "dotl", 14,24, 0x0cfe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "logbf", 14,24, 0x15fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "logbl", 14,24, 0x14fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "polyf", 14,24, 0x09fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "polyl", 14,24, 0x08fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "scalbf", 14,24, 0x11fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "scalbl", 14,24, 0x10fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, +}; + +#define MAX_ARGS 4 +#define ARG_LEN 50 + diff --git a/include/opcode/or32.h b/include/opcode/or32.h new file mode 100644 index 000000000..d72b9bda3 --- /dev/null +++ b/include/opcode/or32.h @@ -0,0 +1,180 @@ +/* Table of opcodes for the OpenRISC 1000 ISA. + Copyright 2002, 2003 Free Software Foundation, Inc. + Contributed by Damjan Lampret (lampret@opencores.org). + + This file is part of or1k_gen_isa, or1ksim, GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We treat all letters the same in encode/decode routines so + we need to assign some characteristics to them like signess etc. */ + +#ifndef OR32_H_ISA +#define OR32_H_ISA + +#define NUM_UNSIGNED (0) +#define NUM_SIGNED (1) + +#define MAX_GPRS 32 +#define PAGE_SIZE 4096 +#undef __HALF_WORD_INSN__ + +#define OPERAND_DELIM (',') + +#define OR32_IF_DELAY (1) +#define OR32_W_FLAG (2) +#define OR32_R_FLAG (4) + +struct or32_letter +{ + char letter; + int sign; + /* int reloc; relocation per letter ?? */ +}; + +/* Main instruction specification array. */ +struct or32_opcode +{ + /* Name of the instruction. */ + char *name; + + /* A string of characters which describe the operands. + Valid characters are: + ,() Itself. Characters appears in the assembly code. + rA Register operand. + rB Register operand. + rD Register operand. + I An immediate operand, range -32768 to 32767. + J An immediate operand, range . (unused) + K An immediate operand, range 0 to 65535. + L An immediate operand, range 0 to 63. + M An immediate operand, range . (unused) + N An immediate operand, range -33554432 to 33554431. + O An immediate operand, range . (unused). */ + char *args; + + /* Opcode and operand encoding. */ + char *encoding; + void (*exec) (void); + unsigned int flags; +}; + +#define OPTYPE_LAST (0x80000000) +#define OPTYPE_OP (0x40000000) +#define OPTYPE_REG (0x20000000) +#define OPTYPE_SIG (0x10000000) +#define OPTYPE_DIS (0x08000000) +#define OPTYPE_DST (0x04000000) +#define OPTYPE_SBIT (0x00001F00) +#define OPTYPE_SHR (0x0000001F) +#define OPTYPE_SBIT_SHR (8) + +/* MM: Data how to decode operands. */ +extern struct insn_op_struct +{ + unsigned long type; + unsigned long data; +} **op_start; + +#ifdef HAS_EXECUTION +extern void l_invalid (void); +extern void l_sfne (void); +extern void l_bf (void); +extern void l_add (void); +extern void l_sw (void); +extern void l_sb (void); +extern void l_sh (void); +extern void l_lwz (void); +extern void l_lbs (void); +extern void l_lbz (void); +extern void l_lhs (void); +extern void l_lhz (void); +extern void l_movhi (void); +extern void l_and (void); +extern void l_or (void); +extern void l_xor (void); +extern void l_sub (void); +extern void l_mul (void); +extern void l_div (void); +extern void l_divu (void); +extern void l_sll (void); +extern void l_sra (void); +extern void l_srl (void); +extern void l_j (void); +extern void l_jal (void); +extern void l_jalr (void); +extern void l_jr (void); +extern void l_rfe (void); +extern void l_nop (void); +extern void l_bnf (void); +extern void l_sfeq (void); +extern void l_sfgts (void); +extern void l_sfges (void); +extern void l_sflts (void); +extern void l_sfles (void); +extern void l_sfgtu (void); +extern void l_sfgeu (void); +extern void l_sfltu (void); +extern void l_sfleu (void); +extern void l_mtspr (void); +extern void l_mfspr (void); +extern void l_sys (void); +extern void l_trap (void); /* CZ 21/06/01. */ +extern void l_macrc (void); +extern void l_mac (void); +extern void l_msb (void); +extern void l_invalid (void); +extern void l_cust1 (void); +extern void l_cust2 (void); +extern void l_cust3 (void); +extern void l_cust4 (void); +#endif +extern void l_none (void); + +extern const struct or32_letter or32_letters[]; + +extern const struct or32_opcode or32_opcodes[]; + +extern const unsigned int or32_num_opcodes; + +/* Calculates instruction length in bytes. Always 4 for OR32. */ +extern int insn_len (int); + +/* Is individual insn's operand signed or unsigned? */ +extern int letter_signed (char); + +/* Number of letters in the individual lettered operand. */ +extern int letter_range (char); + +/* MM: Returns index of given instruction name. */ +extern int insn_index (char *); + +/* MM: Returns instruction name from index. */ +extern const char *insn_name (int); + +/* MM: Constructs new FSM, based on or32_opcodes. */ +extern void build_automata (void); + +/* MM: Destructs FSM. */ +extern void destruct_automata (void); + +/* MM: Decodes instruction using FSM. Call build_automata first. */ +extern int insn_decode (unsigned int); + +/* Disassemble one instruction from insn to disassemble. + Return the size of the instruction. */ +int disassemble_insn (unsigned long); + +#endif diff --git a/include/opcode/pdp11.h b/include/opcode/pdp11.h new file mode 100644 index 000000000..228c221fc --- /dev/null +++ b/include/opcode/pdp11.h @@ -0,0 +1,85 @@ +/* PDP-11 opcde list. + Copyright 2001, 2002 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* + * PDP-11 opcode types. + */ + +#define PDP11_OPCODE_NO_OPS 0 +#define PDP11_OPCODE_REG 1 /* register */ +#define PDP11_OPCODE_OP 2 /* generic operand */ +#define PDP11_OPCODE_REG_OP 3 /* register and generic operand */ +#define PDP11_OPCODE_REG_OP_REV 4 /* register and generic operand, + reversed syntax */ +#define PDP11_OPCODE_AC_FOP 5 /* fpu accumulator and generic float + operand */ +#define PDP11_OPCODE_OP_OP 6 /* two generic operands */ +#define PDP11_OPCODE_DISPL 7 /* pc-relative displacement */ +#define PDP11_OPCODE_REG_DISPL 8 /* redister and pc-relative + displacement */ +#define PDP11_OPCODE_IMM8 9 /* 8-bit immediate */ +#define PDP11_OPCODE_IMM6 10 /* 6-bit immediate */ +#define PDP11_OPCODE_IMM3 11 /* 3-bit immediate */ +#define PDP11_OPCODE_ILLEGAL 12 /* illegal instruction */ +#define PDP11_OPCODE_FOP_AC 13 /* generic float argument, then fpu + accumulator */ +#define PDP11_OPCODE_FOP 14 /* generic float operand */ +#define PDP11_OPCODE_AC_OP 15 /* fpu accumulator and generic int + operand */ +#define PDP11_OPCODE_OP_AC 16 /* generic int argument, then fpu + accumulator */ + +/* + * PDP-11 instruction set extensions. + * + * Please keep the numbers low, as they are used as indices into + * an array. + */ + +#define PDP11_NONE 0 /* not in instruction set */ +#define PDP11_BASIC 1 /* basic instruction set (11/20 etc) */ +#define PDP11_CSM 2 /* commercial instruction set */ +#define PDP11_CIS 3 /* commercial instruction set */ +#define PDP11_EIS 4 /* extended instruction set (11/45 etc) */ +#define PDP11_FIS 5 /* KEV11 floating-point instructions */ +#define PDP11_FPP 6 /* FP-11 floating-point instructions */ +#define PDP11_LEIS 7 /* limited extended instruction set + (11/40 etc) */ +#define PDP11_MFPT 8 /* move from processor type */ +#define PDP11_MPROC 9 /* multiprocessor instructions: tstset, + wrtlck */ +#define PDP11_MXPS 10 /* move from/to processor status */ +#define PDP11_SPL 11 /* set priority level */ +#define PDP11_UCODE 12 /* microcode instructions: ldub, med, xfc */ +#define PDP11_EXT_NUM 13 /* total number of extension types */ + +struct pdp11_opcode +{ + const char *name; + int opcode; + int mask; + int type; + int extension; +}; + +extern const struct pdp11_opcode pdp11_opcodes[]; +extern const struct pdp11_opcode pdp11_aliases[]; +extern const int pdp11_num_opcodes, pdp11_num_aliases; + +/* end of pdp11.h */ diff --git a/include/opcode/pj.h b/include/opcode/pj.h new file mode 100644 index 000000000..f9e44dbef --- /dev/null +++ b/include/opcode/pj.h @@ -0,0 +1,49 @@ +/* Definitions for decoding the picoJava opcode table. + Copyright 1999, 2002, 2003 Free Software Foundation, Inc. + Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* Names used to describe the type of instruction arguments, used by + the assembler and disassembler. Attributes are encoded in various fields. */ + +/* reloc size pcrel uns */ +#define O_N 0 +#define O_16 (1<<4 | 2 | (0<<6) | (0<<3)) +#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3)) +#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3)) +#define O_8 (3<<4 | 1 | (0<<6) | (0<<3)) +#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3)) +#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3)) +#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3)) +#define O_32 (6<<4 | 4 | (0<<6) | (0<<3)) + +#define ASIZE(x) ((x) & 0x7) +#define PCREL(x) (!!((x) & (1<<6))) +#define UNS(x) (!!((x) & (1<<3))) + + +typedef struct pj_opc_info_t +{ + short opcode; + short opcode_next; + char len; + unsigned char arg[2]; + union { + const char *name; + void (*func) (struct pj_opc_info_t *, char *); + } u; +} pj_opc_info_t; diff --git a/include/opcode/pn.h b/include/opcode/pn.h new file mode 100644 index 000000000..8c427a2dd --- /dev/null +++ b/include/opcode/pn.h @@ -0,0 +1,282 @@ +/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. + Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc. + +This file is part of GDB. + +GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +struct gld_opcode +{ + char *name; + unsigned long opcode; + unsigned long mask; + char *args; + int length; +}; + +/* We store four bytes of opcode for all opcodes because that + is the most any of them need. The actual length of an instruction + is always at least 2 bytes, and at most four. The length of the + instruction is based on the opcode. + + The mask component is a mask saying which bits must match + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing characters + that are used to format the arguments to the instruction. */ + +/* Kinds of operands: + r Register in first field + R Register in second field + b Base register in first field + B Base register in second field + v Vector register in first field + V Vector register in first field + A Optional address register (base register) + X Optional index register + I Immediate data (16bits signed) + O Offset field (16bits signed) + h Offset field (15bits signed) + d Offset field (14bits signed) + S Shift count field + + any other characters are printed as is... +*/ + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ +struct gld_opcode gld_opcodes[] = +{ +{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 }, +{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 }, +{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 }, +{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, +{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 }, +{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, +{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, +{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, +{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 }, +{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 }, +{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, +{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, +{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, +{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, +{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 }, +{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 }, +{ "bei", 0x00060000, 0xffff0000, "", 2 }, +{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 }, +{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 }, +{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 }, +{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 }, +{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 }, +{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 }, +{ "bsub", 0x5c080000, 0xff8f0000, "", 2 }, +{ "bsubm", 0x28080000, 0xfc080000, "", 4 }, +{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 }, +{ "call", 0x28080000, 0xfc0f0000, "", 2 }, +{ "callm", 0x5c080000, 0xff880000, "", 4 }, +{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, +{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, +{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, +{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 }, +{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, +{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 }, +{ "cea", 0x000f0000, 0xffff0000, "", 2 }, +{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 }, +{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 }, +{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, +{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, +{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, +{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, +{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 }, +{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 }, +{ "dae", 0x000e0000, 0xffff0000, "", 2 }, +{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 }, +{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 }, +{ "di", 0xfc010000, 0xfc07ffff, "I", 4 }, +{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 }, +{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, +{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 }, +{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 }, +{ "eae", 0x00080000, 0xffff0000, "", 2 }, +{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 }, +{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 }, +{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 }, +{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, +{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, +{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, +{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 }, +{ "es", 0x00040000, 0xfc7f0000, "r", 2 }, +{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 }, +{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 }, +{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 }, +{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, +{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, +{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, +{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, +{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 }, +{ "halt", 0x00000000, 0xffff0000, "", 2 }, +{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 }, +{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 }, +{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 }, +{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 }, +{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 }, +{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 }, +{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 }, +{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 }, +{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 }, +{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, +{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, +{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 }, +{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, +{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, +{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, +{ "nop", 0x00020000, 0xffff0000, "", 2 }, +{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 }, +{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 }, +{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 }, +{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, +{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 }, +{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 }, +{ "return", 0x280e0000, 0xfc7f0000, "", 2 }, +{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 }, +{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 }, +{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 }, +{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 }, +{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 }, +{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 }, +{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 }, +{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, +{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 }, +{ "sea", 0x000d0000, 0xffff0000, "", 2 }, +{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 }, +{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 }, +{ "sipu", 0x000a0000, 0xffff0000, "", 2 }, +{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, +{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, +{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, +{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, +{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, +{ "smc", 0x04070000, 0xfc070000, "", 2 }, +{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, +{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, +{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, +{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, +{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, +{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 }, +{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, +{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 }, +{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 }, +{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, +{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 }, +{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, +{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 }, +{ "svc", 0xc8060000, 0xffff0000, "", 4 }, +{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 }, +{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 }, +{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, +{ "tccr", 0x28040000, 0xfc7f0000, "", 2 }, +{ "td", 0xfc050000, 0xfc070000, "r,f", 4 }, +{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 }, +{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, +{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 }, +{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 }, +{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, +{ "trcc", 0x28050000, 0xfc7f0000, "", 2 }, +{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, +{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, +{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, +{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, +{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 }, +{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, +{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 }, +{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 }, +{ "uei", 0x00070000, 0xffff0000, "", 2 }, +{ "wait", 0x00010000, 0xffff0000, "", 2 }, +{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 }, +{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 }, +{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, +{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 }, +{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 }, +{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 }, +{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 }, +}; + +int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); + +struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / + sizeof(gld_opcodes[0]); diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h new file mode 100644 index 000000000..a21cc301e --- /dev/null +++ b/include/opcode/ppc.h @@ -0,0 +1,310 @@ +/* ppc.h -- Header file for PowerPC opcode table + Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004 + Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef PPC_H +#define PPC_H + +/* The opcode table is an array of struct powerpc_opcode. */ + +struct powerpc_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The defined values + are listed below. */ + unsigned long flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct powerpc_opcode powerpc_opcodes[]; +extern const int powerpc_num_opcodes; + +/* Values defined for the flags field of a struct powerpc_opcode. */ + +/* Opcode is defined for the PowerPC architecture. */ +#define PPC_OPCODE_PPC 1 + +/* Opcode is defined for the POWER (RS/6000) architecture. */ +#define PPC_OPCODE_POWER 2 + +/* Opcode is defined for the POWER2 (Rios 2) architecture. */ +#define PPC_OPCODE_POWER2 4 + +/* Opcode is only defined on 32 bit architectures. */ +#define PPC_OPCODE_32 8 + +/* Opcode is only defined on 64 bit architectures. */ +#define PPC_OPCODE_64 0x10 + +/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 + is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, + but it also supports many additional POWER instructions. */ +#define PPC_OPCODE_601 0x20 + +/* Opcode is supported in both the Power and PowerPC architectures + (ie, compiler's -mcpu=common or assembler's -mcom). */ +#define PPC_OPCODE_COMMON 0x40 + +/* Opcode is supported for any Power or PowerPC platform (this is + for the assembler's -many option, and it eliminates duplicates). */ +#define PPC_OPCODE_ANY 0x80 + +/* Opcode is supported as part of the 64-bit bridge. */ +#define PPC_OPCODE_64_BRIDGE 0x100 + +/* Opcode is supported by Altivec Vector Unit */ +#define PPC_OPCODE_ALTIVEC 0x200 + +/* Opcode is supported by PowerPC 403 processor. */ +#define PPC_OPCODE_403 0x400 + +/* Opcode is supported by PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE 0x800 + +/* Opcode is only supported by 64-bit PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE64 0x1000 + +/* Opcode is supported by PowerPC 440 processor. */ +#define PPC_OPCODE_440 0x2000 + +/* Opcode is only supported by Power4 architecture. */ +#define PPC_OPCODE_POWER4 0x4000 + +/* Opcode isn't supported by Power4 architecture. */ +#define PPC_OPCODE_NOPOWER4 0x8000 + +/* Opcode is only supported by POWERPC Classic architecture. */ +#define PPC_OPCODE_CLASSIC 0x10000 + +/* Opcode is only supported by e500x2 Core. */ +#define PPC_OPCODE_SPE 0x20000 + +/* Opcode is supported by e500x2 Integer select APU. */ +#define PPC_OPCODE_ISEL 0x40000 + +/* Opcode is an e500 SPE floating point instruction. */ +#define PPC_OPCODE_EFS 0x80000 + +/* Opcode is supported by branch locking APU. */ +#define PPC_OPCODE_BRLOCK 0x100000 + +/* Opcode is supported by performance monitor APU. */ +#define PPC_OPCODE_PMR 0x200000 + +/* Opcode is supported by cache locking APU. */ +#define PPC_OPCODE_CACHELCK 0x400000 + +/* Opcode is supported by machine check APU. */ +#define PPC_OPCODE_RFMCI 0x800000 + +/* A macro to extract the major opcode from an instruction. */ +#define PPC_OP(i) (((i) >> 26) & 0x3f) + +/* The operands table is an array of struct powerpc_operand. */ + +struct powerpc_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (*insert) + (unsigned long instruction, long op, int dialect, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & PPC_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) (unsigned long instruction, int dialect, int *invalid); + + /* One bit syntax flags. */ + unsigned long flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the powerpc_opcodes table. */ + +extern const struct powerpc_operand powerpc_operands[]; + +/* Values defined for the flags field of a struct powerpc_operand. */ + +/* This operand takes signed values. */ +#define PPC_OPERAND_SIGNED (01) + +/* This operand takes signed values, but also accepts a full positive + range of values when running in 32 bit mode. That is, if bits is + 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, + this flag is ignored. */ +#define PPC_OPERAND_SIGNOPT (02) + +/* This operand does not actually exist in the assembler input. This + is used to support extended mnemonics such as mr, for which two + operands fields are identical. The assembler should call the + insert function with any op value. The disassembler should call + the extract function, ignore the return value, and check the value + placed in the valid argument. */ +#define PPC_OPERAND_FAKE (04) + +/* The next operand should be wrapped in parentheses rather than + separated from this one by a comma. This is used for the load and + store instructions which want their operands to look like + reg,displacement(reg) + */ +#define PPC_OPERAND_PARENS (010) + +/* This operand may use the symbolic names for the CR fields, which + are + lt 0 gt 1 eq 2 so 3 un 3 + cr0 0 cr1 1 cr2 2 cr3 3 + cr4 4 cr5 5 cr6 6 cr7 7 + These may be combined arithmetically, as in cr2*4+gt. These are + only supported on the PowerPC, not the POWER. */ +#define PPC_OPERAND_CR (020) + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define PPC_OPERAND_GPR (040) + +/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ +#define PPC_OPERAND_GPR_0 (0100) + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define PPC_OPERAND_FPR (0200) + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define PPC_OPERAND_RELATIVE (0400) + +/* This operand is an absolute branch address. The disassembler + prints these symbolically if possible. */ +#define PPC_OPERAND_ABSOLUTE (01000) + +/* This operand is optional, and is zero if omitted. This is used for + example, in the optional BF field in the comparison instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ +#define PPC_OPERAND_OPTIONAL (02000) + +/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand + is omitted, then for the next operand use this operand value plus + 1, ignoring the next operand field for the opcode. This wretched + hack is needed because the Power rotate instructions can take + either 4 or 5 operands. The disassembler should print this operand + out regardless of the PPC_OPERAND_OPTIONAL field. */ +#define PPC_OPERAND_NEXT (04000) + +/* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ +#define PPC_OPERAND_NEGATIVE (010000) + +/* This operand names a vector unit register. The disassembler + prints these with a leading 'v'. */ +#define PPC_OPERAND_VR (020000) + +/* This operand is for the DS field in a DS form instruction. */ +#define PPC_OPERAND_DS (040000) + +/* This operand is for the DQ field in a DQ form instruction. */ +#define PPC_OPERAND_DQ (0100000) + +/* The POWER and PowerPC assemblers use a few macros. We keep them + with the operands table for simplicity. The macro table is an + array of struct powerpc_macro. */ + +struct powerpc_macro +{ + /* The macro name. */ + const char *name; + + /* The number of operands the macro takes. */ + unsigned int operands; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct powerpc_opcode flags field. */ + unsigned long flags; + + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char *format; +}; + +extern const struct powerpc_macro powerpc_macros[]; +extern const int powerpc_num_macros; + +#endif /* PPC_H */ diff --git a/include/opcode/pyr.h b/include/opcode/pyr.h new file mode 100644 index 000000000..d0bed6a47 --- /dev/null +++ b/include/opcode/pyr.h @@ -0,0 +1,305 @@ +/* pyramid.opcode.h -- gdb initial attempt. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* pyramid opcode table: wot to do with this + particular opcode */ + +struct pyr_datum +{ + char nargs; + char * args; /* how to compile said opcode */ + unsigned long mask; /* Bit vector: which operand modes are valid + for this opcode */ + unsigned char code; /* op-code (always 6(?) bits */ +}; + +typedef struct pyr_insn_format +{ + unsigned int mode :4; + unsigned int operator :8; + unsigned int index_scale :2; + unsigned int index_reg :6; + unsigned int operand_1 :6; + unsigned int operand_2:6; +} pyr_insn_format; + + +/* We store four bytes of opcode for all opcodes. + Pyramid is sufficiently RISCy that: + - insns are always an integral number of words; + - the length of any insn can be told from the first word of + the insn. (ie, if there are zero, one, or two words of + immediate operand/offset). + + + The args component is a string containing two characters for each + operand of the instruction. The first specifies the kind of operand; + the second, the place it is stored. */ + +/* Kinds of operands: + mask assembler syntax description + 0x0001: movw Rn,Rn register to register + 0x0002: movw K,Rn quick immediate to register + 0x0004: movw I,Rn long immediate to register + 0x0008: movw (Rn),Rn register indirect to register + movw (Rn)[x],Rn register indirect to register + 0x0010: movw I(Rn),Rn offset register indirect to register + movw I(Rn)[x],Rn offset register indirect, indexed, to register + + 0x0020: movw Rn,(Rn) register to register indirect + 0x0040: movw K,(Rn) quick immediate to register indirect + 0x0080: movw I,(Rn) long immediate to register indirect + 0x0100: movw (Rn),(Rn) register indirect to-register indirect + 0x0100: movw (Rn),(Rn) register indirect to-register indirect + 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect + 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect + + 0x0400: movw Rn,I(Rn) register to register indirect+offset + 0x0800: movw K,I(Rn) quick immediate to register indirect+offset + 0x1000: movw I,I(Rn) long immediate to register indirect+offset + 0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset + 0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect + +offset + 0x0000: (irregular) ??? + + + Each insn has a four-bit field encoding the type(s) of its operands. +*/ + +/* Some common combinations + */ + +/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/ +#define GEN_TO_REG (31) + +#define UNKNOWN ((unsigned long)-1) +#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15)) + +#define CONVERT (1|8|0x10|0x20|0x200) + +#define K_TO_REG (2) +#define I_TO_REG (4) +#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG) +#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG) + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ + +struct pyr_opcode /* pyr opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct pyr_datum datum; /* rest of opcode table [datum] */ +}; + +#define pyr_how args +#define pyr_nargs nargs +#define pyr_mask mask +#define pyr_name name + +struct pyr_opcode pyr_opcodes[] = +{ + {"movb", { 2, "", UNKNOWN, 0x11}, }, + {"movh", { 2, "", UNKNOWN, 0x12} }, + {"movw", { 2, "", ANY, 0x10} }, + {"movl", { 2, "", ANY, 0x13} }, + {"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} }, + {"mnegf", { 2, "", 0x1, 0x15} }, + {"mnegd", { 2, "", 0x1, 0x16} }, + {"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} }, + {"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} }, + {"mabsf", { 2, "", 0x1, 0x19} }, + {"mabsd", { 2, "", 0x1, 0x1a} }, + {"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} }, + {"mtstf", { 2, "", 0x1, 0x1d} }, + {"mtstd", { 2, "", 0x1, 0x1e} }, + {"mova", { 2, "", 0x8|0x10, 0x1f} }, + {"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} }, + {"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} }, + /* 2 insns out of order here */ + {"movbl", { 2, "", 1, 0x4f} }, + {"filbl", { 2, "", 1, 0x4e} }, + + {"cvtbw", { 2, "", CONVERT, 0x22} }, + {"cvthw", { 2, "", CONVERT, 0x23} }, + {"cvtwb", { 2, "", CONVERT, 0x24} }, + {"cvtwh", { 2, "", CONVERT, 0x25} }, + {"cvtwf", { 2, "", CONVERT, 0x26} }, + {"cvtwd", { 2, "", CONVERT, 0x27} }, + {"cvtfw", { 2, "", CONVERT, 0x28} }, + {"cvtfd", { 2, "", CONVERT, 0x29} }, + {"cvtdw", { 2, "", CONVERT, 0x2a} }, + {"cvtdf", { 2, "", CONVERT, 0x2b} }, + + {"addw", { 2, "", GEN_TO_REG, 0x40} }, + {"addwc", { 2, "", GEN_TO_REG, 0x41} }, + {"subw", { 2, "", GEN_TO_REG, 0x42} }, + {"subwb", { 2, "", GEN_TO_REG, 0x43} }, + {"rsubw", { 2, "", GEN_TO_REG, 0x44} }, + {"mulw", { 2, "", GEN_TO_REG, 0x45} }, + {"emul", { 2, "", GEN_TO_REG, 0x47} }, + {"umulw", { 2, "", GEN_TO_REG, 0x46} }, + {"divw", { 2, "", GEN_TO_REG, 0x48} }, + {"ediv", { 2, "", GEN_TO_REG, 0x4a} }, + {"rdivw", { 2, "", GEN_TO_REG, 0x4b} }, + {"udivw", { 2, "", GEN_TO_REG, 0x49} }, + {"modw", { 2, "", GEN_TO_REG, 0x4c} }, + {"umodw", { 2, "", GEN_TO_REG, 0x4d} }, + + + {"addf", { 2, "", 1, 0x50} }, + {"addd", { 2, "", 1, 0x51} }, + {"subf", { 2, "", 1, 0x52} }, + {"subd", { 2, "", 1, 0x53} }, + {"mulf", { 2, "", 1, 0x56} }, + {"muld", { 2, "", 1, 0x57} }, + {"divf", { 2, "", 1, 0x58} }, + {"divd", { 2, "", 1, 0x59} }, + + + {"cmpb", { 2, "", UNKNOWN, 0x61} }, + {"cmph", { 2, "", UNKNOWN, 0x62} }, + {"cmpw", { 2, "", UNKNOWN, 0x60} }, + {"ucmpb", { 2, "", UNKNOWN, 0x66} }, + /* WHY no "ucmph"??? */ + {"ucmpw", { 2, "", UNKNOWN, 0x65} }, + {"xchw", { 2, "", UNKNOWN, 0x0f} }, + + + {"andw", { 2, "", GEN_TO_REG, 0x30} }, + {"orw", { 2, "", GEN_TO_REG, 0x31} }, + {"xorw", { 2, "", GEN_TO_REG, 0x32} }, + {"bicw", { 2, "", GEN_TO_REG, 0x33} }, + {"lshlw", { 2, "", GEN_TO_REG, 0x38} }, + {"ashlw", { 2, "", GEN_TO_REG, 0x3a} }, + {"ashll", { 2, "", GEN_TO_REG, 0x3c} }, + {"ashrw", { 2, "", GEN_TO_REG, 0x3b} }, + {"ashrl", { 2, "", GEN_TO_REG, 0x3d} }, + {"rotlw", { 2, "", GEN_TO_REG, 0x3e} }, + {"rotrw", { 2, "", GEN_TO_REG, 0x3f} }, + + /* push and pop insns are "going away next release". */ + {"pushw", { 2, "", GEN_TO_REG, 0x0c} }, + {"popw", { 2, "", (0x1|0x8|0x10), 0x0d} }, + {"pusha", { 2, "", (0x8|0x10), 0x0e} }, + + {"bitsw", { 2, "", UNKNOWN, 0x35} }, + {"bitcw", { 2, "", UNKNOWN, 0x36} }, + /* some kind of ibra/dbra insns??*/ + {"icmpw", { 2, "", UNKNOWN, 0x67} }, + {"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/ + {"acmpw", { 2, "", 1, 0x6b} }, + + /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op + insn with a 2nd op of tr14. The assembler will have to grok this. */ + {"call", { 2, "", GEN_TO_REG, 0x04} }, + {"call", { 1, "", GEN_TO_REG, 0x04} }, + + {"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/ + /* Ret is usually written as a 0-op insn, but gets disassembled as a + 1-op insn. The operand is always tr15. */ + {"ret", { 0, "", UNKNOWN, 0x09} }, + {"ret", { 1, "", UNKNOWN, 0x09} }, + {"adsf", { 2, "", (1|2|4), 0x08} }, + {"retd", { 2, "", UNKNOWN, 0x0a} }, + {"btc", { 2, "", UNKNOWN, 0x01} }, + {"bfc", { 2, "", UNKNOWN, 0x02} }, + /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */ + {"jump", { 1, "", UNKNOWN, 0x00} }, + {"btp", { 2, "", UNKNOWN, 0xf00} }, + /* read control-stack pointer is another 1-or-2 operand insn. */ + {"rcsp", { 2, "", UNKNOWN, 0x01f} }, + {"rcsp", { 1, "", UNKNOWN, 0x01f} } +}; + +/* end: pyramid.opcode.h */ +/* One day I will have to take the time to find out what operands + are valid for these insns, and guess at what they mean. + + I can't imagine what the "I???" insns (iglob, etc) do. + + the arithmetic-sounding insns ending in "p" sound awfully like BCD + arithmetic insns: + dshlp -> Decimal SHift Left Packed + dshrp -> Decimal SHift Right Packed + and cvtlp would be convert long to packed. + I have no idea how the operands are interpreted; but having them be + a long register with (address, length) of an in-memory packed BCD operand + would not be surprising. + They are unlikely to be a packed bcd string: 64 bits of long give + is only 15 digits+sign, which isn't enough for COBOL. + */ +#if 0 + {"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/ + /* The OSx Operating System Porting Guide claims SSL does things + with tr12 (a register reserved to it) to do with static block-structure + references. SSL=Set Static Link? It's "Going away next release". */ + {"ssl", { 2, "", UNKNOWN, 0x00} }, + {"ccmps", { 2, "", UNKNOWN, 0x00} }, + {"lcd", { 2, "", UNKNOWN, 0x00} }, + {"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/ + {"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/ + {"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/ + {"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/ + {"ldti", { 2, "", UNKNOWN, 0x00} }, + {"ldb", { 2, "", UNKNOWN, 0x00} }, + {"stp", { 2, "", UNKNOWN, 0x00} }, + {"stti", { 2, "", UNKNOWN, 0x00} }, + {"stb", { 2, "", UNKNOWN, 0x00} }, + {"stu", { 2, "", UNKNOWN, 0x00} }, + {"addp", { 2, "", UNKNOWN, 0x00} }, + {"subp", { 2, "", UNKNOWN, 0x00} }, + {"mulp", { 2, "", UNKNOWN, 0x00} }, + {"divp", { 2, "", UNKNOWN, 0x00} }, + {"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */ + {"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */ + {"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/ + {"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/ + {"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/ + {"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/ + {"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/ + {"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/ + {"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/ + {"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/ + {"cmovs", { 2, "", UNKNOWN, 0x00} }, + {"rsubw", { 2, "", UNKNOWN, 0x00} }, + {"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */ + {"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */ + {"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */ + {"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/ + {"callr", { 2, "", UNKNOWN, 0x00} }, + {"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/ + {"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/ + {"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/ + {"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/ + {"ssi", { 2, "", UNKNOWN, 0x00} }, + {"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/ + {"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */ + {"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/ + {"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/ + {"flic", { 2, "", UNKNOWN, 0x00} }, + {"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */ + {"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */ + {"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */ + {"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */ + {"lamst", { 2, "", UNKNOWN, 0x00} }, + {"tio", { 2, "", UNKNOWN, 0x00} }, +#endif diff --git a/include/opcode/s390.h b/include/opcode/s390.h new file mode 100644 index 000000000..f582a4e51 --- /dev/null +++ b/include/opcode/s390.h @@ -0,0 +1,141 @@ +/* s390.h -- Header file for S390 opcode table + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef S390_H +#define S390_H + +/* List of instruction sets variations. */ + +enum s390_opcode_mode_val + { + S390_OPCODE_ESA = 0, + S390_OPCODE_ZARCH + }; + +enum s390_opcode_cpu_val + { + S390_OPCODE_G5 = 0, + S390_OPCODE_G6, + S390_OPCODE_Z900, + S390_OPCODE_Z990 + }; + +/* The opcode table is an array of struct s390_opcode. */ + +struct s390_opcode + { + /* The opcode name. */ + const char * name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned char opcode[6]; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned char mask[6]; + + /* The opcode length in bytes. */ + int oplen; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; + + /* Bitmask of execution modes this opcode is available for. */ + unsigned int modes; + + /* First cpu this opcode is available for. */ + enum s390_opcode_cpu_val min_cpu; + }; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct s390_opcode s390_opcodes[]; +extern const int s390_num_opcodes; + +/* A opcode format table for the .insn pseudo mnemonic. */ +extern const struct s390_opcode s390_opformats[]; +extern const int s390_num_opformats; + +/* Values defined for the flags field of a struct powerpc_opcode. */ + +/* The operands table is an array of struct s390_operand. */ + +struct s390_operand + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + unsigned long flags; + }; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the powerpc_opcodes table. */ + +extern const struct s390_operand s390_operands[]; + +/* Values defined for the flags field of a struct s390_operand. */ + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define S390_OPERAND_GPR 0x1 + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define S390_OPERAND_FPR 0x2 + +/* This operand names an access register. The disassembler + prints these with a leading 'a'. */ +#define S390_OPERAND_AR 0x4 + +/* This operand names a control register. The disassembler + prints these with a leading 'c'. */ +#define S390_OPERAND_CR 0x8 + +/* This operand is a displacement. */ +#define S390_OPERAND_DISP 0x10 + +/* This operand names a base register. */ +#define S390_OPERAND_BASE 0x20 + +/* This operand names an index register, it can be skipped. */ +#define S390_OPERAND_INDEX 0x40 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define S390_OPERAND_PCREL 0x80 + +/* This operand takes signed values. */ +#define S390_OPERAND_SIGNED 0x100 + +/* This operand is a length. */ +#define S390_OPERAND_LENGTH 0x200 + +#endif /* S390_H */ diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h new file mode 100644 index 000000000..c3364933a --- /dev/null +++ b/include/opcode/sparc.h @@ -0,0 +1,241 @@ +/* Definitions for opcode table for the sparc. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, + 2003 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and +the GNU Binutils. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "ansidecl.h" + +/* The SPARC opcode table (and other related data) is defined in + the opcodes library in sparc-opc.c. If you change anything here, make + sure you fix up that file, and vice versa. */ + + /* FIXME-someday: perhaps the ,a's and such should be embedded in the + instruction's name rather than the args. This would make gas faster, pinsn + slower, but would mess up some macros a bit. xoxorich. */ + +/* List of instruction sets variations. + These values are such that each element is either a superset of a + preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P + returns non-zero. + The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. + Don't change this without updating sparc-opc.c. */ + +enum sparc_opcode_arch_val { + SPARC_OPCODE_ARCH_V6 = 0, + SPARC_OPCODE_ARCH_V7, + SPARC_OPCODE_ARCH_V8, + SPARC_OPCODE_ARCH_SPARCLET, + SPARC_OPCODE_ARCH_SPARCLITE, + /* v9 variants must appear last */ + SPARC_OPCODE_ARCH_V9, + SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ + SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */ + SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ +}; + +/* The highest architecture in the table. */ +#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) + +/* Given an enum sparc_opcode_arch_val, return the bitmask to use in + insn encoding/decoding. */ +#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) + +/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ +#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) + +/* Table of cpu variants. */ + +struct sparc_opcode_arch { + const char *name; + /* Mask of sparc_opcode_arch_val's supported. + EG: For v7 this would be + (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). + These are short's because sparc_opcode.architecture is. */ + short supported; +}; + +extern const struct sparc_opcode_arch sparc_opcode_archs[]; + +/* Given architecture name, look up it's sparc_opcode_arch_val value. */ +extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); + +/* Return the bitmask of supported architectures for ARCH. */ +#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) + +/* Non-zero if ARCH1 conflicts with ARCH2. + IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ +#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ +(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ + != SPARC_OPCODE_SUPPORTED (ARCH1)) \ + && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ + != SPARC_OPCODE_SUPPORTED (ARCH2))) + +/* Structure of an opcode table entry. */ + +struct sparc_opcode { + const char *name; + unsigned long match; /* Bits that must be set. */ + unsigned long lose; /* Bits that must not be set. */ + const char *args; + /* This was called "delayed" in versions before the flags. */ + char flags; + short architecture; /* Bitmask of sparc_opcode_arch_val's. */ +}; + +#define F_DELAYED 1 /* Delayed branch */ +#define F_ALIAS 2 /* Alias for a "real" instruction */ +#define F_UNBR 4 /* Unconditional branch */ +#define F_CONDBR 8 /* Conditional branch */ +#define F_JSR 16 /* Subroutine call */ +#define F_FLOAT 32 /* Floating point instruction (not a branch) */ +#define F_FBR 64 /* Floating point branch */ +/* FIXME: Add F_ANACHRONISTIC flag for v9. */ + +/* + +All sparc opcodes are 32 bits, except for the `set' instruction (really a +macro), which is 64 bits. It is handled as a special case. + +The match component is a mask saying which bits must match a particular +opcode in order for an instruction to be an instance of that opcode. + +The args component is a string containing one character for each operand of the +instruction. + +Kinds of operands: + # Number used by optimizer. It is ignored. + 1 rs1 register. + 2 rs2 register. + d rd register. + e frs1 floating point register. + v frs1 floating point register (double/even). + V frs1 floating point register (quad/multiple of 4). + f frs2 floating point register. + B frs2 floating point register (double/even). + R frs2 floating point register (quad/multiple of 4). + g frsd floating point register. + H frsd floating point register (double/even). + J frsd floating point register (quad/multiple of 4). + b crs1 coprocessor register + c crs2 coprocessor register + D crsd coprocessor register + m alternate space register (asr) in rd + M alternate space register (asr) in rs1 + h 22 high bits. + X 5 bit unsigned immediate + Y 6 bit unsigned immediate + 3 SIAM mode (3 bits). (v9b) + K MEMBAR mask (7 bits). (v9) + j 10 bit Immediate. (v9) + I 11 bit Immediate. (v9) + i 13 bit Immediate. + n 22 bit immediate. + k 2+14 bit PC relative immediate. (v9) + G 19 bit PC relative immediate. (v9) + l 22 bit PC relative immediate. + L 30 bit PC relative immediate. + a Annul. The annul bit is set. + A Alternate address space. Stored as 8 bits. + C Coprocessor state register. + F floating point state register. + p Processor state register. + N Branch predict clear ",pn" (v9) + T Branch predict set ",pt" (v9) + z %icc. (v9) + Z %xcc. (v9) + q Floating point queue. + r Single register that is both rs1 and rd. + O Single register that is both rs2 and rd. + Q Coprocessor queue. + S Special case. + t Trap base register. + w Window invalid mask register. + y Y register. + u sparclet coprocessor registers in rd position + U sparclet coprocessor registers in rs1 position + E %ccr. (v9) + s %fprs. (v9) + P %pc. (v9) + W %tick. (v9) + o %asi. (v9) + 6 %fcc0. (v9) + 7 %fcc1. (v9) + 8 %fcc2. (v9) + 9 %fcc3. (v9) + ! Privileged Register in rd (v9) + ? Privileged Register in rs1 (v9) + * Prefetch function constant. (v9) + x OPF field (v9 impdep). + 0 32/64 bit immediate for set or setx (v9) insns + _ Ancillary state register in rd (v9a) + / Ancillary state register in rs1 (v9a) + +The following chars are unused: (note: ,[] are used as punctuation) +[45] + +*/ + +#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ +#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ +#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ +#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ +#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ +#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ +#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ +#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ +#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ +#define F1(x) (OP(x)) +#define DISP30(x) ((x)&0x3fffffff) +#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ +#define RS2(x) ((x)&0x1f) /* rs2 field */ +#define SIMM13(x) ((x)&0x1fff) /* simm13 field */ +#define RD(x) (((x)&0x1f) << 25) /* destination register field */ +#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ +#define ASI_RS2(x) (SIMM13(x)) +#define MEMBAR(x) ((x)&0x7f) +#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ + +#define ANNUL (1<<29) +#define BPRED (1<<19) /* v9 */ +#define IMMED F3I(1) +#define RD_G0 RD(~0) +#define RS1_G0 RS1(~0) +#define RS2_G0 RS2(~0) + +extern const struct sparc_opcode sparc_opcodes[]; +extern const int sparc_num_opcodes; + +extern int sparc_encode_asi (const char *); +extern const char *sparc_decode_asi (int); +extern int sparc_encode_membar (const char *); +extern const char *sparc_decode_membar (int); +extern int sparc_encode_prefetch (const char *); +extern const char *sparc_decode_prefetch (int); +extern int sparc_encode_sparclet_cpreg (const char *); +extern const char *sparc_decode_sparclet_cpreg (int); + +/* + * Local Variables: + * fill-column: 131 + * comment-column: 0 + * End: + */ + +/* end of sparc.h */ diff --git a/include/opcode/tahoe.h b/include/opcode/tahoe.h new file mode 100644 index 000000000..b5cee249e --- /dev/null +++ b/include/opcode/tahoe.h @@ -0,0 +1,213 @@ +/* + * Ported by the State University of New York at Buffalo by the Distributed + * Computer Systems Lab, Department of Computer Science, 1991. + */ + +#ifndef tahoe_opcodeT +#define tahoe_opcodeT int +#endif /* no tahoe_opcodeT */ + +struct vot_wot /* tahoe opcode table: wot to do with this */ + /* particular opcode */ +{ + char * args; /* how to compile said opcode */ + tahoe_opcodeT code; /* op-code (may be > 8 bits!) */ +}; + +struct vot /* tahoe opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct vot_wot detail; /* rest of opcode table [datum] */ +}; + +#define vot_how args +#define vot_code code +#define vot_detail detail +#define vot_name name + +static struct vot +votstrs[] = +{ +{ "halt", {"", 0x00 } }, +{ "sinf", {"", 0x05 } }, +{ "ldf", {"rl", 0x06 } }, +{ "ldd", {"rq", 0x07 } }, +{ "addb2", {"rbmb", 0x08 } }, +{ "movb", {"rbwb", 0x09 } }, +{ "addw2", {"rwmw", 0x0a } }, +{ "movw", {"rwww", 0x0b } }, +{ "addl2", {"rlml", 0x0c } }, +{ "movl", {"rlwl", 0x0d } }, +{ "bbs", {"rlvlbw", 0x0e } }, +{ "nop", {"", 0x10 } }, +{ "brb", {"bb", 0x11 } }, +{ "brw", {"bw", 0x13 } }, +{ "cosf", {"", 0x15 } }, +{ "lnf", {"rl", 0x16 } }, +{ "lnd", {"rq", 0x17 } }, +{ "addb3", {"rbrbwb", 0x18 } }, +{ "cmpb", {"rbwb", 0x19 } }, +{ "addw3", {"rwrwww", 0x1a } }, +{ "cmpw", {"rwww", 0x1b } }, +{ "addl3", {"rlrlwl", 0x1c } }, +{ "cmpl", {"rlwl", 0x1d } }, +{ "bbc", {"rlvlbw", 0x1e } }, +{ "rei", {"", 0x20 } }, +{ "bneq", {"bb", 0x21 } }, +{ "bnequ", {"bb", 0x21 } }, +{ "cvtwl", {"rwwl", 0x23 } }, +{ "stf", {"wl", 0x26 } }, +{ "std", {"wq", 0x27 } }, +{ "subb2", {"rbmb", 0x28 } }, +{ "mcomb", {"rbwb", 0x29 } }, +{ "subw2", {"rwmw", 0x2a } }, +{ "mcomw", {"rwww", 0x2b } }, +{ "subl2", {"rlml", 0x2c } }, +{ "mcoml", {"rlwl", 0x2d } }, +{ "emul", {"rlrlrlwq", 0x2e } }, +{ "aoblss", {"rlmlbw", 0x2f } }, +{ "bpt", {"", 0x30 } }, +{ "beql", {"bb", 0x31 } }, +{ "beqlu", {"bb", 0x31 } }, +{ "cvtwb", {"rwwb", 0x33 } }, +{ "logf", {"", 0x35 } }, +{ "cmpf", {"rl", 0x36 } }, +{ "cmpd", {"rq", 0x37 } }, +{ "subb3", {"rbrbwb", 0x38 } }, +{ "bitb", {"rbrb", 0x39 } }, +{ "subw3", {"rwrwww", 0x3a } }, +{ "bitw", {"rwrw", 0x3b } }, +{ "subl3", {"rlrlwl", 0x3c } }, +{ "bitl", {"rlrl", 0x3d } }, +{ "ediv", {"rlrqwlwl", 0x3e } }, +{ "aobleq", {"rlmlbw", 0x3f } }, +{ "ret", {"", 0x40 } }, +{ "bgtr", {"bb", 0x41 } }, +{ "sqrtf", {"", 0x45 } }, +{ "cmpf2", {"rl", 0x46 } }, +{ "cmpd2", {"rqrq", 0x47 } }, +{ "shll", {"rbrlwl", 0x48 } }, +{ "clrb", {"wb", 0x49 } }, +{ "shlq", {"rbrqwq", 0x4a } }, +{ "clrw", {"ww", 0x4b } }, +{ "mull2", {"rlml", 0x4c } }, +{ "clrl", {"wl", 0x4d } }, +{ "shal", {"rbrlwl", 0x4e } }, +{ "bleq", {"bb", 0x51 } }, +{ "expf", {"", 0x55 } }, +{ "tstf", {"", 0x56 } }, +{ "tstd", {"", 0x57 } }, +{ "shrl", {"rbrlwl", 0x58 } }, +{ "tstb", {"rb", 0x59 } }, +{ "shrq", {"rbrqwq", 0x5a } }, +{ "tstw", {"rw", 0x5b } }, +{ "mull3", {"rlrlwl", 0x5c } }, +{ "tstl", {"rl", 0x5d } }, +{ "shar", {"rbrlwl", 0x5e } }, +{ "bbssi", {"rlmlbw", 0x5f } }, +{ "ldpctx", {"", 0x60 } }, +{ "pushd", {"", 0x67 } }, +{ "incb", {"mb", 0x69 } }, +{ "incw", {"mw", 0x6b } }, +{ "divl2", {"rlml", 0x6c } }, +{ "incl", {"ml", 0x6d } }, +{ "cvtlb", {"rlwb", 0x6f } }, +{ "svpctx", {"", 0x70 } }, +{ "jmp", {"ab", 0x71 } }, +{ "cvlf", {"rl", 0x76 } }, +{ "cvld", {"rl", 0x77 } }, +{ "decb", {"mb", 0x79 } }, +{ "decw", {"mw", 0x7b } }, +{ "divl3", {"rlrlwl", 0x7c } }, +{ "decl", {"ml", 0x7d } }, +{ "cvtlw", {"rlww", 0x7f } }, +{ "bgeq", {"bb", 0x81 } }, +{ "movs2", {"abab", 0x82 } }, +{ "cvfl", {"wl", 0x86 } }, +{ "cvdl", {"wl", 0x87 } }, +{ "orb2", {"rbmb", 0x88 } }, +{ "cvtbl", {"rbwl", 0x89 } }, +{ "orw2", {"rwmw", 0x8a } }, +{ "bispsw", {"rw", 0x8b } }, +{ "orl2", {"rlml", 0x8c } }, +{ "adwc", {"rlml", 0x8d } }, +{ "adda", {"rlml", 0x8e } }, +{ "blss", {"bb", 0x91 } }, +{ "cmps2", {"abab", 0x92 } }, +{ "ldfd", {"rl", 0x97 } }, +{ "orb3", {"rbrbwb", 0x98 } }, +{ "cvtbw", {"rbww", 0x99 } }, +{ "orw3", {"rwrwww", 0x9a } }, +{ "bicpsw", {"rw", 0x9b } }, +{ "orl3", {"rlrlwl", 0x9c } }, +{ "sbwc", {"rlml", 0x9d } }, +{ "suba", {"rlml", 0x9e } }, +{ "bgtru", {"bb", 0xa1 } }, +{ "cvdf", {"", 0xa6 } }, +{ "andb2", {"rbmb", 0xa8 } }, +{ "movzbl", {"rbwl", 0xa9 } }, +{ "andw2", {"rwmw", 0xaa } }, +{ "loadr", {"rwal", 0xab } }, +{ "andl2", {"rlml", 0xac } }, +{ "mtpr", {"rlrl", 0xad } }, +{ "ffs", {"rlwl", 0xae } }, +{ "blequ", {"bb", 0xb1 } }, +{ "negf", {"", 0xb6 } }, +{ "negd", {"", 0xb7 } }, +{ "andb3", {"rbrbwb", 0xb8 } }, +{ "movzbw", {"rbww", 0xb9 } }, +{ "andw3", {"rwrwww", 0xba } }, +{ "storer", {"rwal", 0xbb } }, +{ "andl3", {"rlrlwl", 0xbc } }, +{ "mfpr", {"rlwl", 0xbd } }, +{ "ffc", {"rlwl", 0xbe } }, +{ "calls", {"rbab", 0xbf } }, +{ "prober", {"rbabrl", 0xc0 } }, +{ "bvc", {"bb", 0xc1 } }, +{ "movs3", {"ababrw", 0xc2 } }, +{ "movzwl", {"rwwl", 0xc3 } }, +{ "addf", {"rl", 0xc6 } }, +{ "addd", {"rq", 0xc7 } }, +{ "xorb2", {"rbmb", 0xc8 } }, +{ "movob", {"rbwb", 0xc9 } }, +{ "xorw2", {"rwmw", 0xca } }, +{ "movow", {"rwww", 0xcb } }, +{ "xorl2", {"rlml", 0xcc } }, +{ "movpsl", {"wl", 0xcd } }, +{ "kcall", {"rw", 0xcf } }, +{ "probew", {"rbabrl", 0xd0 } }, +{ "bvs", {"bb", 0xd1 } }, +{ "cmps3", {"ababrw", 0xd2 } }, +{ "subf", {"rq", 0xd6 } }, +{ "subd", {"rq", 0xd7 } }, +{ "xorb3", {"rbrbwb", 0xd8 } }, +{ "pushb", {"rb", 0xd9 } }, +{ "xorw3", {"rwrwww", 0xda } }, +{ "pushw", {"rw", 0xdb } }, +{ "xorl3", {"rlrlwl", 0xdc } }, +{ "pushl", {"rl", 0xdd } }, +{ "insque", {"abab", 0xe0 } }, +{ "bcs", {"bb", 0xe1 } }, +{ "bgequ", {"bb", 0xe1 } }, +{ "mulf", {"rq", 0xe6 } }, +{ "muld", {"rq", 0xe7 } }, +{ "mnegb", {"rbwb", 0xe8 } }, +{ "movab", {"abwl", 0xe9 } }, +{ "mnegw", {"rwww", 0xea } }, +{ "movaw", {"awwl", 0xeb } }, +{ "mnegl", {"rlwl", 0xec } }, +{ "moval", {"alwl", 0xed } }, +{ "remque", {"ab", 0xf0 } }, +{ "bcc", {"bb", 0xf1 } }, +{ "blssu", {"bb", 0xf1 } }, +{ "divf", {"rq", 0xf6 } }, +{ "divd", {"rq", 0xf7 } }, +{ "movblk", {"alalrw", 0xf8 } }, +{ "pushab", {"ab", 0xf9 } }, +{ "pushaw", {"aw", 0xfb } }, +{ "casel", {"rlrlrl", 0xfc } }, +{ "pushal", {"al", 0xfd } }, +{ "callf", {"rbab", 0xfe } }, +{ "" , "" } /* empty is end sentinel */ + +}; diff --git a/include/opcode/tic30.h b/include/opcode/tic30.h new file mode 100644 index 000000000..a70027591 --- /dev/null +++ b/include/opcode/tic30.h @@ -0,0 +1,691 @@ +/* tic30.h -- Header file for TI TMS320C30 opcode table + Copyright 1998 Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a + header file. */ + +#ifndef _TMS320_H_ +#define _TMS320_H_ + +struct _register +{ + char *name; + unsigned char opcode; + unsigned char regtype; +}; + +typedef struct _register reg; + +#define REG_Rn 0x01 +#define REG_ARn 0x02 +#define REG_DP 0x03 +#define REG_OTHER 0x04 + +static const reg tic30_regtab[] = { + { "r0", 0x00, REG_Rn }, + { "r1", 0x01, REG_Rn }, + { "r2", 0x02, REG_Rn }, + { "r3", 0x03, REG_Rn }, + { "r4", 0x04, REG_Rn }, + { "r5", 0x05, REG_Rn }, + { "r6", 0x06, REG_Rn }, + { "r7", 0x07, REG_Rn }, + { "ar0",0x08, REG_ARn }, + { "ar1",0x09, REG_ARn }, + { "ar2",0x0A, REG_ARn }, + { "ar3",0x0B, REG_ARn }, + { "ar4",0x0C, REG_ARn }, + { "ar5",0x0D, REG_ARn }, + { "ar6",0x0E, REG_ARn }, + { "ar7",0x0F, REG_ARn }, + { "dp", 0x10, REG_DP }, + { "ir0",0x11, REG_OTHER }, + { "ir1",0x12, REG_OTHER }, + { "bk", 0x13, REG_OTHER }, + { "sp", 0x14, REG_OTHER }, + { "st", 0x15, REG_OTHER }, + { "ie", 0x16, REG_OTHER }, + { "if", 0x17, REG_OTHER }, + { "iof",0x18, REG_OTHER }, + { "rs", 0x19, REG_OTHER }, + { "re", 0x1A, REG_OTHER }, + { "rc", 0x1B, REG_OTHER }, + { "R0", 0x00, REG_Rn }, + { "R1", 0x01, REG_Rn }, + { "R2", 0x02, REG_Rn }, + { "R3", 0x03, REG_Rn }, + { "R4", 0x04, REG_Rn }, + { "R5", 0x05, REG_Rn }, + { "R6", 0x06, REG_Rn }, + { "R7", 0x07, REG_Rn }, + { "AR0",0x08, REG_ARn }, + { "AR1",0x09, REG_ARn }, + { "AR2",0x0A, REG_ARn }, + { "AR3",0x0B, REG_ARn }, + { "AR4",0x0C, REG_ARn }, + { "AR5",0x0D, REG_ARn }, + { "AR6",0x0E, REG_ARn }, + { "AR7",0x0F, REG_ARn }, + { "DP", 0x10, REG_DP }, + { "IR0",0x11, REG_OTHER }, + { "IR1",0x12, REG_OTHER }, + { "BK", 0x13, REG_OTHER }, + { "SP", 0x14, REG_OTHER }, + { "ST", 0x15, REG_OTHER }, + { "IE", 0x16, REG_OTHER }, + { "IF", 0x17, REG_OTHER }, + { "IOF",0x18, REG_OTHER }, + { "RS", 0x19, REG_OTHER }, + { "RE", 0x1A, REG_OTHER }, + { "RC", 0x1B, REG_OTHER }, + { "", 0, 0 } +}; + +static const reg *const tic30_regtab_end + = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); + +/* Indirect Addressing Modes Modification Fields */ +/* Indirect Addressing with Displacement */ +#define PreDisp_Add 0x00 +#define PreDisp_Sub 0x01 +#define PreDisp_Add_Mod 0x02 +#define PreDisp_Sub_Mod 0x03 +#define PostDisp_Add_Mod 0x04 +#define PostDisp_Sub_Mod 0x05 +#define PostDisp_Add_Circ 0x06 +#define PostDisp_Sub_Circ 0x07 +/* Indirect Addressing with Index Register IR0 */ +#define PreIR0_Add 0x08 +#define PreIR0_Sub 0x09 +#define PreIR0_Add_Mod 0x0A +#define PreIR0_Sub_Mod 0x0B +#define PostIR0_Add_Mod 0x0C +#define PostIR0_Sub_Mod 0x0D +#define PostIR0_Add_Circ 0x0E +#define PostIR0_Sub_Circ 0x0F +/* Indirect Addressing with Index Register IR1 */ +#define PreIR1_Add 0x10 +#define PreIR1_Sub 0x11 +#define PreIR1_Add_Mod 0x12 +#define PreIR1_Sub_Mod 0x13 +#define PostIR1_Add_Mod 0x14 +#define PostIR1_Sub_Mod 0x15 +#define PostIR1_Add_Circ 0x16 +#define PostIR1_Sub_Circ 0x17 +/* Indirect Addressing (Special Cases) */ +#define IndirectOnly 0x18 +#define PostIR0_Add_BitRev 0x19 + +typedef struct { + char *syntax; + unsigned char modfield; + unsigned char displacement; +} ind_addr_type; + +#define IMPLIED_DISP 0x01 +#define DISP_REQUIRED 0x02 +#define NO_DISP 0x03 + +static const ind_addr_type tic30_indaddr_tab[] = { + { "*+ar", PreDisp_Add, IMPLIED_DISP }, + { "*-ar", PreDisp_Sub, IMPLIED_DISP }, + { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, + { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, + { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, + { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, + { "*+ar()", PreDisp_Add, DISP_REQUIRED }, + { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, + { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, + { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, + { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, + { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, + { "*+ar(ir0)", PreIR0_Add, NO_DISP }, + { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, + { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, + { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, + { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, + { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, + { "*+ar(ir1)", PreIR1_Add, NO_DISP }, + { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, + { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, + { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, + { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, + { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, + { "*ar", IndirectOnly, NO_DISP }, + { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, + { "", 0,0 } +}; + +static const ind_addr_type *const tic30_indaddrtab_end + = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); + +/* Possible operand types */ +/* Register types */ +#define Rn 0x0001 +#define ARn 0x0002 +#define DPReg 0x0004 +#define OtherReg 0x0008 +/* Addressing mode types */ +#define Direct 0x0010 +#define Indirect 0x0020 +#define Imm16 0x0040 +#define Disp 0x0080 +#define Imm24 0x0100 +#define Abs24 0x0200 +/* 3 operand addressing mode types */ +#define op3T1 0x0400 +#define op3T2 0x0800 +/* Interrupt vector */ +#define IVector 0x1000 +/* Not required */ +#define NotReq 0x2000 + +#define GAddr1 Rn | Direct | Indirect | Imm16 +#define GAddr2 GAddr1 | AllReg +#define TAddr1 op3T1 | Rn | Indirect +#define TAddr2 op3T2 | Rn | Indirect +#define Reg Rn | ARn +#define AllReg Reg | DPReg | OtherReg + +typedef struct _template +{ + char *name; + unsigned int operands; /* how many operands */ + unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ + /* the bits in opcode_modifier are used to generate the final opcode from + the base_opcode. These bits also are used to detect alternate forms of + the same instruction */ + unsigned int opcode_modifier; + + /* opcode_modifier bits: */ +#define AddressMode 0x00600000 +#define PCRel 0x02000000 +#define StackOp 0x001F0000 +#define Rotate StackOp + + /* operand_types[i] describes the type of operand i. This is made + by OR'ing together all of the possible type masks. (e.g. + 'operand_types[i] = Reg|Imm' specifies that operand i can be + either a register or an immediate operand */ + unsigned int operand_types[3]; + /* This defines the number type of an immediate argument to an instruction. */ + int imm_arg_type; +#define Imm_None 0 +#define Imm_Float 1 +#define Imm_SInt 2 +#define Imm_UInt 3 +} +template; + +static const template tic30_optab[] = { + { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, + { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, + { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, + { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, + { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, + { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, + { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, + { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, + { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, + { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ + { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, + { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, + { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, + { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, + { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, + { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, + { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, + { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, + { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, + { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, + { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, + { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, + { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, + { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, + { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, + { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, + { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, + { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, + { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, + { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, + { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, + { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, + { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, + { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, + { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, + { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, + { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, + { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, + { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, + { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, + { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, + { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, + { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } +}; + +static const template *const tic30_optab_end = + tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); + +typedef struct { + char *name; + unsigned int operands_1; + unsigned int operands_2; + unsigned int base_opcode; + unsigned int operand_types[2][3]; + /* Which operand fits into which part of the final opcode word. */ + int oporder; +} partemplate; + +/* oporder defines - not very descriptive. */ +#define OO_4op1 0 +#define OO_4op2 1 +#define OO_4op3 2 +#define OO_5op1 3 +#define OO_5op2 4 +#define OO_PField 5 + +static const partemplate tic30_paroptab[] = { + { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } +}; + +static const partemplate *const tic30_paroptab_end = + tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); + +#endif diff --git a/include/opcode/tic4x.h b/include/opcode/tic4x.h new file mode 100644 index 000000000..0e6af6460 --- /dev/null +++ b/include/opcode/tic4x.h @@ -0,0 +1,1079 @@ +/* Table of opcodes for the Texas Instruments TMS320C[34]X family. + + Copyright (C) 2002, 2003 Free Software Foundation. + + Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +*/ + +#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33) +#define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44) + +/* Define some bitfield extraction/insertion macros. */ +#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) +#define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l)) +#define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l)) +#define INSERTU(inst, val, m, l) (inst |= ((val) << (l))) +#define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l) + +/* Define register numbers. */ +typedef enum + { + REG_R0, REG_R1, REG_R2, REG_R3, + REG_R4, REG_R5, REG_R6, REG_R7, + REG_AR0, REG_AR1, REG_AR2, REG_AR3, + REG_AR4, REG_AR5, REG_AR6, REG_AR7, + REG_DP, REG_IR0, REG_IR1, REG_BK, + REG_SP, REG_ST, REG_DIE, REG_IIE, + REG_IIF, REG_RS, REG_RE, REG_RC, + REG_R8, REG_R9, REG_R10, REG_R11, + REG_IVTP, REG_TVTP + } +c4x_reg_t; + +/* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */ + +#define REG_IE REG_DIE /* C3x only */ +#define REG_IF REG_IIE /* C3x only */ +#define REG_IOF REG_IIF /* C3x only */ + +#define TIC3X_REG_MAX REG_RC +#define TIC4X_REG_MAX REG_TVTP + +/* Register table size including C4x expansion regs. */ +#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1) + +struct tic4x_register +{ + char * name; + unsigned long regno; +}; + +typedef struct tic4x_register tic4x_register_t; + +/* We could store register synonyms here. */ +static const tic4x_register_t tic3x_registers[] = +{ + {"f0", REG_R0}, + {"r0", REG_R0}, + {"f1", REG_R1}, + {"r1", REG_R1}, + {"f2", REG_R2}, + {"r2", REG_R2}, + {"f3", REG_R3}, + {"r3", REG_R3}, + {"f4", REG_R4}, + {"r4", REG_R4}, + {"f5", REG_R5}, + {"r5", REG_R5}, + {"f6", REG_R6}, + {"r6", REG_R6}, + {"f7", REG_R7}, + {"r7", REG_R7}, + {"ar0", REG_AR0}, + {"ar1", REG_AR1}, + {"ar2", REG_AR2}, + {"ar3", REG_AR3}, + {"ar4", REG_AR4}, + {"ar5", REG_AR5}, + {"ar6", REG_AR6}, + {"ar7", REG_AR7}, + {"dp", REG_DP}, + {"ir0", REG_IR0}, + {"ir1", REG_IR1}, + {"bk", REG_BK}, + {"sp", REG_SP}, + {"st", REG_ST}, + {"ie", REG_IE}, + {"if", REG_IF}, + {"iof", REG_IOF}, + {"rs", REG_RS}, + {"re", REG_RE}, + {"rc", REG_RC}, + {"", 0} +}; + +const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1); + +/* Define C4x registers in addition to C3x registers. */ +static const tic4x_register_t tic4x_registers[] = +{ + {"die", REG_DIE}, /* Clobbers C3x REG_IE */ + {"iie", REG_IIE}, /* Clobbers C3x REG_IF */ + {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */ + {"f8", REG_R8}, + {"r8", REG_R8}, + {"f9", REG_R9}, + {"r9", REG_R9}, + {"f10", REG_R10}, + {"r10", REG_R10}, + {"f11", REG_R11}, + {"r11", REG_R11}, + {"ivtp", REG_IVTP}, + {"tvtp", REG_TVTP}, + {"", 0} +}; + +const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1); + +struct tic4x_cond +{ + char * name; + unsigned long cond; +}; + +typedef struct tic4x_cond tic4x_cond_t; + +/* Define conditional branch/load suffixes. Put desired form for + disassembler last. */ +static const tic4x_cond_t tic4x_conds[] = +{ + { "u", 0x00 }, + { "c", 0x01 }, { "lo", 0x01 }, + { "ls", 0x02 }, + { "hi", 0x03 }, + { "nc", 0x04 }, { "hs", 0x04 }, + { "z", 0x05 }, { "eq", 0x05 }, + { "nz", 0x06 }, { "ne", 0x06 }, + { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 }, + { "le", 0x08 }, + { "p", 0x09 }, { "gt", 0x09 }, + { "nn", 0x0a }, { "ge", 0x0a }, + { "nv", 0x0c }, + { "v", 0x0d }, + { "nuf", 0x0e }, + { "uf", 0x0f }, + { "nlv", 0x10 }, + { "lv", 0x11 }, + { "nluf", 0x12 }, + { "luf", 0x13 }, + { "zuf", 0x14 }, + /* Dummy entry, not included in num_conds. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0} +}; + +const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1); + +struct tic4x_indirect +{ + char * name; + unsigned long modn; +}; + +typedef struct tic4x_indirect tic4x_indirect_t; + +/* Define indirect addressing modes where: + d displacement (signed) + y ir0 + z ir1 */ + +static const tic4x_indirect_t tic4x_indirects[] = +{ + { "*+a(d)", 0x00 }, + { "*-a(d)", 0x01 }, + { "*++a(d)", 0x02 }, + { "*--a(d)", 0x03 }, + { "*a++(d)", 0x04 }, + { "*a--(d)", 0x05 }, + { "*a++(d)%", 0x06 }, + { "*a--(d)%", 0x07 }, + { "*+a(y)", 0x08 }, + { "*-a(y)", 0x09 }, + { "*++a(y)", 0x0a }, + { "*--a(y)", 0x0b }, + { "*a++(y)", 0x0c }, + { "*a--(y)", 0x0d }, + { "*a++(y)%", 0x0e }, + { "*a--(y)%", 0x0f }, + { "*+a(z)", 0x10 }, + { "*-a(z)", 0x11 }, + { "*++a(z)", 0x12 }, + { "*--a(z)", 0x13 }, + { "*a++(z)", 0x14 }, + { "*a--(z)", 0x15 }, + { "*a++(z)%", 0x16 }, + { "*a--(z)%", 0x17 }, + { "*a", 0x18 }, + { "*a++(y)b", 0x19 }, + /* Dummy entry, not included in num_indirects. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0} +}; + +#define TIC3X_MODN_MAX 0x19 + +const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1); + +/* Instruction template. */ +struct tic4x_inst +{ + char * name; + unsigned long opcode; + unsigned long opmask; + char * args; + unsigned long oplevel; +}; + +typedef struct tic4x_inst tic4x_inst_t; + +/* Opcode infix + B condition 16--20 U,C,Z,LO,HI, etc. + C condition 23--27 U,C,Z,LO,HI, etc. + + Arguments + , required arg follows + ; optional arg follows + + Argument types bits [classes] - example + ----------------------------------------------------------- + * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0) + # direct (for LDP) 0--15 [Z] - @start, start + @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start + A address register 22--24 [D] - AR0, AR7 + B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x) + C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5) + E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP + e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 + F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1 + G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP + g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 + H register (0-7) 18--16 [LS,M,P,Q] - R0, R7 + I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) + i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5 + J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) + j indirect (enhanced) 8--15 [M] - *+AR0(1), R5 + K register 19--21 [LL,M,Q,QC] - R0, R7 + L register 22--24 [LL,LS,P,Q,QC] - R0, R7 + M register (R2,R3) 22--22 [M] R2, R3 + N register (R0,R1) 23--23 [M] R0, R1 + O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5) + P displacement (PC Rel) 0--15 [D,J,JS] - @start, start + Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP + q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11 + R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP + r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11 + S short int immediate 0--15 [A,AB,AY,BI] - -5, 5 + T integer (C4x) 16--20 [Z] - -5, 12 + U unsigned integer 0--15 [AU,A3] - 0, 65535 + V vector (C4x: 0--8) 0--4 [Z] - 25, 7 + W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5 + X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP + Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0 + Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP +*/ + +#define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */ +#define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */ + +/* Define the instruction level */ +#define OP_C3X 0x1 /* C30 support - supported by all */ +#define OP_C4X 0x2 /* C40 support - C40, C44 */ +#define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type + I and J is enhanced in these classes - C31>=6.0, + C32>=2.0, C33 */ +#define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0, + LC31, C31>=5.0, C32 */ +#define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0, + C32, C33, C40>=5.0, C44 */ + +/* The following class definition is a classification scheme for + putting instructions with similar type of arguments together. It + simplifies the op-code definitions significantly, as we then only + need to use the class macroes for 95% of the DSP's opcodes. +*/ + +/* A: General 2-operand integer operations + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register (R) + Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI, + SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn, + MBn, MHn, MPYSHI, MPYUHI +*/ +#define A_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,R", level } + +/* AB: General 2-operand integer operation with condition + Syntax: <i>c src, dst + c = Condition + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register (R) + Instr: 1/0 - LDIc +*/ +#define AB_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \ + { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \ + { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \ + { name, opcode|0x40600000, 0xf0600000, "S,R", level } + +/* AU: General 2-operand unsigned integer operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) + dst = Register (R) + Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn +*/ +#define AU_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "U,R", level } + +/* AF: General 2-operand float to integer operation + Syntax: <i> src, dst + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register (R) + Instr: 1/0 - FIX +*/ +#define AF_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,R", level } + +/* A2: Limited 1-operand (integer) operation + Syntax: <i> src + src = Register (Q), Indirect (*), None + Instr: 1/0 - NOP +*/ +#define A2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*", level }, \ + { name, opcode|0x00000000, 0xffe00000, "" , level } + +/* A3: General 1-operand unsigned integer operation + Syntax: <i> src + src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) + Instr: 1/0 - RPTS +*/ +#define A3_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffff0000, "Q", level }, \ + { name, opcode|0x00200000, 0xffff0000, "@", level }, \ + { name, opcode|0x00400000, 0xffff0000, "*", level }, \ + { name, opcode|0x00600000, 0xffff0000, "U", level } + +/* A6: Limited 2-operand integer operation + Syntax: <i> src, dst + src = Direct (@), Indirect (*) + dst = Register (R) + Instr: 1/1 - LDII, C4x: SIGI +*/ +#define A6_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level } + +/* A7: Limited 2-operand integer store operation + Syntax: <i> src, dst + src = Register (R) + dst = Direct (@), Indirect (*) + Instr: 2/0 - STI, STII +*/ +#define A7_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \ + { name, opcode|0x00400000, 0xffe00000, "R,*", level } + +/* AY: General 2-operand signed address load operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Address register - ARx, IRx, DP, BK, SP (Y) + Instr: 0/1 - C4x: LDA + Note: Q and Y should *never* be the same register +*/ +#define AY_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,Y", level } + +/* B: General 2-operand float operation + Syntax: <i> src, dst + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND, + SUBF, SUBRF, C4x: RSQRF, TOIEEE +*/ +#define B_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,r", level } + +/* BA: General 2-operand integer to float operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 0/1 - C4x: CRCPF +*/ +#define BA_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,r", level } + +/* BB: General 2-operand conditional float operation + Syntax: <i>c src, dst + c = Condition + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 1/0 - LDFc +*/ +#define BB_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \ + { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \ + { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \ + { name, opcode|0x40600000, 0xf0600000, "F,r", level } + +/* BI: General 2-operand integer to float operation (yet different to BA) + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register 0-11 (r) + Instr: 1/0 - FLOAT +*/ +#define BI_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,r", level } + +/* B6: Limited 2-operand float operation + Syntax: <i> src, dst + src = Direct (@), Indirect (*) + dst = Register 0-11 (r) + Instr: 1/1 - LDFI, C4x: FRIEEE +*/ +#define B6_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level } + +/* B7: Limited 2-operand float store operation + Syntax: <i> src, dst + src = Register 0-11 (r) + dst = Direct (@), Indirect (*) + Instr: 2/0 - STF, STFI +*/ +#define B7_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \ + { name, opcode|0x00400000, 0xffe00000, "r,*", level } + +/* D: Decrement and brach operations + Syntax: <i>c ARn, dst + c = condition + ARn = AR register 0-7 (A) + dst = Register (Q), PC-relative (P) + Instr: 2/0 - DBc, DBcD + Alias: <name1> <name2> +*/ +#define D_CLASS_INSN(name1, name2, opcode, level) \ + { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ + { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \ + { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ + { name2, opcode|0x02000000, 0xfe200000, "A,P", level } + +/* I: General branch operations + Syntax: <i> dst + dst = Address (B) + Instr: 3/1 - BR, BRD, CALL, C4x: LAJ +*/ + +/* I2: General branch operations (C4x addition) + Syntax: <i> dst + dst = Address (B), C4x: Register (Q) + Instr: 2/0 - RPTB, RPTBD +*/ + +/* J: General conditional branch operations + Syntax: <i>c dst + c = Condition + dst = Register (Q), PC-relative (P) + Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc + Alias: <name1> <name2> +*/ +#define J_CLASS_INSN(name1, name2, opcode, level) \ + { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name1, opcode|0x02000000, 0xffe00000, "P", level }, \ + { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name2, opcode|0x02000000, 0xffe00000, "P", level } + +/* JS: General conditional branch operations + Syntax: <i>c dst + c = Condition + dst = Register (Q), PC-relative (P) + Instr: 1/1 - CALLc, C4X: LAJc +*/ + +/* LL: Load-load parallell operation + Syntax: <i> src2, dst2 || <i> src1, dst1 + src1 = Indirect 0,1,IR0,IR1 (J) + dst1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: Register (i) + dst2 = Register 0-7 (L) + Instr: 2/0 - LDF||LDF, LDI||LDI + Alias: i||i, i1||i2, i2||i1 +*/ +#define LL_CLASS_INSN(name, opcode, level) \ + { name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \ + { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \ + { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level } + +/* LS: Store-store parallell operation + Syntax: <i> src2, dst2 || <i> src1, dst1 + src1 = Register 0-7 (H) + dst1 = Indirect 0,1,IR0,IR1 (J) + src2 = Register 0-7 (L) + dst2 = Indirect 0,1,IR0,IR1, ENH: register (i) + Instr: 2/0 - STF||STF, STI||STI + Alias: i||i, i1||i2, i2||i1. +*/ +#define LS_CLASS_INSN(name, opcode, level) \ + { name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \ + { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \ + { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level } + +/* M: General multiply and add/sub operations + Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual + <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual + <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01] + <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual + <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual + <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03] + src1 = Register 0-7 (K) + src2 = Register 0-7 (H) + src3 = Indirect 0,1,IR0,IR1, ENH: register (j) + src4 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-1 (N) + dst2 = Register 2-3 (M) + Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3 + Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3 +*/ +#define M_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level } + +/* P: General 2-operand operation with parallell store + Syntax: <ia> src2, dst1 || <ib> src3, dst2 + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF, + LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF, + TOIEEE||STF + Alias: a||b, b||a +*/ +#define P_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \ + { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level } + +/* Q: General 3-operand operation with parallell store + Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2 + src1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI + Alias: a||b, b||a, a3||b, b||a3 +*/ +#define Q_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level } + +/* QC: General commutative 3-operand operation with parallell store + Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2 + <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual + src1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI, + OR3||STI, XOR3||STI + Alias: a||b, b||a, a3||b, b||a3 +*/ +#define QC_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ + { namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level } + +/* R: General register integer operation + Syntax: <i> dst + dst = Register (R) + Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC +*/ +#define R_CLASS_INSN(name, opcode, level) \ + { name, opcode, 0xffe0ffff, "R", level } + +/* RF: General register float operation + Syntax: <i> dst + dst = Register 0-11 (r) + Instr: 2/0 - POPF, PUSHF +*/ +#define RF_CLASS_INSN(name, opcode, level) \ + { name, opcode, 0xffe0ffff, "r", level } + +/* S: General 3-operand float operation + Syntax: <i> src2, src1, dst + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register 0-11 (r) + Instr: 1/0 - SUBF3 + Alias: i, i3 +*/ +#define S_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } + +/* SC: General commutative 3-operand float operation + Syntax: <i> src2, src1, dst - Manual + <i> src1, src2, dst + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register 0-11 (r) + Instr: 2/0 - ADDF3, MPYF3 + Alias: i, i3 +*/ +#define SC_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } + +/* S2: General 3-operand float operation with 2 args + Syntax: <i> src2, src1 + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + Instr: 1/0 - CMPF3 + Alias: i, i3 +*/ +#define S2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* T: General 3-operand integer operand + Syntax: <i> src2, src1, dst + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register (R) + Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3 + Alias: i, i3 +*/ +#define T_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } + +/* TC: General commutative 3-operand integer operation + Syntax: <i> src2, src1, dst + <i> src1, src2, dst + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register (R) + Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI + Alias: i, i3 +*/ +#define TC_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } + +/* T2: General 3-operand integer operation with 2 args + Syntax: <i> src2, src1 + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + Instr: 1/0 - CMPI3 + Alias: i, i3 +*/ +#define T2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* T2C: General commutative 3-operand integer operation with 2 args + Syntax: <i> src2, src1 - Manual + <i> src1, src2 + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0) + Instr: 1/0 - TSTB3 + Alias: i, i3 +*/ +#define T2C_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* Z: Misc operations with or without arguments + Syntax: <i> <arg1>,... + Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD, + TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK +*/ + + +/* Define tic4x opcodes for assembler and disassembler. */ +static const tic4x_inst_t tic4x_insts[] = +{ + /* Put synonyms after the desired forms in table so that they get + overwritten in the lookup table. The disassembler will thus + print the `proper' mnemonics. Note that the disassembler + only decodes the 11 MSBs, so instructions like ldp @0x500 will + be printed as ldiu 5, dp. Note that with parallel instructions, + the second part is executed before the first part, unless + the sti1||sti2 form is used. We also allow sti2||sti1 + which is equivalent to the default sti||sti form. + */ + B_CLASS_INSN( "absf", 0x00000000, OP_C3X ), + P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ), + A_CLASS_INSN( "absi", 0x00800000, OP_C3X ), + P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ), + A_CLASS_INSN( "addc", 0x01000000, OP_C3X ), + TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ), + B_CLASS_INSN( "addf", 0x01800000, OP_C3X ), + SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ), + QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ), + A_CLASS_INSN( "addi", 0x02000000, OP_C3X ), + TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ), + QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ), + AU_CLASS_INSN( "and", 0x02800000, OP_C3X ), + TC_CLASS_INSN( "and", 0x01800000, OP_C3X ), + QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ), + AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ), + T_CLASS_INSN( "andn", 0x02000000, OP_C3X ), + A_CLASS_INSN( "ash", 0x03800000, OP_C3X ), + T_CLASS_INSN( "ash", 0x02800000, OP_C3X ), + Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ), + J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ), + J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ), + J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ), + J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ), + { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */ + { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */ + B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ), + S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ), + A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ), + T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ), + D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ), + D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ), + AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ), + P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ), + BI_CLASS_INSN( "float", 0x05800000, OP_C3X ), + P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ), + B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ), + P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ), + { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */ + { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */ + { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + { "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */ + { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */ + { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */ + { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */ + { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ), + A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ), + A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ), + A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ), + AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ), + AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ), + AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ), + AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ), + AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ), + B_CLASS_INSN( "lde", 0x06800000, OP_C3X ), + { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */ + B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ), + LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ), + P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ), + BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ), + B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ), + { "ldhi", 0x1fe00000, 0xffe00000, "U,R" , OP_C4X }, /* Z_CLASS */ + { "ldhi", 0x1fe00000, 0xffe00000, "#,R" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ), + LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ), + P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ), + AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ), + A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ), + { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */ + B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ), + { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */ + { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ), + A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ), + AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ), + AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ), + { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ + A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ), + T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ), + Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ), + A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ), + A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ), + A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ), + A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ), + A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ), + A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ), + A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ), + A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ), + { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ + A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ), + A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ), + A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ), + A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ), + A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ), + A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ), + A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ), + A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ), + B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ), + SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ), + M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ), + QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ), + M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ), + A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ), + TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ), + M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ), + QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ), + M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ), + A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ), + TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ), + A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ), + TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ), + A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ), + B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ), + P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ), + A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ), + P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ), + A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ), + B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ), + AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ), + P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ), + AU_CLASS_INSN( "or", 0x10000000, OP_C3X ), + TC_CLASS_INSN( "or", 0x05800000, OP_C3X ), + QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ), + R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ), + RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ), + R_CLASS_INSN( "push", 0x0f200000, OP_C3X ), + RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ), + BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ), + { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */ + { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */ + { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */ + { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */ + B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ), + R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ), + R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ), + R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ), + R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ), + { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */ + { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ + { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */ + { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ + A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ), + B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ), + { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ), + B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ), + LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ), + B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ), + A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ), + { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */ + { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */ + LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ), + A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ), + { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */ + { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "subb", 0x16800000, OP_C3X ), + T_CLASS_INSN( "subb", 0x06000000, OP_C3X ), + A_CLASS_INSN( "subc", 0x17000000, OP_C3X ), + B_CLASS_INSN( "subf", 0x17800000, OP_C3X ), + S_CLASS_INSN( "subf", 0x06800000, OP_C3X ), + Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ), + A_CLASS_INSN( "subi", 0x18000000, OP_C3X ), + T_CLASS_INSN( "subi", 0x07000000, OP_C3X ), + Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ), + A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ), + B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ), + A_CLASS_INSN( "subri", 0x19800000, OP_C3X ), + { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ), + P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ), + { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */ + { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */ + AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ), + T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ), + AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ), + TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ), + QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ), + + /* Dummy entry, not included in tic4x_num_insts. This + lets code examine entry i + 1 without checking + if we've run off the end of the table. */ + { "", 0x0, 0x00, "", 0 } +}; + +const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1); diff --git a/include/opcode/tic54x.h b/include/opcode/tic54x.h new file mode 100644 index 000000000..ae657225d --- /dev/null +++ b/include/opcode/tic54x.h @@ -0,0 +1,163 @@ +/* tic54x.h -- Header file for TI TMS320C54X opcode table + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Timothy Wall (twall@cygnus.com) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#ifndef _opcode_tic54x_h_ +#define _opcode_tic54x_h_ + +typedef struct _symbol +{ + const char *name; + unsigned short value; +} symbol; + +enum optype { + OPT = 0x8000, + OP_None = 0x0, + + OP_Xmem, /* AR3 or AR4, indirect */ + OP_Ymem, /* AR3 or AR4, indirect */ + OP_pmad, /* PROG mem, direct */ + OP_dmad, /* DATA mem, direct */ + OP_Smem, + OP_Lmem, /* 32-bit single-addressed (direct/indirect) */ + OP_MMR, + OP_PA, + OP_Sind, + OP_xpmad, + OP_xpmad_ms7, + OP_MMRX, + OP_MMRY, + + OP_SRC1, /* src accumulator in bit 8 */ + OP_SRC, /* src accumulator in bit 9 */ + OP_RND, /* rounded result dst accumulator, opposite of bit 8 */ + OP_DST, /* dst accumulator in bit 8 */ + OP_ARX, /* arX in bits 0-3 */ + OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */ + OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */ + OP_B, /* ACC B only */ + OP_A, /* ACC A only */ + + OP_lk, /* 16-bit immediate, '#' optional */ + OP_TS, + OP_k8, /* -128 <= k <= 128 */ + OP_16, /* literal "16" */ + OP_BITC, /* 0 to 16 */ + OP_CC, /* condition code */ + OP_CC2, /* 4-bit condition code */ + OP_CC3, /* 2-bit condition code */ + OP_123, /* 1, 2, or 3 */ + OP_031, /* 0-31, numeric */ + OP_k5, /* 0 to 31 */ + OP_k8u, /* 0 to 255 */ + OP_ASM, /* "ASM" */ + OP_T, /* "T" */ + OP_DP, /* "DP" */ + OP_ARP, /* "ARP" */ + OP_k3, /* 0-7 */ + OP_lku, /* 0 to 65535 */ + OP_N, /* 0/1 or ST0/ST1 */ + OP_SBIT, /* status bit or 0-15 */ + OP_12, /* one or two */ + OP_k9, /* 9 bits of data page (DP) address */ + OP_TRN, /* "TRN" */ + +}; + +typedef struct _template +{ + /* The opcode mnemonic */ + const char *name; + unsigned int words; /* insn size in words */ + int minops, maxops; /* min/max operand count */ + /* The significant bits in the opcode. Other bits are zero. + Instructions with more than 16 bits of opcode store the rest in the upper + 16 bits. + */ + unsigned short opcode; +#define INDIRECT(OP) ((OP)&0x80) +#define MOD(OP) (((OP)>>3)&0xF) +#define ARF(OP) ((OP)&0x7) +#define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12) +#define SRC(OP) ((OP)&0x200) +#define DST(OP) ((OP)&0x100) +#define SRC1(OP) ((OP)&0x100) +#define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F)) +#define SHFT(OP) ((OP)&0xF) +#define ARX(OP) ((OP)&0x7) +#define XMEM(OP) (((OP)&0x00F0)>>4) +#define YMEM(OP) ((OP)&0x000F) +#define XMOD(C) (((C)&0xC)>>2) +#define XARX(C) (((C)&0x3)+2) +#define CC3(OP) (((OP)>>8)&0x3) +#define SBIT(OP) ((OP)&0xF) +#define MMR(OP) ((OP)&0x7F) +#define MMRX(OP) ((((OP)>>4)&0xF)+16) +#define MMRY(OP) (((OP)&0xF)+16) + +#define OPTYPE(X) ((X)&~OPT) + + /* Ones in this mask indicate which bits must match the opcode field. + Zeroes indicate don't care bits (operands and/or opcode options) */ + unsigned short mask; + + /* An array of operand codes (at most 4 operands) */ +#define MAX_OPERANDS 4 + enum optype operand_types[MAX_OPERANDS]; + + /* Special purpose flags (e.g. branch type, parallel, delay, etc) + */ + unsigned short flags; +#define B_NEXT 0 /* normal execution, next insn is next address */ +#define B_BRANCH 1 /* next insn is in opcode */ +#define B_RET 2 /* next insn is on stack */ +#define B_BACC 3 /* next insn is in acc */ +#define B_REPEAT 4 /* next insn repeats */ +#define FL_BMASK 0x07 + +#define FL_DELAY 0x10 /* instruction uses delay slots */ +#define FL_EXT 0x20 /* instruction takes two words */ +#define FL_FAR 0x40 /* far mode addressing */ +#define FL_LP 0x80 /* LP-only instruction */ +#define FL_NR 0x100 /* no repeat allowed */ +#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */ + +#define FL_PAR 0x400 /* Parallel instruction. */ + + unsigned short opcode2, mask2; /* some insns have an extended opcode */ + + const char* parname; + enum optype paroperand_types[MAX_OPERANDS]; + +} template; + +extern const template tic54x_unknown_opcode; +extern const template tic54x_optab[]; +extern const template tic54x_paroptab[]; +extern const symbol mmregs[], regs[]; +extern const symbol condition_codes[], cc2_codes[], status_bits[]; +extern const symbol cc3_codes[]; +extern const char *misc_symbols[]; +struct disassemble_info; +extern const template* tic54x_get_insn (struct disassemble_info *, + bfd_vma, unsigned short, int *); + +#endif /* _opcode_tic54x_h_ */ diff --git a/include/opcode/tic80.h b/include/opcode/tic80.h new file mode 100644 index 000000000..c6a79df28 --- /dev/null +++ b/include/opcode/tic80.h @@ -0,0 +1,282 @@ +/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table + Copyright 1996, 1997, 2003 Free Software Foundation, Inc. + Written by Fred Fish (fnf@cygnus.com), Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef TIC80_H +#define TIC80_H + +/* The opcode table is an array of struct tic80_opcode. */ + +struct tic80_opcode +{ + /* The opcode name. */ + + const char *name; + + /* The opcode itself. Those bits which will be filled in with operands + are zeroes. */ + + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a mask + containing ones indicating those bits which must match the opcode + field, and zeroes indicating those bits which need not match (and are + presumably filled in by operands). */ + + unsigned long mask; + + /* Special purpose flags for this opcode. */ + + unsigned char flags; + + /* An array of operand codes. Each code is an index into the operand + table. They appear in the order which the operands must appear in + assembly code, and are terminated by a zero. FIXME: Adjust size to + match actual requirements when TIc80 support is complete */ + + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise in + the order in which the disassembler should consider instructions. + FIXME: This isn't currently true. */ + +extern const struct tic80_opcode tic80_opcodes[]; +extern const int tic80_num_opcodes; + + +/* The operands table is an array of struct tic80_operand. */ + +struct tic80_operand +{ + /* The number of bits in the operand. */ + + int bits; + + /* How far the operand is left shifted in the instruction. */ + + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + + unsigned long (*insert) + (unsigned long instruction, long op, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & TIC80_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + + long (*extract) (unsigned long instruction, int *invalid); + + /* One bit syntax flags. */ + + unsigned long flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the tic80_opcodes table. */ + +extern const struct tic80_operand tic80_operands[]; + + +/* Values defined for the flags field of a struct tic80_operand. + + Note that flags for all predefined symbols, such as the general purpose + registers (ex: r10), control registers (ex: FPST), condition codes (ex: + eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be + or'd into an int where the lower bits contain the actual numeric value + that correponds to this predefined symbol. This way a single int can + contain both the value of the symbol and it's type. + */ + +/* This operand must be an even register number. Floating point numbers + for example are stored in even/odd register pairs. */ + +#define TIC80_OPERAND_EVEN (1 << 0) + +/* This operand must be an odd register number and must be one greater than + the register number of the previous operand. I.E. the second register in + an even/odd register pair. */ + +#define TIC80_OPERAND_ODD (1 << 1) + +/* This operand takes signed values. */ + +#define TIC80_OPERAND_SIGNED (1 << 2) + +/* This operand may be either a predefined constant name or a numeric value. + An example would be a condition code like "eq0.b" which has the numeric + value 0x2. */ + +#define TIC80_OPERAND_NUM (1 << 3) + +/* This operand should be wrapped in parentheses rather than separated + from the previous one by a comma. This is used for various + instructions, like the load and store instructions, which want + their operands to look like "displacement(reg)" */ + +#define TIC80_OPERAND_PARENS (1 << 4) + +/* This operand is a PC relative branch offset. The disassembler prints + these symbolically if possible. Note that the offsets are taken as word + offsets. */ + +#define TIC80_OPERAND_PCREL (1 << 5) + +/* This flag is a hint to the disassembler for using hex as the prefered + printing format, even for small positive or negative immediate values. + Normally values in the range -999 to 999 are printed as signed decimal + values and other values are printed in hex. */ + +#define TIC80_OPERAND_BITFIELD (1 << 6) + +/* This operand may have a ":m" modifier specified by bit 17 in a short + immediate form instruction. */ + +#define TIC80_OPERAND_M_SI (1 << 7) + +/* This operand may have a ":m" modifier specified by bit 15 in a long + immediate or register form instruction. */ + +#define TIC80_OPERAND_M_LI (1 << 8) + +/* This operand may have a ":s" modifier specified in bit 11 in a long + immediate or register form instruction. */ + +#define TIC80_OPERAND_SCALED (1 << 9) + +/* This operand is a floating point value */ + +#define TIC80_OPERAND_FLOAT (1 << 10) + +/* This operand is an byte offset from a base relocation. The lower + two bits of the final relocated address are ignored when the value is + written to the program counter. */ + +#define TIC80_OPERAND_BASEREL (1 << 11) + +/* This operand is an "endmask" field for a shift instruction. + It is treated special in that it can have values of 0-32, + where 0 and 32 result in the same instruction. The assembler + must be able to accept both endmask values. This disassembler + has no way of knowing from the instruction which value was + given at assembly time, so it just uses '0'. */ + +#define TIC80_OPERAND_ENDMASK (1 << 12) + +/* This operand is one of the 32 general purpose registers. + The disassembler prints these with a leading 'r'. */ + +#define TIC80_OPERAND_GPR (1 << 27) + +/* This operand is a floating point accumulator register. + The disassembler prints these with a leading 'a'. */ + +#define TIC80_OPERAND_FPA ( 1 << 28) + +/* This operand is a control register number, either numeric or + symbolic (like "EIF", "EPC", etc). + The disassembler prints these symbolically. */ + +#define TIC80_OPERAND_CR (1 << 29) + +/* This operand is a condition code, either numeric or + symbolic (like "eq0.b", "ne0.w", etc). + The disassembler prints these symbolically. */ + +#define TIC80_OPERAND_CC (1 << 30) + +/* This operand is a bit number, either numeric or + symbolic (like "eq.b", "or.f", etc). + The disassembler prints these symbolically. + Note that they appear in the instruction in 1's complement relative + to the values given in the manual. */ + +#define TIC80_OPERAND_BITNUM (1 << 31) + +/* This mask is used to strip operand bits from an int that contains + both operand bits and a numeric value in the lsbs. */ + +#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM) + + +/* Flag bits for the struct tic80_opcode flags field. */ + +#define TIC80_VECTOR 01 /* Is a vector instruction */ +#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */ + + +/* The opcodes library contains a table that allows translation from predefined + symbol names to numeric values, and vice versa. */ + +/* Structure to hold information about predefined symbols. */ + +struct predefined_symbol +{ + char *name; /* name to recognize */ + int value; +}; + +#define PDS_NAME(pdsp) ((pdsp) -> name) +#define PDS_VALUE(pdsp) ((pdsp) -> value) + +/* Translation array. */ +extern const struct predefined_symbol tic80_predefined_symbols[]; +/* How many members in the array. */ +extern const int tic80_num_predefined_symbols; + +/* Translate value to symbolic name. */ +const char *tic80_value_to_symbol (int val, int class); + +/* Translate symbolic name to value. */ +int tic80_symbol_to_value (char *name, int class); + +const struct predefined_symbol *tic80_next_predefined_symbol + (const struct predefined_symbol *); + +#endif /* TIC80_H */ diff --git a/include/opcode/v850.h b/include/opcode/v850.h new file mode 100644 index 000000000..75689bff6 --- /dev/null +++ b/include/opcode/v850.h @@ -0,0 +1,166 @@ +/* v850.h -- Header file for NEC V850 opcode table + Copyright 1996, 1997, 2001, 2003 Free Software Foundation, Inc. + Written by J.T. Conklin, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef V850_H +#define V850_H + +/* The opcode table is an array of struct v850_opcode. */ + +struct v850_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; + + /* Which (if any) operand is a memory operand. */ + unsigned int memop; + + /* Target processor(s). A bit field of processors which support + this instruction. Note a bit field is used as some instructions + are available on multiple, different processor types, whereas + other instructions are only available on one specific type. */ + unsigned int processors; +}; + +/* Values for the processors field in the v850_opcode structure. */ +#define PROCESSOR_V850 (1 << 0) /* Just the V850. */ +#define PROCESSOR_ALL -1 /* Any processor. */ +#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */ +#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */ +#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */ +#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */ + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct v850_opcode v850_opcodes[]; +extern const int v850_num_opcodes; + + +/* The operands table is an array of struct v850_operand. */ + +struct v850_operand +{ + /* The number of bits in the operand. */ + /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */ + int bits; + + /* (bits >= 0): How far the operand is left shifted in the instruction. */ + /* (bits == -1): Bit mask of the bits in the operand. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (* insert) + (unsigned long instruction, long op, const char ** errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); + if (o->flags & V850_OPERAND_SIGNED) + op = (op << (32 - o->bits)) >> (32 - o->bits); + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + unsigned long (* extract) (unsigned long instruction, int * invalid); + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the v850_opcodes table. */ + +extern const struct v850_operand v850_operands[]; + +/* Values defined for the flags field of a struct v850_operand. */ + +/* This operand names a general purpose register */ +#define V850_OPERAND_REG 0x01 + +/* This operand names a system register */ +#define V850_OPERAND_SRG 0x02 + +/* This operand names a condition code used in the setf instruction */ +#define V850_OPERAND_CC 0x04 + +/* This operand takes signed values */ +#define V850_OPERAND_SIGNED 0x08 + +/* This operand is the ep register. */ +#define V850_OPERAND_EP 0x10 + +/* This operand is a PC displacement */ +#define V850_OPERAND_DISP 0x20 + +/* This is a relaxable operand. Only used for D9->D22 branch relaxing + right now. We may need others in the future (or maybe handle them like + promoted operands on the mn10300?) */ +#define V850_OPERAND_RELAX 0x40 + +/* The register specified must not be r0 */ +#define V850_NOT_R0 0x80 + +/* push/pop type instruction, V850E specific. */ +#define V850E_PUSH_POP 0x100 + +/* 16 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE16 0x200 + +/* 32 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE32 0x400 + +#endif /* V850_H */ diff --git a/include/opcode/vax.h b/include/opcode/vax.h new file mode 100644 index 000000000..6fda6b255 --- /dev/null +++ b/include/opcode/vax.h @@ -0,0 +1,382 @@ +/* Vax opcde list. + Copyright 1989, 1991, 1992, 1995 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef vax_opcodeT +#define vax_opcodeT int +#endif /* no vax_opcodeT */ + +struct vot_wot /* vax opcode table: wot to do with this */ + /* particular opcode */ +{ + const char *args; /* how to compile said opcode */ + vax_opcodeT code; /* op-code (may be > 8 bits!) */ +}; + +struct vot /* vax opcode text */ +{ + const char *name; /* opcode name: lowercase string [key] */ + struct vot_wot detail; /* rest of opcode table [datum] */ +}; + +#define vot_how args +#define vot_code code +#define vot_detail detail +#define vot_name name + +static const struct vot +votstrs[] = +{ +{ "halt", {"", 0x00 } }, +{ "nop", {"", 0x01 } }, +{ "rei", {"", 0x02 } }, +{ "bpt", {"", 0x03 } }, +{ "ret", {"", 0x04 } }, +{ "rsb", {"", 0x05 } }, +{ "ldpctx", {"", 0x06 } }, +{ "svpctx", {"", 0x07 } }, +{ "cvtps", {"rwabrwab", 0x08 } }, +{ "cvtsp", {"rwabrwab", 0x09 } }, +{ "index", {"rlrlrlrlrlwl", 0x0a } }, +{ "crc", {"abrlrwab", 0x0b } }, +{ "prober", {"rbrwab", 0x0c } }, +{ "probew", {"rbrwab", 0x0d } }, +{ "insque", {"abab", 0x0e } }, +{ "remque", {"abwl", 0x0f } }, +{ "bsbb", {"bb", 0x10 } }, +{ "brb", {"bb", 0x11 } }, +{ "bneq", {"bb", 0x12 } }, +{ "bnequ", {"bb", 0x12 } }, +{ "beql", {"bb", 0x13 } }, +{ "beqlu", {"bb", 0x13 } }, +{ "bgtr", {"bb", 0x14 } }, +{ "bleq", {"bb", 0x15 } }, +{ "jsb", {"ab", 0x16 } }, +{ "jmp", {"ab", 0x17 } }, +{ "bgeq", {"bb", 0x18 } }, +{ "blss", {"bb", 0x19 } }, +{ "bgtru", {"bb", 0x1a } }, +{ "blequ", {"bb", 0x1b } }, +{ "bvc", {"bb", 0x1c } }, +{ "bvs", {"bb", 0x1d } }, +{ "bcc", {"bb", 0x1e } }, +{ "bgequ", {"bb", 0x1e } }, +{ "blssu", {"bb", 0x1f } }, +{ "bcs", {"bb", 0x1f } }, +{ "addp4", {"rwabrwab", 0x20 } }, +{ "addp6", {"rwabrwabrwab", 0x21 } }, +{ "subp4", {"rwabrwab", 0x22 } }, +{ "subp6", {"rwabrwabrwab", 0x23 } }, +{ "cvtpt", {"rwababrwab", 0x24 } }, +{ "mulp", {"rwabrwabrwab", 0x25 } }, +{ "cvttp", {"rwababrwab", 0x26 } }, +{ "divp", {"rwabrwabrwab", 0x27 } }, +{ "movc3", {"rwabab", 0x28 } }, +{ "cmpc3", {"rwabab", 0x29 } }, +{ "scanc", {"rwababrb", 0x2a } }, +{ "spanc", {"rwababrb", 0x2b } }, +{ "movc5", {"rwabrbrwab", 0x2c } }, +{ "cmpc5", {"rwabrbrwab", 0x2d } }, +{ "movtc", {"rwabrbabrwab", 0x2e } }, +{ "movtuc", {"rwabrbabrwab", 0x2f } }, +{ "bsbw", {"bw", 0x30 } }, +{ "brw", {"bw", 0x31 } }, +{ "cvtwl", {"rwwl", 0x32 } }, +{ "cvtwb", {"rwwb", 0x33 } }, +{ "movp", {"rwabab", 0x34 } }, +{ "cmpp3", {"rwabab", 0x35 } }, +{ "cvtpl", {"rwabwl", 0x36 } }, +{ "cmpp4", {"rwabrwab", 0x37 } }, +{ "editpc", {"rwababab", 0x38 } }, +{ "matchc", {"rwabrwab", 0x39 } }, +{ "locc", {"rbrwab", 0x3a } }, +{ "skpc", {"rbrwab", 0x3b } }, +{ "movzwl", {"rwwl", 0x3c } }, +{ "acbw", {"rwrwmwbw", 0x3d } }, +{ "movaw", {"awwl", 0x3e } }, +{ "pushaw", {"aw", 0x3f } }, +{ "addf2", {"rfmf", 0x40 } }, +{ "addf3", {"rfrfwf", 0x41 } }, +{ "subf2", {"rfmf", 0x42 } }, +{ "subf3", {"rfrfwf", 0x43 } }, +{ "mulf2", {"rfmf", 0x44 } }, +{ "mulf3", {"rfrfwf", 0x45 } }, +{ "divf2", {"rfmf", 0x46 } }, +{ "divf3", {"rfrfwf", 0x47 } }, +{ "cvtfb", {"rfwb", 0x48 } }, +{ "cvtfw", {"rfww", 0x49 } }, +{ "cvtfl", {"rfwl", 0x4a } }, +{ "cvtrfl", {"rfwl", 0x4b } }, +{ "cvtbf", {"rbwf", 0x4c } }, +{ "cvtwf", {"rwwf", 0x4d } }, +{ "cvtlf", {"rlwf", 0x4e } }, +{ "acbf", {"rfrfmfbw", 0x4f } }, +{ "movf", {"rfwf", 0x50 } }, +{ "cmpf", {"rfrf", 0x51 } }, +{ "mnegf", {"rfwf", 0x52 } }, +{ "tstf", {"rf", 0x53 } }, +{ "emodf", {"rfrbrfwlwf", 0x54 } }, +{ "polyf", {"rfrwab", 0x55 } }, +{ "cvtfd", {"rfwd", 0x56 } }, + /* opcode 57 is not defined yet */ +{ "adawi", {"rwmw", 0x58 } }, + /* opcode 59 is not defined yet */ + /* opcode 5a is not defined yet */ + /* opcode 5b is not defined yet */ +{ "insqhi", {"abaq", 0x5c } }, +{ "insqti", {"abaq", 0x5d } }, +{ "remqhi", {"aqwl", 0x5e } }, +{ "remqti", {"aqwl", 0x5f } }, +{ "addd2", {"rdmd", 0x60 } }, +{ "addd3", {"rdrdwd", 0x61 } }, +{ "subd2", {"rdmd", 0x62 } }, +{ "subd3", {"rdrdwd", 0x63 } }, +{ "muld2", {"rdmd", 0x64 } }, +{ "muld3", {"rdrdwd", 0x65 } }, +{ "divd2", {"rdmd", 0x66 } }, +{ "divd3", {"rdrdwd", 0x67 } }, +{ "cvtdb", {"rdwb", 0x68 } }, +{ "cvtdw", {"rdww", 0x69 } }, +{ "cvtdl", {"rdwl", 0x6a } }, +{ "cvtrdl", {"rdwl", 0x6b } }, +{ "cvtbd", {"rbwd", 0x6c } }, +{ "cvtwd", {"rwwd", 0x6d } }, +{ "cvtld", {"rlwd", 0x6e } }, +{ "acbd", {"rdrdmdbw", 0x6f } }, +{ "movd", {"rdwd", 0x70 } }, +{ "cmpd", {"rdrd", 0x71 } }, +{ "mnegd", {"rdwd", 0x72 } }, +{ "tstd", {"rd", 0x73 } }, +{ "emodd", {"rdrbrdwlwd", 0x74 } }, +{ "polyd", {"rdrwab", 0x75 } }, +{ "cvtdf", {"rdwf", 0x76 } }, + /* opcode 77 is not defined yet */ +{ "ashl", {"rbrlwl", 0x78 } }, +{ "ashq", {"rbrqwq", 0x79 } }, +{ "emul", {"rlrlrlwq", 0x7a } }, +{ "ediv", {"rlrqwlwl", 0x7b } }, +{ "clrd", {"wd", 0x7c } }, +{ "clrg", {"wg", 0x7c } }, +{ "clrq", {"wd", 0x7c } }, +{ "movq", {"rqwq", 0x7d } }, +{ "movaq", {"aqwl", 0x7e } }, +{ "movad", {"adwl", 0x7e } }, +{ "pushaq", {"aq", 0x7f } }, +{ "pushad", {"ad", 0x7f } }, +{ "addb2", {"rbmb", 0x80 } }, +{ "addb3", {"rbrbwb", 0x81 } }, +{ "subb2", {"rbmb", 0x82 } }, +{ "subb3", {"rbrbwb", 0x83 } }, +{ "mulb2", {"rbmb", 0x84 } }, +{ "mulb3", {"rbrbwb", 0x85 } }, +{ "divb2", {"rbmb", 0x86 } }, +{ "divb3", {"rbrbwb", 0x87 } }, +{ "bisb2", {"rbmb", 0x88 } }, +{ "bisb3", {"rbrbwb", 0x89 } }, +{ "bicb2", {"rbmb", 0x8a } }, +{ "bicb3", {"rbrbwb", 0x8b } }, +{ "xorb2", {"rbmb", 0x8c } }, +{ "xorb3", {"rbrbwb", 0x8d } }, +{ "mnegb", {"rbwb", 0x8e } }, +{ "caseb", {"rbrbrb", 0x8f } }, +{ "movb", {"rbwb", 0x90 } }, +{ "cmpb", {"rbrb", 0x91 } }, +{ "mcomb", {"rbwb", 0x92 } }, +{ "bitb", {"rbrb", 0x93 } }, +{ "clrb", {"wb", 0x94 } }, +{ "tstb", {"rb", 0x95 } }, +{ "incb", {"mb", 0x96 } }, +{ "decb", {"mb", 0x97 } }, +{ "cvtbl", {"rbwl", 0x98 } }, +{ "cvtbw", {"rbww", 0x99 } }, +{ "movzbl", {"rbwl", 0x9a } }, +{ "movzbw", {"rbww", 0x9b } }, +{ "rotl", {"rbrlwl", 0x9c } }, +{ "acbb", {"rbrbmbbw", 0x9d } }, +{ "movab", {"abwl", 0x9e } }, +{ "pushab", {"ab", 0x9f } }, +{ "addw2", {"rwmw", 0xa0 } }, +{ "addw3", {"rwrwww", 0xa1 } }, +{ "subw2", {"rwmw", 0xa2 } }, +{ "subw3", {"rwrwww", 0xa3 } }, +{ "mulw2", {"rwmw", 0xa4 } }, +{ "mulw3", {"rwrwww", 0xa5 } }, +{ "divw2", {"rwmw", 0xa6 } }, +{ "divw3", {"rwrwww", 0xa7 } }, +{ "bisw2", {"rwmw", 0xa8 } }, +{ "bisw3", {"rwrwww", 0xa9 } }, +{ "bicw2", {"rwmw", 0xaa } }, +{ "bicw3", {"rwrwww", 0xab } }, +{ "xorw2", {"rwmw", 0xac } }, +{ "xorw3", {"rwrwww", 0xad } }, +{ "mnegw", {"rwww", 0xae } }, +{ "casew", {"rwrwrw", 0xaf } }, +{ "movw", {"rwww", 0xb0 } }, +{ "cmpw", {"rwrw", 0xb1 } }, +{ "mcomw", {"rwww", 0xb2 } }, +{ "bitw", {"rwrw", 0xb3 } }, +{ "clrw", {"ww", 0xb4 } }, +{ "tstw", {"rw", 0xb5 } }, +{ "incw", {"mw", 0xb6 } }, +{ "decw", {"mw", 0xb7 } }, +{ "bispsw", {"rw", 0xb8 } }, +{ "bicpsw", {"rw", 0xb9 } }, +{ "popr", {"rw", 0xba } }, +{ "pushr", {"rw", 0xbb } }, +{ "chmk", {"rw", 0xbc } }, +{ "chme", {"rw", 0xbd } }, +{ "chms", {"rw", 0xbe } }, +{ "chmu", {"rw", 0xbf } }, +{ "addl2", {"rlml", 0xc0 } }, +{ "addl3", {"rlrlwl", 0xc1 } }, +{ "subl2", {"rlml", 0xc2 } }, +{ "subl3", {"rlrlwl", 0xc3 } }, +{ "mull2", {"rlml", 0xc4 } }, +{ "mull3", {"rlrlwl", 0xc5 } }, +{ "divl2", {"rlml", 0xc6 } }, +{ "divl3", {"rlrlwl", 0xc7 } }, +{ "bisl2", {"rlml", 0xc8 } }, +{ "bisl3", {"rlrlwl", 0xc9 } }, +{ "bicl2", {"rlml", 0xca } }, +{ "bicl3", {"rlrlwl", 0xcb } }, +{ "xorl2", {"rlml", 0xcc } }, +{ "xorl3", {"rlrlwl", 0xcd } }, +{ "mnegl", {"rlwl", 0xce } }, +{ "casel", {"rlrlrl", 0xcf } }, +{ "movl", {"rlwl", 0xd0 } }, +{ "cmpl", {"rlrl", 0xd1 } }, +{ "mcoml", {"rlwl", 0xd2 } }, +{ "bitl", {"rlrl", 0xd3 } }, +{ "clrf", {"wf", 0xd4 } }, +{ "clrl", {"wl", 0xd4 } }, +{ "tstl", {"rl", 0xd5 } }, +{ "incl", {"ml", 0xd6 } }, +{ "decl", {"ml", 0xd7 } }, +{ "adwc", {"rlml", 0xd8 } }, +{ "sbwc", {"rlml", 0xd9 } }, +{ "mtpr", {"rlrl", 0xda } }, +{ "mfpr", {"rlwl", 0xdb } }, +{ "movpsl", {"wl", 0xdc } }, +{ "pushl", {"rl", 0xdd } }, +{ "moval", {"alwl", 0xde } }, +{ "movaf", {"afwl", 0xde } }, +{ "pushal", {"al", 0xdf } }, +{ "pushaf", {"af", 0xdf } }, +{ "bbs", {"rlvbbb", 0xe0 } }, +{ "bbc", {"rlvbbb", 0xe1 } }, +{ "bbss", {"rlvbbb", 0xe2 } }, +{ "bbcs", {"rlvbbb", 0xe3 } }, +{ "bbsc", {"rlvbbb", 0xe4 } }, +{ "bbcc", {"rlvbbb", 0xe5 } }, +{ "bbssi", {"rlvbbb", 0xe6 } }, +{ "bbcci", {"rlvbbb", 0xe7 } }, +{ "blbs", {"rlbb", 0xe8 } }, +{ "blbc", {"rlbb", 0xe9 } }, +{ "ffs", {"rlrbvbwl", 0xea } }, +{ "ffc", {"rlrbvbwl", 0xeb } }, +{ "cmpv", {"rlrbvbrl", 0xec } }, +{ "cmpzv", {"rlrbvbrl", 0xed } }, +{ "extv", {"rlrbvbwl", 0xee } }, +{ "extzv", {"rlrbvbwl", 0xef } }, +{ "insv", {"rlrlrbvb", 0xf0 } }, +{ "acbl", {"rlrlmlbw", 0xf1 } }, +{ "aoblss", {"rlmlbb", 0xf2 } }, +{ "aobleq", {"rlmlbb", 0xf3 } }, +{ "sobgeq", {"mlbb", 0xf4 } }, +{ "sobgtr", {"mlbb", 0xf5 } }, +{ "cvtlb", {"rlwb", 0xf6 } }, +{ "cvtlw", {"rlww", 0xf7 } }, +{ "ashp", {"rbrwabrbrwab", 0xf8 } }, +{ "cvtlp", {"rlrwab", 0xf9 } }, +{ "callg", {"abab", 0xfa } }, +{ "calls", {"rlab", 0xfb } }, +{ "xfc", {"", 0xfc } }, + /* undefined opcodes here */ +{ "cvtdh", {"rdwh", 0x32fd } }, +{ "cvtgf", {"rgwh", 0x33fd } }, +{ "addg2", {"rgmg", 0x40fd } }, +{ "addg3", {"rgrgwg", 0x41fd } }, +{ "subg2", {"rgmg", 0x42fd } }, +{ "subg3", {"rgrgwg", 0x43fd } }, +{ "mulg2", {"rgmg", 0x44fd } }, +{ "mulg3", {"rgrgwg", 0x45fd } }, +{ "divg2", {"rgmg", 0x46fd } }, +{ "divg3", {"rgrgwg", 0x47fd } }, +{ "cvtgb", {"rgwb", 0x48fd } }, +{ "cvtgw", {"rgww", 0x49fd } }, +{ "cvtgl", {"rgwl", 0x4afd } }, +{ "cvtrgl", {"rgwl", 0x4bfd } }, +{ "cvtbg", {"rbwg", 0x4cfd } }, +{ "cvtwg", {"rwwg", 0x4dfd } }, +{ "cvtlg", {"rlwg", 0x4efd } }, +{ "acbg", {"rgrgmgbw", 0x4ffd } }, +{ "movg", {"rgwg", 0x50fd } }, +{ "cmpg", {"rgrg", 0x51fd } }, +{ "mnegg", {"rgwg", 0x52fd } }, +{ "tstg", {"rg", 0x53fd } }, +{ "emodg", {"rgrwrgwlwg", 0x54fd } }, +{ "polyg", {"rgrwab", 0x55fd } }, +{ "cvtgh", {"rgwh", 0x56fd } }, + /* undefined opcodes here */ +{ "addh2", {"rhmh", 0x60fd } }, +{ "addh3", {"rhrhwh", 0x61fd } }, +{ "subh2", {"rhmh", 0x62fd } }, +{ "subh3", {"rhrhwh", 0x63fd } }, +{ "mulh2", {"rhmh", 0x64fd } }, +{ "mulh3", {"rhrhwh", 0x65fd } }, +{ "divh2", {"rhmh", 0x66fd } }, +{ "divh3", {"rhrhwh", 0x67fd } }, +{ "cvthb", {"rhwb", 0x68fd } }, +{ "cvthw", {"rhww", 0x69fd } }, +{ "cvthl", {"rhwl", 0x6afd } }, +{ "cvtrhl", {"rhwl", 0x6bfd } }, +{ "cvtbh", {"rbwh", 0x6cfd } }, +{ "cvtwh", {"rwwh", 0x6dfd } }, +{ "cvtlh", {"rlwh", 0x6efd } }, +{ "acbh", {"rhrhmhbw", 0x6ffd } }, +{ "movh", {"rhwh", 0x70fd } }, +{ "cmph", {"rhrh", 0x71fd } }, +{ "mnegh", {"rhwh", 0x72fd } }, +{ "tsth", {"rh", 0x73fd } }, +{ "emodh", {"rhrwrhwlwh", 0x74fd } }, +{ "polyh", {"rhrwab", 0x75fd } }, +{ "cvthg", {"rhwg", 0x76fd } }, + /* undefined opcodes here */ +{ "clrh", {"wh", 0x7cfd } }, +{ "clro", {"wo", 0x7cfd } }, +{ "movo", {"rowo", 0x7dfd } }, +{ "movah", {"ahwl", 0x7efd } }, +{ "movao", {"aowl", 0x7efd } }, +{ "pushah", {"ah", 0x7ffd } }, +{ "pushao", {"ao", 0x7ffd } }, + /* undefined opcodes here */ +{ "cvtfh", {"rfwh", 0x98fd } }, +{ "cvtfg", {"rfwg", 0x99fd } }, + /* undefined opcodes here */ +{ "cvthf", {"rhwf", 0xf6fd } }, +{ "cvthd", {"rhwd", 0xf7fd } }, + /* undefined opcodes here */ +{ "bugl", {"rl", 0xfdff } }, +{ "bugw", {"rw", 0xfeff } }, + /* undefined opcodes here */ + +{ "", {"", 0} } /* empty is end sentinel */ + +}; /* votstrs */ + +/* end: vax.opcode.h */ diff --git a/include/os9k.h b/include/os9k.h new file mode 100644 index 000000000..596f56d5a --- /dev/null +++ b/include/os9k.h @@ -0,0 +1,181 @@ +/* os9k.h - OS-9000 i386 module header definitions + Copyright 2000 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#if !defined(_MODULE_H) +#define _MODULE_H + +#define _MPF386 + +/* Size of common header less parity field. */ +#define N_M_PARITY (sizeof(mh_com)-sizeof(unisgned short)) +#define OLD_M_PARITY 46 +#define M_PARITY N_M_PARITY + +#ifdef _MPF68K +#define MODSYNC 0x4afc /* Module header sync code for 680x0 processors. */ +#endif + +#ifdef _MPF386 +#define MODSYNC 0x4afc /* Module header sync code for 80386 processors. */ +#endif + +#define MODREV 1 /* Module format revision 1. */ +#define CRCCON 0x800063 /* CRC polynomial constant. */ + +/* Module access permission values. */ +#define MP_OWNER_READ 0x0001 +#define MP_OWNER_WRITE 0x0002 +#define MP_OWNER_EXEC 0x0004 +#define MP_GROUP_READ 0x0010 +#define MP_GROUP_WRITE 0x0020 +#define MP_GROUP_EXEC 0x0040 +#define MP_WORLD_READ 0x0100 +#define MP_WORLD_WRITE 0x0200 +#define MP_WORLD_EXEC 0x0400 +#define MP_WORLD_ACCESS 0x0777 +#define MP_OWNER_MASK 0x000f +#define MP_GROUP_MASK 0x00f0 +#define MP_WORLD_MASK 0x0f00 +#define MP_SYSTM_MASK 0xf000 + +/* Module Type/Language values. */ +#define MT_ANY 0 +#define MT_PROGRAM 0x0001 +#define MT_SUBROUT 0x0002 +#define MT_MULTI 0x0003 +#define MT_DATA 0x0004 +#define MT_TRAPLIB 0x000b +#define MT_SYSTEM 0x000c +#define MT_FILEMAN 0x000d +#define MT_DEVDRVR 0x000e +#define MT_DEVDESC 0x000f +#define MT_MASK 0xff00 + +#define ML_ANY 0 +#define ML_OBJECT 1 +#define ML_ICODE 2 +#define ML_PCODE 3 +#define ML_CCODE 4 +#define ML_CBLCODE 5 +#define ML_FRTNCODE 6 +#define ML_MASK 0x00ff + +#define mktypelang(type, lang) (((type) << 8) | (lang)) + +/* Module Attribute values. */ +#define MA_REENT 0x80 +#define MA_GHOST 0x40 +#define MA_SUPER 0x20 +#define MA_MASK 0xff00 +#define MR_MASK 0x00ff + +#define mkattrevs(attr, revs) (((attr) << 8) | (revs)) + +#define m_user m_owner.grp_usr.usr +#define m_group m_owner.grp_usr.grp +#define m_group_user m_owner.group_user + +/* Macro definitions for accessing module header fields. */ +#define MODNAME(mod) ((u_char*)((u_char*)mod + ((Mh_com)mod)->m_name)) +#if 0 +/* Appears not to be used, and the u_int32 typedef is gone (because it + conflicted with a Mach header. */ +#define MODSIZE(mod) ((u_int32)((Mh_com)mod)->m_size) +#endif /* 0 */ +#define MHCOM_BYTES_SIZE 80 +#define N_BADMAG(a) (((a).a_info) != MODSYNC) + +typedef struct mh_com +{ + /* Sync bytes ($4afc). */ + unsigned char m_sync[2]; + unsigned char m_sysrev[2]; /* System revision check value. */ + unsigned char m_size[4]; /* Module size. */ + unsigned char m_owner[4]; /* Group/user id. */ + unsigned char m_name[4]; /* Offset to module name. */ + unsigned char m_access[2]; /* Access permissions. */ + unsigned char m_tylan[2]; /* Type/lang. */ + unsigned char m_attrev[2]; /* Rev/attr. */ + unsigned char m_edit[2]; /* Edition. */ + unsigned char m_needs[4]; /* Module hardware requirements flags. (reserved). */ + unsigned char m_usage[4]; /* Comment string offset. */ + unsigned char m_symbol[4]; /* Symbol table offset. */ + unsigned char m_exec[4]; /* Offset to execution entry point. */ + unsigned char m_excpt[4]; /* Offset to exception entry point. */ + unsigned char m_data[4]; /* Data storage requirement. */ + unsigned char m_stack[4]; /* Stack size. */ + unsigned char m_idata[4]; /* Offset to initialized data. */ + unsigned char m_idref[4]; /* Offset to data reference lists. */ + unsigned char m_init[4]; /* Initialization routine offset. */ + unsigned char m_term[4]; /* Termination routine offset. */ + unsigned char m_ident[2]; /* Ident code for ident program. */ + char m_spare[8]; /* Reserved bytes. */ + unsigned char m_parity[2]; /* Header parity. */ +} mh_com,*Mh_com; + +/* Executable memory module. */ +typedef mh_com *Mh_exec,mh_exec; + +/* Data memory module. */ +typedef mh_com *Mh_data,mh_data; + +/* File manager memory module. */ +typedef mh_com *Mh_fman,mh_fman; + +/* Device driver module. */ +typedef mh_com *Mh_drvr,mh_drvr; + +/* Trap handler module. */ +typedef mh_com mh_trap, *Mh_trap; + +/* Device descriptor module. */ +typedef mh_com *Mh_dev,mh_dev; + +/* Configuration module. */ +typedef mh_com *Mh_config, mh_config; + +#if 0 + +#if !defined(_MODDIR_H) +/* Go get _os_fmod (and others). */ +#include <moddir.h> +#endif + +error_code _os_crc (void *, u_int32, int *); +error_code _os_datmod (char *, u_int32, u_int16 *, u_int16 *, u_int32, void **, mh_data **); +error_code _os_get_moddir (void *, u_int32 *); +error_code _os_initdata (mh_com *, void *); +error_code _os_link (char **, mh_com **, void **, u_int16 *, u_int16 *); +error_code _os_linkm (mh_com *, void **, u_int16 *, u_int16 *); +error_code _os_load (char *, mh_com **, void **, u_int32, u_int16 *, u_int16 *, u_int32); +error_code _os_mkmodule (char *, u_int32, u_int16 *, u_int16 *, u_int32, void **, mh_com **, u_int32); +error_code _os_modaddr (void *, mh_com **); +error_code _os_setcrc (mh_com *); +error_code _os_slink (u_int32, char *, void **, void **, mh_com **); +error_code _os_slinkm (u_int32, mh_com *, void **, void **); +error_code _os_unlink (mh_com *); +error_code _os_unload (char *, u_int32); +error_code _os_tlink (u_int32, char *, void **, mh_trap **, void *, u_int32); +error_code _os_tlinkm (u_int32, mh_com *, void **, void *, u_int32); +error_code _os_iodel (mh_com *); +error_code _os_vmodul (mh_com *, mh_com *, u_int32); +#endif /* 0 */ + +#endif diff --git a/include/partition.h b/include/partition.h new file mode 100644 index 000000000..5d3623f71 --- /dev/null +++ b/include/partition.h @@ -0,0 +1,85 @@ +/* List implementation of a partition of consecutive integers. + Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by CodeSourcery, LLC. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* This package implements a partition of consecutive integers. The + elements are partitioned into classes. Each class is represented + by one of its elements, the canonical element, which is chosen + arbitrarily from elements in the class. The principal operations + on a partition are FIND, which takes an element, determines its + class, and returns the canonical element for that class, and UNION, + which unites the two classes that contain two given elements into a + single class. + + The list implementation used here provides constant-time finds. By + storing the size of each class with the class's canonical element, + it is able to perform unions over all the classes in the partition + in O (N log N) time. */ + +#ifndef _PARTITION_H +#define _PARTITION_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ansidecl.h" +#include <stdio.h> + +struct partition_elem +{ + /* The canonical element that represents the class containing this + element. */ + int class_element; + /* The next element in this class. Elements in each class form a + circular list. */ + struct partition_elem* next; + /* The number of elements in this class. Valid only if this is the + canonical element for its class. */ + unsigned class_count; +}; + +typedef struct partition_def +{ + /* The number of elements in this partition. */ + int num_elements; + /* The elements in the partition. */ + struct partition_elem elements[1]; +} *partition; + +extern partition partition_new PARAMS((int)); +extern void partition_delete PARAMS((partition)); +extern int partition_union PARAMS((partition, + int, + int)); +extern void partition_print PARAMS((partition, + FILE*)); + +/* Returns the canonical element corresponding to the class containing + ELEMENT__ in PARTITION__. */ + +#define partition_find(partition__, element__) \ + ((partition__)->elements[(element__)].class_element) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _PARTITION_H */ diff --git a/include/progress.h b/include/progress.h new file mode 100644 index 000000000..23b096007 --- /dev/null +++ b/include/progress.h @@ -0,0 +1,37 @@ +/* Default definitions for progress macros. + Copyright 1994 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* The default definitions below are intended to be replaced by real + definitions, if building the tools for an interactive programming + environment. */ + +#ifndef _PROGRESS_H +#define _PROGRESS_H + +#ifndef START_PROGRESS +#define START_PROGRESS(STR,N) +#endif + +#ifndef PROGRESS +#define PROGRESS(X) +#endif + +#ifndef END_PROGRESS +#define END_PROGRESS(STR) +#endif + +#endif /* _PROGRESS_H */ diff --git a/include/safe-ctype.h b/include/safe-ctype.h new file mode 100644 index 000000000..69a3f74cc --- /dev/null +++ b/include/safe-ctype.h @@ -0,0 +1,119 @@ +/* <ctype.h> replacement macros. + + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Contributed by Zack Weinberg <zackw@stanford.edu>. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is a compatible replacement of the standard C library's <ctype.h> + with the following properties: + + - Implements all isxxx() macros required by C99. + - Also implements some character classes useful when + parsing C-like languages. + - Does not change behavior depending on the current locale. + - Behaves properly for all values in the range of a signed or + unsigned char. + + To avoid conflicts, this header defines the isxxx functions in upper + case, e.g. ISALPHA not isalpha. */ + +#ifndef SAFE_CTYPE_H +#define SAFE_CTYPE_H + +#ifdef isalpha + #error "safe-ctype.h and ctype.h may not be used simultaneously" +#endif + +/* Determine host character set. */ +#define HOST_CHARSET_UNKNOWN 0 +#define HOST_CHARSET_ASCII 1 +#define HOST_CHARSET_EBCDIC 2 + +#if '\n' == 0x0A && ' ' == 0x20 && '0' == 0x30 \ + && 'A' == 0x41 && 'a' == 0x61 && '!' == 0x21 +# define HOST_CHARSET HOST_CHARSET_ASCII +#else +# if '\n' == 0x15 && ' ' == 0x40 && '0' == 0xF0 \ + && 'A' == 0xC1 && 'a' == 0x81 && '!' == 0x5A +# define HOST_CHARSET HOST_CHARSET_EBCDIC +# else +# define HOST_CHARSET HOST_CHARSET_UNKNOWN +# endif +#endif + +/* Categories. */ + +enum { + /* In C99 */ + _sch_isblank = 0x0001, /* space \t */ + _sch_iscntrl = 0x0002, /* nonprinting characters */ + _sch_isdigit = 0x0004, /* 0-9 */ + _sch_islower = 0x0008, /* a-z */ + _sch_isprint = 0x0010, /* any printing character including ' ' */ + _sch_ispunct = 0x0020, /* all punctuation */ + _sch_isspace = 0x0040, /* space \t \n \r \f \v */ + _sch_isupper = 0x0080, /* A-Z */ + _sch_isxdigit = 0x0100, /* 0-9A-Fa-f */ + + /* Extra categories useful to cpplib. */ + _sch_isidst = 0x0200, /* A-Za-z_ */ + _sch_isvsp = 0x0400, /* \n \r */ + _sch_isnvsp = 0x0800, /* space \t \f \v \0 */ + + /* Combinations of the above. */ + _sch_isalpha = _sch_isupper|_sch_islower, /* A-Za-z */ + _sch_isalnum = _sch_isalpha|_sch_isdigit, /* A-Za-z0-9 */ + _sch_isidnum = _sch_isidst|_sch_isdigit, /* A-Za-z0-9_ */ + _sch_isgraph = _sch_isalnum|_sch_ispunct, /* isprint and not space */ + _sch_iscppsp = _sch_isvsp|_sch_isnvsp, /* isspace + \0 */ + _sch_isbasic = _sch_isprint|_sch_iscppsp /* basic charset of ISO C + (plus ` and @) */ +}; + +/* Character classification. */ +extern const unsigned short _sch_istable[256]; + +#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (unsigned short)(bit)) + +#define ISALPHA(c) _sch_test(c, _sch_isalpha) +#define ISALNUM(c) _sch_test(c, _sch_isalnum) +#define ISBLANK(c) _sch_test(c, _sch_isblank) +#define ISCNTRL(c) _sch_test(c, _sch_iscntrl) +#define ISDIGIT(c) _sch_test(c, _sch_isdigit) +#define ISGRAPH(c) _sch_test(c, _sch_isgraph) +#define ISLOWER(c) _sch_test(c, _sch_islower) +#define ISPRINT(c) _sch_test(c, _sch_isprint) +#define ISPUNCT(c) _sch_test(c, _sch_ispunct) +#define ISSPACE(c) _sch_test(c, _sch_isspace) +#define ISUPPER(c) _sch_test(c, _sch_isupper) +#define ISXDIGIT(c) _sch_test(c, _sch_isxdigit) + +#define ISIDNUM(c) _sch_test(c, _sch_isidnum) +#define ISIDST(c) _sch_test(c, _sch_isidst) +#define IS_ISOBASIC(c) _sch_test(c, _sch_isbasic) +#define IS_VSPACE(c) _sch_test(c, _sch_isvsp) +#define IS_NVSPACE(c) _sch_test(c, _sch_isnvsp) +#define IS_SPACE_OR_NUL(c) _sch_test(c, _sch_iscppsp) + +/* Character transformation. */ +extern const unsigned char _sch_toupper[256]; +extern const unsigned char _sch_tolower[256]; +#define TOUPPER(c) _sch_toupper[(c) & 0xff] +#define TOLOWER(c) _sch_tolower[(c) & 0xff] + +#endif /* SAFE_CTYPE_H */ diff --git a/include/sort.h b/include/sort.h new file mode 100644 index 000000000..3f3a92f18 --- /dev/null +++ b/include/sort.h @@ -0,0 +1,48 @@ +/* Sorting algorithms. + Copyright (C) 2000, 2002 Free Software Foundation, Inc. + Contributed by Mark Mitchell <mark@codesourcery.com>. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef SORT_H +#define SORT_H + +#include <sys/types.h> /* For size_t */ +#ifdef __STDC__ +#include <stddef.h> +#endif /* __STDC__ */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ansidecl.h" + +/* Sort an array of pointers. */ + +extern void sort_pointers PARAMS ((size_t, void **, void **)); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SORT_H */ + + + + diff --git a/include/splay-tree.h b/include/splay-tree.h new file mode 100644 index 000000000..e05aeb5af --- /dev/null +++ b/include/splay-tree.h @@ -0,0 +1,159 @@ +/* A splay-tree datatype. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. + Contributed by Mark Mitchell (mark@markmitchell.com). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* For an easily readable description of splay-trees, see: + + Lewis, Harry R. and Denenberg, Larry. Data Structures and Their + Algorithms. Harper-Collins, Inc. 1991. + + The major feature of splay trees is that all basic tree operations + are amortized O(log n) time for a tree with n nodes. */ + +#ifndef _SPLAY_TREE_H +#define _SPLAY_TREE_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ansidecl.h" + +#ifndef GTY +#define GTY(X) +#endif + +/* Use typedefs for the key and data types to facilitate changing + these types, if necessary. These types should be sufficiently wide + that any pointer or scalar can be cast to these types, and then + cast back, without loss of precision. */ +typedef unsigned long int splay_tree_key; +typedef unsigned long int splay_tree_value; + +/* Forward declaration for a node in the tree. */ +typedef struct splay_tree_node_s *splay_tree_node; + +/* The type of a function which compares two splay-tree keys. The + function should return values as for qsort. */ +typedef int (*splay_tree_compare_fn) PARAMS((splay_tree_key, splay_tree_key)); + +/* The type of a function used to deallocate any resources associated + with the key. */ +typedef void (*splay_tree_delete_key_fn) PARAMS((splay_tree_key)); + +/* The type of a function used to deallocate any resources associated + with the value. */ +typedef void (*splay_tree_delete_value_fn) PARAMS((splay_tree_value)); + +/* The type of a function used to iterate over the tree. */ +typedef int (*splay_tree_foreach_fn) PARAMS((splay_tree_node, void*)); + +/* The type of a function used to allocate memory for tree root and + node structures. The first argument is the number of bytes needed; + the second is a data pointer the splay tree functions pass through + to the allocator. This function must never return zero. */ +typedef PTR (*splay_tree_allocate_fn) PARAMS((int, void *)); + +/* The type of a function used to free memory allocated using the + corresponding splay_tree_allocate_fn. The first argument is the + memory to be freed; the latter is a data pointer the splay tree + functions pass through to the freer. */ +typedef void (*splay_tree_deallocate_fn) PARAMS((void *, void *)); + +/* The nodes in the splay tree. */ +struct splay_tree_node_s GTY(()) +{ + /* The key. */ + splay_tree_key GTY ((use_param1)) key; + + /* The value. */ + splay_tree_value GTY ((use_param2)) value; + + /* The left and right children, respectively. */ + splay_tree_node GTY ((use_params)) left; + splay_tree_node GTY ((use_params)) right; +}; + +/* The splay tree itself. */ +struct splay_tree_s GTY(()) +{ + /* The root of the tree. */ + splay_tree_node GTY ((use_params)) root; + + /* The comparision function. */ + splay_tree_compare_fn comp; + + /* The deallocate-key function. NULL if no cleanup is necessary. */ + splay_tree_delete_key_fn delete_key; + + /* The deallocate-value function. NULL if no cleanup is necessary. */ + splay_tree_delete_value_fn delete_value; + + /* Allocate/free functions, and a data pointer to pass to them. */ + splay_tree_allocate_fn allocate; + splay_tree_deallocate_fn deallocate; + PTR GTY((skip)) allocate_data; + +}; +typedef struct splay_tree_s *splay_tree; + +extern splay_tree splay_tree_new PARAMS((splay_tree_compare_fn, + splay_tree_delete_key_fn, + splay_tree_delete_value_fn)); +extern splay_tree splay_tree_new_with_allocator + PARAMS((splay_tree_compare_fn, + splay_tree_delete_key_fn, + splay_tree_delete_value_fn, + splay_tree_allocate_fn, + splay_tree_deallocate_fn, + void *)); +extern void splay_tree_delete PARAMS((splay_tree)); +extern splay_tree_node splay_tree_insert + PARAMS((splay_tree, + splay_tree_key, + splay_tree_value)); +extern void splay_tree_remove PARAMS((splay_tree, + splay_tree_key)); +extern splay_tree_node splay_tree_lookup + PARAMS((splay_tree, + splay_tree_key)); +extern splay_tree_node splay_tree_predecessor + PARAMS((splay_tree, + splay_tree_key)); +extern splay_tree_node splay_tree_successor + PARAMS((splay_tree, + splay_tree_key)); +extern splay_tree_node splay_tree_max + PARAMS((splay_tree)); +extern splay_tree_node splay_tree_min + PARAMS((splay_tree)); +extern int splay_tree_foreach PARAMS((splay_tree, + splay_tree_foreach_fn, + void*)); +extern int splay_tree_compare_ints PARAMS((splay_tree_key, + splay_tree_key)); +extern int splay_tree_compare_pointers PARAMS((splay_tree_key, + splay_tree_key)); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _SPLAY_TREE_H */ diff --git a/include/symcat.h b/include/symcat.h new file mode 100644 index 000000000..61ce1e9b3 --- /dev/null +++ b/include/symcat.h @@ -0,0 +1,49 @@ +/* Symbol concatenation utilities. + + Copyright (C) 1998, 2000 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef SYM_CAT_H +#define SYM_CAT_H + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CONCAT2(a,b) a##b +#define CONCAT3(a,b,c) a##b##c +#define CONCAT4(a,b,c,d) a##b##c##d +#define STRINGX(s) #s +#else +/* Note one should never pass extra whitespace to the CONCATn macros, + e.g. CONCAT2(foo, bar) because traditonal C will keep the space between + the two labels instead of concatenating them. Instead, make sure to + write CONCAT2(foo,bar). */ +#define CONCAT2(a,b) a/**/b +#define CONCAT3(a,b,c) a/**/b/**/c +#define CONCAT4(a,b,c,d) a/**/b/**/c/**/d +#define STRINGX(s) "s" +#endif + +#define XCONCAT2(a,b) CONCAT2(a,b) +#define XCONCAT3(a,b,c) CONCAT3(a,b,c) +#define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d) + +/* Note the layer of indirection here is typically used to allow + stringification of the expansion of macros. I.e. "#define foo + bar", "XSTRING(foo)", to yield "bar". Be aware that this only + works for __STDC__, not for traditional C which will still resolve + to "foo". */ +#define XSTRING(s) STRINGX(s) + +#endif /* SYM_CAT_H */ diff --git a/include/ternary.h b/include/ternary.h new file mode 100644 index 000000000..40d442e62 --- /dev/null +++ b/include/ternary.h @@ -0,0 +1,51 @@ +/* ternary.h - Ternary Search Trees + Copyright 2001 Free Software Foundation, Inc. + + Contributed by Daniel Berlin (dan@cgsoftware.com) + + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ +#ifndef TERNARY_H_ +#define TERNARY_H_ +/* Ternary search trees */ + +typedef struct ternary_node_def *ternary_tree; + +typedef struct ternary_node_def +{ + char splitchar; + ternary_tree lokid; + ternary_tree eqkid; + ternary_tree hikid; +} +ternary_node; + +/* Insert string S into tree P, associating it with DATA. + Return the data in the tree associated with the string if it's + already there, and replace is 0. + Otherwise, replaces if it it exists, inserts if it doesn't, and + returns the data you passed in. */ +PTR ternary_insert PARAMS ((ternary_tree *p, const char *s, + PTR data, int replace)); + +/* Delete the ternary search tree rooted at P. + Does NOT delete the data you associated with the strings. */ +void ternary_cleanup PARAMS ((ternary_tree p)); + +/* Search the ternary tree for string S, returning the data associated + with it if found. */ +PTR ternary_search PARAMS ((const ternary_node *p, const char *s)); +#endif diff --git a/include/xregex.h b/include/xregex.h new file mode 100644 index 000000000..645195bbc --- /dev/null +++ b/include/xregex.h @@ -0,0 +1,28 @@ +/* This file redefines all regex external names before including + a renamed copy of glibc's regex.h. */ + +#ifndef _XREGEX_H +#define _XREGEX_H 1 + +# define regfree xregfree +# define regexec xregexec +# define regcomp xregcomp +# define regerror xregerror +# define re_set_registers xre_set_registers +# define re_match_2 xre_match_2 +# define re_match xre_match +# define re_search xre_search +# define re_compile_pattern xre_compile_pattern +# define re_set_syntax xre_set_syntax +# define re_search_2 xre_search_2 +# define re_compile_fastmap xre_compile_fastmap +# define re_syntax_options xre_syntax_options +# define re_max_failures xre_max_failures + +# define _REGEX_RE_COMP +# define re_comp xre_comp +# define re_exec xre_exec + +#include "xregex2.h" + +#endif /* xregex.h */ diff --git a/include/xregex2.h b/include/xregex2.h new file mode 100644 index 000000000..2991daf9b --- /dev/null +++ b/include/xregex2.h @@ -0,0 +1,571 @@ +/* Definitions for data structures and routines for the regular + expression library, version 0.12. + Copyright (C) 1985,1989-1993,1995-1998, 2000 Free Software Foundation, Inc. + This file is part of the GNU C Library. Its master source is NOT part of + the C library, however. The master source lives in /gd/gnu/lib. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +#ifndef _REGEX_H +#define _REGEX_H 1 + +/* Allow the use in C++ code. */ +#ifdef __cplusplus +extern "C" { +#endif + +/* POSIX says that <sys/types.h> must be included (by the caller) before + <regex.h>. */ + +#if !defined _POSIX_C_SOURCE && !defined _POSIX_SOURCE && defined VMS +/* VMS doesn't have `size_t' in <sys/types.h>, even though POSIX says it + should be there. */ +# include <stddef.h> +#endif + +/* The following two types have to be signed and unsigned integer type + wide enough to hold a value of a pointer. For most ANSI compilers + ptrdiff_t and size_t should be likely OK. Still size of these two + types is 2 for Microsoft C. Ugh... */ +typedef long int s_reg_t; +typedef unsigned long int active_reg_t; + +/* The following bits are used to determine the regexp syntax we + recognize. The set/not-set meanings are chosen so that Emacs syntax + remains the value 0. The bits are given in alphabetical order, and + the definitions shifted by one from the previous bit; thus, when we + add or remove a bit, only one other definition need change. */ +typedef unsigned long int reg_syntax_t; + +/* If this bit is not set, then \ inside a bracket expression is literal. + If set, then such a \ quotes the following character. */ +#define RE_BACKSLASH_ESCAPE_IN_LISTS ((unsigned long int) 1) + +/* If this bit is not set, then + and ? are operators, and \+ and \? are + literals. + If set, then \+ and \? are operators and + and ? are literals. */ +#define RE_BK_PLUS_QM (RE_BACKSLASH_ESCAPE_IN_LISTS << 1) + +/* If this bit is set, then character classes are supported. They are: + [:alpha:], [:upper:], [:lower:], [:digit:], [:alnum:], [:xdigit:], + [:space:], [:print:], [:punct:], [:graph:], and [:cntrl:]. + If not set, then character classes are not supported. */ +#define RE_CHAR_CLASSES (RE_BK_PLUS_QM << 1) + +/* If this bit is set, then ^ and $ are always anchors (outside bracket + expressions, of course). + If this bit is not set, then it depends: + ^ is an anchor if it is at the beginning of a regular + expression or after an open-group or an alternation operator; + $ is an anchor if it is at the end of a regular expression, or + before a close-group or an alternation operator. + + This bit could be (re)combined with RE_CONTEXT_INDEP_OPS, because + POSIX draft 11.2 says that * etc. in leading positions is undefined. + We already implemented a previous draft which made those constructs + invalid, though, so we haven't changed the code back. */ +#define RE_CONTEXT_INDEP_ANCHORS (RE_CHAR_CLASSES << 1) + +/* If this bit is set, then special characters are always special + regardless of where they are in the pattern. + If this bit is not set, then special characters are special only in + some contexts; otherwise they are ordinary. Specifically, + * + ? and intervals are only special when not after the beginning, + open-group, or alternation operator. */ +#define RE_CONTEXT_INDEP_OPS (RE_CONTEXT_INDEP_ANCHORS << 1) + +/* If this bit is set, then *, +, ?, and { cannot be first in an re or + immediately after an alternation or begin-group operator. */ +#define RE_CONTEXT_INVALID_OPS (RE_CONTEXT_INDEP_OPS << 1) + +/* If this bit is set, then . matches newline. + If not set, then it doesn't. */ +#define RE_DOT_NEWLINE (RE_CONTEXT_INVALID_OPS << 1) + +/* If this bit is set, then . doesn't match NUL. + If not set, then it does. */ +#define RE_DOT_NOT_NULL (RE_DOT_NEWLINE << 1) + +/* If this bit is set, nonmatching lists [^...] do not match newline. + If not set, they do. */ +#define RE_HAT_LISTS_NOT_NEWLINE (RE_DOT_NOT_NULL << 1) + +/* If this bit is set, either \{...\} or {...} defines an + interval, depending on RE_NO_BK_BRACES. + If not set, \{, \}, {, and } are literals. */ +#define RE_INTERVALS (RE_HAT_LISTS_NOT_NEWLINE << 1) + +/* If this bit is set, +, ? and | aren't recognized as operators. + If not set, they are. */ +#define RE_LIMITED_OPS (RE_INTERVALS << 1) + +/* If this bit is set, newline is an alternation operator. + If not set, newline is literal. */ +#define RE_NEWLINE_ALT (RE_LIMITED_OPS << 1) + +/* If this bit is set, then `{...}' defines an interval, and \{ and \} + are literals. + If not set, then `\{...\}' defines an interval. */ +#define RE_NO_BK_BRACES (RE_NEWLINE_ALT << 1) + +/* If this bit is set, (...) defines a group, and \( and \) are literals. + If not set, \(...\) defines a group, and ( and ) are literals. */ +#define RE_NO_BK_PARENS (RE_NO_BK_BRACES << 1) + +/* If this bit is set, then \<digit> matches <digit>. + If not set, then \<digit> is a back-reference. */ +#define RE_NO_BK_REFS (RE_NO_BK_PARENS << 1) + +/* If this bit is set, then | is an alternation operator, and \| is literal. + If not set, then \| is an alternation operator, and | is literal. */ +#define RE_NO_BK_VBAR (RE_NO_BK_REFS << 1) + +/* If this bit is set, then an ending range point collating higher + than the starting range point, as in [z-a], is invalid. + If not set, then when ending range point collates higher than the + starting range point, the range is ignored. */ +#define RE_NO_EMPTY_RANGES (RE_NO_BK_VBAR << 1) + +/* If this bit is set, then an unmatched ) is ordinary. + If not set, then an unmatched ) is invalid. */ +#define RE_UNMATCHED_RIGHT_PAREN_ORD (RE_NO_EMPTY_RANGES << 1) + +/* If this bit is set, succeed as soon as we match the whole pattern, + without further backtracking. */ +#define RE_NO_POSIX_BACKTRACKING (RE_UNMATCHED_RIGHT_PAREN_ORD << 1) + +/* If this bit is set, do not process the GNU regex operators. + If not set, then the GNU regex operators are recognized. */ +#define RE_NO_GNU_OPS (RE_NO_POSIX_BACKTRACKING << 1) + +/* If this bit is set, turn on internal regex debugging. + If not set, and debugging was on, turn it off. + This only works if regex.c is compiled -DDEBUG. + We define this bit always, so that all that's needed to turn on + debugging is to recompile regex.c; the calling code can always have + this bit set, and it won't affect anything in the normal case. */ +#define RE_DEBUG (RE_NO_GNU_OPS << 1) + +/* If this bit is set, a syntactically invalid interval is treated as + a string of ordinary characters. For example, the ERE 'a{1' is + treated as 'a\{1'. */ +#define RE_INVALID_INTERVAL_ORD (RE_DEBUG << 1) + +/* This global variable defines the particular regexp syntax to use (for + some interfaces). When a regexp is compiled, the syntax used is + stored in the pattern buffer, so changing this does not affect + already-compiled regexps. */ +extern reg_syntax_t re_syntax_options; + +/* Define combinations of the above bits for the standard possibilities. + (The [[[ comments delimit what gets put into the Texinfo file, so + don't delete them!) */ +/* [[[begin syntaxes]]] */ +#define RE_SYNTAX_EMACS 0 + +#define RE_SYNTAX_AWK \ + (RE_BACKSLASH_ESCAPE_IN_LISTS | RE_DOT_NOT_NULL \ + | RE_NO_BK_PARENS | RE_NO_BK_REFS \ + | RE_NO_BK_VBAR | RE_NO_EMPTY_RANGES \ + | RE_DOT_NEWLINE | RE_CONTEXT_INDEP_ANCHORS \ + | RE_UNMATCHED_RIGHT_PAREN_ORD | RE_NO_GNU_OPS) + +#define RE_SYNTAX_GNU_AWK \ + ((RE_SYNTAX_POSIX_EXTENDED | RE_BACKSLASH_ESCAPE_IN_LISTS | RE_DEBUG) \ + & ~(RE_DOT_NOT_NULL | RE_INTERVALS | RE_CONTEXT_INDEP_OPS)) + +#define RE_SYNTAX_POSIX_AWK \ + (RE_SYNTAX_POSIX_EXTENDED | RE_BACKSLASH_ESCAPE_IN_LISTS \ + | RE_INTERVALS | RE_NO_GNU_OPS) + +#define RE_SYNTAX_GREP \ + (RE_BK_PLUS_QM | RE_CHAR_CLASSES \ + | RE_HAT_LISTS_NOT_NEWLINE | RE_INTERVALS \ + | RE_NEWLINE_ALT) + +#define RE_SYNTAX_EGREP \ + (RE_CHAR_CLASSES | RE_CONTEXT_INDEP_ANCHORS \ + | RE_CONTEXT_INDEP_OPS | RE_HAT_LISTS_NOT_NEWLINE \ + | RE_NEWLINE_ALT | RE_NO_BK_PARENS \ + | RE_NO_BK_VBAR) + +#define RE_SYNTAX_POSIX_EGREP \ + (RE_SYNTAX_EGREP | RE_INTERVALS | RE_NO_BK_BRACES \ + | RE_INVALID_INTERVAL_ORD) + +/* P1003.2/D11.2, section 4.20.7.1, lines 5078ff. */ +#define RE_SYNTAX_ED RE_SYNTAX_POSIX_BASIC + +#define RE_SYNTAX_SED RE_SYNTAX_POSIX_BASIC + +/* Syntax bits common to both basic and extended POSIX regex syntax. */ +#define _RE_SYNTAX_POSIX_COMMON \ + (RE_CHAR_CLASSES | RE_DOT_NEWLINE | RE_DOT_NOT_NULL \ + | RE_INTERVALS | RE_NO_EMPTY_RANGES) + +#define RE_SYNTAX_POSIX_BASIC \ + (_RE_SYNTAX_POSIX_COMMON | RE_BK_PLUS_QM) + +/* Differs from ..._POSIX_BASIC only in that RE_BK_PLUS_QM becomes + RE_LIMITED_OPS, i.e., \? \+ \| are not recognized. Actually, this + isn't minimal, since other operators, such as \`, aren't disabled. */ +#define RE_SYNTAX_POSIX_MINIMAL_BASIC \ + (_RE_SYNTAX_POSIX_COMMON | RE_LIMITED_OPS) + +#define RE_SYNTAX_POSIX_EXTENDED \ + (_RE_SYNTAX_POSIX_COMMON | RE_CONTEXT_INDEP_ANCHORS \ + | RE_CONTEXT_INDEP_OPS | RE_NO_BK_BRACES \ + | RE_NO_BK_PARENS | RE_NO_BK_VBAR \ + | RE_CONTEXT_INVALID_OPS | RE_UNMATCHED_RIGHT_PAREN_ORD) + +/* Differs from ..._POSIX_EXTENDED in that RE_CONTEXT_INDEP_OPS is + removed and RE_NO_BK_REFS is added. */ +#define RE_SYNTAX_POSIX_MINIMAL_EXTENDED \ + (_RE_SYNTAX_POSIX_COMMON | RE_CONTEXT_INDEP_ANCHORS \ + | RE_CONTEXT_INVALID_OPS | RE_NO_BK_BRACES \ + | RE_NO_BK_PARENS | RE_NO_BK_REFS \ + | RE_NO_BK_VBAR | RE_UNMATCHED_RIGHT_PAREN_ORD) +/* [[[end syntaxes]]] */ + +/* Maximum number of duplicates an interval can allow. Some systems + (erroneously) define this in other header files, but we want our + value, so remove any previous define. */ +#ifdef RE_DUP_MAX +# undef RE_DUP_MAX +#endif +/* If sizeof(int) == 2, then ((1 << 15) - 1) overflows. */ +#define RE_DUP_MAX (0x7fff) + + +/* POSIX `cflags' bits (i.e., information for `regcomp'). */ + +/* If this bit is set, then use extended regular expression syntax. + If not set, then use basic regular expression syntax. */ +#define REG_EXTENDED 1 + +/* If this bit is set, then ignore case when matching. + If not set, then case is significant. */ +#define REG_ICASE (REG_EXTENDED << 1) + +/* If this bit is set, then anchors do not match at newline + characters in the string. + If not set, then anchors do match at newlines. */ +#define REG_NEWLINE (REG_ICASE << 1) + +/* If this bit is set, then report only success or fail in regexec. + If not set, then returns differ between not matching and errors. */ +#define REG_NOSUB (REG_NEWLINE << 1) + + +/* POSIX `eflags' bits (i.e., information for regexec). */ + +/* If this bit is set, then the beginning-of-line operator doesn't match + the beginning of the string (presumably because it's not the + beginning of a line). + If not set, then the beginning-of-line operator does match the + beginning of the string. */ +#define REG_NOTBOL 1 + +/* Like REG_NOTBOL, except for the end-of-line. */ +#define REG_NOTEOL (1 << 1) + + +/* If any error codes are removed, changed, or added, update the + `re_error_msg' table in regex.c. */ +typedef enum +{ +#ifdef _XOPEN_SOURCE + REG_ENOSYS = -1, /* This will never happen for this implementation. */ +#endif + + REG_NOERROR = 0, /* Success. */ + REG_NOMATCH, /* Didn't find a match (for regexec). */ + + /* POSIX regcomp return error codes. (In the order listed in the + standard.) */ + REG_BADPAT, /* Invalid pattern. */ + REG_ECOLLATE, /* Not implemented. */ + REG_ECTYPE, /* Invalid character class name. */ + REG_EESCAPE, /* Trailing backslash. */ + REG_ESUBREG, /* Invalid back reference. */ + REG_EBRACK, /* Unmatched left bracket. */ + REG_EPAREN, /* Parenthesis imbalance. */ + REG_EBRACE, /* Unmatched \{. */ + REG_BADBR, /* Invalid contents of \{\}. */ + REG_ERANGE, /* Invalid range end. */ + REG_ESPACE, /* Ran out of memory. */ + REG_BADRPT, /* No preceding re for repetition op. */ + + /* Error codes we've added. */ + REG_EEND, /* Premature end. */ + REG_ESIZE, /* Compiled pattern bigger than 2^16 bytes. */ + REG_ERPAREN /* Unmatched ) or \); not returned from regcomp. */ +} reg_errcode_t; + +/* This data structure represents a compiled pattern. Before calling + the pattern compiler, the fields `buffer', `allocated', `fastmap', + `translate', and `no_sub' can be set. After the pattern has been + compiled, the `re_nsub' field is available. All other fields are + private to the regex routines. */ + +#ifndef RE_TRANSLATE_TYPE +# define RE_TRANSLATE_TYPE char * +#endif + +struct re_pattern_buffer +{ +/* [[[begin pattern_buffer]]] */ + /* Space that holds the compiled pattern. It is declared as + `unsigned char *' because its elements are + sometimes used as array indexes. */ + unsigned char *buffer; + + /* Number of bytes to which `buffer' points. */ + unsigned long int allocated; + + /* Number of bytes actually used in `buffer'. */ + unsigned long int used; + + /* Syntax setting with which the pattern was compiled. */ + reg_syntax_t syntax; + + /* Pointer to a fastmap, if any, otherwise zero. re_search uses + the fastmap, if there is one, to skip over impossible + starting points for matches. */ + char *fastmap; + + /* Either a translate table to apply to all characters before + comparing them, or zero for no translation. The translation + is applied to a pattern when it is compiled and to a string + when it is matched. */ + RE_TRANSLATE_TYPE translate; + + /* Number of subexpressions found by the compiler. */ + size_t re_nsub; + + /* Zero if this pattern cannot match the empty string, one else. + Well, in truth it's used only in `re_search_2', to see + whether or not we should use the fastmap, so we don't set + this absolutely perfectly; see `re_compile_fastmap' (the + `duplicate' case). */ + unsigned can_be_null : 1; + + /* If REGS_UNALLOCATED, allocate space in the `regs' structure + for `max (RE_NREGS, re_nsub + 1)' groups. + If REGS_REALLOCATE, reallocate space if necessary. + If REGS_FIXED, use what's there. */ +#define REGS_UNALLOCATED 0 +#define REGS_REALLOCATE 1 +#define REGS_FIXED 2 + unsigned regs_allocated : 2; + + /* Set to zero when `regex_compile' compiles a pattern; set to one + by `re_compile_fastmap' if it updates the fastmap. */ + unsigned fastmap_accurate : 1; + + /* If set, `re_match_2' does not return information about + subexpressions. */ + unsigned no_sub : 1; + + /* If set, a beginning-of-line anchor doesn't match at the + beginning of the string. */ + unsigned not_bol : 1; + + /* Similarly for an end-of-line anchor. */ + unsigned not_eol : 1; + + /* If true, an anchor at a newline matches. */ + unsigned newline_anchor : 1; + +/* [[[end pattern_buffer]]] */ +}; + +typedef struct re_pattern_buffer regex_t; + +/* Type for byte offsets within the string. POSIX mandates this. */ +typedef int regoff_t; + + +/* This is the structure we store register match data in. See + regex.texinfo for a full description of what registers match. */ +struct re_registers +{ + unsigned num_regs; + regoff_t *start; + regoff_t *end; +}; + + +/* If `regs_allocated' is REGS_UNALLOCATED in the pattern buffer, + `re_match_2' returns information about at least this many registers + the first time a `regs' structure is passed. */ +#ifndef RE_NREGS +# define RE_NREGS 30 +#endif + + +/* POSIX specification for registers. Aside from the different names than + `re_registers', POSIX uses an array of structures, instead of a + structure of arrays. */ +typedef struct +{ + regoff_t rm_so; /* Byte offset from string's start to substring's start. */ + regoff_t rm_eo; /* Byte offset from string's start to substring's end. */ +} regmatch_t; + +/* Declarations for routines. */ + +/* To avoid duplicating every routine declaration -- once with a + prototype (if we are ANSI), and once without (if we aren't) -- we + use the following macro to declare argument types. This + unfortunately clutters up the declarations a bit, but I think it's + worth it. */ + +#if __STDC__ + +# define _RE_ARGS(args) args + +#else /* not __STDC__ */ + +# define _RE_ARGS(args) () + +#endif /* not __STDC__ */ + +/* Sets the current default syntax to SYNTAX, and return the old syntax. + You can also simply assign to the `re_syntax_options' variable. */ +extern reg_syntax_t re_set_syntax _RE_ARGS ((reg_syntax_t syntax)); + +/* Compile the regular expression PATTERN, with length LENGTH + and syntax given by the global `re_syntax_options', into the buffer + BUFFER. Return NULL if successful, and an error string if not. */ +extern const char *re_compile_pattern + _RE_ARGS ((const char *pattern, size_t length, + struct re_pattern_buffer *buffer)); + + +/* Compile a fastmap for the compiled pattern in BUFFER; used to + accelerate searches. Return 0 if successful and -2 if was an + internal error. */ +extern int re_compile_fastmap _RE_ARGS ((struct re_pattern_buffer *buffer)); + + +/* Search in the string STRING (with length LENGTH) for the pattern + compiled into BUFFER. Start searching at position START, for RANGE + characters. Return the starting position of the match, -1 for no + match, or -2 for an internal error. Also return register + information in REGS (if REGS and BUFFER->no_sub are nonzero). */ +extern int re_search + _RE_ARGS ((struct re_pattern_buffer *buffer, const char *string, + int length, int start, int range, struct re_registers *regs)); + + +/* Like `re_search', but search in the concatenation of STRING1 and + STRING2. Also, stop searching at index START + STOP. */ +extern int re_search_2 + _RE_ARGS ((struct re_pattern_buffer *buffer, const char *string1, + int length1, const char *string2, int length2, + int start, int range, struct re_registers *regs, int stop)); + + +/* Like `re_search', but return how many characters in STRING the regexp + in BUFFER matched, starting at position START. */ +extern int re_match + _RE_ARGS ((struct re_pattern_buffer *buffer, const char *string, + int length, int start, struct re_registers *regs)); + + +/* Relates to `re_match' as `re_search_2' relates to `re_search'. */ +extern int re_match_2 + _RE_ARGS ((struct re_pattern_buffer *buffer, const char *string1, + int length1, const char *string2, int length2, + int start, struct re_registers *regs, int stop)); + + +/* Set REGS to hold NUM_REGS registers, storing them in STARTS and + ENDS. Subsequent matches using BUFFER and REGS will use this memory + for recording register information. STARTS and ENDS must be + allocated with malloc, and must each be at least `NUM_REGS * sizeof + (regoff_t)' bytes long. + + If NUM_REGS == 0, then subsequent matches should allocate their own + register data. + + Unless this function is called, the first search or match using + PATTERN_BUFFER will allocate its own register data, without + freeing the old data. */ +extern void re_set_registers + _RE_ARGS ((struct re_pattern_buffer *buffer, struct re_registers *regs, + unsigned num_regs, regoff_t *starts, regoff_t *ends)); + +#if defined _REGEX_RE_COMP || defined _LIBC +# ifndef _CRAY +/* 4.2 bsd compatibility. */ +extern char *re_comp _RE_ARGS ((const char *)); +extern int re_exec _RE_ARGS ((const char *)); +# endif +#endif + +/* GCC 2.95 and later have "__restrict"; C99 compilers have + "restrict", and "configure" may have defined "restrict". */ +#ifndef __restrict +# if ! (2 < __GNUC__ || (2 == __GNUC__ && 95 <= __GNUC_MINOR__)) +# if defined restrict || 199901L <= __STDC_VERSION__ +# define __restrict restrict +# else +# define __restrict +# endif +# endif +#endif + +/* GCC 3.1 and later support declaring arrays as non-overlapping + using the syntax array_name[restrict] */ +#ifndef __restrict_arr +# if ! (3 < __GNUC__ || (3 == __GNUC__ && 1 <= __GNUC_MINOR__)) || defined (__GNUG__) +# define __restrict_arr +# else +# define __restrict_arr __restrict +# endif +#endif + +/* POSIX compatibility. */ +extern int regcomp _RE_ARGS ((regex_t *__restrict __preg, + const char *__restrict __pattern, + int __cflags)); + +extern int regexec _RE_ARGS ((const regex_t *__restrict __preg, + const char *__restrict __string, size_t __nmatch, + regmatch_t __pmatch[__restrict_arr], + int __eflags)); + +extern size_t regerror _RE_ARGS ((int __errcode, const regex_t *__preg, + char *__errbuf, size_t __errbuf_size)); + +extern void regfree _RE_ARGS ((regex_t *__preg)); + + +#ifdef __cplusplus +} +#endif /* C++ */ + +#endif /* regex.h */ + +/* +Local variables: +make-backup-files: t +version-control: t +trim-versions-without-asking: nil +End: +*/ diff --git a/include/xtensa-config.h b/include/xtensa-config.h new file mode 100644 index 000000000..4191c3685 --- /dev/null +++ b/include/xtensa-config.h @@ -0,0 +1,139 @@ +/* Xtensa configuration settings. + Copyright (C) 2001,2002,2003 Free Software Foundation, Inc. + Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 1 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 0 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 0 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 0 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 0 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 0 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 8192 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 8192 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 16 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 16 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 0 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 1 + +#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 4 + + +#undef XCHAL_EXTRA_SA_SIZE +#define XCHAL_EXTRA_SA_SIZE 0 + +#undef XCHAL_EXTRA_SA_ALIGN +#define XCHAL_EXTRA_SA_ALIGN 1 + +#endif /* !XTENSA_CONFIG_H */ diff --git a/include/xtensa-isa-internal.h b/include/xtensa-isa-internal.h new file mode 100644 index 000000000..7f221eae4 --- /dev/null +++ b/include/xtensa-isa-internal.h @@ -0,0 +1,114 @@ +/* Internal definitions for configurable Xtensa ISA support. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Use the statically-linked version for the GNU tools. */ +#define STATIC_LIBISA 1 + +#define ISA_INTERFACE_VERSION 3 + +struct config_struct +{ + char *param_name; + char *param_value; +}; + +/* Encode/decode function types for immediate operands. */ +typedef uint32 (*xtensa_immed_decode_fn) (uint32); +typedef xtensa_encode_result (*xtensa_immed_encode_fn) (uint32 *); + +/* Field accessor function types. */ +typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf); +typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32); + +/* PC-relative relocation function types. */ +typedef uint32 (*xtensa_do_reloc_fn) (uint32, uint32); +typedef uint32 (*xtensa_undo_reloc_fn) (uint32, uint32); + +/* Instruction decode function type. */ +typedef int (*xtensa_insn_decode_fn) (const xtensa_insnbuf); + +/* Instruction encoding template function type (each of these functions + returns a constant template; they exist only to make it easier for the + TIE compiler to generate endian-independent DLLs). */ +typedef xtensa_insnbuf (*xtensa_encoding_template_fn) (void); + + +typedef struct xtensa_operand_internal_struct +{ + char *operand_kind; /* e.g., "a", "f", "i", "l".... */ + char inout; /* '<', '>', or '='. */ + char isPCRelative; /* Is this a PC-relative offset? */ + xtensa_get_field_fn get_field; /* Get encoded value of the field. */ + xtensa_set_field_fn set_field; /* Set field with an encoded value. */ + xtensa_immed_encode_fn encode; /* Encode the operand value. */ + xtensa_immed_decode_fn decode; /* Decode the value from the field. */ + xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative relocation. */ + xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */ +} xtensa_operand_internal; + + +typedef struct xtensa_iclass_internal_struct +{ + int num_operands; /* Size of "operands" array. */ + xtensa_operand_internal **operands; /* Array of operand structures. */ +} xtensa_iclass_internal; + + +typedef struct xtensa_opcode_internal_struct +{ + const char *name; /* Opcode mnemonic. */ + int length; /* Length in bytes of the insn. */ + xtensa_encoding_template_fn template; /* Fn returning encoding template. */ + xtensa_iclass_internal *iclass; /* Iclass for this opcode. */ +} xtensa_opcode_internal; + + +typedef struct opname_lookup_entry_struct +{ + const char *key; /* Opcode mnemonic. */ + xtensa_opcode opcode; /* Internal opcode number. */ +} opname_lookup_entry; + + +typedef struct xtensa_isa_internal_struct +{ + int is_big_endian; /* Endianness. */ + int insn_size; /* Maximum length in bytes. */ + int insnbuf_size; /* Number of insnbuf_words. */ + int num_opcodes; /* Total number for all modules. */ + xtensa_opcode_internal **opcode_table;/* Indexed by internal opcode #. */ + int num_modules; /* Number of modules (DLLs) loaded. */ + int *module_opcode_base; /* Starting opcode # for each module. */ + xtensa_insn_decode_fn *module_decode_fn; /* Decode fn for each module. */ + opname_lookup_entry *opname_lookup_table; /* Lookup table for each module. */ + struct config_struct *config; /* Table of configuration parameters. */ + int has_density; /* Is density option available? */ +} xtensa_isa_internal; + + +typedef struct xtensa_isa_module_struct +{ + int (*get_num_opcodes_fn) (void); + xtensa_opcode_internal **(*get_opcodes_fn) (void); + int (*decode_insn_fn) (const xtensa_insnbuf); + struct config_struct *(*get_config_table_fn) (void); +} xtensa_isa_module; + +extern xtensa_isa_module xtensa_isa_modules[]; + diff --git a/include/xtensa-isa.h b/include/xtensa-isa.h new file mode 100644 index 000000000..54f750c9a --- /dev/null +++ b/include/xtensa-isa.h @@ -0,0 +1,230 @@ +/* Interface definition for configurable Xtensa ISA support. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef XTENSA_LIBISA_H +#define XTENSA_LIBISA_H + +/* Use the statically-linked version for the GNU tools. */ +#define STATIC_LIBISA 1 + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef uint32 +#define uint32 unsigned int +#endif + +/* This file defines the interface to the Xtensa ISA library. This library + contains most of the ISA-specific information for a particular Xtensa + processor. For example, the set of valid instructions, their opcode + encodings and operand fields are all included here. To support Xtensa's + configurability and user-defined instruction extensions (i.e., TIE), the + library is initialized by loading one or more dynamic libraries; only a + small set of interface code is present in the statically-linked portion + of the library. + + This interface basically defines four abstract data types. + + . an instruction buffer - for holding the raw instruction bits + . ISA info - information about the ISA as a whole + . opcode info - information about individual instructions + . operand info - information about specific instruction operands + + It would be nice to implement these as classes in C++, but the library is + implemented in C to match the expectations of the GNU tools. + Instead, the interface defines a set of functions to access each data + type. With the exception of the instruction buffer, the internal + representations of the data structures are hidden. All accesses must be + made through the functions defined here. */ + +typedef void* xtensa_isa; +typedef void* xtensa_operand; + + +/* Opcodes are represented here using sequential integers beginning with 0. + The specific value used for a particular opcode is only fixed for a + particular instantiation of an xtensa_isa structure, so these values + should only be used internally. */ +typedef int xtensa_opcode; + +/* Define a unique value for undefined opcodes ("static const int" doesn't + seem to work for this because EGCS 1.0.3 on i686-Linux without -O won't + allow it to be used as an initializer). */ +#define XTENSA_UNDEFINED -1 + + +typedef int libisa_module_specifier; + +extern xtensa_isa xtensa_isa_init (void); + + +/* Instruction buffers. */ + +typedef uint32 xtensa_insnbuf_word; +typedef xtensa_insnbuf_word *xtensa_insnbuf; + +/* Get the size in words of the xtensa_insnbuf array. */ +extern int xtensa_insnbuf_size (xtensa_isa); + +/* Allocate (with malloc) an xtensa_insnbuf of the right size. */ +extern xtensa_insnbuf xtensa_insnbuf_alloc (xtensa_isa); + +/* Release (with free) an xtensa_insnbuf of the right size. */ +extern void xtensa_insnbuf_free (xtensa_insnbuf); + +/* Inward and outward conversion from memory images (byte streams) to our + internal instruction representation. */ +extern void xtensa_insnbuf_to_chars (xtensa_isa, const xtensa_insnbuf, + char *); + +extern void xtensa_insnbuf_from_chars (xtensa_isa, xtensa_insnbuf, + const char *); + + +/* ISA information. */ + +/* Load the ISA information from a shared library. If successful, this returns + a value which identifies the ISA for use in subsequent calls to the ISA + library; otherwise, it returns NULL. Multiple ISAs can be loaded to support + heterogeneous multiprocessor systems. */ +extern xtensa_isa xtensa_load_isa (libisa_module_specifier); + +/* Extend an existing set of ISA information by loading an additional shared + library of ISA information. This is primarily intended for loading TIE + extensions. If successful, the return value is non-zero. */ +extern int xtensa_extend_isa (xtensa_isa, libisa_module_specifier); + +/* The default ISA. This variable is set automatically to the ISA most + recently loaded and is provided as a convenience. An exception is the GNU + opcodes library, where there is a fixed interface that does not allow + passing the ISA as a parameter and the ISA must be taken from this global + variable. (Note: Since this variable is just a convenience, it is not + exported when libisa is built as a DLL, due to the hassle of dealing with + declspecs.) */ +extern xtensa_isa xtensa_default_isa; + + +/* Deallocate an xtensa_isa structure. */ +extern void xtensa_isa_free (xtensa_isa); + +/* Get the maximum instruction size in bytes. */ +extern int xtensa_insn_maxlength (xtensa_isa); + +/* Get the total number of opcodes for this processor. */ +extern int xtensa_num_opcodes (xtensa_isa); + +/* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if + the name is not a valid opcode mnemonic. */ +extern xtensa_opcode xtensa_opcode_lookup (xtensa_isa, const char *); + +/* Decode a binary instruction buffer. Returns the opcode or + XTENSA_UNDEFINED if the instruction is illegal. */ +extern xtensa_opcode xtensa_decode_insn (xtensa_isa, const xtensa_insnbuf); + + +/* Opcode information. */ + +/* Set the opcode field(s) in a binary instruction buffer. The operand + fields are set to zero. */ +extern void xtensa_encode_insn (xtensa_isa, xtensa_opcode, xtensa_insnbuf); + +/* Get the mnemonic name for an opcode. */ +extern const char * xtensa_opcode_name (xtensa_isa, xtensa_opcode); + +/* Find the length (in bytes) of an instruction. */ +extern int xtensa_insn_length (xtensa_isa, xtensa_opcode); + +/* Find the length of an instruction by looking only at the first byte. */ +extern int xtensa_insn_length_from_first_byte (xtensa_isa, char); + +/* Find the number of operands for an instruction. */ +extern int xtensa_num_operands (xtensa_isa, xtensa_opcode); + +/* Get the information about operand number "opnd" of a particular opcode. */ +extern xtensa_operand xtensa_get_operand (xtensa_isa, xtensa_opcode, int); + +/* Operand information. */ + +/* Find the kind of operand. There are three possibilities: + 1) PC-relative immediates (e.g., "l", "L"). These can be identified with + the xtensa_operand_isPCRelative function. + 2) non-PC-relative immediates ("i"). + 3) register-file short names (e.g., "a", "b", "m" and others defined + via TIE). */ +extern char * xtensa_operand_kind (xtensa_operand); + +/* Check if an operand is an input ('<'), output ('>'), or inout ('=') + operand. Note: The output operand of a conditional assignment + (e.g., movnez) appears here as an inout ('=') even if it is declared + in the TIE code as an output ('>'); this allows the compiler to + properly handle register allocation for conditional assignments. */ +extern char xtensa_operand_inout (xtensa_operand); + +/* Get and set the raw (encoded) value of the field for the specified + operand. The "set" function does not check if the value fits in the + field; that is done by the "encode" function below. */ +extern uint32 xtensa_operand_get_field (xtensa_operand, const xtensa_insnbuf); + +extern void xtensa_operand_set_field (xtensa_operand, xtensa_insnbuf, uint32); + + +/* Encode and decode operands. The raw bits in the operand field + may be encoded in a variety of different ways. These functions hide the + details of that encoding. The encode function has a special return type + (xtensa_encode_result) to indicate success or the reason for failure; the + encoded value is returned through the argument pointer. The decode function + has no possibility of failure and returns the decoded value. */ + +typedef enum +{ + xtensa_encode_result_ok, + xtensa_encode_result_align, + xtensa_encode_result_not_in_table, + xtensa_encode_result_too_low, + xtensa_encode_result_too_high, + xtensa_encode_result_not_ok, + xtensa_encode_result_max = xtensa_encode_result_not_ok +} xtensa_encode_result; + +extern xtensa_encode_result xtensa_operand_encode (xtensa_operand, uint32 *); + +extern uint32 xtensa_operand_decode (xtensa_operand, uint32); + + +/* For PC-relative offset operands, the interpretation of the offset may vary + between opcodes, e.g., is it relative to the current PC or that of the next + instruction? The following functions are defined to perform PC-relative + relocations and to undo them (as in the disassembler). The first function + takes the desired address and the PC of the current instruction and returns + the unencoded value to be stored in the offset field. The second function + takes the unencoded offset value and the current PC and returns the address. + Note that these functions do not replace the encode/decode functions; the + operands must be encoded/decoded separately. */ + +extern int xtensa_operand_isPCRelative (xtensa_operand); + +extern uint32 xtensa_operand_do_reloc (xtensa_operand, uint32, uint32); + +extern uint32 xtensa_operand_undo_reloc (xtensa_operand, uint32, uint32); + +#ifdef __cplusplus +} +#endif +#endif /* XTENSA_LIBISA_H */ |