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-rw-r--r--include/ChangeLog22
-rw-r--r--include/bfdlink.h2
-rw-r--r--include/dis-asm.h3
-rw-r--r--include/elf/ChangeLog5
-rw-r--r--include/elf/common.h8
-rw-r--r--include/elf/frv.h95
-rw-r--r--include/elf/i386.h23
-rw-r--r--include/elf/ia64.h2
-rw-r--r--include/gdb/ChangeLog4
-rw-r--r--include/gdb/sim-arm.h2
-rw-r--r--include/gdb/sim-d10v.h76
-rw-r--r--include/opcode/ChangeLog18
-rw-r--r--include/opcode/dlx.h2
-rw-r--r--include/opcode/h8300.h86
-rw-r--r--include/opcode/ia64.h4
-rw-r--r--include/opcode/mips.h4
-rw-r--r--include/opcode/sparc.h4
-rw-r--r--include/sim-d10v.h103
18 files changed, 250 insertions, 213 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index dd0a2302a..d64d48cae 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,25 @@
+2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net>
+
+ * dis-asm.h: Prototype print_insn_dlx.
+
+2002-05-23 Andrew Cagney <ac131313@redhat.com>
+
+ * sim-d10v.h: Delete file. Moved to include/gdb/.
+
+2002-05-23 Jakub Jelinek <jakub@redhat.com>
+
+ * elf/common.h (PT_TLS, SHF_TLS, STT_TLS, DF_STATIC_TLS): Define.
+ * elf/ia64.h (R_IA64_LTOFF_TPREL22): Renamed from R_IA64_LTOFF_TP22.
+ * elf/i386.h: Add TLS relocs.
+
+2002-05-21 H.J. Lu (hjl@gnu.org)
+
+ * bfdlink.h (bfd_link_info): Add allow_multiple_definition.
+
+2002-05-17 J"orn Rennecke <joern.rennecke@superh.com>
+
+ * dis-asm.h (print_insn_shl, print_insn_sh64l): Remove prototype.
+
2002-04-16 David S. Miller <davem@redhat.com>
* xregex2.h (__restrict_arr): Define to __restrict on GCC
diff --git a/include/bfdlink.h b/include/bfdlink.h
index a03454721..b1411c381 100644
--- a/include/bfdlink.h
+++ b/include/bfdlink.h
@@ -231,6 +231,8 @@ struct bfd_link_info
select an appropriate memset function. Apparently it is also
normal for HPPA shared libraries to have undefined symbols. */
boolean allow_shlib_undefined;
+ /* True if ok to have multiple definition. */
+ boolean allow_multiple_definition;
/* Which symbols to strip. */
enum bfd_link_strip strip;
/* Which local symbols to discard. */
diff --git a/include/dis-asm.h b/include/dis-asm.h
index decc863c6..8d38f7e8d 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -205,6 +205,7 @@ extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_avr PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_d30v PARAMS ((bfd_vma, disassemble_info*));
+extern int print_insn_dlx PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_fr30 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_hppa PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i860 PARAMS ((bfd_vma, disassemble_info*));
@@ -226,7 +227,6 @@ extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_s390 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*));
-extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_tic54x PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_tic80 PARAMS ((bfd_vma, disassemble_info*));
@@ -235,7 +235,6 @@ extern int print_insn_vax PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_xstormy16 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_sh64 PARAMS ((bfd_vma, disassemble_info *));
-extern int print_insn_sh64l PARAMS ((bfd_vma, disassemble_info *));
extern int print_insn_sh64x_media PARAMS ((bfd_vma, disassemble_info *));
extern disassembler_ftype arc_get_disassembler PARAMS ((void *));
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index fe3823b1b..1deec0daa 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net>
+
+ * common.h (EM_DLX): Define.
+ * dlx.h: New file.
+
2002-05-08 Jason Thorpe <thorpej@wasabisystems.com>
* common.h (NT_GNU_ABI_TAG): Define.
diff --git a/include/elf/common.h b/include/elf/common.h
index f8b0832e8..48e2f4ae5 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -236,6 +236,10 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
Written in the absense of an ABI. */
#define EM_OPENRISC_OLD 0x3426
+/* DLX magic number
+ Written in the absense of an ABI. */
+#define EM_DLX 0x5aa5
+
#define EM_XSTORMY16 0xad45
/* See the above comment before you add a new EM_* value here. */
@@ -254,6 +258,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define PT_NOTE 4 /* Auxiliary information */
#define PT_SHLIB 5 /* Reserved, unspecified semantics */
#define PT_PHDR 6 /* Entry for header table itself */
+#define PT_TLS 7 /* Thread local storage segment */
#define PT_LOOS 0x60000000 /* OS-specific */
#define PT_HIOS 0x6fffffff /* OS-specific */
#define PT_LOPROC 0x70000000 /* Processor-specific */
@@ -322,6 +327,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define SHF_LINK_ORDER (1 << 7) /* Preserve section ordering when linking */
#define SHF_OS_NONCONFORMING (1 << 8) /* OS specific processing required */
#define SHF_GROUP (1 << 9) /* Member of a section group */
+#define SHF_TLS (1 << 10) /* Thread local storage section */
/* #define SHF_MASKOS 0x0F000000 *//* OS-specific semantics */
#define SHF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */
@@ -417,6 +423,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define STT_SECTION 3 /* Symbol associated with a section */
#define STT_FILE 4 /* Symbol gives a file name */
#define STT_COMMON 5 /* An uninitialised common block */
+#define STT_TLS 6 /* Thread local data object */
#define STT_LOOS 10 /* OS-specific semantics */
#define STT_HIOS 12 /* OS-specific semantics */
#define STT_LOPROC 13 /* Application-specific semantics */
@@ -585,6 +592,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define DF_SYMBOLIC (1 << 1)
#define DF_TEXTREL (1 << 2)
#define DF_BIND_NOW (1 << 3)
+#define DF_STATIC_TLS (1 << 4)
/* These constants are used for the version number of a Elf32_Verdef
structure. */
diff --git a/include/elf/frv.h b/include/elf/frv.h
new file mode 100644
index 000000000..65ce97d1e
--- /dev/null
+++ b/include/elf/frv.h
@@ -0,0 +1,95 @@
+/* FRV ELF support for BFD.
+ Copyright (C) 2002 Free Software Foundation, Inc.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _ELF_FRV_H
+#define _ELF_FRV_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations. */
+START_RELOC_NUMBERS (elf_frv_reloc_type)
+ RELOC_NUMBER (R_FRV_NONE, 0)
+ RELOC_NUMBER (R_FRV_32, 1)
+ RELOC_NUMBER (R_FRV_LABEL16, 2)
+ RELOC_NUMBER (R_FRV_LABEL24, 3)
+ RELOC_NUMBER (R_FRV_LO16, 4)
+ RELOC_NUMBER (R_FRV_HI16, 5)
+ RELOC_NUMBER (R_FRV_GPREL12, 6)
+ RELOC_NUMBER (R_FRV_GPRELU12, 7)
+ RELOC_NUMBER (R_FRV_GPREL32, 8)
+ RELOC_NUMBER (R_FRV_GPRELHI, 9)
+ RELOC_NUMBER (R_FRV_GPRELLO, 10)
+ RELOC_NUMBER (R_FRV_GNU_VTINHERIT, 200)
+ RELOC_NUMBER (R_FRV_GNU_VTENTRY, 201)
+END_RELOC_NUMBERS(R_FRV_max)
+
+/* Processor specific flags for the ELF header e_flags field. */
+ /* gpr support */
+#define EF_FRV_GPR_MASK 0x00000003 /* mask for # of gprs */
+#define EF_FRV_GPR_32 0x00000001 /* -mgpr-32 */
+#define EF_FRV_GPR_64 0x00000002 /* -mgpr-64 */
+
+ /* fpr support */
+#define EF_FRV_FPR_MASK 0x0000000c /* mask for # of fprs */
+#define EF_FRV_FPR_32 0x00000004 /* -mfpr-32 */
+#define EF_FRV_FPR_64 0x00000008 /* -mfpr-64 */
+#define EF_FRV_FPR_NONE 0x0000000c /* -msoft-float */
+
+ /* double word support */
+#define EF_FRV_DWORD_MASK 0x00000030 /* mask for dword support */
+#define EF_FRV_DWORD_YES 0x00000010 /* use double word insns */
+#define EF_FRV_DWORD_NO 0x00000020 /* don't use double word insn*/
+
+#define EF_FRV_DOUBLE 0x00000040 /* -mdouble */
+#define EF_FRV_MEDIA 0x00000080 /* -mmedia */
+
+#define EF_FRV_PIC 0x00000100 /* -fpic */
+#define EF_FRV_NON_PIC_RELOCS 0x00000200 /* used non pic safe relocs */
+
+#define EF_FRV_MULADD 0x00000400 /* -mmuladd */
+#define EF_FRV_BIGPIC 0x00000800 /* -fPIC */
+#define EF_FRV_LIBPIC 0x00001000 /* -mlibrary-pic */
+#define EF_FRV_G0 0x00002000 /* -G 0, no small data ptr */
+#define EF_FRV_NOPACK 0x00004000 /* -mnopack */
+
+#define EF_FRV_CPU_MASK 0xff000000 /* specific cpu bits */
+#define EF_FRV_CPU_GENERIC 0x00000000 /* generic FRV */
+#define EF_FRV_CPU_FR500 0x01000000 /* FRV500 */
+#define EF_FRV_CPU_FR300 0x02000000 /* FRV300 */
+#define EF_FRV_CPU_SIMPLE 0x03000000 /* SIMPLE */
+#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */
+#define EF_FRV_CPU_FR400 0x05000000 /* FRV400 */
+
+ /* Mask of PIC related bits */
+#define EF_FRV_PIC_FLAGS (EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC)
+
+ /* Mask of all flags */
+#define EF_FRV_ALL_FLAGS (EF_FRV_GPR_MASK | \
+ EF_FRV_FPR_MASK | \
+ EF_FRV_DWORD_MASK | \
+ EF_FRV_DOUBLE | \
+ EF_FRV_MEDIA | \
+ EF_FRV_PIC_FLAGS | \
+ EF_FRV_NON_PIC_RELOCS | \
+ EF_FRV_MULADD | \
+ EF_FRV_G0 | \
+ EF_FRV_NOPACK | \
+ EF_FRV_CPU_MASK)
+
+#endif /* _ELF_FRV_H */
diff --git a/include/elf/i386.h b/include/elf/i386.h
index 4a15efc49..c6e9709a1 100644
--- a/include/elf/i386.h
+++ b/include/elf/i386.h
@@ -34,12 +34,31 @@ START_RELOC_NUMBERS (elf_i386_reloc_type)
RELOC_NUMBER (R_386_RELATIVE, 8) /* Adjust by program base */
RELOC_NUMBER (R_386_GOTOFF, 9) /* 32 bit offset to GOT */
RELOC_NUMBER (R_386_GOTPC, 10) /* 32 bit PC relative offset to GOT */
- FAKE_RELOC (FIRST_INVALID_RELOC, 11)
- FAKE_RELOC (LAST_INVALID_RELOC, 19)
+ RELOC_NUMBER (R_386_32PLT, 11) /* Used by Sun */
+ FAKE_RELOC (FIRST_INVALID_RELOC, 12)
+ FAKE_RELOC (LAST_INVALID_RELOC, 16)
+ RELOC_NUMBER (R_386_TLS_LE, 17)
+ RELOC_NUMBER (R_386_TLS_GD, 18)
+ RELOC_NUMBER (R_386_TLS_LDM, 19)
RELOC_NUMBER (R_386_16, 20)
RELOC_NUMBER (R_386_PC16, 21)
RELOC_NUMBER (R_386_8, 22)
RELOC_NUMBER (R_386_PC8, 23)
+ RELOC_NUMBER (R_386_TLS_GD_32, 24)
+ RELOC_NUMBER (R_386_TLS_GD_PUSH, 25)
+ RELOC_NUMBER (R_386_TLS_GD_CALL, 26)
+ RELOC_NUMBER (R_386_TLS_GD_POP, 27)
+ RELOC_NUMBER (R_386_TLS_LDM_32, 28)
+ RELOC_NUMBER (R_386_TLS_LDM_PUSH, 29)
+ RELOC_NUMBER (R_386_TLS_LDM_CALL, 30)
+ RELOC_NUMBER (R_386_TLS_LDM_POP, 31)
+ RELOC_NUMBER (R_386_TLS_LDO_32, 32)
+ RELOC_NUMBER (R_386_TLS_IE_32, 33)
+ RELOC_NUMBER (R_386_TLS_LE_32, 34)
+ RELOC_NUMBER (R_386_TLS_DTPMOD32, 35)
+ RELOC_NUMBER (R_386_TLS_DTPOFF32, 36)
+ RELOC_NUMBER (R_386_TLS_TPOFF32, 37)
+
/* These are GNU extensions to enable C++ vtable garbage collection. */
RELOC_NUMBER (R_386_GNU_VTINHERIT, 250)
RELOC_NUMBER (R_386_GNU_VTENTRY, 251)
diff --git a/include/elf/ia64.h b/include/elf/ia64.h
index 5e632ed01..310a7f74a 100644
--- a/include/elf/ia64.h
+++ b/include/elf/ia64.h
@@ -192,7 +192,7 @@ START_RELOC_NUMBERS (elf_ia64_reloc_type)
RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* @tprel(sym+add), data8 MSB */
RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* @tprel(sym+add), data8 LSB */
- RELOC_NUMBER (R_IA64_LTOFF_TP22, 0x9a) /* @ltoff(@tprel(s+a)), add imm22 */
+ RELOC_NUMBER (R_IA64_LTOFF_TPREL22, 0x9a) /* @ltoff(@tprel(s+a)), add imm22 */
RELOC_NUMBER (R_IA64_DTPMOD64MSB, 0xa6) /* @dtpmod(sym+add), data8 MSB */
RELOC_NUMBER (R_IA64_DTPMOD64LSB, 0xa7) /* @dtpmod(sym+add), data8 LSB */
diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog
index 96a4a058a..e0992c95a 100644
--- a/include/gdb/ChangeLog
+++ b/include/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2002-05-23 Andrew Cagney <ac131313@redhat.com>
+
+ * sim-d10v.h: New file. Moved from include/sim-d10v.h.
+
2002-05-10 Elena Zannoni <ezannoni@redhat.com>
* sim-sh.h: New file, for sh gdb<->sim interface.
diff --git a/include/gdb/sim-arm.h b/include/gdb/sim-arm.h
index 1e49781e8..6d80700ad 100644
--- a/include/gdb/sim-arm.h
+++ b/include/gdb/sim-arm.h
@@ -28,7 +28,7 @@
extern "C" { // }
#endif
-enum sim_arm_regnum
+enum sim_arm_regs
{
SIM_ARM_R0_REGNUM,
SIM_ARM_R1_REGNUM,
diff --git a/include/gdb/sim-d10v.h b/include/gdb/sim-d10v.h
index f153a4194..9d29e0584 100644
--- a/include/gdb/sim-d10v.h
+++ b/include/gdb/sim-d10v.h
@@ -1,6 +1,5 @@
/* This file defines the interface between the d10v simulator and gdb.
-
- Copyright 1999, 2002 Free Software Foundation, Inc.
+ Copyright 1999 Free Software Foundation, Inc.
This file is part of GDB.
@@ -76,61 +75,26 @@ extern unsigned long sim_d10v_translate_addr
/* The simulator makes use of the following register information. */
-enum sim_d10v_regs
-{
- SIM_D10V_R0_REGNUM,
- SIM_D10V_R1_REGNUM,
- SIM_D10V_R2_REGNUM,
- SIM_D10V_R3_REGNUM,
- SIM_D10V_R4_REGNUM,
- SIM_D10V_R5_REGNUM,
- SIM_D10V_R6_REGNUM,
- SIM_D10V_R7_REGNUM,
- SIM_D10V_R8_REGNUM,
- SIM_D10V_R9_REGNUM,
- SIM_D10V_R10_REGNUM,
- SIM_D10V_R11_REGNUM,
- SIM_D10V_R12_REGNUM,
- SIM_D10V_R13_REGNUM,
- SIM_D10V_R14_REGNUM,
- SIM_D10V_R15_REGNUM,
- SIM_D10V_CR0_REGNUM,
- SIM_D10V_CR1_REGNUM,
- SIM_D10V_CR2_REGNUM,
- SIM_D10V_CR3_REGNUM,
- SIM_D10V_CR4_REGNUM,
- SIM_D10V_CR5_REGNUM,
- SIM_D10V_CR6_REGNUM,
- SIM_D10V_CR7_REGNUM,
- SIM_D10V_CR8_REGNUM,
- SIM_D10V_CR9_REGNUM,
- SIM_D10V_CR10_REGNUM,
- SIM_D10V_CR11_REGNUM,
- SIM_D10V_CR12_REGNUM,
- SIM_D10V_CR13_REGNUM,
- SIM_D10V_CR14_REGNUM,
- SIM_D10V_CR15_REGNUM,
- SIM_D10V_A0_REGNUM,
- SIM_D10V_A1_REGNUM,
- SIM_D10V_SPI_REGNUM,
- SIM_D10V_SPU_REGNUM,
- SIM_D10V_IMAP0_REGNUM,
- SIM_D10V_IMAP1_REGNUM,
- SIM_D10V_DMAP0_REGNUM,
- SIM_D10V_DMAP1_REGNUM,
- SIM_D10V_DMAP2_REGNUM,
- SIM_D10V_DMAP3_REGNUM,
- SIM_D10V_TS2_DMAP_REGNUM
-};
-
enum
-{
- SIM_D10V_NR_R_REGS = 16,
- SIM_D10V_NR_A_REGS = 2,
- SIM_D10V_NR_IMAP_REGS = 2,
- SIM_D10V_NR_DMAP_REGS = 4,
- SIM_D10V_NR_CR_REGS = 16
-};
+ {
+ SIM_D10V_R0_REGNUM = 0,
+ SIM_D10V_CR0_REGNUM = 16,
+ SIM_D10V_A0_REGNUM = 32,
+ SIM_D10V_SPI_REGNUM = 34,
+ SIM_D10V_SPU_REGNUM = 35,
+ SIM_D10V_IMAP0_REGNUM = 36,
+ SIM_D10V_DMAP0_REGNUM = 38,
+ SIM_D10V_TS2_DMAP_REGNUM = 40
+ };
+
+enum
+ {
+ SIM_D10V_NR_R_REGS = 16,
+ SIM_D10V_NR_A_REGS = 2,
+ SIM_D10V_NR_IMAP_REGS = 2,
+ SIM_D10V_NR_DMAP_REGS = 4,
+ SIM_D10V_NR_CR_REGS = 16
+ };
#ifdef __cplusplus
}
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 2882ce568..100c886a7 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,21 @@
+2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net>
+
+ * dlx.h: New file.
+
+2002-05-25 Alan Modra <amodra@bigpond.net.au>
+
+ * ia64.h: Use #include "" instead of <> for local header files.
+ * sparc.h: Likewise.
+
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
+2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
+
+ * h8300.h: Corrected defs of all control regs
+ and eepmov instr.
+
2002-04-11 Alan Modra <amodra@bigpond.net.au>
* i386.h: Add intel mode cmpsd and movsd.
diff --git a/include/opcode/dlx.h b/include/opcode/dlx.h
index e1b249f85..23e3b00bc 100644
--- a/include/opcode/dlx.h
+++ b/include/opcode/dlx.h
@@ -163,7 +163,7 @@ struct dlx_opcode
char *args;
};
-static const struct dlx_opcode dlx_opcodes[] =
+static CONST struct dlx_opcode dlx_opcodes[] =
{
/* Arithmetic and Logic R-TYPE instructions. */
{ "nop", (ALUOP|NOPF), "N" }, /* NOP */
diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h
index 9cd40a6cb..18d17c537 100644
--- a/include/opcode/h8300.h
+++ b/include/opcode/h8300.h
@@ -333,8 +333,8 @@ struct h8_opcode h8_opcodes[] =
NEW_SOP(O(O_AND,SL),0,6,"and.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x6,B30|RD32,IMM32LIST,E}} EOP,
NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E}} EOP,
- NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
- NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
+ NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR|DST,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
+ NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
BRANCH(O(O_BRA,SB),"bra",0x0),
@@ -391,14 +391,14 @@ struct h8_opcode h8_opcodes[] =
NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E }},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP,
NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E }},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP,
- NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
- NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP,
+ NEW_SOP(O(O_DIVU,SB),1,13,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
+ NEW_SOP(O(O_DIVU,SW),0,21,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP,
- NEW_SOP(O(O_DIVS,SB),0,20,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
- NEW_SOP(O(O_DIVS,SW),0,02,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
+ NEW_SOP(O(O_DIVS,SB),0,13,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
+ NEW_SOP(O(O_DIVS,SW),0,21,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
- NEW_SOP(O(O_EEPMOV,SB),1,50,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP,
- NEW_SOP(O(O_EEPMOV,SW),0,50,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP,
+ NEW_SOP(O(O_EEPMOV,SB),1,4,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP,
+ NEW_SOP(O(O_EEPMOV,SW),0,4,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP,
NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{{OR16,E,0}},{{0x1,0x7,0xD,OR16,E }}EOP,
NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{{OR32,E,0}},{{0x1,0x7,0xF,OR32|B30,E }}EOP,
@@ -419,23 +419,23 @@ struct h8_opcode h8_opcodes[] =
SOP(O(O_JSR,SB),8,"jsr"),{{SRC|ABSJMP,E,0}},{{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP,
SOP(O(O_JSR,SB),8,"jsr"),{{SRC|MEMIND,E,0}},{{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP,
- NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR,E}}, {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
- NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR,E}}, {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR,E}}, {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR,E}}, {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR,E}}, {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR,E}}, {{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP,
-
- NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
- NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR,E}}, {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+ NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR|DST,E}}, {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
+ NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR|DST,E}}, {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR|DST,E}}, {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR|DST,E}}, {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR|DST,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR|DST,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR|DST,E}}, {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR|DST,E}}, {{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+
+ NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
+ NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR|DST,E}}, {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP,
SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}}, {{ 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP,
SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{ABS|SRC|L_32|MEMRELAX,RD8,E }}, {{ 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }}EOP,
@@ -520,8 +520,8 @@ struct h8_opcode h8_opcodes[] =
NEW_SOP(O(O_OR,SL),0,6,"or.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x4,B30|RD32,IMM32LIST,E}} EOP,
NEW_SOP(O(O_OR,SL),0,2,"or.l"),{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E}} EOP,
- NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
- NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
+ NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
+ NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{{OR16,E,0}},{{ 0x6,0xD,0x7,OR16,E,0,0,0,0}}EOP,
NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}}EOP,
@@ -544,25 +544,25 @@ struct h8_opcode h8_opcodes[] =
SOP(O(O_SLEEP,SN),2,"sleep"),{{E,0,0}},{{ 0x0,0x1,0x8,0x0,E,0,0,0,0}} EOP,
- NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
+ NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR|SRC,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RSIND,E}}, {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RDDEC,E}}, {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RSIND,E}}, {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDDEC,E}}, {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS16SRC,E}}, {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS32SRC,E}}, {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS16DST,E}}, {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS32DST,E}}, {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
- NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
+ NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR|SRC,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RSIND,E}}, {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RDDEC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RSIND,E}}, {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDDEC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS16SRC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS32SRC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS16DST,E}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS32DST,E}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
SOP(O(O_SUB,SB),2,"sub.b"),{{RS8,RD8,E}},{{ 0x1,0x8,RS8,RD8,E,0,0,0,0}}EOP,
@@ -585,8 +585,8 @@ struct h8_opcode h8_opcodes[] =
NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x5,B30|RD32,IMM32LIST,E}} EOP,
NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E}} EOP,
- SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
- SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
+ SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
+ SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP,
NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP,
diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h
index 642330cc1..d4e6d1081 100644
--- a/include/opcode/ia64.h
+++ b/include/opcode/ia64.h
@@ -1,5 +1,5 @@
/* ia64.h -- Header file for ia64 opcode table
- Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ Copyright (C) 1998, 1999, 2002 David Mosberger-Tang <davidm@hpl.hp.com>
See the file HP-COPYRIGHT for additional information. */
@@ -8,7 +8,7 @@
#include <sys/types.h>
-#include <bfd.h>
+#include "bfd.h"
typedef BFD_HOST_U_64_BIT ia64_insn;
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 96c7a576e..06f5625c3 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 5b6b5d149..c41292364 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -1,5 +1,5 @@
/* Definitions for opcode table for the sparc.
- Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000
+ Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
@@ -20,7 +20,7 @@ along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-#include <ansidecl.h>
+#include "ansidecl.h"
/* The SPARC opcode table (and other related data) is defined in
the opcodes library in sparc-opc.c. If you change anything here, make
diff --git a/include/sim-d10v.h b/include/sim-d10v.h
deleted file mode 100644
index 9d29e0584..000000000
--- a/include/sim-d10v.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* This file defines the interface between the d10v simulator and gdb.
- Copyright 1999 Free Software Foundation, Inc.
-
-This file is part of GDB.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
-#if !defined (SIM_D10V_H)
-#define SIM_D10V_H
-
-#ifdef __cplusplus
-extern "C" { // }
-#endif
-
-/* GDB interprets addresses as:
-
- 0x00xxxxxx: Physical unified memory segment (Unified memory)
- 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)
- 0x02xxxxxx: Physical data memory segment (On-chip data memory)
- 0x10xxxxxx: Logical data address segment (DMAP translated memory)
- 0x11xxxxxx: Logical instruction address segment (IMAP translated memory)
-
- The remote d10v board interprets addresses as:
-
- 0x00xxxxxx: Physical unified memory segment (Unified memory)
- 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)
- 0x02xxxxxx: Physical data memory segment (On-chip data memory)
-
- The following translate a virtual DMAP/IMAP offset into a physical
- memory segment assigning the translated address to PHYS. Since a
- memory access may cross a page boundrary the number of bytes for
- which the translation is applicable (or 0 for an invalid virtual
- offset) is returned. */
-
-enum
- {
- SIM_D10V_MEMORY_UNIFIED = 0x00000000,
- SIM_D10V_MEMORY_INSN = 0x01000000,
- SIM_D10V_MEMORY_DATA = 0x02000000,
- SIM_D10V_MEMORY_DMAP = 0x10000000,
- SIM_D10V_MEMORY_IMAP = 0x11000000
- };
-
-extern unsigned long sim_d10v_translate_dmap_addr
- (unsigned long offset,
- int nr_bytes,
- unsigned long *phys,
- unsigned long (*dmap_register) (int reg_nr));
-
-extern unsigned long sim_d10v_translate_imap_addr
- (unsigned long offset,
- int nr_bytes,
- unsigned long *phys,
- unsigned long (*imap_register) (int reg_nr));
-
-extern unsigned long sim_d10v_translate_addr
- (unsigned long vaddr,
- int nr_bytes,
- unsigned long *phys,
- unsigned long (*dmap_register) (int reg_nr),
- unsigned long (*imap_register) (int reg_nr));
-
-
-/* The simulator makes use of the following register information. */
-
-enum
- {
- SIM_D10V_R0_REGNUM = 0,
- SIM_D10V_CR0_REGNUM = 16,
- SIM_D10V_A0_REGNUM = 32,
- SIM_D10V_SPI_REGNUM = 34,
- SIM_D10V_SPU_REGNUM = 35,
- SIM_D10V_IMAP0_REGNUM = 36,
- SIM_D10V_DMAP0_REGNUM = 38,
- SIM_D10V_TS2_DMAP_REGNUM = 40
- };
-
-enum
- {
- SIM_D10V_NR_R_REGS = 16,
- SIM_D10V_NR_A_REGS = 2,
- SIM_D10V_NR_IMAP_REGS = 2,
- SIM_D10V_NR_DMAP_REGS = 4,
- SIM_D10V_NR_CR_REGS = 16
- };
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 18:37:04 +0300