diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/elf/ChangeLog | 25 | ||||
| -rw-r--r-- | include/elf/aarch64.h | 4 | ||||
| -rw-r--r-- | include/elf/common.h | 5 | ||||
| -rw-r--r-- | include/elf/mips.h | 6 | ||||
| -rw-r--r-- | include/elf/msp430.h | 47 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 17 | ||||
| -rw-r--r-- | include/opcode/avr.h | 13 | ||||
| -rw-r--r-- | include/opcode/mips.h | 19 | ||||
| -rw-r--r-- | include/opcode/msp430.h | 70 |
10 files changed, 193 insertions, 18 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index f084976f3..4d02320bc 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2013-05-06 Paul Brook <paul@codesourcery.com> + + include/elf/ + * mips.h (R_MIPS_PC32): Update comment. + 2013-04-03 Jason Merrill <jason@redhat.com> Demangle C++11 ref-qualifier. diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index c72659207..9be3cff6c 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,28 @@ +2013-05-30 Paul Brook <paul@codesourcery.com> + + * mips.h (R_MIPS_EH): New. + +2013-05-28 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (R_AARCH64_TLSDESC_LD64_PREL19): Rename to ... + (R_AARCH64_TLSDESC_LD_PREL19): ... this. + (R_AARCH64_TLSDESC_ADR_PAGE): Rename to ... + (R_AARCH64_TLSDESC_ADR_PAGE21): ... this. + +2013-05-22 H.J. Lu <hongjiu.lu@intel.com> + + * common.h (EM_INTEL205): New. + (EM_INTEL206): Likewise. + (EM_INTEL207): Likewise. + (EM_INTEL208): Likewise. + (EM_INTEL209): Likewise. + +2013-05-02 Nick Clifton <nickc@redhat.com> + + * msp430.h: Add MSP430X relocs. + Add some more MSP430 machine numbers. + Add values used by .MSP430.attributes section. + 2013-03-21 Michael Schewe <michael.schewe@gmx.net> * h8.h: Add new reloc R_H8_DISP32A16 for relaxation of diff --git a/include/elf/aarch64.h b/include/elf/aarch64.h index e3af4442a..a7b86c10e 100644 --- a/include/elf/aarch64.h +++ b/include/elf/aarch64.h @@ -178,9 +178,9 @@ RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12_NC, 551) FAKE_RELOC (R_AARCH64_tls_max, 552) FAKE_RELOC (R_AARCH64_tlsdesc_min, 560) -RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_PREL19, 560) +RELOC_NUMBER (R_AARCH64_TLSDESC_LD_PREL19, 560) RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PREL21, 561) -RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PAGE, 562) +RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PAGE21, 562) RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_LO12_NC, 563) RELOC_NUMBER (R_AARCH64_TLSDESC_ADD_LO12_NC, 564) RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G1, 565) diff --git a/include/elf/common.h b/include/elf/common.h index 8bdefa60b..cd3bcdd2b 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -296,6 +296,11 @@ #define EM_TILEGX 191 /* Tilera TILE-Gx multicore architecture family */ #define EM_RL78 197 /* Renesas RL78 family. */ #define EM_78K0R 199 /* Renesas 78K0R. */ +#define EM_INTEL205 205 /* Reserved by Intel */ +#define EM_INTEL206 206 /* Reserved by Intel */ +#define EM_INTEL207 207 /* Reserved by Intel */ +#define EM_INTEL208 208 /* Reserved by Intel */ +#define EM_INTEL209 209 /* Reserved by Intel */ /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision diff --git a/include/elf/mips.h b/include/elf/mips.h index ca9fdcd78..b5f7e1a89 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -152,10 +152,10 @@ START_RELOC_NUMBERS (elf_mips_reloc_type) FAKE_RELOC (R_MICROMIPS_max, 174) /* This was a GNU extension used by embedded-PIC. It was co-opted by - mips-linux for exception-handling data. It is no longer used, but - should continue to be supported by the linker for backward - compatibility. (GCC stopped using it in May, 2004.) */ + mips-linux for exception-handling data. GCC stopped using it in + May, 2004, then started using it again for compact unwind tables. */ RELOC_NUMBER (R_MIPS_PC32, 248) + RELOC_NUMBER (R_MIPS_EH, 249) /* FIXME: this relocation is used internally by gas. */ RELOC_NUMBER (R_MIPS_GNU_REL16_S2, 250) /* These are GNU extensions to enable C++ vtable garbage collection. */ diff --git a/include/elf/msp430.h b/include/elf/msp430.h index 44f5c51a7..ac8e28c31 100644 --- a/include/elf/msp430.h +++ b/include/elf/msp430.h @@ -1,5 +1,5 @@ /* MSP430 ELF support for BFD. - Copyright (C) 2002, 2003, 2004, 2010 Free Software Foundation, Inc. + Copyright (C) 2002-2013 Free Software Foundation, Inc. Contributed by Dmitry Diky <diwil@mail.ru> This file is part of BFD, the Binary File Descriptor library. @@ -33,6 +33,11 @@ #define E_MSP430_MACH_MSP430x14 14 #define E_MSP430_MACH_MSP430x15 15 #define E_MSP430_MACH_MSP430x16 16 +#define E_MSP430_MACH_MSP430x20 20 +#define E_MSP430_MACH_MSP430x22 22 +#define E_MSP430_MACH_MSP430x23 23 +#define E_MSP430_MACH_MSP430x24 24 +#define E_MSP430_MACH_MSP430x26 26 #define E_MSP430_MACH_MSP430x31 31 #define E_MSP430_MACH_MSP430x32 32 #define E_MSP430_MACH_MSP430x33 33 @@ -40,6 +45,19 @@ #define E_MSP430_MACH_MSP430x42 42 #define E_MSP430_MACH_MSP430x43 43 #define E_MSP430_MACH_MSP430x44 44 +#define E_MSP430_MACH_MSP430X 45 +#define E_MSP430_MACH_MSP430x46 46 +#define E_MSP430_MACH_MSP430x47 47 +#define E_MSP430_MACH_MSP430x54 54 + +#define SHT_MSP430_ATTRIBUTES 0x70000003 /* Section holds ABI attributes. */ +#define SHT_MSP430_SEC_FLAGS 0x7f000005 /* Holds TI compiler's section flags. */ +#define SHT_MSP430_SYM_ALIASES 0x7f000006 /* Holds TI compiler's symbol aliases. */ + +/* Tag values for an attribute section. */ +#define OFBA_MSPABI_Tag_ISA 4 +#define OFBA_MSPABI_Tag_Code_Model 6 +#define OFBA_MSPABI_Tag_Data_Model 8 /* Relocations. */ START_RELOC_NUMBERS (elf_msp430_reloc_type) @@ -52,7 +70,32 @@ START_RELOC_NUMBERS (elf_msp430_reloc_type) RELOC_NUMBER (R_MSP430_16_PCREL_BYTE, 6) RELOC_NUMBER (R_MSP430_2X_PCREL, 7) RELOC_NUMBER (R_MSP430_RL_PCREL, 8) - + RELOC_NUMBER (R_MSP430_8, 9) + RELOC_NUMBER (R_MSP430_SYM_DIFF, 10) END_RELOC_NUMBERS (R_MSP430_max) +START_RELOC_NUMBERS (elf_msp430x_reloc_type) + RELOC_NUMBER (R_MSP430_ABS32, 1) /* aka R_MSP430_32 */ + RELOC_NUMBER (R_MSP430_ABS16, 2) /* aka R_MSP430_16 */ + RELOC_NUMBER (R_MSP430_ABS8, 3) + RELOC_NUMBER (R_MSP430_PCR16, 4) /* aka R_MSP430_16_PCREL */ + RELOC_NUMBER (R_MSP430X_PCR20_EXT_SRC, 5) + RELOC_NUMBER (R_MSP430X_PCR20_EXT_DST, 6) + RELOC_NUMBER (R_MSP430X_PCR20_EXT_ODST, 7) + RELOC_NUMBER (R_MSP430X_ABS20_EXT_SRC, 8) + RELOC_NUMBER (R_MSP430X_ABS20_EXT_DST, 9) + RELOC_NUMBER (R_MSP430X_ABS20_EXT_ODST, 10) + RELOC_NUMBER (R_MSP430X_ABS20_ADR_SRC, 11) + RELOC_NUMBER (R_MSP430X_ABS20_ADR_DST, 12) + RELOC_NUMBER (R_MSP430X_PCR16, 13) /* Like R_MSP430_PCR16 but with overflow checking. */ + RELOC_NUMBER (R_MSP430X_PCR20_CALL, 14) + RELOC_NUMBER (R_MSP430X_ABS16, 15) /* Like R_MSP430_ABS16 but with overflow checking. */ + RELOC_NUMBER (R_MSP430_ABS_HI16, 16) + RELOC_NUMBER (R_MSP430_PREL31, 17) + RELOC_NUMBER (R_MSP430_EHTYPE, 18) /* Mentioned in ABI. */ + RELOC_NUMBER (R_MSP430X_10_PCREL, 19) /* Red Hat invention. Used for Jump instructions. */ + RELOC_NUMBER (R_MSP430X_2X_PCREL, 20) /* Red Hat invention. Used for relaxing jumps. */ + RELOC_NUMBER (R_MSP430X_SYM_DIFF, 21) /* Red Hat invention. Used for relaxing debug info. */ +END_RELOC_NUMBERS (R_MSP430x_max) + #endif /* _ELF_MSP430_H */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 9eed10498..7ed2c6874 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,20 @@ +2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> + + * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. + +2013-05-09 Andrew Pinski <apinski@cavium.com> + + * mips.h (OP_MASK_CODE10): Correct definition. + (OP_SH_CODE10): Likewise. + Add a comment that "+J" is used now for OP_*CODE10. + (INSN_ASE_MASK): Update. + (INSN_VIRT): New macro. + (INSN_VIRT64): New macro + +2013-05-02 Nick Clifton <nickc@redhat.com> + + * msp430.h: Add patterns for MSP430X instructions. + 2013-04-06 David S. Miller <davem@davemloft.net> * sparc.h (F_PREFERRED): Define. diff --git a/include/opcode/avr.h b/include/opcode/avr.h index 6e86c07ba..f1d73ad92 100644 --- a/include/opcode/avr.h +++ b/include/opcode/avr.h @@ -33,7 +33,7 @@ #define AVR_ISA_MOVW 0x1000 /* device has MOVW */ #define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */ #define AVR_ISA_DES 0x4000 /* device has DES */ -#define AVR_ISA_XCH 0x8000 /* device has XCH, LAC, LAS, LAT */ +#define AVR_ISA_RMW 0x8000 /* device has RMW instructions XCH,LAC,LAS,LAT */ #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) @@ -53,7 +53,8 @@ #define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) #define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) #define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND) -#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES | AVR_ISA_XCH) +#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES) +#define AVR_ISA_XMEGAU (AVR_ISA_XMEGA | AVR_ISA_RMW) #define AVR_ISA_AVR1 AVR_ISA_TINY1 #define AVR_ISA_AVR2 AVR_ISA_2xxx @@ -266,10 +267,10 @@ AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) /* Atomic memory operations for XMEGA. List before `sts'. */ -AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_XCH, 0x9204) -AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_XCH, 0x9205) -AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_XCH, 0x9206) -AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_XCH, 0x9207) +AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204) +AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205) +AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206) +AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207) /* Known to be decoded as `nop' by the old core. */ AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) diff --git a/include/opcode/mips.h b/include/opcode/mips.h index ef81bbe2b..07259ea06 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -212,6 +212,10 @@ #define OP_OP_SDC2 0x3e #define OP_OP_SDC3 0x3f /* a.k.a. sd */ +/* MIPS VIRT ASE */ +#define OP_MASK_CODE10 0x3ff +#define OP_SH_CODE10 11 + /* Values in the 'VSEL' field. */ #define MDMX_FMTSEL_IMM_QH 0x1d #define MDMX_FMTSEL_IMM_OB 0x1e @@ -255,8 +259,6 @@ of the operand handling in GAS. The fields below only exist in the microMIPS encoding, so define each one to have an empty range. */ -#define OP_MASK_CODE10 0 -#define OP_SH_CODE10 0 #define OP_MASK_TRAP 0 #define OP_SH_TRAP 0 #define OP_MASK_OFFSET10 0 @@ -486,6 +488,9 @@ struct mips_opcode "~" 12 bit offset (OP_*_OFFSET12) "\" 3 bit position for aset and aclr (OP_*_3BITPOS) + VIRT ASE usage: + "+J" 10-bit hypcall code (OP_*CODE10) + UDI immediates: "+1" UDI immediate bits 6-10 "+2" UDI immediate bits 6-15 @@ -528,7 +533,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234" - "ABCDEFGHIPQSTXZ" + "ABCDEFGHIJPQSTXZ" "abcpstxz" */ @@ -726,7 +731,7 @@ static const unsigned int mips_isa_table[] = #define INSN_OCTEON2 0x00000100 /* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x3c00f010 +#define INSN_ASE_MASK 0x3c00f0d0 /* DSP ASE */ #define INSN_DSP 0x00001000 @@ -735,6 +740,10 @@ static const unsigned int mips_isa_table[] = /* MIPS R5900 instruction */ #define INSN_5900 0x00004000 +/* Virtualization ASE */ +#define INSN_VIRT 0x00000080 +#define INSN_VIRT64 0x00000040 + /* MIPS-3D ASE */ #define INSN_MIPS3D 0x00008000 @@ -1061,6 +1070,7 @@ enum M_LDC1_AB, M_LDC2_AB, M_LDC2_OB, + M_LQC2_AB, M_LDC3_AB, M_LDL_AB, M_LDL_OB, @@ -1154,6 +1164,7 @@ enum M_SDC1_AB, M_SDC2_AB, M_SDC2_OB, + M_SQC2_AB, M_SDC3_AB, M_SDL_AB, M_SDL_OB, diff --git a/include/opcode/msp430.h b/include/opcode/msp430.h index d3bf130ee..caddc42db 100644 --- a/include/opcode/msp430.h +++ b/include/opcode/msp430.h @@ -1,6 +1,6 @@ /* Opcode table for the TI MSP430 microcontrollers - Copyright 2002, 2004, 2010 Free Software Foundation, Inc. + Copyright 2002-2013 Free Software Foundation, Inc. Contributed by Dmitry Diky <diwil@mail.ru> This program is free software; you can redistribute it and/or modify @@ -119,6 +119,74 @@ static struct msp430_opcode_s msp430_opcodes[] = MSP_INSN (bleu, 5, 2, 0, 0xffff), MSP_INSN (ble, 5, 3, 0, 0xffff), + /* MSP430X instructions - these ones use an extension word. + A negative format indicates an MSP430X instruction. */ + MSP_INSN (addcx, -2, 2, 0x6000, 0xf000), + MSP_INSN (addx, -2, 2, 0x5000, 0xf000), + MSP_INSN (andx, -2, 2, 0xf000, 0xf000), + MSP_INSN (bicx, -2, 2, 0xc000, 0xf000), + MSP_INSN (bisx, -2, 2, 0xd000, 0xf000), + MSP_INSN (bitx, -2, 2, 0xb000, 0xf000), + MSP_INSN (cmpx, -2, 2, 0x9000, 0xf000), + MSP_INSN (daddx, -2, 2, 0xa000, 0xf000), + MSP_INSN (movx, -2, 2, 0x4000, 0xf000), + MSP_INSN (subcx, -2, 2, 0x7000, 0xf000), + MSP_INSN (subx, -2, 2, 0x8000, 0xf000), + MSP_INSN (xorx, -2, 2, 0xe000, 0xf000), + + /* MSP430X Synthetic instructions. */ + MSP_INSN (adcx, -1, 1, 0x6300, 0xff30), + MSP_INSN (clra, -1, 1, 0x4300, 0xff30), + MSP_INSN (clrx, -1, 1, 0x4300, 0xff30), + MSP_INSN (dadcx, -1, 1, 0xa300, 0xff30), + MSP_INSN (decx, -1, 1, 0x8310, 0xff30), + MSP_INSN (decda, -1, 1, 0x8320, 0xff30), + MSP_INSN (decdx, -1, 1, 0x8320, 0xff30), + MSP_INSN (incx, -1, 1, 0x5310, 0xff30), + MSP_INSN (incda, -1, 1, 0x5320, 0xff30), + MSP_INSN (incdx, -1, 1, 0x5320, 0xff30), + MSP_INSN (invx, -1, 1, 0xe330, 0xfff0), + MSP_INSN (popx, -1, 1, 0x4130, 0xff30), + MSP_INSN (rlax, -1, 2, 0x5000, 0xf000), + MSP_INSN (rlcx, -1, 2, 0x6000, 0xf000), + MSP_INSN (sbcx, -1, 1, 0x7300, 0xff30), + MSP_INSN (tsta, -1, 1, 0x9300, 0xff30), + MSP_INSN (tstx, -1, 1, 0x9300, 0xff30), + + MSP_INSN (pushx, -3, 1, 0x1200, 0xff80), + MSP_INSN (rrax, -3, 1, 0x1100, 0xff80), + MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80), + MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0), + MSP_INSN (sxtx, -3, 1, 0x1180, 0xffc0), + + /* MSP430X Address instructions - no extension word needed. + The insn_opnumb field is used to encode the nature of the + instruction for assembly and disassembly purposes. */ + MSP_INSN (calla, -1, 4, 0x1300, 0xff00), + + MSP_INSN (popm, -1, 5, 0x1600, 0xfe00), + MSP_INSN (pushm, -1, 5, 0x1400, 0xfe00), + + MSP_INSN (rrcm, -1, 6, 0x0040, 0xf3e0), + MSP_INSN (rram, -1, 6, 0x0140, 0xf3e0), + MSP_INSN (rlam, -1, 6, 0x0240, 0xf3e0), + MSP_INSN (rrum, -1, 6, 0x0340, 0xf3e0), + + MSP_INSN (rrux, -1, 7, 0x0340, 0xffe0), /* Synthesized in terms of RRUM. */ + + MSP_INSN (adda, -1, 8, 0x00a0, 0xf0b0), + MSP_INSN (cmpa, -1, 8, 0x0090, 0xf0b0), + MSP_INSN (suba, -1, 8, 0x00b0, 0xf0b0), + + MSP_INSN (reta, -1, 9, 0x0110, 0xffff), + MSP_INSN (bra, -1, 9, 0x0000, 0xf0cf), + MSP_INSN (mova, -1, 9, 0x0000, 0xf080), + MSP_INSN (mova, -1, 9, 0x0080, 0xf0b0), + MSP_INSN (mova, -1, 9, 0x00c0, 0xf0f0), + + /* Pseudo instruction to set the repeat field in the extension word. */ + MSP_INSN (rpt, -1, 10, 0x0000, 0x0000), + /* End of instruction set. */ { NULL, 0, 0, 0, 0 } }; |