diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 10 | ||||
| -rw-r--r-- | include/opcode/tic6x-opcode-table.h | 33 | ||||
| -rw-r--r-- | include/opcode/tic6x.h | 9 |
3 files changed, 36 insertions, 16 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index a46900ac1..69d0859e1 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,13 @@ +2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR gas/15095 + * tic6x.h (enum tic6x_coding_method): Add + tic6x_coding_dreg_(msb|lsb) field coding type in order to encode + separately the msb and lsb of a register pair. This is needed to + encode the opcodes in the same way as TI assembler does. + * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp + and rsqrdp opcodes to use the new field coding types. + 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm.h (CRC_EXT_ARMV8): New constant. diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h index 45e26fb87..abebd3c17 100644 --- a/include/opcode/tic6x-opcode-table.h +++ b/include/opcode/tic6x-opcode-table.h @@ -1,6 +1,5 @@ /* TI C6X opcode table. - Copyright 2010, 2011 - Free Software Foundation, Inc. + Copyright 2010-2013 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -129,9 +128,10 @@ INSN(abs2, l, unary, 1cycle, C64X, 0, ENC(dst, reg, 1))) INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x2c), FIX(x, 0), FIX(src1, 0)), + FIX2(FIX(op, 0x2c), FIX(x, 0)), OP2(ORREGD1, OWREGD12), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), + ENC(dst, reg, 1))) INSN(abssp, s, unary, 1cycle, C67X, 0, FIX1(FIX(op, 0)), @@ -916,19 +916,22 @@ INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x8), FIX(x, 0), FIX(src1, 0)), + FIX2(FIX(op, 0x8), FIX(x, 0)), OP2(ORREGD1, OWREG4), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), + ENC(dst, reg, 1))) INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x9), FIX(x, 0), FIX(src1, 0)), + FIX2(FIX(op, 0x9), FIX(x, 0)), OP2(ORREGD1, OWREG4), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), + ENC(dst, reg, 1))) INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x1), FIX(x, 0), FIX(src1, 0)), + FIX2(FIX(op, 0x1), FIX(x, 0)), OP2(ORREGD1, OWREG4), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), + ENC(dst, reg, 1))) INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x1)), @@ -1617,9 +1620,10 @@ INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0, ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x2d), FIX(x, 0), FIX(src1, 0)), + FIX2(FIX(op, 0x2d), FIX(x, 0)), OP2(ORREGD1, OWREGD12), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), + ENC(dst, reg, 1))) INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0, FIX2(FIX(op, 0x3d), FIX(src1, 0)), @@ -1677,9 +1681,10 @@ INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0, ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x2e), FIX(x, 0), FIX(src1, 0)), + FIX2(FIX(op, 0x2e), FIX(x, 0)), OP2(ORREGD1, OWREGD12), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), + ENC(dst, reg, 1))) INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0, FIX2(FIX(op, 0x3e), FIX(src1, 0)), diff --git a/include/opcode/tic6x.h b/include/opcode/tic6x.h index 2a7a2463d..168f66023 100644 --- a/include/opcode/tic6x.h +++ b/include/opcode/tic6x.h @@ -1,6 +1,5 @@ /* TI C6X opcode information. - Copyright 2010, 2011 - Free Software Foundation, Inc. + Copyright 2010-2013 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -380,6 +379,12 @@ typedef enum the field. When applied to a memory reference, encode the base register. */ tic6x_coding_reg, + /* Encode the register-pair's lsb (even register) for instructions + that use src1 as port for loading lsb of double-precision + operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp). */ + tic6x_coding_regpair_lsb, + /* Encode the register-pair's msb (odd register), see above. */ + tic6x_coding_regpair_msb, /* Store 0 for register B14, 1 for register B15. When applied to a memory reference, encode the base register. */ tic6x_coding_areg, |