| Age | Commit message (Collapse) | Author |
|---|
|
mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
values.
|
|
|
|
2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.h (CpuPNI): Removed.
(CpuUnknownFlags): Replace CpuPNI with CpuSSE3.
* config/tc-i386.c (md_assemble): Likewise.
include/opcode/
2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
|
|
(my_get_expression): Const operand of some instructions can not be symbol in assembly.
(get_insn_class_from_type): Handle instruction type Insn_internal.
(do_macro_ldst_label): Modify inst.type.
(Insn_PIC): Delete.
* score-inst.h (enum score_insn_type): Add Insn_internal.
* tc-score.c (data_op2): The immediate value in lw is 15 bit signed.
* score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.
|
|
|
|
|
|
|
|
2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.h (CpuMNI): Renamed to ...
(CpuSSSE3): This.
(CpuUnknownFlags): Updated.
(processor_type): Replace PROCESSOR_YONAH with PROCESSOR_CORE
and PROCESSOR_MEROM with PROCESSOR_CORE2.
* config/tc-i386.c: Updated.
* doc/c-i386.texi: Likewise.
* config/tc-i386.c (cpu_arch): Add ".ssse3", "core" and "core2".
include/opcode/
2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
* i386.h: Replace CpuMNI with CpuSSSE3.
|
|
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
|
|
|
|
* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
movdq2q and movq2dq.
|
|
|
|
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run nops and x86-64-nops.
* gas/i386/nops.d: New file.
* gas/i386/nops.s: Likewise.
* gas/i386/x86-64-nops.d: Likewise.
* gas/i386/x86-64-nops.s: Likewise.
include/opcode/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Add "nop" with memory reference.
opcodes/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
(twobyte_has_modrm): Set 1 for 0x1f.
|
|
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Don't add rex64 for
"xchg %rax,%rax".
gas/testsuite/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/opcode.s: Add "xchg %ax,%ax".
* gas/i386/opcode.d: Updated.
* gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax,
xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8.
* gas/i386/x86-64-opcode.d: Updated.
include/opcode/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Update comment for 64bit NOP.
opcodes/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (NOP_Fixup): Removed.
(NOP_Fixup1): New.
(NOP_Fixup2): Likewise.
(dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
|
|
* ppc.h (PPC_OPCODE_POWER6): Define.
Adjust whitespace.
gas/
* config/tc-ppc.c (parse_cpu): Handle "-mpower6".
(md_show_usage): Document it.
(ppc_setup_opcodes): Test power6 opcode flag bits.
* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
opcodes/
* ppc-dis.c (powerpc_dialect): Handle power6 option.
(print_ppc_disassembler_options): Mention power6.
|
|
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
appropriate.
(mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
(mips_ip): Make overflowed/underflowed constant arguments in DSP
and MT instructions a fatal error. Use INSERT_OPERAND where
appropriate. Improve warnings for break and wait code overflows.
Use symbolic constant of OP_MASK_COPZ.
(mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d,
gas/mips/mips32-mt.s: Remove instructions with invalid arguments.
* gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file.
[ include/opcode/ChangeLog ]
* mips.h: Improve description of MT flags.
|
|
* m68k.h (mcf_mask): Define.
opcodes/
* m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
and fmovem entries. Put register list entries before immediate
mask entries. Use "l" rather than "L" in the fmovem entries.
* m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
out from INFO.
(m68k_scan_mask): New function, split out from...
(print_insn_m68k): ...here. If no architecture has been set,
first try printing an m680x0 instruction, then try a Coldfire one.
gas/testsuite/
* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
* gas/m68k/mcf-fpu.d: Adjust accordingly.
|
|
* config/tc-mips.c (macro_build): Add case 'k' to handle cache
instruction.
(macro): Add new case M_CACHE_AB.
[ opcodes/ChangeLog ]
* mips-opc.c: Add macro for cache instruction.
[ include/opcode/ChangeLog ]
* mips.h (enum): Add macro M_CACHE_AB.
|
|
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
* gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2.
* gas/mips/set-arch.d: Adjust according to opcode table changes.
[ include/opcode/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips.h: Add INSN_SMARTMIPS define.
[ opcodes/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips-dis.c (mips_arch_choices): Add smartmips instruction
decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
MIPS64R2.
* mips-opc.c: fix random typos in comments.
(INSN_SMARTMIPS): New defines.
(mips_builtin_opcodes): Add paired single support for MIPS32R2.
Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
FP_S and FP_D flags to denote single and double register
accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
for MIPS32R2. Add SmartMIPS instructions. Add two-argument
variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
release 2 ISAs.
* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
|
|
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
(mips_immed): New table that records various handling of udi
instruction patterns.
(mips_ip): Adds udi handling.
[ include/opcode/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips.h: Defines udi bits and masks. Add description of
characters which may appear in the args field of udi
instructions.
[ opcodes/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips-opc.c (mips_builtin_opcodes): Add udi instructions
"udi0" to "udi15".
* mips-dis.c (print_insn_args): Adds udi argument handling.
|
|
|
|
fields.
|
|
attiny85, attiny24, attiny44, attiny84, at90pwm2, at90pwm3, atmega164,
atmega324, atmega644, atmega329, atmega3290, atmega649, atmega6490,
atmega406, atmega640, atmega1280, atmega1281, at90can32, at90can64,
at90usb646, at90usb647, at90usb1286 and at90usb1287.
Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
|
|
* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
m68020_control_regs, m68040_control_regs, m68060_control_regs,
mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
mcf5282_ctrl, mcfv4e_ctrl): ... these.
(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
(struct m68k_cpu): Change chip field to control_regs.
(current_chip): Remove.
(control_regs): New.
(m68k_archs, m68k_extensions): Adjust.
(m68k_cpus): Reorder to be in cpu number order. Adjust.
(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
(find_cf_chip): Reimplement for new organization of cpu table.
(select_control_regs): Remove.
(mri_chip): Adjust.
(struct save_opts): Save control regs, not chip.
(s_save, s_restore): Adjust.
(m68k_lookup_cpu): Give deprecated warning when necessary.
(m68k_init_arch): Adjust.
(md_show_usage): Adjust for new cpu table organization.
include/opcodes:
* m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
|
|
include/opcode/
* arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
|
|
* m68k.h (m68008, m68ec030, m68882): Remove.
(m68k_mask): New.
(cpu_m68k, cpu_cf): New.
(mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407
|
|
first. Correct mask of bb "B" opcode.
|
|
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (output_insn): Support Intel Merom New
Instructions.
* gas/config/tc-i386.h (CpuMNI): New.
(CpuUnknownFlags): Add CpuMNI.
gas/testsuite/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add merom and x86-64-merom.
* gas/i386/merom.d: New file.
* gas/i386/merom.s: Likewise.
* gas/i386/x86-64-merom.d: Likewise.
* gas/i386/x86-64-merom.s: Likewise.
include/opcode/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Support Intel Merom New Instructions.
opcodes/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
Intel Merom New Instructions.
(THREE_BYTE_0): Likewise.
(THREE_BYTE_1): Likewise.
(three_byte_table): Likewise.
(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
THREE_BYTE_1 for entry 0x3a.
(twobyte_has_modrm): Updated.
(twobyte_uses_SSE_prefix): Likewise.
(print_insn): Handle 3-byte opcodes used by Intel Merom New
Instructions.
|
|
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
|
|
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* cpu-ia64-opc.c (ins_immu5b): New.
(ext_immu5b): Likewise.
(elf64_ia64_operands): Add IMMU5b.
gas/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
gas/testsuite/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/opc-i.s: Add tests for tf.
* gas/ia64/pseudo.s: Likewise.
* gas/ia64/opc-i.d: Updated.
* gas/ia64/pseudo.d: Likewise.
include/opcode/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
opcodes/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* ia64-opc-i.c (bXc): New.
(mXc): Likewise.
(OpX2TaTbYaXcC): Likewise.
(TF). Likewise.
(TFCM). Likewise.
(ia64_opcodes_i): Add instructions for tf.
* ia64-opc.h (IMMU5b): New.
* ia64-asmtab.c: Regenerated.
|
|
Richard Earnshaw <rearnsha@arm.com>
* gas/config/tc-arm.c: Use arm_feature_set.
(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
New variables.
(insns): Use them.
(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
feature flags.
(arm_legacy_option_table, arm_option_cpu_value_table): New types.
(arm_opts): Move old cpu/arch options from here...
(arm_legacy_opts): ... to here.
(md_parse_option): Search arm_legacy_opts.
(arm_cpus, arm_archs, arm_extensions, arm_fpus)
(arm_float_abis, arm_eabis): Make const.
* include/opcode/arm.h: Use ARM_CPU_FEATURE.
(ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
(arm_feature_set): Change to a structure.
(ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
ARM_FEATURE): New macros.
|
|
(MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
(ADD_PC_INCR_OPCODE): Don't define.
|
|
2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
PR gas/1874
* config/tc-i386.c (match_template): Handle monitor.
(process_suffix): Likewise.
gas/testsuite/
2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
PR gas/1874
* gas/i386/i386.exp: Add x86-64-prescott for 64bit.
* gas/i386/prescott.s: Test address size override for monitor.
* gas/i386/prescott.d: Updated.
* gas/i386/x86-64-prescott.d: New file.
* gas/i386/x86-64-prescott.s: Likewise.
include/opcode/
2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
PR gas/1874
* i386.h (i386_optab): Add 64bit support for monitor and mwait.
opcodes/
2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
PR gas/1874
* i386-dis.c (address_mode): New enum type.
(address_mode): New variable.
(mode_64bit): Removed.
(ckprefix): Updated to check address_mode instead of mode_64bit.
(prefix_name): Likewise.
(print_insn): Likewise.
(putop): Likewise.
(print_operand_value): Likewise.
(intel_operand_size): Likewise.
(OP_E): Likewise.
(OP_G): Likewise.
(set_op): Likewise.
(OP_REG): Likewise.
(OP_I): Likewise.
(OP_I64): Likewise.
(OP_OFF): Likewise.
(OP_OFF64): Likewise.
(ptr_reg): Likewise.
(OP_C): Likewise.
(SVME_Fixup): Likewise.
(print_insn): Set address_mode.
(PNI_Fixup): Add 64bit and address size override support for
monitor and mwait.
|
|
instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
save/restore encoding of the args field.
* mips16-opc.c: Add MIPS16e save/restore opcodes.
* mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M'
codes for save/restore.
* config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes
for the MIPS16e save/restore instructions.
* gas/mips/mips.exp: Run new save/restore tests.
* gas/testsuite/gas/mips/mips16e-save.s: New test for generating
different styles of save/restore instructions.
* gas/testsuite/gas/mips/mips16e-save.d: New.
|
|
Contribute the following changes:
2003-09-29 Dave Brolley <brolley@redhat.com>
* dis-asm.h (disassemble_info): insn_sets now (void *) to allow for
more exotic underlying types to be used.
|
|
Contribute the following changes:
2005-02-16 Dave Brolley <brolley@redhat.com>
* cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
cgen_isa_mask_* to cgen_bitset_*.
* cgen.h: Likewise.
|
|
|
|
2005-10-24 Jan Beulich <jbeulich@novell.com>
* ia64.h (enum ia64_opnd): Move memory operand out of set of
indirect operands.
bfd/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* cpu-ia64-opc.c (elf64_ia64_operands): Move memory operand out of
set of indirect operands.
gas/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (enum reg_symbol): Delete IND_MEM.
(dot_rot): Change type of num_* variables. Check for positive count.
(ia64_optimize_expr): Re-structure.
(md_operand): Check for general register.
gas/testsuite/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* gas/ia64/index.[sl]: New.
* gas/ia64/rotX.[sl]: New.
* gas/ia64/ia64.exp: Run new tests.
opcodes/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* ia64-asmtab.c: Regenerate.
|
|
Add FLAG_STRICT to pa10 ftest opcode.
|
|
instructions from system.s.
* gas/hppa/basic/system.s (lha): Remove.
* hppa.h (pa_opcodes): Remove lha entries.
|
|
(pa_ip): Promote from PA 1.0 to 1.1 immediately when 1.1 match is
found. Simplify handling of "ma" and "mb" completers.
* hppa.h (FLAG_STRICT): Revise comment.
(pa_opcode): Revise ordering rules. Add/move strict pa10 variants
before corresponding pa11 opcodes. Add strict pa10 register-immediate
entries for "fdc".
|
|
|
|
|
|
OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
define.
Document !, $, *, &, g, +t, +T operand formats for MT instructions.
(INSN_ASE_MASK): Update to include INSN_MT.
(INSN_MT): New define for MT ASE.
|
|
OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
instructions.
(INSN_DSP): New define for DSP ASE.
|
|
|
|
* config/tc-ppc.c (parse_cpu): Add -me300 support.
(md_show_usage): Likewise.
* doc/c-ppc.texi (PowerPC-Opts): Document it.
include/opcode/
* ppc.h (PPC_OPCODE_E300): Define.
opcodes/
* ppc-dis.c (powerpc_dialect): Handle e300.
(print_ppc_disassembler_options): Likewise.
* ppc-opc.c (PPCE300): Define.
(powerpc_opcodes): Mark icbt as available for the e300.
binutils/
* doc/binutils.texi (objdump): Document -M e300.
|
|
|
|
* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
and pitlb.
|
|
2005-07-27 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add comment to movd. Use LongMem for all
movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
Add movq-s as 64-bit variants of movd-s.
|
