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2009-09-05 * bfd/coff-arm.c (coff_arm_relocate_section)Nick Clifton
(record_thumb_to_arm_glue, bfd_arm_process_before_allocation): Change member name class to symbol_class. * bfd/coff-i960.c (coff_i960_relocate_section) Rename variable class to class_val. Change member name class to symbol_class. * bfd/coff-rs6000.c (_bfd_xcoff_swap_aux_in) (_bfd_xcoff_swap_aux_out): Rename arguments class to in_class. * bfd/coff-stgo32.c (adjust_aux_in_post) (adjust_aux_out_pre, adjust_aux_out_post): Rename arguments class to in_class. * bfd/coff64-rs6000.c (_bfd_xcoff64_swap_aux_in) (_bfd_xcoff64_swap_aux_out): Rename arguments class to in_class. * bfd/coffcode.h (coff_pointerize_aux_hook): Rename variable class to n_sclass. * bfd/coffgen.c (coff_write_symbol, coff_pointerize_aux): Rename variables named class to n_sclass. (coff_write_symbols): Rename variable class to sym_class. (bfd_coff_set_symbol_class): Rename argument class to symbol_class. * bfd/cofflink.c (_bfd_coff_link_hash_newfunc) (coff_link_add_symbols, _bfd_coff_link_input_bfd) (_bfd_coff_write_global_sym, _bfd_coff_generic_relocate_section): Update code to use renamed members. * bfd/coffswap.h (coff_swap_aux_in, coff_swap_aux_out): Rename argument class to in_class. * bfd/libcoff-in.h (struct coff_link_hash_entry, struct coff_debug_merge_type) Renamed members class to symbol_class and type_class. * bfd/libcoff.h Regenerated. * bfd/peXXigen.c: (_bfd_XXi_swap_aux_in, _bfd_XXi_swap_aux_out): Rename argument class to in_class. * bfd/pef.c (bfd_pef_parse_imported_symbol): Update code to use renamed members. * bfd/pef.h (struct bfd_pef_imported_symbol): Changed name of member class to symbol_class. * binutils/ieee.c (ieee_read_cxx_misc, ieee_read_cxx_class) (ieee_read_reference): Rename variables named class to cxxclass. * gas/config/tc-arc.c (struct syntax_classes): Rename member class to s_class. (arc_extinst): Rename variable class to s_class. Update code to use renamed members. * gas/config/tc-mips.c (insn_uses_reg): Rename argument class to regclass. * gas/config/tc-ppc.c (ppc_csect, ppc_change_csect, ppc_function) (ppc_tc, ppc_is_toc_sym, ppc_symbol_new_hook, ppc_frob_label) (ppc_fix_adjustable, md_apply_fix): Update code to use renamed members. * gas/config/tc-ppc.h (struct ppc_tc_sy): Change name of member from class to symbol_class. (OBJ_COPY_SYMBOL_ATTRIBUTES): Update code to use renamed members. * gas/config/tc-score.c (s3_adjust_paritybit): Rename argument class to i_class. * gas/config/tc-score7.c (s7_adjust_paritybit): Rename argument class to i_class. * gprof/corefile.c (core_create_function_syms): Rename variable class to cxxclass. * include/coff/ti.h (GET_LNSZ_SIZE, PUT_LNSZ_SIZE): Updated name of class variable to in_class to match changes in function that use this macro. * include/opcode/ia64.h (struct ia64_operand): Renamed member class to op_class * ld/emultempl/elf32.em (gld${EMULATION_NAME}_load_symbols) (gld${EMULATION_NAME}_try_needed): Rename variable class to link_class * opcodes/ia64-dis.c (print_insn_ia64): Update code to use renamed member. * opcodes/m88k-dis.c (m88kdis): Rename variable class to in_class. * opcodes/tic80-opc.c (tic80_symbol_to_value) (tic80_value_to_symbol): Rename argument class to symbol_class.
2009-09-04 gas/Jie Zhang
* config/bfin-parse.y (asm_1): Implement HLT instruction. Fix comments for DBGA, DBGAH and DBGAL. * config/tc-bfin.c (bfin_gen_pseudodbg_assert): Change according to the new encoding of DBGA, DBGAH, and DBGAL. include/ * opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): Adjust accordingly. (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and PseudoDbg_Assert_grp_mask. opcodes/ * bfin-dis.c (decode_pseudodbg_assert_0): Change according to the new encoding of DBGA, DBGAH, and DBGAL. (_print_insn_bfin): Likewise.
2009-09-02update copyright datesAlan Modra
2009-08-30 Updated sources to avoid using the identifier name "new", which is aNick Clifton
keyword in c++. * bfd/aoutx.h (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol. * bfd/coffgen.c (coff_make_empty_symbol) (coff_bfd_make_debug_symbol): Rename variable new to new_symbol. * bfd/cpu-ia64-opc.c (ext_reg, ins_imms_scaled): Rename variable new to new_insn. * bfd/doc/chew.c (newentry, add_intrinsic): Rename variable new to new_d. * bfd/ecoff.c (_bfd_ecoff_make_empty_symbol): Rename variable new to new_symbol. * bfd/elf32-m68k.c (elf_m68k_get_got_entry_type): Rename argument new to new_reloc. * bfd/hash.c (bfd_hash_lookup): Rename variable new to new_string. * bfd/ieee.c (ieee_make_empty_symbol): Rename variable new to new_symbol. * bfd/linker.c (bfd_new_link_order): Rename variable new to new_lo. * bfd/mach-o.c (bfd_mach_o_sizeof_headers): Rename variable new to symbol. * bfd/oasys.c (oasys_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/pdp11.c (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol_type. * bfd/plugin.c (bfd_plugin_make_empty_symbol): Rename variable new to new_symbol. * bfd/rs6000-core.c (CoreHdr, VmInfo): Rename union member new to new_dump. (read_hdr, rs6000coff_core_p) (rs6000coff_core_file_matches_executable_p) (rs6000coff_core_file_failing_command) (rs6000coff_core_file_failing_signal): Updated function to use new union member name. * bfd/som.c (som_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/syms.c (_bfd_generic_make_empty_symbol): Rename variable new to new_symbol. * bfd/tekhex.c (first_phase, tekhex_make_empty_symbol): Rename variable new to new_symbol. * binutils/nlmconv.c (main): Rename variable new to new_name. * gas/config/tc-arm.c (insert_reg_alias): Rename variable new to new_reg. * gas/config/tc-dlx.c (parse_operand): Rename variable new to new_pos. * gas/config/tc-ia64.c (ia64_gen_real_reloc_type): Rename variable new to newr. * gas/config/tc-mcore.c (parse_exp, parse_imm): Rename variable new to new_pointer. * gas/config/tc-microblaze.c (parse_exp, parse_imm, check_got): Change name from new to new_pointer. * gas/config/tc-or32.c (parse_operand): Rename variable new to new_pointer. * gas/config/tc-pdp11.c (md_assemble): Rename variable new to new_pointer. * gas/config/tc-pj.c (alias): Change argument new to new_name. * gas/config/tc-score.c (s3_build_score_ops_hsh): Rename variable new to new_opcode. (s3_build_dependency_insn_hsh) Rename variable new to new_i2n. (s3_convert): Rename variables old and new to r_old and r_new. * gas/config/tc-score7.c (s7_build_score_ops_hsh): Rename variable new to new_opcode. (s7_build_dependency_insn_hsh): Rename variable new to new_i2d. (s7_b32_relax_to_b16, s7_convert_frag): Rename variables old and new to r_old and r_new. * gas/config/tc-sh.c (parse_exp): Rename variable new to new_pointer. * gas/config/tc-sh64.c (shmedia_parse_exp): Rename variable new to new_pointer. * gas/config/tc-tic4x.c (tic4x_operand_parse): Rename variable new to new_pointer. * gas/config/tc-z8k.c (parse_exp): Rename variable new to new_pointer. * gas/listing.c (listing_newline): Rename variable new to new_i. * ld/ldexp.c (exp_intop, exp_bigintop, exp_relop, exp_binop) (exp_trinop, exp_unop, exp_nameop, exp_assop): Rename variable new to new_e. * ld/ldfile.c (ldfile_add_library_path): Rename variable new to new_dirs. (ldfile_add_arch): Rename variable new to new_arch. * ld/ldlang.c (new_statement, lang_final, lang_add_wild) (lang_target, lang_add_fill, lang_add_data, lang_add_assignment) (lang_add_insert): Rename variable new to new_stmt. (new_afile): Added missing cast. (lang_memory_region_lookup): Rename variable new to new_region. (init_os): Rename variable new to new_userdata. (lang_add_section): Rename variable new to new_section. (ldlang_add_undef): Rename variable new to new_undef. (realsymbol): Rename variable new to new_name. * opcodes/z8kgen.c (internal, gas): Rename variable new to new_op. Updated sources to avoid using the identifier name "template", which is a keyword in c++. * bfd/elf32-arm.c (struct stub_def): Rename member template to template_sequence. (arm_build_one_stub, find_stub_size_and_template, arm_size_one_stub, arm_map_one_stub): Rename variable template to template_sequence. * bfd/elfxx-ia64.c (elfNN_ia64_relax_br, elfNN_ia64_relax_brl): Rename variable template to template_val. * gas/config/tc-arm.c (struct asm_cond, struct asm_psr, struct asm_barrier_opt): Change member template to template_name. (md_begin): Update code to reflect new member names. * gas/config/tc-i386.c (struct templates, struct _i386_insn) (match_template, cpu_flags_match, match_reg_size, match_mem_size) (operand_size_match, md_begin, i386_print_statistics, pi) (build_vex_prefix, md_assemble, parse_insn, optimize_imm) (optimize_disp): Updated code to use new names. (parse_insn): Added casts. * gas/config/tc-ia64.c (dot_template, emit_one_bundle): Updated code to use new names. * gas/config/tc-score.c (struct s3_asm_opcode): Renamed member template to template_name. (s3_parse_16_32_inst, s3_parse_48_inst, s3_do_macro_ldst_label, s3_build_score_ops_hsh): Update code to use new names. * gas/config/tc-score7.c (struct s7_asm_opcode): Renamed member template to template_name. (s7_parse_16_32_inst, s7_do_macro_ldst_label, s7_build_score_ops_hsh): Update code to use new names. * gas/config/tc-tic30.c (md_begin, struct tic30_insn) (md_assemble): Update code to use new names. * gas/config/tc-tic54x.c (struct _tic54x_insn, md_begin) (optimize_insn, tic54x_parse_insn, next_line_shows_parallel): Update code to use new names. * include/opcode/tic30.h (template): Rename type template to insn_template. Updated code to use new name. * include/opcode/tic54x.h (template): Rename type template to insn_template. * opcodes/cris-dis.c (bytes_to_skip): Update code to use new name. * opcodes/i386-dis.c (putop): Update code to use new name. * opcodes/i386-gen.c (process_i386_opcodes): Update code to use new name. * opcodes/i386-opc.h (struct template): Rename struct template to insn_template. Update code accordingly. * opcodes/i386-tbl.h (i386_optab): Update type to use new name. * opcodes/ia64-dis.c (print_insn_ia64): Rename variable template to template_val. * opcodes/tic30-dis.c (struct instruction, get_tic30_instruction): Update code to use new name. * opcodes/tic54x-dis.c (has_lkaddr, get_insn_size) (print_parallel_instruction, print_insn_tic54x, tic54x_get_insn): Update code to use new name. * opcodes/tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab): Update type to new name.
2009-08-21hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.Nick Hudson
2009-06-11Add PC-relative branch instructions to moxie port.Anthony Green
2009-06-06Print moxie addresses nicely.Anthony Green
2009-04-16Add new binutils target: moxieNick Clifton
2009-04-07[bfd]DJ Delorie
* elf32-h8300.c (elf32_h8_relax_section): Relax MOVA opcodes. [gas] * tc-h8300.c (do_a_fix_imm): Pass the insn, force relocs for MOVA immediates. (build_bytes): Pass insn to do_a_fix_imm. [include/opcode] * h8300.h: Add relaxation attributes to MOVA opcodes.
2009-03-10include/opcode/Alan Modra
* ppc.h (ppc_parse_cpu): Declare. opcodes/ * ppc-dis.c: Include "opintl.h". (struct ppc_mopt, ppc_opts): New. (ppc_parse_cpu): New function. (powerpc_init_dialect): Use it. (print_ppc_disassembler_options): Dump options from ppc_opts. Internationalize message. gas/ * config/tc-ppc.c (parse_cpu): Delete. (md_parse_option, ppc_machine): Use ppc_parse_cpu. gas/testsuite/ * gas/ppc/altivec_and_spe.d (objdump): Add -Maltivec. * gas/ppc/common.d: Adjust for -Mcom not including -Mppc.
2009-03-02Add support for Score7 architecture.Nick Clifton
2009-02-27gas/Peter Bergner
* config/tc-ppc.c (pre_defined_registers): Add "f32" to "f63", "f.32" to "f.63", "vs0" to "vs63" and "vs.0" to "vs.63". (parse_cpu): Extend -mpower7 to accept power7 and isel instructions. gas/testsuite/ * gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests. * gas/ppc/e500mc.s: Likewise. * gas/ppc/power6.d ("cdtbcd", "cbcdtd", "addg6s"): Add tests. * gas/ppc/power6.s: Likewise. * gas/ppc/power7.d ("lfdpx", "mffgpr", "mftgpr"): Remove invalid tests. ("wait", "waitsrv", "waitimpl", "divwe", "divwe.", "divweo", "divweo.", "divweu", "divweu.", "divweuo", "divweuo.", "bpermd", "popcntw", "popcntd", "ldbrx", "stdbrx", "lfiwzx", "lfiwzx", "fcfids", "fcfids.", "fcfidus", "fcfidus.", "fctiwu", "fctiwu.", "fctiwuz", "fctiwuz.", "fctidu", "fctidu.", "fctiduz", "fctiduz.", "fcfidu", "fcfidu.", "ftdiv", "ftdiv", "ftsqrt", "ftsqrt", "dcbtt", "dcbtstt", "dcffix", "dcffix.", "lbarx", "lbarx", "lbarx", "lharx", "lharx", "lharx", "stbcx.", "sthcx.", "fre", "fre.", "fres", "fres.", "frsqrte", "frsqrte.", "frsqrtes", "frsqrtes.", "isel"): Add tests. * gas/ppc/power7.s: Likewise. * gas/ppc/vsx.d: New test. * gas/ppc/vsx.s: Likewise. * gas/ppc/ppc.exp: Run it. include/opcode/ * ppc.h (PPC_OPCODE_POWER7): New. opcodes/ * ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble the power7 and the isel instructions. * ppc-opc.c (insert_xc6, extract_xc6): New static functions. (insert_dm, extract_dm): Likewise. (XB6): Update comment to include XX2 form. (WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK, XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New. (RemoveXX3DM): Delete. (powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr", "mftgpr">: Deprecate for POWER7. <"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte", "frsqrte.">: Deprecate the three operand form and enable the two operand form for POWER7 and later. <"wait">: Extend to accept optional parameter. Enable for POWER7. <"waitsrv", "waitimpl">: Add extended opcodes. <"ldbrx", "stdbrx">: Enable for POWER7. <"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes. <"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde", "divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo", "divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.", "divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.", "fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.", "fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx", "lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes. <"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx", "stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp", "xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds", "xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp", "xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp", "xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp", "xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic", "xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp", "xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp", "xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp", "xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.", "xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp", "xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp", "xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp", "xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp", "xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp", "xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp", "xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp", "xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp", "xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp", "xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi", "xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp", "xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp", "xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp", "xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor", "xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd", "xxspltw", "xxswapd">: Add VSX opcodes.
2009-02-07 * i386.h: Add comment regarding sse* insns and prefixes.Doug Evans
2009-02-03bfd:Joseph Myers
2009-02-03 Sandip Matte <sandip@rmicorp.com> * aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr. * archures.c (bfd_mach_mips_xlr): Define. * bfd-in2.h: Regenerate. * cpu-mips.c (I_xlr): Define. (arch_info_struct): Add XLR entry. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR. (mips_set_isa_flags): Handle bfd_mach_mips_xlr (mips_mach_extensions): Add XLR entry. binutils: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR. gas: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT and M_MSGWAIT_T. (mips_cpu_info_table): Add XLR entry. * doc/c-mips.texi (-march): Document xlr. gas/testsuite: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * gas/mips/mips.exp (xlr): New architecture. (xlr-ext): Run test. * gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New. include/elf: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips.h (E_MIPS_MACH_XLR): Define. include/opcode: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips.h (INSN_XLR): Define. (INSN_CHIP_MASK): Update. (CPU_XLR): Define. (OPCODE_IS_MEMBER): Update. (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. opcodes: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define. (mips_arch_choices): Add XLR entry. * mips-opc.c (XLR): Define. (mips_builtin_opcodes): Add XLR instructions.
2009-01-29fix typo in previous entryDoug Evans
2009-01-29 * opcode/i386.h: Add multiple inclusion protection.Doug Evans
(EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM) (EDI_REG_NUM): New macros. (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros. (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros. (REG_PREFIX_P): New macro. * amd64-tdep.h (amd64_displaced_step_copy_insn): Declare. (amd64_displaced_step_fixup): Declare. * amd64-tdep.c: #include opcode/i386.h, dis-asm.h. (amd64_arch_regmap): Move out of amd64_analyze_stack_align and make static global. (amd64_arch_regmap_len): New static global. (amd64_arch_reg_to_regnum): New function. (struct amd64_insn): New struct. (struct displaced_step_closure): New struct. (onebyte_has_modrm,twobyte_has_modrm): New static globals. (rex_prefix_p,skip_prefixes) (amd64_insn_length_fprintf,amd64_insn_length_init_dis) (amd64_insn_length,amd64_get_unused_input_int_reg) (amd64_get_insn_details,fixup_riprel,fixup_displaced_copy) (amd64_displaced_step_copy_insn) (amd64_absolute_jmp_p,amd64_absolute_call_p,amd64_ret_p) (amd64_call_p,amd64_breakpoint_p,amd64_syscall_p) (amd64_displaced_step_fixup): New functions. * amd64-linux-tdep.c: #include arch-utils.h. (amd64_linux_init_abi): Install displaced stepping support. * gdb.arch/amd64-disp-step.S: New file. * gdb.arch/amd64-disp-step.exp: New file. * gdb.arch/i386-disp-step.S: New file. * gdb.arch/i386-disp-step.exp: New file.
2009-01-09gas/Peter Bergner
* config/tc-ppc.c (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test. Test the new "deprecated" opcode field. include/opcode/ * ppc.h (struct powerpc_opcode): New field "deprecated". (PPC_OPCODE_NOPOWER4): Delete. opcodes/ * ppc-opc.c (PPCNONE): Define. (NOPOWER4): Delete. (powerpc_opcodes): Initialize the new "deprecated" field.
2008-11-28 * aoutx.h (NAME): Add case statements for bfd_mach_mips14000,Thiemo Seufer
bfd_mach_mips16000. * archures.c (bfd_architecture): Add .#defines for bfd_mach_mips14000, bfd_mach_mips16000. * bfd-in2.h: Regenerate. * cpu-mips.c: Add enums I_mips14000, I_mips16000. (arch_info_struct): Add refs to R14000, R16000. * elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000, bfd_mach_mips16000. (mips_mach_extensions): Map R14000, R16000 to R10000. * config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000. (mips_cpu_info_table): Add r14000, r16000. * doc/c-mips.texi: Add entries for 14000, 16000. * mips-dis.c (mips_arch_choices): Add r14000, r16000. * mips.h: Define CPU_R14000, CPU_R16000. (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
2008-11-18Add support for ARM half-precision conversion instructions.Catherine Moore
2008-11-062008-11-06 Chao-ying Fu <fu@mips.com>Chao-ying Fu
* mips.h: Doucument '1' for 5-bit sync type.
2008-08-28gas/H.J. Lu
2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (CR_IIB0): New. (CR_IIB1): Likewise. (cr): Add cr.iib0 and cr.iib1. (specify_resource): Handle IA64_RS_CR_IIB and CR_IIB0/CR_IIB1. gas/testsuite/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/dv-raw-err.s: Add tests for cr.iib0 and cr.iib1. * gas/ia64/dv-waw-err.s: Likewise. * gas/ia64/regs.s: Likewise. * gas/ia64/dv-raw-err.l: Updated. * gas/ia64/dv-waw-err.l: Likewise. * gas/ia64/regs.d: Likewise. include/opcode/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update IA64_RS_CR. opcodes/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1. * ia64-gen.c (lookup_specifier): Likewise. * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1. * ia64-raw.tbl: Likewise. * ia64-waw.tbl: Likewise. * ia64-asmtab.c: Regenerated.
2008-08-09Add AVR architectures avr25, avr31, avr35, and avr51 to match GCC.Eric Weddington
bfd/ * archures.c (bfd_mach_avr25, bfd_mach_avr31, bfd_mach_avr35, bfd_mach_avr51): New. * bfd-in2.h: Regenerate. * cpu-avr.c (arch_info_struct): Add avr25, avr31, avr35, and avr51 architectures. Change comments to match architecture comments in GCC. (compatible): Add test for new AVR architectures. * elf32-avr.c (bfd_elf_avr_final_write_processing): Recognize bfd_mach_avr25, bfd_mach_avr31, bfd_mach_avr35 and bfd_mach_avr51. (elf32_avr_object_p): Recognize E_AVR_MACH_AVR25, E_AVR_MACH_AVR31, E_AVR_MACH_AVR35 and E_AVR_MACH_AVR51. gas/ * config/tc-avr.c (mcu_types): Add avr25, avr31, avr35, and avr51 architectures. Reorganize list to put mcu types in correct architectures and to order list same as in GCC. Use new ISA definitions in include/opcode/avr.h. * doc/c-avr.texi: Add avr25, avr31, avr35, and avr51 architecture descriptions. Reorganize descriptions to put mcu types in correct architectures and to order lists same as in GCC. include/ * elf/avr.h (E_AVR_MACH_AVR25, E_AVR_MACH_AVR31, E_AVR_MACH_AVR35, E_AVR_MACH_AVR51): Define. (EF_AVR_MACH): Redefine to 0x7F. * opcode/avr.h (AVR_ISA_TINY3, AVR_ISA_ALL, AVR_ISA_USB162): Remove. (AVR_ISA_AVR3): Redefine. (AVR_ISA_AVR1, AVR_ISA_AVR2, AVR_ISA_AVR31, AVR_ISA_AVR35, AVR_ISA_AVR3_ALL, AVR_ISA_AVR4, AVR_ISA_AVR5, AVR_ISA_AVR51, AVR_ISA_AVR6): Define. ld/ * Makefile.am (ALL_EMULATIONS): Add eavr25.o, eavr31.o, eavr35.o, and eavr51.o. Add rules for eavr25.c, eavr31.c, eavr35.c, eavr51.c. * Makefile.in: Regenerate. * configure.tgt (avr-*-*, targ_extra_emuls): Add avr25, avr31, avr35 and avr51. * emulparams/avr25.sh: New file. * emulparams/avr31.sh: New file. * emulparams/avr35.sh: New file. * emulparams/avr51.sh: New file.
2008-08-02gas/Peter Bergner
* config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags. Handle -mvsx and -mpower7. (md_show_usage): Document -mpower7 and -mvsx. * doc/as.texinfo (Target PowerPC): Document -mvsx. * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7. gas/testsuite/ * gas/ppc/power7.d: New. * gas/ppc/power7.s: Likewise. * gas/ppc/ppc.exp: Run power7 test. include/opcode/ * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. opcodes/ * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. (print_insn_powerpc): Prepend 'vs' when printing VSX registers. (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. * ppc-opc.c (insert_xt6): New static function. (extract_xt6): Likewise. (insert_xa6): Likewise. (extract_xa6: Likewise. (insert_xb6): Likewise. (extract_xb6): Likewise. (insert_xb6s): Likewise. (extract_xb6s): Likewise. (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, XX3DM_MASK, PPCVSX): New. (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
2008-07-30include/opcode/Alan Modra
* ppc.h (PPC_OPCODE_405): Define. (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. gas/ * config/tc-ppc.c (parse_cpu): Separate handling of -m403/405. (md_show_usage): Likewise. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields. * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands. (insert_sprg, PPC405): Use PPC_OPCODE_405. (powerpc_opcodes): Add Xilinx APU related opcodes.
2008-06-14include/opcode/Peter Bergner
* ppc.h (ppc_cpu_t): New typedef. (struct powerpc_opcode <flags>): Use it. (struct powerpc_operand <insert, extract>): Likewise. (struct powerpc_macro <flags>): Likewise. gas/ * config/tc-ppc.c (ppc_cpu): Use ppc_cpu_t typedef. (ppc_insert_operand): Likewise. (ppc_machine): Likewise. * config/tc-ppc.h: #include "opcode/ppc.h" (struct _ppc_fix_extra <ppc_cpu>): Use ppc_cpu_t typedef. (ppc_cpu): Update extern decl. opcodes/ * ppc-dis.c (print_insn_powerpc): Update prototye to use new ppc_cpu_t typedef. (struct dis_private): New. (POWERPC_DIALECT): New define. (powerpc_dialect): Renamed to... (powerpc_init_dialect): This. Update to use ppc_cpu_t and struct dis_private. (print_insn_big_powerpc): Update for using structure in info->private_data. (print_insn_little_powerpc): Likewise. (operand_value_powerpc): Change type of dialect param to ppc_cpu_t. (skip_optional_operands): Likewise. (print_insn_powerpc): Likewise. Remove initialization of dialect. * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp, extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe, extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr, extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm, insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe, insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs, insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect param to be of type ppc_cpu_t. Update prototype.
2008-06-13 * mips.h: Document new field descriptors +Q.Nick Clifton
(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptor +Q. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, seqi, sne and snei. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q. (mips_ip): Likewise. (macro_build): Likewise. (CPU_HAS_SEQ): New macro. (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne*. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi and snei.
2008-06-12include/opcode/Nick Clifton
* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. Update comment before MIPS16 field descriptors to mention MIPS16. (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for BBIT. (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): New bit masks and shift counts for cins and exts. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptors +x, +X, +p, +P, +s, +S. (mips_ip): Likewise. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, +s, +S. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test. * gas/mips/mips.exp: Run it. Run octeon test with run_dump_test_arches.
2008-04-28 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.Adam Nemet
(INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
2008-04-16Move entries for changes in sub-directories into the changelogs in those sub-Nick Clifton
directories.
2008-04-14ppc e500mc supportAlan Modra
2008-04-03binutils/H.J. Lu
2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Add AVX registers. (dwarf_regnames_x86_64): Likewise. gas/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. Document -msse2avx, .avx, .aes, .clmul and .fma. * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. (vex_prefix): Likewise. (sse2avx): Likewise. (CPU_FLAGS_ARCH_MATCH): Likewise. (CPU_FLAGS_64BIT_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Likewise. (CPU_FLAGS_PERFECT_MATCH): Likewise. (regymm): Likewise. (vex_imm4): Likewise. (fits_in_imm4): Likewise. (build_vex_prefix): Likewise. (VEX_check_operands): Likewise. (bad_implicit_operand): Likewise. (OPTION_MSSE2AVX): Likewise. (T_YMMWORD): Likewise. (_i386_insn): Add vex. (cpu_arch): Add .avx, .aes, .clmul and .fma. (cpu_flags_match): Changed to take a pointer to const template. Enable encoding SSE instructions with VEX prefix for -msse2avx. (match_mem_size): Also check ymmword. (operand_type_match): Clear ymmword. (md_begin): Allow '_' in mnemonic. (type_names): Add OPERAND_TYPE_VEX_IMM4. (process_immext): Update assert. (md_assemble): Don't call process_immext if sse2avx and immext are true. Call build_vex_prefix if vex is true. (parse_insn): Updated for cpu_flags_match. (swap_operands): Handle 5 operands. (match_template): Handle 5 operands. Updated for cpu_flags_match. Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. (process_suffix): Handle YMMWORD_MNEM_SUFFIX. (check_byte_reg): Check regymm. (process_operands): Duplicate the destination register for -msse2avx if needed. (build_modrm_byte): Updated for instructions with VEX encoding. (output_insn): Output VEX prefix if needed. (md_longopts): Add msse2avx. (md_parse_option): Handle OPTION_MSSE2AVX. (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. (intel_e09): Support YMMWORD. (intel_e11): Likewise. (intel_get_token): Likewise. gas/testsuite/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, x86-64-avx-intel and x86-64-inval-avx. * gas/cfi/cfi-i386.s: Add tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/i386/aes.d: New. * gas/i386/aes.s: Likewise. * gas/i386/aes-intel.d: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/i386.exp: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/inval-avx.s: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-aes.d: Likewise. * gas/i386/x86-64-aes.s: Likewise. * gas/i386/x86-64-aes-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/rexw.s: Add AVX tests. * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/rexw.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. include/opcode/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386.h (MAX_OPERANDS): Set to 5. (MAX_MNEM_SIZE): Changed to 20. opcodes/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. (OP_E_memory): Likewise. (OP_VEX): Likewise. (OP_EX_Vex): Likewise. (OP_EX_VexW): Likewise. (OP_XMM_Vex): Likewise. (OP_XMM_VexW): Likewise. (OP_REG_VexI4): Likewise. (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (rex_original): Likewise. (rex_ignored): Likewise. (Mxmm): Likewise. (XMM): Likewise. (EXxmm): Likewise. (EXxmmq): Likewise. (EXymmq): Likewise. (Vex): Likewise. (Vex128): Likewise. (Vex256): Likewise. (VexI4): Likewise. (EXdVex): Likewise. (EXqVex): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (XMVex): Likewise. (XMVexW): Likewise. (XMVexI4): Likewise. (PCLMUL): Likewise. (VZERO): Likewise. (VCMP): Likewise. (VPERMIL2): Likewise. (xmm_mode): Likewise. (xmmq_mode): Likewise. (ymmq_mode): Likewise. (vex_mode): Likewise. (vex128_mode): Likewise. (vex256_mode): Likewise. (USE_VEX_C4_TABLE): Likewise. (USE_VEX_C5_TABLE): Likewise. (USE_VEX_LEN_TABLE): Likewise. (VEX_C4_TABLE): Likewise. (VEX_C5_TABLE): Likewise. (VEX_LEN_TABLE): Likewise. (REG_VEX_XX): Likewise. (MOD_VEX_XXX): Likewise. (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. (PREFIX_0F3A44): Likewise. (PREFIX_0F3ADF): Likewise. (PREFIX_VEX_XXX): Likewise. (VEX_OF): Likewise. (VEX_OF38): Likewise. (VEX_OF3A): Likewise. (VEX_LEN_XXX): Likewise. (vex): Likewise. (need_vex): Likewise. (need_vex_reg): Likewise. (vex_i4_done): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (OP_REG_VexI4): Likewise. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise. (m_mode): Updated. (es_reg): Likewise. (PREFIX_0F38F0): Likewise. (PREFIX_0F3A60): Likewise. (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF and PREFIX_VEX_XXX entries. (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and PREFIX_0F3ADF. (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. Add MOD_VEX_XXX entries. (ckprefix): Initialize rex_original and rex_ignored. Store the REX byte in rex_original. (get_valid_dis386): Handle the implicit prefix in VEX prefix bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before calling get_valid_dis386. Use rex_original and rex_ignored when printing out REX. (putop): Handle "XY". (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and ymmq_mode. (OP_E_extended): Updated to use OP_E_register and OP_E_memory. (OP_XMM): Handle VEX. (OP_EX): Likewise. (XMM_Fixup): Likewise. (CMP_Fixup): Use ARRAY_SIZE. * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, CPU_FMA_FLAGS and CPU_AVX_FLAGS. (operand_type_init): Add OPERAND_TYPE_REGYMM and OPERAND_TYPE_VEX_IMM4. (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, VexImmExt and SSE2AVX. (operand_types): Add RegYMM, Ymmword and Vex_Imm4. * i386-opc.h (CpuAVX): New. (CpuAES): Likewise. (CpuCLMUL): Likewise. (CpuFMA): Likewise. (Vex): Likewise. (Vex256): Likewise. (VexNDS): Likewise. (VexNDD): Likewise. (VexW0): Likewise. (VexW1): Likewise. (Vex0F): Likewise. (Vex0F38): Likewise. (Vex0F3A): Likewise. (Vex3Sources): Likewise. (VexImmExt): Likewise. (SSE2AVX): Likewise. (RegYMM): Likewise. (Ymmword): Likewise. (Vex_Imm4): Likewise. (Implicit1stXmm0): Likewise. (CpuXsave): Updated. (CpuLM): Likewise. (ByteOkIntel): Likewise. (OldGcc): Likewise. (Control): Likewise. (Unspecified): Likewise. (OTMax): Likewise. (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, vex3sources, veximmext and sse2avx. (i386_operand_type): Add regymm, ymmword and vex_imm4. * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. * i386-reg.tbl: Add AVX registers, ymm0..ymm15. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-03-29/gas:Eric Weddington
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Add attiny167. * doc/c-avr.texi: Likewise. /include: 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * opcode/avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
2008-03-192008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>Andreas Krebbel
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added. (s390_cond_extensions): Reduced extensions to the compare related. (main): z10 cpu type option added. (expandConditionalJump): Renamed to ... (insertExpandedMnemonic): ... this. * opcodes/s390-opc.c: Re-group the operand format makros. (INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI, INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU, INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0, INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU, INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU, INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI, INSTR_SIL_RDU): New instruction formats added. (MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI, MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0, MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI, MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR, MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD, MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format masks added. (s390_opformats): New formats added "ris", "rrs", "sil". * opcodes/s390-opc.txt: Add the conditional jumps with the extensions removed from automatic expansion in s390-mkopc.c manually. (asi - trtre): Add new System z10 EC instructions. * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * config/tc-s390.c (md_parse_option): z10 option added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: New file. * gas/s390/zarch-z10.s: New file. * gas/s390/s390.exp: Run the z10 testcases.
2008-03-092008-03-09 Paul Brook <paul@codesourcery.com>Paul Brook
bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new Tag_VFP_arch values. binutils/ * readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16". gas/ * config/tc-arm.c (fpu_vfp_ext_d32): New vairable. (parse_vfp_reg_list, encode_arm_vfp_reg): Use it. (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3. (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16. * doc/c-arm.texi: Document new ARM FPU variants. gas/testsuite/ * gas/arm/vfpv3-d16-bad.d: New test. * gas/arm/vfpv3-d16-bad.l: New test. include/opcode/ * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
2008-03-052008-03-04 Paul Brook <paul@codesourcery.com>Paul Brook
gas/ * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New. (arm_ext_v7m): Rename... (arm_ext_m): ... to this. Include v6-M. (do_t_add_sub): Allow narrow low-reg non flag setting adds. (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m. (md_assemble): Allow wide msr instructions. (insns): Add classifications for v6-m instructions. (arm_cpu_option_table): Add cortex-m1. (arm_arch_option_table): Add armv6-m. (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants. gas/testsuite/ * gas/arm/archv6m.d: New test. * gas/arm/archv6m.s: New test. * gas/arm/t16-bad.s: Test low register non flag setting add. * gas/arm/t16-bad.l: Update expected output. include/opcode/ * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
2008-02-29Change accreditation for patch for PR3134Nick Clifton
2008-02-27 PR 3134Nick Clifton
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction with a 32-bit displacement but without the top bit of the 4th byte set. * gas/h8300/pr3134.s: New test. * gas/h8300/pr3134.d: Expected disassembly * gas/h8300/h8300.exp: Run the new test. * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to accept h8300-rtemscoff not just h8300-rtems.
2008-02-18 * cr16.h (cr16_num_optab): Declared.Nick Clifton
* cr16-opc.c (cr16_num_optab): Defined
2008-02-14 PR gas/2626Nick Clifton
* avr.h (AVR_ISA_2xxe): Define. * config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26 to AVR_ISA_2xxe. (avr_operand): Disallow post-increment addressing in the lpm instruction for the attiny26.
2008-02-04 * mips.h: Update copyright.Adam Nemet
(INSN_CHIP_MASK): New macro. (INSN_OCTEON): New macro. (CPU_OCTEON): New macro. (OPCODE_IS_MEMBER): Handle Octeon instructions.
2008-01-23/gas:Eric Weddington
2008-01-23 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Change opcode set for at86rf401. /include: 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com> * opcode/avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
2008-01-16/gas:Eric Weddington
2008-01-03 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Change opcode set for avr3, at90usb82, at90usb162. * doc/c-avr.texi: Change architecture grouping for at90usb82, at90usb162. These changes support the new avr35 architecture group in gcc. /include: 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com> * opcode/avr.h (AVR_ISA_USB162): Add new opcode set. (AVR_ISA_AVR3): Likewise.
2007-11-29 bfd/Mark Shinwell
* archures.c (bfd_mach_mips_loongson_2e): New. (bfd_mach_mips_loongson_2f): New. * bfd-in2.h (bfd_mach_mips_loongson_2e): New. (bfd_mach_mips_loongson_2f): New. * cpu-mips.c: Add I_loongson_2e and I_loongson_2f to anonymous enum. (arch_info_struct): Add Loongson-2E and Loongson-2F entries. * elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E and Loongson-2F flags. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Add Loongson-2E and Loongson-2F entries. binutils/ * readelf.c (get_machine_flags): Handle Loongson-2E and -2F flags. gas/ * config/tc-mips.c (mips_cpu_info_table): Add loongson2e and loongson2f entries. * doc/c-mips.texi: Document -march=loongson{2e,2f} options. gas/testsuite/ * gas/mips/mips.exp: Add loongson-2e and -2f tests. * gas/mips/loongson-2e.d: New. * gas/mips/loongson-2e.s: New. * gas/mips/loongson-2f.d: New. * gas/mips/loongson-2f.s: New. include/elf/ * mips.h (E_MIPS_MACH_LS2E): New. (E_MIPS_MACH_LS2F): New. include/opcode/ * mips.h (INSN_LOONGSON_2E): New. (INSN_LOONGSON_2F): New. (CPU_LOONGSON_2E): New. (CPU_LOONGSON_2F): New. (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. opcodes/ * mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F entries. * mips-opc.c (IL2E): New. (IL2F): New. (mips_builtin_opcodes): Add Loongson-2E and -2F instructions. Allow movz and movn for Loongson-2E and -2F. Add movnz entry. Move coprocessor encodings to the end of the table. Allow certain MIPS V .ps instructions on the Loongson-2E and -2F.
2007-11-29 include/opcode/Mark Shinwell
* mips.h (INSN_ISA*): Redefine certain values as an enumeration. Update comments. (mips_isa_table): New. (ISA_MIPS*): Redefine to match enumeration. (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* values. opcodes/ * mips-opc.c (I3_32, I3_33, I4_32, I4_33, I5_33): New. (mips_builtin_opcodes): Use these new I* values.
2007-08-24binutils/Ben Elliston
* doc/binutils.texi (objdump): Document -Mppcps. gas/ * config/tc-ppc.c (parse_cpu): Handle "750cl". (pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7". (md_show_usage): Document -m750cl. (md_assemble): Handle two delimiters in succession (eg. `),'). * doc/c-ppc.texi (PowerPC-Opts): Document -m750cl. * testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests. * testsuite/gas/ppc/ppc750ps.s: New file. * testsuite/gas/ppc/ppc750ps.d: Likewise. include/opcode/ * ppc.h (PPC_OPCODE_PPCPS): New. opcodes/ * ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New. (XOPS, XOPS_MASK, XW, XW_MASK): Likewise. (PPCPS): Likewise. (powerpc_opcodes): Add all pair singles instructions. * ppc-dis.c (powerpc_dialect): Handle "ppcps". (print_ppc_disassembler_options): Document -Mppcps.
2007-08-01Correct ChangeLog entries.H.J. Lu
2007-07-03 gas/testsuite/Nathan Sidwell
* gas/m68k/mcf-coproc.d: New. * gas/m68k/mcf-coproc.s: New. * gas/m68k/all.exp: Add it. gas/ * config/tc-m68k.c (m68k_ip): Add j & K operand types. (install_operand): Add E encoding. (md_begin): Check and skip initial '.' arg character. (get_num): Add 0..511 case. include/ * opcode/m68k.h: Document j K & E. opcodes/ * m68k-dis.c (fetch_arg): Add E. Replace length switch with direct masking. (print_ins_arg): Add j & K operand types. (match_insn_m68k): Check and skip initial '.' arg character. (m68k_scan_mask): Likewise. * m68k-opc.c (m68k_opcodes): Add coprocessor instructions.
2007-06-29New port: National Semiconductor's CR16Nick Clifton
2007-05-02gas/Alan Modra
PR 4448 * config/tc-ppc.c (ppc_insert_operand): Don't increase min for PPC_OPERAND_PLUS1. include/opcode/ * ppc.h (PPC_OPERAND_PLUS1): Update comment.
2007-04-23 gas/testsuite/Nathan Sidwell
* gas/m68k/br-isaa.s: New. * gas/m68k/br-isaa.d: New. * gas/m68k/br-isab.s: New. * gas/m68k/br-isab.d: New. * gas/m68k/br-isac.s: New. * gas/m68k/br-isac.d: New. * gas/m68k/all.exp: Adjust. gas/ * config/tc-m68k.c (mcf54455_ctrl): New. (HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New. (m68k_archs): Add isac. (m68k_cpus): Add 54455 family. (m68k_ip): Split Bg into Bb, Bs, Bg. (m68k_elf_final_processing): Add ISA_C. * doc/c-m68k.texi (M680x0 Options): Add isac. include/opcode/ * m68k.h (mcfisa_c): New. (mcfusp, mcf_mask): Adjust. bfd/ * archures.c (bfd_mach_mcf_isa_c, bfd_mach_mcf_isa_c_mac, bfd_mach_mcf_isa_c_emac): New. * elf32-m68k.c (ISAC_PLT_ENTRY_SIZE, elf_isac_plt0_entry, elf_isac_plt_entry, elf_isac_plt_info): New. (elf32_m68k_object_p): Add ISA_C. (elf32_m68k_print_private_bfd_data): Print ISA_C. (elf32_m68k_get_plt_info): Detect ISA_C. * cpu-m68k.c (arch_info): Add ISAC. (m68k_arch_features): Likewise, (bfd_m68k_compatible): ISAs B & C are not compatible. opcodes/ * m68k-opc.c: Mark mcfisa_c instructions.
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