From f545964009beb43bb99b9bb937bb52a18e7f1bb6 Mon Sep 17 00:00:00 2001 From: Jeff Johnston Date: Fri, 18 Oct 2002 21:09:02 +0000 Subject: 2002-10-04 Michael Snyder * m32r/m32r-lib.c (exceptionHandler): Fix computation of exception vector address, as suggested by Mitsubishi. (getExceptionVector): Ditto. --- libgloss/ChangeLog | 6 ++++++ libgloss/m32r/m32r-lib.c | 23 ++++++++++++++--------- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/libgloss/ChangeLog b/libgloss/ChangeLog index 9aeb47863..43f542c92 100644 --- a/libgloss/ChangeLog +++ b/libgloss/ChangeLog @@ -7,6 +7,12 @@ * mips/ddb.ld: KEEP .init and .fini. * mips/ddb-kseg0.ld: Likewise. +2002-10-04 Michael Snyder + + * m32r/m32r-lib.c (exceptionHandler): Fix computation of + exception vector address, as suggested by Mitsubishi. + (getExceptionVector): Ditto. + 2002-08-01 Chris Demetriou * mips/cfe.ld (STARTUP): New definition. diff --git a/libgloss/m32r/m32r-lib.c b/libgloss/m32r/m32r-lib.c index cad55f54e..1d2d29131 100644 --- a/libgloss/m32r/m32r-lib.c +++ b/libgloss/m32r/m32r-lib.c @@ -109,15 +109,22 @@ void phex(long x) mesg(buf); } -/* Setup trap TT to go to ROUTINE. */ +/* + * These routines set and get exception handlers. They look a little + * funny because the M32R uses branch instructions in its exception + * vectors, not just the addresses. The instruction format used is + * BRA pcdisp24. + */ -void +#define TRAP_VECTOR_BASE_ADDR 0x00000040 + +/* Setup trap TT to go to ROUTINE. */ +void exceptionHandler (int tt, unsigned long routine) { #ifndef REVC - unsigned long *tb = (unsigned long *) 0x40; /* Trap vector base address */ - - tb[tt] = ((routine >> 2) | 0xff000000) - tt - (0x40 >> 2); + unsigned long *tb = (unsigned long *) TRAP_VECTOR_BASE_ADDR; + tb[tt] = (0xff000000 | ((routine - (unsigned long) (&tb[tt])) >> 2)); #else unsigned long *tb = 0; /* Trap vector base address */ @@ -126,14 +133,12 @@ exceptionHandler (int tt, unsigned long routine) } /* Return the address of trap TT handler */ - unsigned long getExceptionHandler (int tt) { #ifndef REVC - unsigned long *tb = (unsigned long *) 0x40; /* Trap vector base address */ - - return ((tb[tt] + tt + (0x40 >> 2)) | 0xff000000) << 2; + unsigned long *tb = (unsigned long *) TRAP_VECTOR_BASE_ADDR; + return ((tb[tt] & ~0xff000000) << 2) + (unsigned long) (&tb[tt]); #else unsigned long *tb = 0; /* Trap vector base address */ -- cgit v1.2.3