From f9b846656db1cb7c0eea270641135969b536a1f4 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 9 Aug 2011 14:25:29 +0000 Subject: include/opcode/ * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. (INSN2_READ_GPR_MMN): Likewise. (INSN2_READ_FPR_D): Change the bit used. (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. (INSN2_COND_BRANCH): Likewise. (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. (INSN2_MOD_GPR_MN): Likewise. gas/ * config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG, INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode register use checks. (gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN, INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use checks. (gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register use flag with INSN_WRITE_GPR_S. Add INSN2_WRITE_GPR_MB, INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP opcode register use checks. (can_swap_branch_p): Enable microMIPS branch swapping. (append_insn): Likewise. gas/testsuite/ * gas/mips/micromips.d: Update according to changes to enable microMIPS branch swapping. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips@jal-svr4pic.d: Likewise. * gas/mips/micromips@loc-swap.d: Likewise. * gas/mips/micromips@loc-swap-dis.d: Likewise. opcodes/ * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros. (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise. (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros. (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise. (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise. (WR_s): Update macro. (micromips_opcodes): Update register use flags of: "addiu", "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu", "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j", "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li", "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not", "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw", "swm" and "xor" instructions. --- include/opcode/ChangeLog | 20 ++++++++++++++ include/opcode/mips.h | 68 +++++++++++++++++++++++++----------------------- 2 files changed, 55 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 84b862f10..4d88f2489 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,23 @@ +2011-08-09 Maciej W. Rozycki + + * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. + (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. + (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. + (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. + (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. + (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. + (INSN2_READ_GPR_MMN): Likewise. + (INSN2_READ_FPR_D): Change the bit used. + (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. + (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. + (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. + (INSN2_COND_BRANCH): Likewise. + (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. + (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. + (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. + (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. + (INSN2_MOD_GPR_MN): Likewise. + 2011-08-05 David S. Miller * sparc.h: Document new format codes '4', '5', and '('. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index eba71913c..1db4aed8e 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -585,6 +585,8 @@ struct mips_opcode #define FP_D 0x20000000 /* Instruction is part of the tx39's integer multiply family. */ #define INSN_MULT 0x40000000 +/* Modifies the general purpose register in MICROMIPSOP_*_RS. */ +#define INSN_WRITE_GPR_S 0x80000000 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff @@ -622,46 +624,46 @@ struct mips_opcode #define INSN2_BRANCH_DELAY_16BIT 0x00000400 /* Instruction has a branch delay slot that requires a 32-bit instruction. */ #define INSN2_BRANCH_DELAY_32BIT 0x00000800 -/* Modifies the general purpose register in MICROMIPSOP_*_RS. */ -#define INSN2_WRITE_GPR_S 0x00001000 /* Reads the floating point register in MICROMIPSOP_*_FD. */ -#define INSN2_READ_FPR_D 0x00002000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MB. */ -#define INSN2_MOD_GPR_MB 0x00004000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MC. */ -#define INSN2_MOD_GPR_MC 0x00008000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MD. */ -#define INSN2_MOD_GPR_MD 0x00010000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_ME. */ -#define INSN2_MOD_GPR_ME 0x00020000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MF. */ -#define INSN2_MOD_GPR_MF 0x00040000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MG. */ -#define INSN2_MOD_GPR_MG 0x00080000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MJ. */ -#define INSN2_MOD_GPR_MJ 0x00100000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MP. */ -#define INSN2_MOD_GPR_MP 0x00200000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MQ. */ -#define INSN2_MOD_GPR_MQ 0x00400000 +#define INSN2_READ_FPR_D 0x00001000 +/* Modifies the general purpose register in MICROMIPSOP_*_MB. */ +#define INSN2_WRITE_GPR_MB 0x00002000 +/* Reads the general purpose register in MICROMIPSOP_*_MC. */ +#define INSN2_READ_GPR_MC 0x00004000 +/* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */ +#define INSN2_MOD_GPR_MD 0x00008000 +/* Reads the general purpose register in MICROMIPSOP_*_ME. */ +#define INSN2_READ_GPR_ME 0x00010000 +/* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */ +#define INSN2_MOD_GPR_MF 0x00020000 +/* Reads the general purpose register in MICROMIPSOP_*_MG. */ +#define INSN2_READ_GPR_MG 0x00040000 +/* Reads the general purpose register in MICROMIPSOP_*_MJ. */ +#define INSN2_READ_GPR_MJ 0x00080000 +/* Modifies the general purpose register in MICROMIPSOP_*_MJ. */ +#define INSN2_WRITE_GPR_MJ 0x00100000 +/* Reads the general purpose register in MICROMIPSOP_*_MP. */ +#define INSN2_READ_GPR_MP 0x00200000 +/* Modifies the general purpose register in MICROMIPSOP_*_MP. */ +#define INSN2_WRITE_GPR_MP 0x00400000 +/* Reads the general purpose register in MICROMIPSOP_*_MQ. */ +#define INSN2_READ_GPR_MQ 0x00800000 /* Reads/Writes the stack pointer ($29). */ -#define INSN2_MOD_SP 0x00800000 +#define INSN2_MOD_SP 0x01000000 /* Reads the RA ($31) register. */ -#define INSN2_READ_GPR_31 0x01000000 +#define INSN2_READ_GPR_31 0x02000000 /* Reads the global pointer ($28). */ -#define INSN2_READ_GP 0x02000000 +#define INSN2_READ_GP 0x04000000 /* Reads the program counter ($pc). */ -#define INSN2_READ_PC 0x04000000 +#define INSN2_READ_PC 0x08000000 /* Is an unconditional branch insn. */ -#define INSN2_UNCOND_BRANCH 0x08000000 +#define INSN2_UNCOND_BRANCH 0x10000000 /* Is a conditional branch insn. */ -#define INSN2_COND_BRANCH 0x10000000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MH/I. */ -#define INSN2_MOD_GPR_MHI 0x20000000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MM. */ -#define INSN2_MOD_GPR_MM 0x40000000 -/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MN. */ -#define INSN2_MOD_GPR_MN 0x80000000 +#define INSN2_COND_BRANCH 0x20000000 +/* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */ +#define INSN2_WRITE_GPR_MHI 0x40000000 +/* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */ +#define INSN2_READ_GPR_MMN 0x80000000 /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that -- cgit v1.2.3