New generation!

14 files changed, 9375 insertions, 10123 deletions

diff --git a/CoolGirl.qpf b/CoolGirl.qpf
index 0eca6b4..6519ccc 100644
--- a/CoolGirl.qpf
+++ b/CoolGirl.qpf
@@ -1,29 +1,30 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 1991-2013 Altera Corporation
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions 
 # and other software and tools, and its AMPP partner logic 
 # functions, and any output files from any of the foregoing 
 # (including device programming or simulation files), and any 
 # associated documentation or information are expressly subject 
 # to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
 #
 # -------------------------------------------------------------------------- #
 #
-# Quartus II 64-Bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 02:44:40  January 07, 2016
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 19:53:22  May 05, 2016
 #
 # -------------------------------------------------------------------------- #
 
-QUARTUS_VERSION = "13.0"
-DATE = "02:44:40  January 07, 2016"
+QUARTUS_VERSION = "15.1"
+DATE = "19:53:22  May 05, 2016"
 
 # Revisions
 
diff --git a/CoolGirl.qsf b/CoolGirl.qsf
index c96425d..e634dec 100644
--- a/CoolGirl.qsf
+++ b/CoolGirl.qsf
@@ -1,24 +1,25 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 1991-2013 Altera Corporation
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions 
 # and other software and tools, and its AMPP partner logic 
 # functions, and any output files from any of the foregoing 
 # (including device programming or simulation files), and any 
 # associated documentation or information are expressly subject 
 # to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
 #
 # -------------------------------------------------------------------------- #
 #
-# Quartus II 64-Bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 02:44:41  January 07, 2016
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 19:53:22  May 05, 2016
 #
 # -------------------------------------------------------------------------- #
 #
@@ -30,115 +31,122 @@
 #		assignment_defaults.qdf
 #
 # 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
+#    file is updated automatically by the Quartus Prime software
 #    and any changes you make may be lost or overwritten.
 #
 # -------------------------------------------------------------------------- #
 
 
 set_global_assignment -name FAMILY "MAX II"
-set_global_assignment -name DEVICE EPM570T100C5
+set_global_assignment -name DEVICE EPM1270T144C5
 set_global_assignment -name TOP_LEVEL_ENTITY CoolGirl
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:44:41  JANUARY 07, 2016"
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:53:22  MAY 05, 2016"
 set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name VERILOG_FILE CoolGirl.v
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
 set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
-set_location_assignment PIN_68 -to cpu_addr_in[14]
-set_location_assignment PIN_69 -to cpu_addr_in[13]
-set_location_assignment PIN_12 -to cpu_addr_in[12]
-set_location_assignment PIN_6 -to cpu_addr_in[11]
-set_location_assignment PIN_5 -to cpu_addr_in[10]
-set_location_assignment PIN_4 -to cpu_addr_in[9]
-set_location_assignment PIN_3 -to cpu_addr_in[8]
-set_location_assignment PIN_2 -to cpu_addr_in[7]
-set_location_assignment PIN_1 -to cpu_addr_in[6]
-set_location_assignment PIN_100 -to cpu_addr_in[5]
-set_location_assignment PIN_99 -to cpu_addr_in[4]
-set_location_assignment PIN_98 -to cpu_addr_in[3]
-set_location_assignment PIN_97 -to cpu_addr_in[2]
-set_location_assignment PIN_96 -to cpu_addr_in[1]
-set_location_assignment PIN_95 -to cpu_addr_in[0]
-set_location_assignment PIN_91 -to cpu_addr_out[26]
-set_location_assignment PIN_92 -to cpu_addr_out[25]
-set_location_assignment PIN_18 -to cpu_addr_out[24]
-set_location_assignment PIN_17 -to cpu_addr_out[23]
-set_location_assignment PIN_71 -to cpu_addr_out[22]
-set_location_assignment PIN_20 -to cpu_addr_out[21]
-set_location_assignment PIN_19 -to cpu_addr_out[20]
-set_location_assignment PIN_72 -to cpu_addr_out[19]
-set_location_assignment PIN_73 -to cpu_addr_out[18]
-set_location_assignment PIN_89 -to cpu_addr_out[17]
-set_location_assignment PIN_16 -to cpu_addr_out[16]
-set_location_assignment PIN_15 -to cpu_addr_out[15]
-set_location_assignment PIN_8 -to cpu_addr_out[14]
-set_location_assignment PIN_7 -to cpu_addr_out[13]
-set_location_assignment PIN_87 -to cpu_data_in[7]
-set_location_assignment PIN_86 -to cpu_data_in[6]
-set_location_assignment PIN_85 -to cpu_data_in[5]
-set_location_assignment PIN_84 -to cpu_data_in[4]
-set_location_assignment PIN_83 -to cpu_data_in[3]
-set_location_assignment PIN_82 -to cpu_data_in[2]
-set_location_assignment PIN_81 -to cpu_data_in[1]
-set_location_assignment PIN_78 -to cpu_data_in[0]
-set_location_assignment PIN_64 -to cpu_rw_in
-set_location_assignment PIN_77 -to flash_oe
-set_location_assignment PIN_21 -to flash_we
-set_location_assignment PIN_66 -to irq
-set_location_assignment PIN_70 -to m2
-set_location_assignment PIN_47 -to ppu_addr_in[13]
-set_location_assignment PIN_48 -to ppu_addr_in[12]
-set_location_assignment PIN_49 -to ppu_addr_in[11]
-set_location_assignment PIN_50 -to ppu_addr_in[10]
-set_location_assignment PIN_51 -to ppu_addr_in[9]
-set_location_assignment PIN_53 -to ppu_addr_in[8]
-set_location_assignment PIN_55 -to ppu_addr_in[7]
-set_location_assignment PIN_56 -to ppu_addr_in[6]
-set_location_assignment PIN_54 -to ppu_addr_in[5]
-set_location_assignment PIN_52 -to ppu_addr_in[4]
-set_location_assignment PIN_43 -to ppu_addr_in[3]
-set_location_assignment PIN_42 -to ppu_addr_in[2]
-set_location_assignment PIN_41 -to ppu_addr_in[1]
-set_location_assignment PIN_40 -to ppu_addr_in[0]
-set_location_assignment PIN_36 -to ppu_addr_out[17]
-set_location_assignment PIN_38 -to ppu_addr_out[16]
-set_location_assignment PIN_35 -to ppu_addr_out[15]
-set_location_assignment PIN_33 -to ppu_addr_out[14]
-set_location_assignment PIN_30 -to ppu_addr_out[13]
-set_location_assignment PIN_29 -to ppu_addr_out[12]
-set_location_assignment PIN_27 -to ppu_addr_out[11]
-set_location_assignment PIN_28 -to ppu_addr_out[10]
-set_location_assignment PIN_57 -to ppu_ciram_a10
-set_location_assignment PIN_58 -to ppu_ciram_ce
-set_location_assignment PIN_61 -to ppu_rd_in
-set_location_assignment PIN_26 -to ppu_rd_out
-set_location_assignment PIN_62 -to ppu_wr_in
-set_location_assignment PIN_34 -to ppu_wr_out
-set_location_assignment PIN_67 -to romsel
-set_location_assignment PIN_76 -to sram_ce
-set_location_assignment PIN_75 -to sram_oe
-set_location_assignment PIN_74 -to sram_we
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
 set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
 set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to romsel
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to cpu_rw_in
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ppu_rd_in
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name OPTIMIZATION_MODE BALANCED
 set_global_assignment -name ENABLE_OCT_DONE OFF
 set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
 set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER OFF
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
-set_global_assignment -name VERILOG_INCLUDE_FILE mappers.vh
-set_global_assignment -name VERILOG_FILE CoolGirl.v
-set_global_assignment -name CDF_FILE output_files/CoolGirl.cdf
\ No newline at end of file
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_location_assignment PIN_1 -to cpu_addr_out[18]
+set_location_assignment PIN_2 -to cpu_addr_out[25]
+set_location_assignment PIN_3 -to cpu_addr_out[19]
+set_location_assignment PIN_4 -to cpu_addr_out[26]
+set_location_assignment PIN_5 -to cpu_addr_out[22]
+set_location_assignment PIN_6 -to cpu_addr_out[17]
+set_location_assignment PIN_7 -to flash_we
+set_location_assignment PIN_8 -to cpu_addr_out[21]
+set_location_assignment PIN_11 -to cpu_addr_out[20]
+set_location_assignment PIN_12 -to cpu_addr_out[13]
+set_location_assignment PIN_14 -to cpu_addr_out[15]
+set_location_assignment PIN_13 -to cpu_addr_out[14]
+set_location_assignment PIN_15 -to cpu_addr_out[16]
+set_location_assignment PIN_16 -to cpu_addr_out[23]
+set_location_assignment PIN_18 -to cpu_addr_out[24]
+set_location_assignment PIN_42 -to ppu_addr_out[16]
+set_location_assignment PIN_43 -to ppu_rd_out
+set_location_assignment PIN_44 -to ppu_addr_out[10]
+set_location_assignment PIN_45 -to ppu_addr_out[11]
+set_location_assignment PIN_48 -to ppu_addr_out[12]
+set_location_assignment PIN_89 -to ppu_addr_in[12]
+set_location_assignment PIN_72 -to ppu_addr_in[13]
+set_location_assignment PIN_50 -to ppu_wr_out
+set_location_assignment PIN_51 -to ppu_addr_out[14]
+set_location_assignment PIN_52 -to ppu_addr_out[15]
+set_location_assignment PIN_53 -to ppu_addr_in[6]
+set_location_assignment PIN_55 -to ppu_addr_in[7]
+set_location_assignment PIN_57 -to ppu_addr_in[5]
+set_location_assignment PIN_58 -to ppu_addr_in[8]
+set_location_assignment PIN_59 -to ppu_addr_in[4]
+set_location_assignment PIN_63 -to ppu_addr_in[3]
+set_location_assignment PIN_68 -to ppu_addr_in[2]
+set_location_assignment PIN_69 -to ppu_addr_in[1]
+set_location_assignment PIN_70 -to ppu_addr_in[0]
+set_location_assignment PIN_71 -to ppu_addr_out[17]
+set_location_assignment PIN_73 -to ppu_addr_in[10]
+set_location_assignment PIN_74 -to ppu_addr_in[11]
+set_location_assignment PIN_81 -to ppu_not_a13
+set_location_assignment PIN_94 -to ppu_ciram_ce
+set_location_assignment PIN_95 -to ppu_ciram_a10
+set_location_assignment PIN_96 -to ppu_rd_in
+set_location_assignment PIN_101 -to ppu_wr_in
+set_location_assignment PIN_102 -to irq
+set_location_assignment PIN_103 -to cpu_rw_in
+set_location_assignment PIN_106 -to romsel
+set_location_assignment PIN_107 -to sram_we
+set_location_assignment PIN_108 -to sram_ce
+set_location_assignment PIN_110 -to cpu_addr_in[14]
+set_location_assignment PIN_111 -to cpu_addr_in[13]
+set_location_assignment PIN_112 -to flash_ce
+set_location_assignment PIN_114 -to flash_oe
+set_location_assignment PIN_117 -to cpu_addr_in[1]
+set_location_assignment PIN_118 -to cpu_addr_in[0]
+set_location_assignment PIN_119 -to cpu_data_in[0]
+set_location_assignment PIN_120 -to cpu_addr_in[3]
+set_location_assignment PIN_121 -to cpu_data_in[1]
+set_location_assignment PIN_122 -to cpu_addr_in[2]
+set_location_assignment PIN_123 -to cpu_data_in[2]
+set_location_assignment PIN_124 -to cpu_addr_in[4]
+set_location_assignment PIN_125 -to cpu_data_in[3]
+set_location_assignment PIN_127 -to cpu_data_in[4]
+set_location_assignment PIN_129 -to cpu_data_in[5]
+set_location_assignment PIN_131 -to cpu_addr_in[5]
+set_location_assignment PIN_132 -to cpu_data_in[6]
+set_location_assignment PIN_133 -to cpu_addr_in[6]
+set_location_assignment PIN_134 -to cpu_data_in[7]
+set_location_assignment PIN_137 -to cpu_addr_in[7]
+set_location_assignment PIN_138 -to cpu_addr_in[8]
+set_location_assignment PIN_139 -to cpu_addr_in[9]
+set_location_assignment PIN_140 -to cpu_addr_in[10]
+set_location_assignment PIN_141 -to cpu_addr_in[11]
+set_location_assignment PIN_142 -to cpu_addr_in[12]
+set_location_assignment PIN_143 -to sram_addr_out[13]
+set_location_assignment PIN_144 -to sram_addr_out[14]
+set_location_assignment PIN_60 -to ppu_addr_in[9]
+set_location_assignment PIN_91 -to m2
+set_location_assignment PIN_49 -to ppu_addr_out[13]
+set_location_assignment PIN_130 -to sram_oe
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to m2
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to ppu_rd_in
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to ppu_wr_in
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to irq
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to cpu_rw_in
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to romsel
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to sram_we
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to sram_ce
+set_global_assignment -name CDF_FILE CoolGirl.cdf
+set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to ppu_ciram_ce
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name OPTIMIZATION_MODE BALANCED
\ No newline at end of file
diff --git a/CoolGirl.v b/CoolGirl.v
index 5233962..3a0adb2 100644
--- a/CoolGirl.v
+++ b/CoolGirl.v
@@ -1,33 +1,37 @@
 module CoolGirl # (
-		parameter USE_VRC2 = 1,					// mappers #21, #22, #23, #25
-		parameter USE_VRC2a = 0,				// mapper #22
-		parameter USE_VRC4_INTERRUPTS = 1,	// for VRC4
-		parameter USE_TAITO = 1,				// mappers #33 & #48
-		parameter USE_TAITO_INTERRUPTS = 1,	// mapper #48
-		parameter USE_SUNSOFT = 0, 			// mapper #69
-		parameter USE_MAPPER_78 = 0,			// mapper #78 - Holy Diver
-		parameter USE_COLOR_DREAMS = 1,		// mapper #11
-		parameter USE_GxROM = 0,				// mapper #66
-		parameter USE_CHEETAHMEN2 = 1, 		// mapper #228
-		parameter USE_FIRE_HAWK = 0,			// for Fire Hawk only (mapper #71)
-		parameter USE_TxSROM = 0,				// mapper #118
-		parameter USE_IREM_TAMS1 = 0,			// mapper #97
-		parameter USE_IREM_G101 = 0,			// mapper #32
-		parameter USE_MAPPER_87 = 0,			// mapper #87
-		parameter USE_MMC2 = 0,					// mapper #9
-		parameter USE_MMC4 = 0,					// mapper #10
-		parameter USE_MAPPER_093 = 0,			// mapper #093
-		parameter USE_MAPPER_189 = 0			// mapper #189
+		parameter USE_MAPPER_009_010 = 1,			// mapper #9 - MMC2, #10 - MMC4
+		parameter USE_MAPPER_011 = 1,					// mapper #11 - Color Dreams
+		parameter USE_MAPPER_018 = 1,					// mapper #18
+		parameter USE_MAPPER_021_022_023_025 = 1,	// mappers #21, #22, #23, #25 - VRC2, VRC4
+		parameter USE_MAPPER_022 = 1,					// mapper #22 - VRC2a (shifted CHR lines)
+		parameter USE_VRC4_INTERRUPTS = 1,			// for VRC4
+		parameter USE_MAPPER_032 = 1,					// mapper #32 - IREM-G101
+		parameter USE_MAPPER_033_048 = 1,			// mappers #33 & #48 - Taito
+		parameter USE_MAPPER_048_INTERRUPTS = 1,	// mapper #48 - Taito
+		parameter USE_MAPPER_066 = 1,					// mapper #66 - GxROM
+		parameter USE_MAPPER_069 = 1, 				// mapper #69 - Sunsoft
+		parameter USE_MAPPER_071 = 1,					// mapper #71 (for Fire Hawk only)
+		parameter USE_MAPPER_078 = 1,					// mapper #78 - Holy Diver
+		parameter USE_MAPPER_087 = 1,					// mapper #87
+		parameter USE_MAPPER_090 = 1,					// mapper #90 - JY, for Aladdin only
+		parameter USE_MAPPER_093 = 1,					// mapper #93
+		parameter USE_MAPPER_097 = 1,					// mapper #97 - IREM TAMS1
+		parameter USE_MAPPER_118 = 1,					// mapper #118 - TxSROM
+		parameter USE_MAPPER_163 = 1,					// mapper #163
+		parameter USE_MAPPER_189 = 1,					// mapper #189
+		parameter USE_MAPPER_228 = 1 					// mapper #228 - Cheetahmen II only
 	)
 	(
 	input	m2,
 	input romsel,
 	input cpu_rw_in,
 	input [14:0] cpu_addr_in,
-	input [7:0] cpu_data_in,
+	inout [7:0] cpu_data_in,
 	output [26:13] cpu_addr_out,
+	output [14:13] sram_addr_out,
 	output flash_we,
 	output flash_oe,
+	output flash_ce,
 	output sram_ce,
 	output sram_we,
 	output sram_oe,
@@ -39,152 +43,47 @@ module CoolGirl # (
 	output ppu_rd_out,
 	output ppu_wr_out,
 	output ppu_ciram_a10,
-	//output ppu_ciram_ce,
+	input ppu_not_a13,
+	output ppu_ciram_ce,
 		
 	output irq
 );
-	reg [26:14] cpu_base = 0;
-	reg [18:14] cpu_mask = 0;
-	reg [17:13] chr_mask = 0;
-	reg [2:0] prg_mode = 0;
-	reg map_rom_on_6000 = 0;
-	reg [5:0] prg_bank_6000 = 0;
-	reg [5:0] prg_bank_a = 0;
-	reg [5:0] prg_bank_b = 6'b111101;
-	reg [5:0] prg_bank_c = 6'b111110;
-	reg [5:0] prg_bank_d = 6'b111111;
-	reg [2:0] chr_mode = 0;
-	reg [7:0] chr_bank_a = 0;
-	reg [7:0] chr_bank_b = 1;
-	reg [7:0] chr_bank_c = 2;
-	reg [7:0] chr_bank_d = 3;
-	reg [7:0] chr_bank_e = 4;
-	reg [7:0] chr_bank_f = 5;
-	reg [7:0] chr_bank_g = 6;
-	reg [7:0] chr_bank_h = 7;
-	reg [4:0] mapper = 0;
-	reg [2:0] flags = 0;
-	reg sram_enabled = 0;
-	reg [1:0] sram_page = 0;
-	reg chr_write_enabled = 0;
-	reg prg_write_enabled = 0;
-	reg [1:0] mirroring = 0;
-	reg lockout = 0;
+	reg [7:0] new_dendy_init = 8'b11111111;
+	reg new_dendy = 0;
 	
-	// some common registers for all mappers
-	reg [7:0] r0 = 0;
-
-	assign cpu_addr_out[26:15] = {cpu_base[26:15] | (cpu_addr_mapped[18:15] & ~cpu_mask[18:15])};
-	assign cpu_addr_out[14:13] = (~sram_enabled | map_rom_on_6000 | ~romsel | ~m2) ?
-		{cpu_base[14] | (cpu_addr_mapped[14] & ~cpu_mask[14]), cpu_addr_mapped[13]} 
-		: sram_page[1:0];
+	assign cpu_addr_out[26:13] = {cpu_base[26:14] | (cpu_addr_mapped[20:14] & ~prg_mask[20:14]), cpu_addr_mapped[13]};
+	assign sram_addr_out[14:13] = sram_page[1:0];
 	assign ppu_addr_out[17:10] = {ppu_addr_mapped[17:13] & ~chr_mask[17:13], ppu_addr_mapped[12:10]};
 
-	assign flash_we = cpu_rw_in | romsel | ~prg_write_enabled;
-	assign flash_oe = ~(cpu_rw_in & m2 & (~romsel | (map_rom_on_6000 & cpu_addr_in[14] & cpu_addr_in[13])));
+	assign cpu_data_in = cpu_data_out_enabled ? cpu_data_out : 8'bZZZZZZZZ;	
+	wire flash_ce_w = ~(~romsel | (m2 & map_rom_on_6000 & cpu_addr_in[14] & cpu_addr_in[13]));
+	assign flash_ce = flash_ce_w
+		| cpu_data_out_enabled;
+	assign flash_oe = (~cpu_rw_in | flash_ce_w) 
+		& ~cpu_data_out_enabled; // to switch data direction
+	assign flash_we = cpu_rw_in | flash_ce_w | ~prg_write_enabled;
 	wire sram_ce_w = ~(cpu_addr_in[14] & cpu_addr_in[13] & m2 & romsel & sram_enabled & ~map_rom_on_6000);
 	assign sram_ce = sram_ce_w;
 	assign sram_we = cpu_rw_in | sram_ce_w;
-	assign sram_oe = ~cpu_rw_in | sram_ce_w;
+	assign sram_oe = ~cpu_rw_in | sram_ce_w | cpu_data_out_enabled;
 	assign ppu_rd_out = ppu_rd_in | ppu_addr_in[13];
 	assign ppu_wr_out = ppu_wr_in | ppu_addr_in[13] | ~chr_write_enabled;
-	assign irq = (irq_scanline_out | irq_cpu_out) ? 1'b0 : 1'bZ;
-	//assign ppu_ciram_ce = 1'bZ; // for backward compatibility	
+	assign ppu_ciram_ce = 1'bZ; // ppu_not_a13;
 
-	// for scanline-based interrupts
-	reg [7:0] irq_scanline_counter = 0;
-	reg [1:0] a12_low_time = 0;
-	reg irq_scanline_reload = 0;
-	reg [7:0] irq_scanline_latch = 0;
-	reg irq_scanline_reload_clear = 0;
-	reg irq_scanline_enabled = 0;
-	reg irq_scanline_value = 0;
-	reg irq_scanline_ready = 0;
-	reg irq_scanline_out = 0;
-	
-	// for CPU interrupts
-	reg [15:0] irq_cpu_value = 0;
-	reg irq_cpu_out = 0;
-	reg [2:0] irq_cpu_control = 0;
-	reg [7:0] vrc4_irq_latch = 0;
-	reg [6:0] vrc4_irq_prescaler = 0;
-	reg [1:0] vrc4_irq_prescaler_counter = 0;
-	// for VRC
-	wire vrc_2b_hi = cpu_addr_in[1] | cpu_addr_in[3] | cpu_addr_in[5] | cpu_addr_in[7];
-	wire vrc_2b_low = cpu_addr_in[0] | cpu_addr_in[2] | cpu_addr_in[4] | cpu_addr_in[6];
-	// for MMC2/MMC4
-	reg ppu_latch0 = 0;
-	reg ppu_latch1 = 0;
-	
-	reg writed;
-	
-	assign ppu_ciram_a10 = (USE_TxSROM & (mapper == 5'b10100) & flags[0]) ? ppu_addr_mapped[17] :
-		(mirroring[1] ? mirroring[0] : (mirroring[0] ? ppu_addr_in[11] : ppu_addr_in[10])); // vertical / horizontal, 1Sa, 1Sb			
+	always @ (posedge m2)
+	begin
+		if (new_dendy_init != 0)
+			new_dendy_init = new_dendy_init - 1'b1;
+	end
 	
-	wire [18:13] cpu_addr_mapped = (map_rom_on_6000 & romsel & m2) ? prg_bank_6000 :
-	(
-		prg_mode[2] ? (
-			prg_mode[1] ? (
-				// 11x - 0x8000(A)
-				{prg_bank_a[5:2], cpu_addr_in[14:13]}
-			) : ( // prg_mode[1]
-				prg_mode[0] ? (
-					// 101 - 0x2000(C)+0x2000(B)+0x2000(A)+0x2000(D)
-					cpu_addr_in[14] ? (cpu_addr_in[13] ? prg_bank_d : prg_bank_a) : (cpu_addr_in[13] ? prg_bank_b : prg_bank_c)
-				) : ( // prg_mode[0]
-					// 100 - 0x2000(A)+0x2000(B)+0x2000(C)+0x2000(D)
-					cpu_addr_in[14] ? (cpu_addr_in[13] ? prg_bank_d : prg_bank_c) : (cpu_addr_in[13] ? prg_bank_b : prg_bank_a)
-				)
-			)
-		) : ( // prg_mode[2]
-			prg_mode[0] ? (
-				// 0x1 - 0x4000(C) + 0x4000 (A)
-				{cpu_addr_in[14] ? prg_bank_a[5:1] : prg_bank_c[5:1], cpu_addr_in[13]}
-			) : ( // prg_mode[0]
-				// 0x0 - 0x4000(A) + 0x4000 (С)
-				{cpu_addr_in[14] ? prg_bank_c[5:1] : prg_bank_a[5:1], cpu_addr_in[13]}
-			)
-		)
-	);
-	
-	wire [17:10] ppu_addr_mapped = chr_mode[2] ? (
-		chr_mode[1] ? (
-			chr_mode[0] ? ( 
-				// 111 - 0x400(A)+0x400(B)+0x400(C)+0x400(D)+0x400(E)+0x400(F)+0x400(G)+0x400(H)
-				ppu_addr_in[12] ? 
-					(ppu_addr_in[11] ? (ppu_addr_in[10] ? chr_bank_h : chr_bank_g) : 
-					(ppu_addr_in[10] ? chr_bank_f : chr_bank_e)) : (ppu_addr_in[11] ? (ppu_addr_in[10] ? chr_bank_d : chr_bank_c) : (ppu_addr_in[10] ? chr_bank_b : chr_bank_a))
-			) : ( // chr_mode[0]
-				// 110 - 0x800(A)+0x800(C)+0x800(E)+0x800(G)
-				{ppu_addr_in[12] ? 
-					(ppu_addr_in[11] ? chr_bank_g[7:1] : chr_bank_e[7:1]) : 
-					(ppu_addr_in[11] ? chr_bank_c[7:1] : chr_bank_a[7:1]), ppu_addr_in[10]}
-			)
-		) : ( // chr_mode[1]
-			// 100 - 0x1000(A) + 0x1000(E)
-			// 101 - 0x1000(A/B) + 0x1000(E/F) - MMC2 и MMC4
-			{ppu_addr_in[12] ? 
-				(((USE_MMC2|USE_MMC4)&chr_mode[0]&ppu_latch1) ? chr_bank_f[7:2] : chr_bank_e[7:2]) : 
-				(((USE_MMC2|USE_MMC4)&chr_mode[0]&ppu_latch0) ? chr_bank_b[7:2] : chr_bank_a[7:2]),
-			ppu_addr_in[11:10]}
-		)
-	) : ( // chr_mode[2]
-		chr_mode[1] ? (
-			// 010 - 0x800(A)+0x800(C)+0x400(E)+0x400(F)+0x400(G)+0x400(H) 
-			// 011 - 0x400(E)+0x400(F)+0x400(G)+0x400(H)+0x800(A)+0x800(С)
-			(ppu_addr_in[12]^chr_mode[0]) ? 
-				(ppu_addr_in[11] ?
-					(ppu_addr_in[10] ? chr_bank_h : chr_bank_g) : 
-					(ppu_addr_in[10] ? chr_bank_f : chr_bank_e)
-				) : (
-					ppu_addr_in[11] ? {chr_bank_c[7:1],ppu_addr_in[10]} : {chr_bank_a[7:1],ppu_addr_in[10]}
-				)
-		) : ( // chr_mode[1]
-			// 00x - 0x2000(A)
-			{chr_bank_a[7:3], ppu_addr_in[12:10]}
-		)
-	);	
+	always @ (negedge ppu_rd_in)
+	begin
+		if (new_dendy_init == 0 && (ppu_addr_in[13] != ~ppu_not_a13))
+			new_dendy = 1;
+	end
 	
 `include "mappers.vh"
 	
 endmodule
+
+
diff --git a/board/BoardOutline.gbr b/board/BoardOutline.gbr
index bc76fc3..08dbdfa 100644
--- a/board/BoardOutline.gbr
+++ b/board/BoardOutline.gbr
@@ -20,10 +20,14 @@ Y10750D1*
 X41875D1*
 Y11687D1*
 X43437D1*
-Y18625D1*
-X39000Y23062D1*
-X8375D1*
-X3937Y18625D1*
+X43441Y13626D1*
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+Y21126D1*
+X10438D1*
+X3937Y14626D1*
 Y11687D1*
 X5500D1*
 Y10750D1*
diff --git a/board/Bottom.gbr b/board/Bottom.gbr
index d48c906..ae8d347 100644
--- a/board/Bottom.gbr
+++ b/board/Bottom.gbr
@@ -1,25 +1,24 @@
 G04 DipTrace 2.4.0.2*
 %INBottom.gbr*%
 %MOIN*%
-%ADD13C,0.0157*%
-%ADD14C,0.0118*%
-%ADD15C,0.0394*%
-%ADD16C,0.0059*%
+%ADD13C,0.0059*%
+%ADD14C,0.0157*%
+%ADD15C,0.0118*%
+%ADD16C,0.0394*%
 %ADD17C,0.025*%
 %ADD19R,0.0748X0.0748*%
-%ADD20C,0.0748*%
-%ADD21R,0.0354X0.0276*%
-%ADD22R,0.063X0.063*%
-%ADD23C,0.063*%
-%ADD24R,0.0276X0.0354*%
-%ADD25R,0.063X0.0709*%
-%ADD26R,0.0709X0.2559*%
-%ADD27R,0.0669X0.0669*%
-%ADD28C,0.0669*%
-%ADD30R,0.0118X0.063*%
-%ADD31R,0.063X0.0118*%
-%ADD33R,0.0236X0.1181*%
-%ADD39C,0.0276*%
+%ADD20C,0.0669*%
+%ADD21R,0.0787X0.1575*%
+%ADD22R,0.0354X0.0276*%
+%ADD23R,0.063X0.063*%
+%ADD24C,0.063*%
+%ADD25R,0.0276X0.0354*%
+%ADD26R,0.063X0.0709*%
+%ADD27R,0.0709X0.2559*%
+%ADD28R,0.0118X0.063*%
+%ADD29R,0.063X0.0118*%
+%ADD34R,0.0236X0.1181*%
+%ADD37C,0.0276*%
 %FSLAX44Y44*%
 G04*
 G70*
@@ -28,3328 +27,2843 @@ G75*
 G01*
 %LNBottom*%
 %LPD*%
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@@ -3380,151 +2894,213 @@ X35186D3*
 X36186D3*
 X37186D3*
 X38186D3*
-D27*
-X29125Y21000D3*
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 D28*
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 M02*
diff --git a/board/BottomMask.gbr b/board/BottomMask.gbr
index e9b1ce4..207bcc7 100644
--- a/board/BottomMask.gbr
+++ b/board/BottomMask.gbr
@@ -1,19 +1,18 @@
 G04 DipTrace 2.4.0.2*
 %INBottomMask.gbr*%
 %MOIN*%
-%ADD19R,0.0748X0.0748*%
-%ADD20C,0.0748*%
-%ADD52R,0.0315X0.126*%
-%ADD56R,0.0709X0.0197*%
-%ADD58R,0.0197X0.0709*%
-%ADD62R,0.0787X0.2638*%
-%ADD64R,0.0709X0.0787*%
-%ADD66R,0.0354X0.0433*%
-%ADD68C,0.0709*%
-%ADD70R,0.0709X0.0709*%
-%ADD72R,0.0433X0.0354*%
-%ADD74C,0.0827*%
-%ADD75R,0.0827X0.0827*%
+%ADD46R,0.0315X0.126*%
+%ADD54R,0.0709X0.0197*%
+%ADD56R,0.0197X0.0709*%
+%ADD58R,0.0787X0.2638*%
+%ADD60R,0.0709X0.0787*%
+%ADD62R,0.0354X0.0433*%
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+%ADD66R,0.0709X0.0709*%
+%ADD68R,0.0433X0.0354*%
+%ADD70R,0.0866X0.1654*%
+%ADD72C,0.0748*%
+%ADD74R,0.0827X0.0827*%
 %FSLAX44Y44*%
 G04*
 G70*
@@ -22,36 +21,42 @@ G75*
 G01*
 %LNBotMask*%
 %LPD*%
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 D74*
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 D70*
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 D66*
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 D62*
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 X9186Y5399D3*
 X10186D3*
 X11186D3*
@@ -82,151 +87,213 @@ X35186D3*
 X36186D3*
 X37186D3*
 X38186D3*
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 D56*
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 M02*
diff --git a/board/BottomSilk.gbr b/board/BottomSilk.gbr
index bf42d66..7dde486 100644
--- a/board/BottomSilk.gbr
+++ b/board/BottomSilk.gbr
@@ -2,8 +2,8 @@ G04 DipTrace 2.4.0.2*
 %INBottomSilk.gbr*%
 %MOIN*%
 %ADD10C,0.0098*%
+%ADD14C,0.0157*%
 %ADD18C,0.0237*%
-%ADD29C,0.0164*%
 %ADD76C,0.0077*%
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 G04*
@@ -14,463 +14,663 @@ G01*
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 %LPD*%
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diff --git a/board/Through.drl b/board/Through.drl
index 8c2901c..ec9bd2e 100644
--- a/board/Through.drl
+++ b/board/Through.drl
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 T00
 M30
diff --git a/board/Top.gbr b/board/Top.gbr
index 3f53026..c0cb7b0 100644
--- a/board/Top.gbr
+++ b/board/Top.gbr
@@ -1,28 +1,26 @@
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 M02*
diff --git a/board/TopMask.gbr b/board/TopMask.gbr
index 0e673e2..102b211 100644
--- a/board/TopMask.gbr
+++ b/board/TopMask.gbr
@@ -1,23 +1,21 @@
 G04 DipTrace 2.4.0.2*
 %INTopMask.gbr*%
 %MOIN*%
-%ADD19R,0.0748X0.0748*%
-%ADD20C,0.0748*%
-%ADD44R,0.0236X0.0787*%
-%ADD46R,0.0787X0.0236*%
-%ADD48R,0.1358X0.0925*%
-%ADD50R,0.0453X0.0925*%
-%ADD54R,0.126X0.0197*%
-%ADD56R,0.0709X0.0197*%
-%ADD58R,0.0197X0.0709*%
-%ADD62R,0.0787X0.2638*%
-%ADD64R,0.0709X0.0787*%
-%ADD66R,0.0354X0.0433*%
-%ADD68C,0.0709*%
-%ADD70R,0.0709X0.0709*%
-%ADD72R,0.0433X0.0354*%
-%ADD74C,0.0827*%
-%ADD75R,0.0827X0.0827*%
+%ADD42R,0.0236X0.0787*%
+%ADD44R,0.0197X0.0866*%
+%ADD48R,0.126X0.0197*%
+%ADD50R,0.1358X0.0925*%
+%ADD52R,0.0453X0.0925*%
+%ADD54R,0.0709X0.0197*%
+%ADD58R,0.0787X0.2638*%
+%ADD60R,0.0709X0.0787*%
+%ADD62R,0.0354X0.0433*%
+%ADD64C,0.0709*%
+%ADD66R,0.0709X0.0709*%
+%ADD68R,0.0433X0.0354*%
+%ADD70R,0.0866X0.1654*%
+%ADD72C,0.0748*%
+%ADD74R,0.0827X0.0827*%
 %FSLAX44Y44*%
 G04*
 G70*
@@ -26,31 +24,32 @@ G75*
 G01*
 %LNTopMask*%
 %LPD*%
-D75*
-X42687Y17812D3*
 D74*
-X34616D3*
+X41378Y13063D3*
 D72*
-X8074Y19500D3*
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 D70*
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 D68*
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 D66*
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 D62*
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 X9186Y5399D3*
 X10186D3*
 X11186D3*
@@ -81,274 +80,279 @@ X35186D3*
 X36186D3*
 X37186D3*
 X38186D3*
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+G36*
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 D72*
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 M02*
diff --git a/board/TopSilk.gbr b/board/TopSilk.gbr
index 84f4ca8..ccc5830 100644
--- a/board/TopSilk.gbr
+++ b/board/TopSilk.gbr
@@ -2,7 +2,7 @@ G04 DipTrace 2.4.0.2*
 %INTopSilk.gbr*%
 %MOIN*%
 %ADD10C,0.0098*%
-%ADD34C,0.0154*%
+%ADD30C,0.0154*%
 %ADD76C,0.0077*%
 %ADD77C,0.0124*%
 %ADD78C,0.0062*%
@@ -14,862 +14,862 @@ G75*
 G01*
 %LNTopSilk*%
 %LPD*%
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 M02*
diff --git a/board/coolgirl.dch b/board/coolgirl.dch
deleted file mode 100644
index 5ca52ca..0000000
--- a/board/coolgirl.dch
+++ /dev/null
diff --git a/board/coolgirl.dip b/board/coolgirl.dip
index 6626aa0..085cfdf 100644
--- a/board/coolgirl.dip
+++ b/board/coolgirl.dip
diff --git a/mappers.vh b/mappers.vh
index bb378fe..1cc0b45 100644
--- a/mappers.vh
+++ b/mappers.vh
@@ -1,3 +1,167 @@
+	reg [26:14] cpu_base = 0;
+	reg [20:14] prg_mask = 7'b1111000;
+	reg [17:13] chr_mask = 0;
+	reg [2:0] prg_mode = 0;
+	reg map_rom_on_6000 = 0;
+	reg [7:0] prg_bank_6000 = 0;
+	reg [7:0] prg_bank_a = 0;
+	reg [7:0] prg_bank_b = 6'b111101;
+	reg [7:0] prg_bank_c = 6'b111110;
+	reg [7:0] prg_bank_d = 6'b111111;
+	reg [2:0] chr_mode = 0;
+	reg [7:0] chr_bank_a = 0;
+	reg [7:0] chr_bank_b = 1;
+	reg [7:0] chr_bank_c = 2;
+	reg [7:0] chr_bank_d = 3;
+	reg [7:0] chr_bank_e = 4;
+	reg [7:0] chr_bank_f = 5;
+	reg [7:0] chr_bank_g = 6;
+	reg [7:0] chr_bank_h = 7;
+	reg [4:0] mapper = 0;
+	reg [2:0] flags = 0;
+	reg sram_enabled = 0;
+	reg [1:0] sram_page = 0;
+	reg chr_write_enabled = 0;
+	reg prg_write_enabled = 0;
+	reg [1:0] mirroring = 0;
+	reg lockout = 0;	
+
+	// some common registers for all mappers
+	reg [7:0] r0 = 0;
+	reg [7:0] r1 = 0;
+	reg [7:0] r2 = 0;
+	reg [7:0] r3 = 0;
+	reg [7:0] r4 = 0;
+	reg [7:0] r5 = 0;
+	
+	reg [7:0] mul1;
+	reg [7:0] mul2;
+	wire [15:0] mul = mul1*mul2;
+	
+	// for scanline-based interrupts
+	reg [7:0] irq_scanline_counter = 0;
+	reg [1:0] a12_low_time = 0;
+	reg irq_scanline_reload = 0;
+	reg [7:0] irq_scanline_latch = 0;
+	reg irq_scanline_reload_clear = 0;
+	reg irq_scanline_enabled = 0;
+	reg irq_scanline_value = 0;
+	reg irq_scanline_ready = 0;
+	reg irq_scanline_out = 0;
+	reg [7:0] scanline = 0;
+	reg [9:0] ppu_rd_hi_time = 0;
+	reg new_screen = 0;
+	reg new_screen_clear = 0;
+	
+	// for CPU interrupts
+	reg [15:0] irq_cpu_value = 0;
+	reg irq_cpu_out = 0;
+	reg [3:0] irq_cpu_control = 0;
+	reg [15:0] irq_cpu_latch = 0;
+	reg [6:0] vrc4_irq_prescaler = 0;
+	reg [1:0] vrc4_irq_prescaler_counter = 0;
+
+	// for MMC2/MMC4
+	reg ppu_latch0 = 0;
+	reg ppu_latch1 = 0;
+	reg ppu_mapper_163_latch = 0;
+	
+	reg writed;
+
+	wire cpu_data_out_enabled;
+	wire [7:0] cpu_data_out;
+	assign {cpu_data_out_enabled, cpu_data_out} = 
+		(m2 & romsel & cpu_rw_in) ?
+		(
+			((mapper == 0) && (cpu_addr_in[14:12] == 3'b101)) ? {8'b10000000, new_dendy} :
+			(USE_MAPPER_163 && (mapper == 5'b00110) && ({cpu_addr_in[14:12],cpu_addr_in[10:8]} == 6'b101001)) ? 
+					{1'b1, r2 | r0 | r1 | ~r3} :
+			(USE_MAPPER_163 && (mapper == 5'b00110) && ({cpu_addr_in[14:12],cpu_addr_in[10:8]} == 6'b101101)) ? 
+					{1'b1, r5[0] ? r2 : r1} :
+			//(USE_MAPPER_090_MUL && (mapper == 5'b01101) && (cpu_addr_in[14:0] == 15'h5800)) ? {1'b1, mul[7:0]} :
+			//(USE_MAPPER_090_MUL && (mapper == 5'b01101) && (cpu_addr_in[14:0] == 15'h5801)) ? {1'b1, mul[15:8]} :
+			9'b000000000
+		): 9'b000000000;
+		
+	assign ppu_ciram_a10 = (USE_MAPPER_118 & (mapper == 5'b10100) & flags[0]) ? ppu_addr_mapped[17] :
+		(mirroring[1] ? mirroring[0] : (mirroring[0] ? ppu_addr_in[11] : ppu_addr_in[10])); // vertical / horizontal, 1Sa, 1Sb			
+
+	wire [20:13] cpu_addr_mapped = (map_rom_on_6000 & romsel & m2) ? prg_bank_6000 :
+	(
+		prg_mode[2] ? (
+			prg_mode[1] ? (				
+				prg_mode[0] ? (
+					// 111 - 0x8000(A)
+					{prg_bank_a[7:2], cpu_addr_in[14:13]}
+				) : (
+					// 110 - 0x8000(B)
+					{prg_bank_b[7:2], cpu_addr_in[14:13]}
+				)
+			) : ( // prg_mode[1]
+				prg_mode[0] ? (
+					// 101 - 0x2000(C)+0x2000(B)+0x2000(A)+0x2000(D)
+					cpu_addr_in[14] ? (cpu_addr_in[13] ? prg_bank_d : prg_bank_a) : (cpu_addr_in[13] ? prg_bank_b : prg_bank_c)
+				) : ( // prg_mode[0]
+					// 100 - 0x2000(A)+0x2000(B)+0x2000(C)+0x2000(D)
+					cpu_addr_in[14] ? (cpu_addr_in[13] ? prg_bank_d : prg_bank_c) : (cpu_addr_in[13] ? prg_bank_b : prg_bank_a)
+				)
+			)
+		) : ( // prg_mode[2]
+			prg_mode[0] ? (
+				// 0x1 - 0x4000(C) + 0x4000 (A)
+				{cpu_addr_in[14] ? prg_bank_a[7:1] : prg_bank_c[7:1], cpu_addr_in[13]}
+			) : ( // prg_mode[0]
+				// 0x0 - 0x4000(A) + 0x4000 (С)
+				{cpu_addr_in[14] ? prg_bank_c[7:1] : prg_bank_a[7:1], cpu_addr_in[13]}
+			)
+		)
+	);
+	
+	wire [17:10] ppu_addr_mapped = chr_mode[2] ? (
+		chr_mode[1] ? (
+			chr_mode[0] ? ( 
+				// 111 - 0x400(A)+0x400(B)+0x400(C)+0x400(D)+0x400(E)+0x400(F)+0x400(G)+0x400(H)
+				ppu_addr_in[12] ? 
+					(ppu_addr_in[11] ? (ppu_addr_in[10] ? chr_bank_h : chr_bank_g) : 
+					(ppu_addr_in[10] ? chr_bank_f : chr_bank_e)) : (ppu_addr_in[11] ? (ppu_addr_in[10] ? chr_bank_d : chr_bank_c) : (ppu_addr_in[10] ? chr_bank_b : chr_bank_a))
+			) : ( // chr_mode[0]
+				// 110 - 0x800(A)+0x800(C)+0x800(E)+0x800(G)
+				{ppu_addr_in[12] ? 
+					(ppu_addr_in[11] ? chr_bank_g[7:1] : chr_bank_e[7:1]) : 
+					(ppu_addr_in[11] ? chr_bank_c[7:1] : chr_bank_a[7:1]), ppu_addr_in[10]}
+			)
+		) : ( // chr_mode[1]
+			// 100 - 0x1000(A) + 0x1000(E)
+			// 101 - 0x1000(A/B) + 0x1000(E/F) - MMC2 и MMC4
+			{ppu_addr_in[12] ?
+				(((USE_MAPPER_009_010) && chr_mode[0] && ppu_latch1) ? chr_bank_f[7:2] : chr_bank_e[7:2]) : 
+				(((USE_MAPPER_009_010) && chr_mode[0] && ppu_latch0) ? chr_bank_b[7:2] : chr_bank_a[7:2]),
+			ppu_addr_in[11:10]}
+		)
+	) : ( // chr_mode[2]
+		chr_mode[1] ? (
+			// 010 - 0x800(A)+0x800(C)+0x400(E)+0x400(F)+0x400(G)+0x400(H) 
+			// 011 - 0x400(E)+0x400(F)+0x400(G)+0x400(H)+0x800(A)+0x800(С)
+			(ppu_addr_in[12]^chr_mode[0]) ? 
+				(ppu_addr_in[11] ?
+					(ppu_addr_in[10] ? chr_bank_h : chr_bank_g) : 
+					(ppu_addr_in[10] ? chr_bank_f : chr_bank_e)
+				) : (
+					ppu_addr_in[11] ? {chr_bank_c[7:1],ppu_addr_in[10]} : {chr_bank_a[7:1],ppu_addr_in[10]}
+				)
+		) : ( // chr_mode[1]			
+			(USE_MAPPER_163 && chr_mode[0]) ? (
+				// 001 - Mapper #163 special
+				{ppu_mapper_163_latch, ppu_addr_in[11:10]}
+			) : (
+				// 000 - 0x2000(A)
+				{chr_bank_a[7:3], ppu_addr_in[12:10]}
+			)
+		)
+	);
+	
+	assign irq = (irq_scanline_out | irq_cpu_out) ? 1'b0 : 1'bZ;
+
 	/*
 	reg romsel_alt = 1;
 	reg romsel_alt_clean = 0;
@@ -11,6 +175,10 @@
 	end
 	*/
 	
+	// for VRC
+	wire vrc_2b_hi = cpu_addr_in[1] | cpu_addr_in[3] | cpu_addr_in[5] | cpu_addr_in[7];
+	wire vrc_2b_low = cpu_addr_in[0] | cpu_addr_in[2] | cpu_addr_in[4] | cpu_addr_in[6];
+	
 	always @ (negedge m2)
 	begin
 		if (cpu_rw_in == 1) // read
@@ -27,15 +195,15 @@
 				begin
 					case (cpu_addr_in[2:0])
 						3'b000: // $5xx0
-							{prg_mode[2:0], cpu_base[26:22]} = cpu_data_in[7:0]; // PRG mode, CPU base address A26-A22
+							{cpu_base[26:22]} = cpu_data_in[4:0];						// CPU base address A26-A22
 						3'b001: // $5xx1
 							cpu_base[21:14] = cpu_data_in[7:0]; 						// CPU base address A21-A14
 						3'b010: // $5xx2
-							cpu_mask[18:14] = cpu_data_in[4:0]; 						// CPU mask A18-A14
+							prg_mask[20:14] = cpu_data_in[6:0]; 						// CPU mask A18-A14
 						3'b011: // $5xx3
-							{chr_mode, chr_bank_a[7:3]} = cpu_data_in[7:0];			// CHR mode, direct chr_bank_a access
+							{prg_mode[2:0], chr_bank_a[7:3]} = cpu_data_in[7:0];	// PRG mode, direct chr_bank_a access
 						3'b100: // $5xx4
-							chr_mask[17:13] = cpu_data_in[4:0];							// CHR mask A17-A13
+							{chr_mode[2:0], chr_mask[17:13]} = cpu_data_in[7:0];	// CHR mode, CHR mask A17-A13
 						3'b101: // $5xx5
 							{prg_bank_a[5:1], sram_page[1:0]} = cpu_data_in[6:0]; // direct prg_bank_a access, current SRAM page 0-3
 						3'b110: // $5xx6
@@ -46,14 +214,57 @@
 					endcase
 				end
 				
+				// Mapper #163				
+				if (USE_MAPPER_163 && mapper == 5'b00110)
+				begin
+					if (cpu_addr_in[14:0] == 15'h5101)
+					begin
+						if ((r4 != 0) && (cpu_data_in == 0))
+							r5[0] = ~r5[0];
+						r4 = cpu_data_in;					
+					end else if ((cpu_addr_in[14:0] == 15'h5100) && (cpu_data_in == 6))
+					begin
+						prg_mode[0] = 0;
+						prg_bank_b = 4'b1100;
+					end else if (cpu_addr_in[14:12] == 3'b101) begin
+						case (cpu_addr_in[9:8])
+							2'b10: begin
+									prg_mode[0] = 1;
+									prg_bank_a[7:6] = cpu_data_in[1:0];
+									r0 = cpu_data_in;
+								end
+							2'b00: begin
+									prg_mode[0] = 1;
+									prg_bank_a[5:2] = cpu_data_in[3:0];
+									chr_mode[0] = cpu_data_in[7];
+									r1 = cpu_data_in;
+								end
+							2'b11: r2 = cpu_data_in;
+							2'b01: r3 = cpu_data_in;
+						endcase
+					end					
+				end
+				
 				// Mapper #87
-				if (USE_MAPPER_87 && mapper == 5'b01100)
+				if (USE_MAPPER_087 && mapper == 5'b01100)
 				begin
 					if (cpu_addr_in[14] & cpu_addr_in[13]) // $6000-$7FFF
 					begin
 						chr_bank_a[4:3] = {cpu_data_in[0], cpu_data_in[1]};
 					end
 				end
+				
+				// Mapper #90 - JY
+				/*
+				if (USE_MAPPER_090_MUL && mapper == 5'b01101)
+				begin
+					if (cpu_addr_in[14:0] == 15'h5800)
+						mul1 = cpu_data_in;
+					if (cpu_addr_in[14:0] == 15'h5801)
+						mul2 = cpu_data_in;
+				end
+				*/
+				
 				// Mapper #189
 				// It's MMC3 with flag1
 				if (USE_MAPPER_189 & flags[1] & (mapper == 5'b10100))
@@ -62,14 +273,35 @@
 					begin
 						prg_bank_a[5:2] = cpu_data_in[3:0] | cpu_data_in[7:4];
 					end
+				end				
+				
+				
+				// temp/test
+				/*
+				if (mapper == 5'b11111)
+				begin
+					if (cpu_addr_in[14:0] == 15'h4025)
+					begin
+						mirroring = {1'b0, cpu_data_in[3]};
+					end
 				end
+				*/
 			end else begin // $8000-$FFFF
+				// temp/test
+				/*
+				if (mapper == 5'b11111)
+				begin
+					prg_bank_6000 = cpu_data_in[4:1] + 4;
+					map_rom_on_6000 = 1;
+				end
+				*/
+				
 				// Mapper #2 - UxROM
 				// flag0 - mapper #71 - for Fire Hawk only.
 				// other mapper-#71 games are UxROM
 				if (mapper == 5'b00001)
 				begin
-					if (!USE_FIRE_HAWK | ~flags[0] | (cpu_addr_in[14:12] != 3'b001))
+					if (!USE_MAPPER_071 | ~flags[0] | (cpu_addr_in[14:12] != 3'b001))
 					begin
 						prg_bank_a[5:1] = cpu_data_in[4:0];
 					end else begin // CodeMasters, blah. Mirroring control used only by Fire Hawk
@@ -84,7 +316,7 @@
 				end
 				
 				// Mapper #78 - Holy Diver 
-				if (USE_MAPPER_78 && mapper == 5'b00011)
+				if (USE_MAPPER_078 && mapper == 5'b00011)
 				begin
 					prg_bank_a[3:1] = cpu_data_in[2:0];
 					chr_bank_a[6:3] = cpu_data_in[7:4];
@@ -92,7 +324,7 @@
 				end
 
 				// Mapper #97 - Irem's TAM-S1
-				if (USE_IREM_TAMS1 && mapper == 5'b00100)
+				if (USE_MAPPER_097 && mapper == 5'b00100)
 				begin
 					prg_bank_a[4:1] = cpu_data_in[3:0];
 					mirroring = cpu_data_in[7:6] ^ {~cpu_data_in[6], 1'b0};
@@ -104,6 +336,51 @@
 					prg_bank_a[3:1] = {cpu_data_in[6:4]};
 					chr_write_enabled = cpu_data_in[0];
 				end
+				
+				// Mapper #18 - Sunsoft-2
+				if (USE_MAPPER_018 && mapper == 5'b00111)
+				begin
+					case ({cpu_addr_in[14:12], cpu_addr_in[1:0]})
+						5'b00000: prg_bank_a[3:0] = cpu_data_in[3:0]; // $8000
+						5'b00001: prg_bank_a[7:4] = cpu_data_in[3:0]; // $8001
+						5'b00010: prg_bank_b[3:0] = cpu_data_in[3:0]; // $8002
+						5'b00011: prg_bank_b[7:4] = cpu_data_in[3:0]; // $8003
+						5'b00100: prg_bank_c[3:0] = cpu_data_in[3:0]; // $9000
+						5'b00101: prg_bank_c[7:4] = cpu_data_in[3:0]; // $9001
+						5'b00110: ; // $9002
+						5'b00111: ; // $9003
+						5'b01000: chr_bank_a[3:0] = cpu_data_in[3:0]; // $A000
+						5'b01001: chr_bank_a[7:4] = cpu_data_in[3:0]; // $A001
+						5'b01010: chr_bank_b[3:0] = cpu_data_in[3:0]; // $A002
+						5'b01011: chr_bank_b[7:4] = cpu_data_in[3:0]; // $A003
+						5'b01100: chr_bank_c[3:0] = cpu_data_in[3:0]; // $B000
+						5'b01101: chr_bank_c[7:4] = cpu_data_in[3:0]; // $B001
+						5'b01110: chr_bank_d[3:0] = cpu_data_in[3:0]; // $B002
+						5'b01111: chr_bank_d[7:4] = cpu_data_in[3:0]; // $B003
+						5'b10000: chr_bank_e[3:0] = cpu_data_in[3:0]; // $C000
+						5'b10001: chr_bank_e[7:4] = cpu_data_in[3:0]; // $C001
+						5'b10010: chr_bank_f[3:0] = cpu_data_in[3:0]; // $C002
+						5'b10011: chr_bank_f[7:4] = cpu_data_in[3:0]; // $C003
+						5'b10100: chr_bank_g[3:0] = cpu_data_in[3:0]; // $D000
+						5'b10101: chr_bank_g[7:4] = cpu_data_in[3:0]; // $D001
+						5'b10110: chr_bank_h[3:0] = cpu_data_in[3:0]; // $D002
+						5'b10111: chr_bank_h[7:4] = cpu_data_in[3:0]; // $D003
+						5'b11000: irq_cpu_latch[3:0] = cpu_data_in[3:0]; // $E000
+						5'b11001: irq_cpu_latch[7:4] = cpu_data_in[3:0]; // $E001
+						5'b11010: irq_cpu_latch[11:8] = cpu_data_in[3:0]; // $E002
+						5'b11011: irq_cpu_latch[15:12] = cpu_data_in[3:0]; // $E003
+						5'b11100: begin // $F000
+								irq_cpu_value[15:0] = irq_cpu_latch[15:0];
+								irq_cpu_out = 0;
+							end
+						5'b11101: begin // $F001
+								irq_cpu_control[3:0] = cpu_data_in[3:0];
+								irq_cpu_out = 0;
+							end
+						5'b11110: mirroring = cpu_data_in[1:0] ^ {1'b0, ~cpu_data_in[1]}; // $F002
+						5'b11111: ; // $F003 - sound
+					endcase
+				end
 
 				// Mapper #7 - AxROM
 				if (mapper == 5'b01000)
@@ -113,7 +390,7 @@
 				end
 				
 				// Mapper #228 - Cheetahmen II				
-				if (USE_CHEETAHMEN2 && mapper == 5'b01001)
+				if (USE_MAPPER_228 && mapper == 5'b01001)
 				begin
 					prg_bank_a[5:2] = cpu_addr_in[10:7];
 					chr_bank_a[7:3] = {/*cpu_addr_in[3]*/cpu_addr_in[2:0], cpu_data_in[1:0]}; // only 256k, sorry
@@ -121,19 +398,66 @@
 				end
 				
 				// Mapper #11 - ColorDreams
-				if (USE_COLOR_DREAMS && mapper == 5'b01010)
+				if (USE_MAPPER_011 && mapper == 5'b01010)
 				begin
 					prg_bank_a[3:2] = cpu_data_in[1:0];
 					chr_bank_a[6:3] = cpu_data_in[7:4];
 				end
 				
 				// Mapper #66 - GxROM
-				if (USE_GxROM && mapper == 5'b01011)
+				if (USE_MAPPER_066 && mapper == 5'b01011)
 				begin
 					prg_bank_a[3:2] = cpu_data_in[5:4];
 					chr_bank_a[4:3] = cpu_data_in[1:0];					
 				end
 				
+				// Mapper #90 - JY
+				if (USE_MAPPER_090 && mapper == 5'b01101)
+				begin
+					if (cpu_addr_in[14:12] == 3'b000) // $800x
+					begin
+						case (cpu_addr_in[1:0])
+							2'b00: prg_bank_a = cpu_data_in;
+							2'b01: prg_bank_b = cpu_data_in;
+							2'b10: prg_bank_c = cpu_data_in;
+							2'b11: prg_bank_d = cpu_data_in;
+						endcase
+					end
+					if (cpu_addr_in[14:12] == 3'b001) // $900x
+					begin
+						case (cpu_addr_in[2:0])
+							3'b000: chr_bank_a = cpu_data_in;
+							3'b001: chr_bank_b = cpu_data_in;
+							3'b010: chr_bank_c = cpu_data_in;
+							3'b011: chr_bank_d = cpu_data_in;
+							3'b100: chr_bank_e = cpu_data_in;
+							3'b101: chr_bank_f = cpu_data_in;
+							3'b110: chr_bank_g = cpu_data_in;
+							3'b111: chr_bank_h = cpu_data_in;
+						endcase
+					end
+					if ({cpu_addr_in[14:12], cpu_addr_in[1:0]} == 5'b10101) // $D001
+						mirroring = cpu_data_in[1:0];
+					/*
+					if (USE_MAPPER_090_INTERRUPTS && cpu_addr_in[14:12] == 3'b100) // $C00x
+					begin
+						case (cpu_addr_in[2:0])
+							3'b000: irq_scanline_enabled = cpu_data_in[0];
+							3'b001: ;
+							3'b010: irq_scanline_enabled = 0;
+							3'b011: irq_scanline_enabled = 1;
+							3'b100: ;
+							3'b101: begin
+									irq_scanline_latch = cpu_data_in ^ r0;
+									irq_scanline_reload = 1;
+								end
+							3'b110: r0 = cpu_data_in;
+							3'b111: ;								
+						endcase
+					end
+					*/
+				end
+				
 				// Mapper #1 - MMC1
 				/*
 				r0 - load register
@@ -194,10 +518,10 @@
 				
 				// Mapper #9 and #10 - MMC2 and MMC4
 				// flag0 - 0=MMC2, 1=MMC4
-				if ((USE_MMC2 | USE_MMC4) && mapper[4:0] == 5'b10001)
+				if ((USE_MAPPER_009_010 | USE_MAPPER_009_010) && mapper[4:0] == 5'b10001)
 				begin
 					case (cpu_addr_in[14:12])
-						3'b010: if ((USE_MMC2 & ~flags[0]) | !USE_MMC4) // $A000-$AFFF
+						3'b010: if (~flags[0]) // $A000-$AFFF
 										prg_bank_a[3:0] = cpu_data_in[3:0];
 									else
 										prg_bank_a[4:1] = cpu_data_in[3:0];
@@ -254,7 +578,7 @@
 
 				// Mappers #33 + #48 - Taito
 				// flag0=0 - #33, flag0=1 - #48
-				if (USE_TAITO && (mapper[4:0] == 5'b10110))
+				if (USE_MAPPER_033_048 && (mapper[4:0] == 5'b10110))
 				begin
 					case ({cpu_addr_in[14:13], cpu_addr_in[1:0]})
 						4'b0000: begin
@@ -269,9 +593,9 @@
 						4'b0101: chr_bank_f = cpu_data_in; // $A001, CHR Reg 2 (1k @ $1400)
 						4'b0110: chr_bank_g = cpu_data_in; // $A002, CHR Reg 2 (1k @ $1800)
 						4'b0111: chr_bank_h = cpu_data_in; // $A003, CHR Reg 2 (1k @ $1C00)
-						4'b1100: if (flags[0]) mirroring = cpu_data_in[6];	// $E000, mirroring, for mapper #48
+						4'b1100: if (flags[0]) mirroring = {1'b0, cpu_data_in[6]};	// $E000, mirroring, for mapper #48
 					endcase
-					if (USE_TAITO_INTERRUPTS)
+					if (USE_MAPPER_048_INTERRUPTS)
 					begin
 						case ({cpu_addr_in[14:13], cpu_addr_in[1:0]})
 							4'b1000: irq_scanline_latch = ~cpu_data_in; // $C000, IRQ latch
@@ -287,7 +611,7 @@
 				flag0 - switches A0 and A1 lines. 0=A0,A1 like VRC2b (mapper #23), 1=A1,A0 like VRC2a(#22), VRC2c(#25)
 				flag1 - divides CHR bank select by two (mapper #22, VRC2a)
 				*/
-				if (USE_VRC2 && mapper == 5'b11000)
+				if (USE_MAPPER_021_022_023_025 && mapper == 5'b11000)
 				begin
 					case ({cpu_addr_in[14:12], flags[0] ? vrc_2b_low : vrc_2b_hi, flags[0] ? vrc_2b_hi : vrc_2b_low})
 						5'b00000,
@@ -295,7 +619,7 @@
 						5'b00010,
 						5'b00011: prg_bank_a[4:0] = cpu_data_in[4:0];  // $8000-$8003, PRG0
 						5'b00100,
-						5'b00101: mirroring = {1'b0, cpu_data_in[0]};  // $9000-$9001, mirroring
+						5'b00101: if (cpu_data_in != 8'b11111111) mirroring = cpu_data_in[1:0]; // $9000-$9001, mirroring
 						5'b00110,
 						5'b00111: prg_mode[0] = cpu_data_in[1]; // $9002-$9004, PRG swap
 						5'b01000,
@@ -304,7 +628,7 @@
 						5'b01011: prg_bank_b[4:0] = cpu_data_in[4:0];  // $A000-$A003, PRG1
 					endcase
 					// flags[0] to shift lines
-					if (!USE_VRC2a | ~flags[1])
+					if (!USE_MAPPER_022 | ~flags[1])
 					begin
 						case ({cpu_addr_in[14:12], flags[0] ? vrc_2b_low : vrc_2b_hi, flags[0] ? vrc_2b_hi : vrc_2b_low})
 							5'b01100: chr_bank_a[3:0] = cpu_data_in[3:0];  // $B000, CHR0 low
@@ -351,15 +675,15 @@
 						if (cpu_addr_in[14:12] == 3'b111)
 						begin
 							case ({flags[0] ? vrc_2b_low : vrc_2b_hi, flags[0] ? vrc_2b_hi : vrc_2b_low}) 
-								2'b00: vrc4_irq_latch[3:0] = cpu_data_in[3:0];  // IRQ latch low
-								2'b01: vrc4_irq_latch[7:4] = cpu_data_in[3:0];  // IRQ latch hi
+								2'b00: irq_cpu_latch[3:0] = cpu_data_in[3:0];  // IRQ latch low
+								2'b01: irq_cpu_latch[7:4] = cpu_data_in[3:0];  // IRQ latch hi
 								2'b10: begin // IRQ control
 									irq_cpu_out = 0; // ack
 									irq_cpu_control[2:0] = cpu_data_in[2:0]; // mode, enabled, enabled after ack
 									if (irq_cpu_control[1]) begin // if E is set
 										vrc4_irq_prescaler_counter = 2'b00; // reset prescaler
 										vrc4_irq_prescaler = 0;
-										irq_cpu_value[7:0] = vrc4_irq_latch; // reload with latch
+										irq_cpu_value[7:0] = irq_cpu_latch[7:0]; // reload with latch
 									end
 								end
 								2'b11: begin // IRQ ack
@@ -375,7 +699,7 @@
 				/*
 				r0 - command register
 				*/				
-				if (USE_SUNSOFT && mapper == 5'b11001)
+				if (USE_MAPPER_069 && mapper == 5'b11001)
 				begin
 					if (cpu_addr_in[14:13] == 2'b00) r0[3:0] = cpu_data_in[3:0];
 					if (cpu_addr_in[14:13] == 2'b01)
@@ -389,7 +713,7 @@
 							4'b0101: chr_bank_f = cpu_data_in; // CHR5
 							4'b0110: chr_bank_g = cpu_data_in; // CHR6
 							4'b0111: chr_bank_h = cpu_data_in; // CHR7
-							4'b1000: {sram_enabled, map_rom_on_6000, prg_bank_6000} = {cpu_data_in[7], ~cpu_data_in[6], cpu_data_in[5:0]}; // PRG0
+							4'b1000: {sram_enabled, map_rom_on_6000, prg_bank_6000[5:0]} = {cpu_data_in[7], ~cpu_data_in[6], cpu_data_in[5:0]}; // PRG0
 							4'b1001: prg_bank_a[5:0] = cpu_data_in[5:0]; // PRG1
 							4'b1010: prg_bank_b[5:0] = cpu_data_in[5:0]; // PRG2
 							4'b1011: prg_bank_c[5:0] = cpu_data_in[5:0]; // PRG3
@@ -405,7 +729,7 @@
 				end
 				
 				// Mapper #32 - IREM G-101
-				if (USE_IREM_G101 && mapper == 5'b11010)
+				if (USE_MAPPER_032 && mapper == 5'b11010)
 				begin
 					case (cpu_addr_in[13:12])
 						2'b00: prg_bank_a[5:0] = cpu_data_in[5:0]; // PRG0
@@ -433,16 +757,16 @@
 			irq_scanline_reload = 0;
 		
 		// IRQ for VRC4
-		if (USE_VRC2 & USE_VRC4_INTERRUPTS & (mapper == 5'b11000) & (irq_cpu_control[1]))
+		if (USE_MAPPER_021_022_023_025 & USE_VRC4_INTERRUPTS & (mapper == 5'b11000) & (irq_cpu_control[1]))
 		begin
 			// Cycle mode without prescaler is not used by any games? It's missed in fceux source code.
 			if (irq_cpu_control[2]) // cycle mode
 			begin
-				irq_cpu_value[7:0] = (irq_cpu_value[7:0] + 1'b1); // just count IRQ value
+				irq_cpu_value[7:0] = irq_cpu_value[7:0] + 1'b1; // just count IRQ value
 				if (irq_cpu_value[7:0] == 0)
 				begin
 					irq_cpu_out = 1;
-					irq_cpu_value[7:0] = vrc4_irq_latch;
+					irq_cpu_value[7:0] = irq_cpu_latch[7:0];
 				end
 			end else begin // scanline mode
 				vrc4_irq_prescaler = vrc4_irq_prescaler + 1'b1; // count prescaler
@@ -455,19 +779,41 @@
 					if (irq_cpu_value[7:0] == 0)
 					begin
 						irq_cpu_out = 1;
-						irq_cpu_value[7:0] = vrc4_irq_latch;
+						irq_cpu_value[7:0] = irq_cpu_latch[7:0];
 					end
 				end
 			end
 		end
 
 		// IRQ for Sunsoft FME-7
-		if (USE_SUNSOFT & (mapper == 5'b11001) & (irq_cpu_control[1]))
+		if (USE_MAPPER_069 & (mapper == 5'b11001) & (irq_cpu_control[1]))
 		begin
 			if ((irq_cpu_value[15:0] == 0) & irq_cpu_control[0]) irq_cpu_out = 1;
 			irq_cpu_value[15:0] = irq_cpu_value[15:0] - 1'b1;
 		end
 		
+		// Mapper #18 - Sunsoft-2
+		if (USE_MAPPER_018 && mapper == 5'b00111)
+		begin
+			if (irq_cpu_control[0])
+			begin
+				if (irq_cpu_control[3])
+				begin
+					if (irq_cpu_value[3:0] == 0) irq_cpu_out = 1;
+					irq_cpu_value[3:0] = irq_cpu_value[3:0] - 1'b1;
+				end else if (irq_cpu_control[2]) begin
+					if (irq_cpu_value[7:0] == 0) irq_cpu_out = 1;
+					irq_cpu_value[7:0] = irq_cpu_value[7:0] - 1'b1;
+				end else if (irq_cpu_control[1]) begin
+					if (irq_cpu_value[11:0] == 0) irq_cpu_out = 1;
+					irq_cpu_value[11:0] = irq_cpu_value[11:0] - 1'b1;
+				end else begin
+					if (irq_cpu_value[15:0] == 0) irq_cpu_out = 1;
+					irq_cpu_value[15:0] = irq_cpu_value[15:0] - 1'b1;
+				end
+			end
+		end
+
 		/*
 		if (~romsel_alt)
 			romsel_alt_clean = 1;
@@ -492,7 +838,7 @@
 	
 	// IRQ counter
 	always @ (posedge ppu_addr_in[12])
-	begin
+	begin	
 		if (a12_low_time == 3)
 		begin
 			if ((irq_scanline_reload && !irq_scanline_reload_clear) || (irq_scanline_counter == 0))
@@ -507,6 +853,24 @@
 				irq_scanline_value = 0;
 		end
 		if (!irq_scanline_reload) irq_scanline_reload_clear = 0;		
+
+		// Scanline counter for mapper #163
+		if (USE_MAPPER_163)
+		begin
+			if (new_screen & ~new_screen_clear)
+			begin
+				scanline = 0;			
+				new_screen_clear = 1;
+			end else if (a12_low_time >= 3)
+			begin
+				if (~new_screen && new_screen_clear) new_screen_clear = 0;
+				scanline = scanline + 1'b1;
+				if (scanline == 240)
+					ppu_mapper_163_latch = 0;
+				if (scanline == 128)
+					ppu_mapper_163_latch = 1;
+			end
+		end
 	end
 	
 	// A12 must be low for 3 rises of M2
@@ -518,10 +882,23 @@
 			a12_low_time = a12_low_time + 1'b1;
 	end
 	
+	// V-blank detector	
+	always @ (negedge m2, negedge ppu_rd_in)
+	begin
+		if (~ppu_rd_in)
+		begin
+			ppu_rd_hi_time = 0;
+			if (new_screen_clear) new_screen = 0;
+		end else if (ppu_rd_hi_time < 9'b111111111)
+		begin
+			ppu_rd_hi_time = ppu_rd_hi_time + 1'b1;
+		end else new_screen = 1;
+	end
+
 	// for MMC2/MMC4
 	always @ (negedge ppu_rd_in)
 	begin
-		if (USE_MMC2 | USE_MMC4)
+		if (USE_MAPPER_009_010)
 		begin
 			if (ppu_addr_in[13:3] == 11'b00111111011) ppu_latch0 = 0;
 			if (ppu_addr_in[13:3] == 11'b00111111101) ppu_latch0 = 1;
@@ -529,3 +906,5 @@
 			if (ppu_addr_in[13:3] == 11'b01111111101) ppu_latch1 = 1;
 		end
 	end
+
+	
\ No newline at end of file