Reorganised the location of Ethernet files in Hardware folders

15 files changed, 637 insertions, 26 deletions

diff --git a/.cproject b/.cproject
index 22f6757a..ee7d703b 100644
--- a/.cproject
+++ b/.cproject
@@ -123,7 +123,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/Hardware/ksz8081rna|src/Hardware/SAME70|src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME5x|src/Networking/LwipEthernet/|src/DuetNG|src/Networking/W5500Ethernet/|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Display|src/Networking/ESP8266WiFi/|src/Pccb|src/DuetM" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME70|src/Hardware/SAME5x|src/Networking/LwipEthernet/|src/DuetNG|src/Networking/W5500Ethernet/|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Display|src/Hardware/ksz8081rna|src/Networking/ESP8266WiFi/|src/Pccb|src/DuetM" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -281,7 +281,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/Hardware/ksz8081rna|src/Hardware/SAME70|src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME5x|src/Networking/LwipEthernet|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Pccb|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME70|src/Hardware/SAME5x|src/Networking/LwipEthernet|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Hardware/ksz8081rna|src/Pccb|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -438,7 +438,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/Hardware/ksz8081rna|src/Hardware/SAME70|src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME5x|src/Networking/LwipEthernet|src/DuetNG|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Networking/ESP8266WiFi|src/Pccb|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME70|src/Hardware/SAME5x|src/Networking/LwipEthernet|src/DuetNG|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Hardware/ksz8081rna|src/Networking/ESP8266WiFi|src/Pccb|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -596,7 +596,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/Hardware/ksz8081rna|src/Hardware/SAME70|src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME5x|src/Networking/LwipEthernet|src/DuetNG|src/Networking/W5500Ethernet/|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Display|src/Networking/ESP8266WiFi|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME70|src/Hardware/SAME5x|src/Networking/LwipEthernet|src/DuetNG|src/Networking/W5500Ethernet/|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Display|src/Hardware/ksz8081rna|src/Networking/ESP8266WiFi|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -1288,7 +1288,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/Hardware/ksz8081rna|src/Hardware/SAME70|src/atmel|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME5x|src/Networking/LwipEthernet|src/Networking/W5500Ethernet/|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Networking/ESP8266WiFi/|src/Pccb|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/atmel|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/Hardware/SAME70|src/Hardware/SAME5x|src/Networking/LwipEthernet|src/Networking/W5500Ethernet/|src/Alligator|src/arm|src/Duet5LC|src/Duet3_V06|src/Hardware/ksz8081rna|src/Networking/ESP8266WiFi/|src/Pccb|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -1440,7 +1440,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/Hardware/SAME70|src/Networking/LwipEthernet/Lwip/doc|src/Networking/LwipEthernet/Lwip/src/apps/tftp|src/Networking/LwipEthernet/Lwip/src/apps/sntp|src/Networking/LwipEthernet/Lwip/src/apps/snmp|src/Networking/LwipEthernet/Lwip/src/apps/smtp|src/Networking/LwipEthernet/Lwip/src/apps/mqtt|src/Networking/LwipEthernet/Lwip/src/apps/lwiperf|src/Networking/LwipEthernet/Lwip/src/apps/http|src/Networking/LwipEthernet/Lwip/src/apps/altcp_tls|src/Networking/LwipEthernet/Lwip/src/netif/ppp|src/Networking/W5500Ethernet|src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/DuetNG|src/Alligator|src/arm|src/Duet3_V06|src/Networking/ESP8266WiFi|src/Pccb|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V03|src/Duet|src/Hardware/SAME70|src/DuetNG|src/Networking/W5500Ethernet|src/Alligator|src/Pccb|src/Networking/LwipEthernet/Lwip/src/apps/mqtt|src/Networking/LwipEthernet/Lwip/doc|src/Networking/LwipEthernet/Lwip/src/apps/snmp|src/Networking/LwipEthernet/Lwip/src/apps/smtp|src/Duet3_V05|src/Networking/LwipEthernet/Lwip/src/apps/tftp|src/Networking/LwipEthernet/Lwip/src/netif/ppp|src/Networking/LwipEthernet/Lwip/src/apps/lwiperf|src/Networking/LwipEthernet/Lwip/src/apps/altcp_tls|src/arm|src/Networking/LwipEthernet/Lwip/src/apps/sntp|src/Networking/LwipEthernet/Lwip/src/apps/http|src/Duet3_V06|src/Networking/ESP8266WiFi|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -1587,7 +1587,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/Hardware/SAME70|src/Networking/LwipEthernet/Lwip/doc|src/Networking/LwipEthernet/Lwip/src/apps/tftp|src/Networking/LwipEthernet/Lwip/src/apps/sntp|src/Networking/LwipEthernet/Lwip/src/apps/snmp|src/Networking/LwipEthernet/Lwip/src/apps/smtp|src/Networking/LwipEthernet/Lwip/src/apps/mqtt|src/Networking/LwipEthernet/Lwip/src/apps/lwiperf|src/Networking/LwipEthernet/Lwip/src/apps/http|src/Networking/LwipEthernet/Lwip/src/apps/altcp_tls|src/Networking/LwipEthernet/Lwip/src/netif/ppp|src/Networking/W5500Ethernet|src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V05|src/Duet3_V03|src/Duet|src/DuetNG|src/Alligator|src/arm|src/Duet3_V06|src/Networking/ESP8266WiFi|src/Pccb|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/atmel|src/Linux|src/SAME70xpld|src/Duet3_V03|src/Duet|src/Hardware/SAME70|src/DuetNG|src/Networking/W5500Ethernet|src/Alligator|src/Pccb|src/Networking/LwipEthernet/Lwip/src/apps/mqtt|src/Networking/LwipEthernet/Lwip/doc|src/Networking/LwipEthernet/Lwip/src/apps/snmp|src/Networking/LwipEthernet/Lwip/src/apps/smtp|src/Duet3_V05|src/Networking/LwipEthernet/Lwip/src/apps/tftp|src/Networking/LwipEthernet/Lwip/src/netif/ppp|src/Networking/LwipEthernet/Lwip/src/apps/lwiperf|src/Networking/LwipEthernet/Lwip/src/apps/altcp_tls|src/arm|src/Networking/LwipEthernet/Lwip/src/apps/sntp|src/Networking/LwipEthernet/Lwip/src/apps/http|src/Duet3_V06|src/Networking/ESP8266WiFi|src/DuetM|src/RADDS" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
diff --git a/src/DuetM/Pins_DuetM.h b/src/DuetM/Pins_DuetM.h
index bed16211..b7d2141d 100644
--- a/src/DuetM/Pins_DuetM.h
+++ b/src/DuetM/Pins_DuetM.h
@@ -124,7 +124,7 @@ constexpr uint8_t TMC22xx_UART_PINS = APINS_UART0;
 // To write a register we need to send 8 bytes. To read a register we send 4 bytes and receive 8 bytes after a programmable delay.
 // So at 500kbaud it takes about 128us to write a register, and 192us+ to read a register.
 // In testing I found that 500kbaud was not reliable, so now using 250kbaud.
-constexpr uint32_t DriversBaudRate = 2500000;
+constexpr uint32_t DriversBaudRate = 250000;
 constexpr uint32_t TransferTimeout = 2;				// any transfer should complete within 2 ticks @ 1ms/tick
 constexpr uint32_t DefaultStandstillCurrentPercent = 75;
 
diff --git a/src/Hardware/SAME5x/Ethernet/Phy/ethernet_phy.c b/src/Hardware/SAME5x/Ethernet/Phy/ethernet_phy.c
new file mode 100644
index 00000000..9dba7dc4
--- /dev/null
+++ b/src/Hardware/SAME5x/Ethernet/Phy/ethernet_phy.c
@@ -0,0 +1,184 @@
+/**
+ * \file
+ *
+ * \brief Ethernet PHY functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "ethernet_phy.h"
+#include <utils_assert.h>
+/**
+ * \brief Perform a HW initialization to the PHY
+ */
+int32_t ethernet_phy_init(struct ethernet_phy_descriptor *const descr, struct mac_async_descriptor *const mac,
+                          uint16_t addr)
+{
+	ASSERT(descr && mac && (addr <= 0x1F));
+
+	descr->mac  = mac;
+	descr->addr = addr;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set PHY address
+ */
+int32_t ethernet_phy_set_address(struct ethernet_phy_descriptor *const descr, uint16_t addr)
+{
+	ASSERT(descr && (addr <= 0x1F));
+
+	descr->addr = addr;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Read PHY Register value.
+ */
+int32_t ethernet_phy_read_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t *val)
+{
+	ASSERT(descr && descr->mac && (reg <= 0x1F) && val);
+
+	return mac_async_read_phy_reg(descr->mac, descr->addr, reg, val);
+}
+
+/**
+ * \brief Write PHY Register value.
+ */
+int32_t ethernet_phy_write_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t val)
+{
+	ASSERT(descr && descr->mac && (reg <= 0x1F));
+	return mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
+}
+
+/**
+ * \brief Setting bit for a PHY Register
+ */
+int32_t ethernet_phy_set_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst)
+{
+	int32_t  rst;
+	uint16_t val;
+
+	ASSERT(descr && descr->mac && (reg <= 0x1F));
+
+	rst = mac_async_read_phy_reg(descr->mac, descr->addr, reg, &val);
+	if (rst == ERR_NONE) {
+		val |= ofst;
+		rst = mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
+	}
+	return rst;
+}
+/**
+ * \brief Clear bit for a PHY Register
+ */
+int32_t ethernet_phy_clear_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst)
+{
+	int32_t  rst;
+	uint16_t val;
+
+	ASSERT(descr && (reg <= 0x1F));
+
+	rst = mac_async_read_phy_reg(descr->mac, descr->addr, reg, &val);
+	if (rst == ERR_NONE) {
+		val &= ~ofst;
+		rst = mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
+	}
+	return rst;
+}
+/**
+ * \brief Set PHY low-power consumption state.
+ */
+int32_t ethernet_phy_set_powerdown(struct ethernet_phy_descriptor *const descr, bool state)
+{
+	ASSERT(descr);
+	if (state) {
+		return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_POWER_DOWN);
+	} else {
+		return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_POWER_DOWN);
+	}
+}
+
+/**
+ * \brief Set PHY electrically isolate state.
+ */
+int32_t ethernet_phy_set_isolate(struct ethernet_phy_descriptor *const descr, bool state)
+{
+	ASSERT(descr);
+	if (state) {
+		return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_ISOLATE);
+	} else {
+		return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_ISOLATE);
+	}
+}
+
+/**
+ * \brief Restart an auto negotiation of the PHY.
+ */
+int32_t ethernet_phy_restart_autoneg(struct ethernet_phy_descriptor *const descr)
+{
+	ASSERT(descr);
+	return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_RESTART_AUTONEG);
+}
+
+/**
+ * \brief Set PHY placed in a loopback mode of operation.
+ */
+int32_t ethernet_phy_set_loopback(struct ethernet_phy_descriptor *const descr, bool state)
+{
+	ASSERT(descr);
+	if (state) {
+		return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_LOOPBACK);
+	} else {
+		return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_LOOPBACK);
+	}
+}
+
+/**
+ * \brief Get PHY link status
+ */
+int32_t ethernet_phy_get_link_status(struct ethernet_phy_descriptor *const descr, bool *status)
+{
+	int32_t  rst;
+	uint16_t val;
+
+	ASSERT(descr && descr->mac && status);
+	rst = mac_async_read_phy_reg(descr->mac, descr->addr, MDIO_REG1_BMSR, &val);
+	if (rst == ERR_NONE) {
+		*status = (val & MDIO_REG1_BIT_LINK_STATUS) ? true : false;
+	}
+	return rst;
+}
+
+/**
+ * \brief Reset PHY.
+ */
+int32_t ethernet_phy_reset(struct ethernet_phy_descriptor *const descr)
+{
+	ASSERT(descr);
+	return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_RESET);
+}
diff --git a/src/Hardware/SAME5x/Ethernet/Phy/ethernet_phy.h b/src/Hardware/SAME5x/Ethernet/Phy/ethernet_phy.h
new file mode 100644
index 00000000..65ad5afe
--- /dev/null
+++ b/src/Hardware/SAME5x/Ethernet/Phy/ethernet_phy.h
@@ -0,0 +1,230 @@
+/**
+ * \file
+ *
+ * \brief Ethernet PHY functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ETHERNET_PHY_H_INCLUDED
+#define ETHERNET_PHY_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "compiler.h"
+#include "hal_mac_async.h"
+#include "ieee8023_mii_standard_register.h"
+
+struct ethernet_phy_descriptor {
+	struct mac_async_descriptor *mac;  /* MAC descriptor handler */
+	uint16_t                     addr; /* PHY address, defined by IEEE802.3
+	                                      section 22.2.4.5.5 */
+};
+
+/**
+ * \brief Perform a HW initialization to the PHY
+ *
+ * This should be called only once to initialize the PHY pre-settings.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] mac   MAC descriptor, the descriptor should be initialized.
+ * \param[in] addr  Ethernet PHY 5 bits address.
+ *
+ * \return Operation result
+ * \retval ERR_NONE initializing successful.
+ */
+int32_t ethernet_phy_init(struct ethernet_phy_descriptor *const descr, struct mac_async_descriptor *const mac,
+                          uint16_t addr);
+
+/**
+ * \brief Set PHY address
+ *
+ * Set PHY management PHY address which defined by IEEE802.3 section 22.2.4.5.5
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] addr  PHY address
+ *
+ * \return Operation result
+ * \retval ERR_NONE Set address successful.
+ */
+int32_t ethernet_phy_set_address(struct ethernet_phy_descriptor *const descr, uint16_t addr);
+
+/**
+ * \brief Read PHY Register value.
+ *
+ * Read PHY Register value from PHY.
+ *
+ * \note For conformance with the 802.3 specification, MDC must not exceed
+ *       2.5 MHz (MDC is only active during MDIO read and write operations).
+ *       The function execution time depend on MDC frequency.
+ *
+ * \param[in]  descr Ethernet PHY descriptor.
+ * \param[in]  reg   Register address
+ * \param[out] val   Register value
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Read register successful.
+ */
+int32_t ethernet_phy_read_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t *val);
+
+/**
+ * \brief Write PHY Register value.
+ *
+ * Read PHY Register value from PHY.
+ *
+ * \note For conformance with the 802.3 specification, MDC must not exceed
+ *       2.5 MHz (MDC is only active during MDIO read and write operations).
+ *       The function execution time depend on MDC frequency.
+ *
+ * \param[in]  descr Ethernet PHY descriptor.
+ * \param[in]  reg   Register address
+ * \param[out] val   Register value
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Write register successful.
+ */
+int32_t ethernet_phy_write_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t val);
+
+/**
+ * \brief Setting bit for a PHY Register
+ *
+ * Bit setting for a PHY Register.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] reg   Register address.
+ * \param[in] ofst  Register bit mask.
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Set register bit successful.
+ */
+int32_t ethernet_phy_set_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst);
+
+/**
+ * \brief Clear bit for a PHY Register
+ *
+ * Clear bit for a PHY Register.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] reg   Register address.
+ * \param[in] ofst  Register bit mask.
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Clear register bit successful.
+ */
+int32_t ethernet_phy_clear_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst);
+
+/**
+ * \brief Set PHY low-power consumption state.
+ *
+ * The specific behavior of a PHY in the power-down state is implementation
+ * specific. While in the power-down state, the PHY shall respond to management
+ * transactions. During the transition to the power-down state and while in the
+ * power-down state, the PHY shall not generate spurious signals on the MII or
+ * GMII.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] state The state of the power-down mode.
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Power-Down has been config successful.
+ */
+int32_t ethernet_phy_set_powerdown(struct ethernet_phy_descriptor *const descr, bool state);
+
+/**
+ * \brief Set PHY electrically isolate state.
+ *
+ * When the PHY is isolated from the MII or RMII it shall not respond to the
+ * data bundle.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] state The state of the isolate mode.
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Isolate has been config successful.
+ */
+int32_t ethernet_phy_set_isolate(struct ethernet_phy_descriptor *const descr, bool state);
+
+/**
+ * \brief Restart an auto negotiation of the PHY.
+ *
+ * Restart Auto_Negotantion process
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ *
+ * \return Operation result
+ * \retval ERR_NONE Auto-Negotiation has been initiated.
+ */
+int32_t ethernet_phy_restart_autoneg(struct ethernet_phy_descriptor *const descr);
+
+/**
+ * \brief Set PHY placed in a loopback mode of operation.
+ *
+ * When in loopback mode, the PHY shall accept data from the MII/RMII transmit
+ * data path and return it to the MII/RMII receive data path.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] state State of the loopback mode.
+ *
+ * \return Operation result
+ * \retval ERR_NONE Loopback has been set successful.
+ */
+int32_t ethernet_phy_set_loopback(struct ethernet_phy_descriptor *const descr, bool state);
+
+/**
+ * \brief Get PHY link status
+ *
+ * Get PHY link status
+ *
+ * \param[in]  descr  Ethernet PHY descriptor.
+ * \param[out] status Pointer to the Link Status.
+ *
+ * \return ERR_NONE if successfully
+ */
+int32_t ethernet_phy_get_link_status(struct ethernet_phy_descriptor *const descr, bool *status);
+
+/**
+ * \brief Reset PHY.
+ *
+ * Resetting PHY, this action set all the status and control register to their
+ * default states. As a consequence this action may change the internal state
+ * of the PHY and the state of the physical link associated with the PHY. The
+ * reset process shall be completed within 0.5 second.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ *
+ * \return ERR_NONE if successfully
+ */
+int32_t ethernet_phy_reset(struct ethernet_phy_descriptor *const descr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef ETHERNET_PHY_H_INCLUDED */
diff --git a/src/Hardware/SAME5x/Ethernet/Phy/ieee8023_mii_standard_register.h b/src/Hardware/SAME5x/Ethernet/Phy/ieee8023_mii_standard_register.h
new file mode 100644
index 00000000..e36caddf
--- /dev/null
+++ b/src/Hardware/SAME5x/Ethernet/Phy/ieee8023_mii_standard_register.h
@@ -0,0 +1,137 @@
+/**
+ * \file
+ *
+ * \brief IEEE802.3 MII Management Standard Register Set
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ETHERNET_MII_REGISTER_H_INCLUDED
+#define ETHERNET_MII_REGISTER_H_INCLUDED
+
+/* IEEE 802.3 Clause22.2.4 defined Standard Registers.
+ * The MII basic register set consists of two registers referred to as the
+ * Control register (Register 0) and the Status register (Register 1). All
+ * PHYs that provide an MII shall incorporate the basic register set. All PHYs
+ * that provide a GMII shall incorporate an extended basic register set
+ * consisting of the Control register (Register 0), Status register
+ * (Register 1), and Extended Status register (Register 15). The status and
+ * control functions defined here are considered basic and fundamental to
+ * 100 Mb/s and 1000 Mb/s PHYs. Registers 2 through 14 are part of the
+ * extended register set. The format of Registers 4 through 10 are defined for
+ * the specific Auto-Negotiation protocol used (Clause 28 or Clause 37). The
+ * format of these registers is selected by the bit settings of Registers 1
+ * and 15.
+ **/
+#define MDIO_REG0_BMCR 0x00    /*  Basic Control */
+#define MDIO_REG1_BMSR 0x01    /*  Basic Status */
+#define MDIO_REG2_PHYID1 0x02  /*  PHY Idendifier 1 */
+#define MDIO_REG3_PHYID2 0x03  /*  PHY Idendifier 2 */
+#define MDIO_REG4_ANA 0x04     /*  Auto_Negotiation Advertisement */
+#define MDIO_REG5_ANLPA 0x05   /*  Auto_negotiation Link Partner Base Page Ability */
+#define MDIO_REG6_ANE 0x06     /*  Auto-negotiation Expansion */
+#define MDIO_REG7_ANNPT 0x07   /*  Auto-negotiation Next Page Transmit */
+#define MDIO_REG8_ANLPRNP 0x08 /*  Auto-Negotiation Link Partner Received Next Page */
+#define MDIO_REG9_MSC 0x09     /*  MASTER-SLAVE Control Register */
+#define MDIO_REG10_MSS 0x0A    /*  MASTER-SLAVE Status Register */
+#define MDIO_REG11_PSEC 0x0B   /*  PSE Control Register */
+#define MDIO_REG12_PSES 0x0C   /*  PSE Status Register */
+#define MDIO_REG13_MMDAC 0x0D  /*  MMD Access Control Register */
+#define MDIO_REG14_MMDAAD 0x0E /*  MMD Access Address Data Register */
+#define MDIO_REG15_EXTS 0x0F   /*  Extended Status */
+/* Register 16 to 31 are Reserved for Vendor Specific */
+
+/* Bit definitions: MDIO_REG0_BMCR 0x00 Basic Control */
+#define MDIO_REG0_BIT_RESET (1 << 15)            /*  1 = Software Reset; 0 = Normal Operation */
+#define MDIO_REG0_BIT_LOOPBACK (1 << 14)         /*  1 = loopback Enabled; 0 = Normal Operation */
+#define MDIO_REG0_BIT_SPEED_SELECT_LSB (1 << 13) /*  1 = 100Mbps; 0=10Mbps */
+#define MDIO_REG0_BIT_AUTONEG (1 << 12)          /*  1 = Auto-negotiation Enable */
+#define MDIO_REG0_BIT_POWER_DOWN (1 << 11)       /*  1 = Power down 0=Normal operation */
+#define MDIO_REG0_BIT_ISOLATE (1 << 10)          /*  1 = Isolates 0 = Normal operation */
+#define MDIO_REG0_BIT_RESTART_AUTONEG (1 << 9)   /*  1 = Restart auto-negotiation 0 = Normal operation */
+#define MDIO_REG0_BIT_DUPLEX_MODE (1 << 8)       /*  1 = Full duplex operation 0 = Normal operation */
+#define MDIO_REG0_BIT_COLLISION_TEST (1 << 7)    /*  1 = Enable COL test; 0 = Disable COL test */
+#define MDIO_REG0_BIT_SPEED_SELECT_MSB (1 << 6)  /*  1 with LSB0 = 1000Mbps */
+#define MDIO_REG0_BIT_UNIDIR_ENABLE (1 << 5)     /*  Unidirectional Enable */
+/* Reserved                     4 to 0       Read as 0, ignore on write */
+
+/* Bit definitions: MDIO_BMSR 0x01 Basic Status */
+#define MDIO_REG1_BIT_100BASE_T4 (1 << 15)     /*  100BASE-T4 Capable */
+#define MDIO_REG1_BIT_100BASE_TX_FD (1 << 14)  /*  100BASE-TX Full Duplex Capable */
+#define MDIO_REG1_BIT_100BASE_TX_HD (1 << 13)  /*  100BASE-TX Half Duplex Capable */
+#define MDIO_REG1_BIT_10BASE_T_FD (1 << 12)    /*  10BASE-T Full Duplex Capable */
+#define MDIO_REG1_BIT_10BASE_T_HD (1 << 11)    /*  10BASE-T Half Duplex Capable */
+#define MDIO_REG1_BIT_100BASE_T2_FD (1 << 10)  /*  1000BASE-T2 Full Duplex Capable */
+#define MDIO_REG1_BIT_100BASE_T2_HD (1 << 9)   /*  1000BASE-T2 Half Duplex Capable */
+#define MDIO_REG1_BIT_EXTEND_STATUS (1 << 8)   /*  1 = Extend Status Information In Reg 15 */
+#define MDIO_REG1_BIT_UNIDIR_ABILITY (1 << 7)  /*  Unidirectional ability */
+#define MDIO_REG1_BIT_MF_PREAMB_SUPPR (1 << 6) /*  MII Frame Preamble Suppression */
+#define MDIO_REG1_BIT_AUTONEG_COMP (1 << 5)    /*  Auto-negotiation Complete */
+#define MDIO_REG1_BIT_REMOTE_FAULT (1 << 4)    /*  Remote Fault */
+#define MDIO_REG1_BIT_AUTONEG_ABILITY (1 << 3) /*  Auto Configuration Ability */
+#define MDIO_REG1_BIT_LINK_STATUS (1 << 2)     /*  Link Status */
+#define MDIO_REG1_BIT_JABBER_DETECT (1 << 1)   /*  Jabber Detect */
+#define MDIO_REG1_BIT_EXTEND_CAPAB (1 << 0)    /*  Extended Capability */
+
+/*  Bit definitions: MDIO_PHYID1 0x02 PHY Idendifier 1 */
+/*  Bit definitions: MDIO_PHYID2 0x03 PHY Idendifier 2 */
+#define MDIO_LSB_MASK 0x3F
+#define MDIO_OUI_MSB 0x0022
+#define MDIO_OUI_LSB 0x1572
+
+/* Bit definitions: MDIO_REG4_ANA 0x04 Auto-Negotiation advertisement */
+#define MDIO_REG4_BIT_NEXTPAGE (15 << 0)     /* Next Page */
+#define MDIO_REG4_BIT_REMOTE_FAULT (13 << 0) /* Remote Fault */
+#define MDIO_REG4_BIT_EXT_NEXTPAGE (12 << 0) /* Extended Next Page */
+
+/*  Bit definitions: MDIO_ANAR   0x04 Auto_Negotiation Advertisement */
+/*  Bit definitions: MDIO_ANLPAR 0x05 Auto_negotiation Link Partner Ability */
+#define MDIO_NP (1 << 15)         /*  Next page Indication */
+#define MDIO_RF (1 << 13)         /*  Remote Fault */
+#define MDIO_PAUSE_MASK (3 << 10) /*  0,0 = No Pause 1,0 = Asymmetric Pause(link partner) */
+                                  /*  0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) */
+#define MDIO_100T4 (1 << 9)       /*  100BASE-T4 Support */
+#define MDIO_100TX_FDX (1 << 8)   /*  100BASE-TX Full Duplex Support */
+#define MDIO_100TX_HDX (1 << 7)   /*  100BASE-TX Half Duplex Support */
+#define MDIO_10_FDX (1 << 6)      /*  10BASE-T Full Duplex Support */
+#define MDIO_10_HDX (1 << 5)      /*  10BASE-T Half Duplex Support */
+#define MDIO_AN_IEEE_802_3 0x0001 /*  [00001] = IEEE 802.3 */
+
+/* Bit definitions: MDIO_ANER 0x06 Auto-negotiation Expansion */
+#define MDIO_PDF (1 << 4)        /*  Local Device Parallel Detection Fault */
+#define MDIO_LP_NP_ABLE (1 << 3) /*  Link Partner Next Page Able */
+#define MDIO_NP_ABLE (1 << 2)    /*  Local Device Next Page Able */
+#define MDIO_PAGE_RX (1 << 1)    /*  New Page Received */
+#define MDIO_LP_AN_ABLE (1 << 0) /*  Link Partner Auto-negotiation Able */
+
+/* Bit definitions: MDIO_PCR1 0x1E PHY Control 1 */
+#define MDIO_OMI_10BASE_T_HD 0x0001
+#define MDIO_OMI_100BASE_TX_HD 0x0002
+#define MDIO_OMI_10BASE_T_FD 0x0005
+
+#endif /* #ifndef ETHERNET_MII_REGISTER_H_INCLUDED */
diff --git a/src/Hardware/SAME5x/Ethernet/SAME5x_gmac.cpp b/src/Hardware/SAME5x/Ethernet/gmac.cpp
index f3a0c60a..07c7f1a6 100644
--- a/src/Hardware/SAME5x/Ethernet/SAME5x_gmac.cpp
+++ b/src/Hardware/SAME5x/Ethernet/gmac.cpp
@@ -1,5 +1,5 @@
 /*
- * SAME5x_gmac.cpp
+ * gmac.cpp
  *
  *  Created on: 19 Jun 2020
  *      Author: David
@@ -8,6 +8,7 @@
 //TODO
 
 #include <Core.h>
+#include "gmac.h"
 
 extern "C" {
 #include "lwip/opt.h"
diff --git a/src/Hardware/SAME5x/Ethernet/gmac.h b/src/Hardware/SAME5x/Ethernet/gmac.h
new file mode 100644
index 00000000..8d69a4e1
--- /dev/null
+++ b/src/Hardware/SAME5x/Ethernet/gmac.h
@@ -0,0 +1,48 @@
+/*
+ * SAME5x_gmac.h
+ *
+ *  Created on: 19 Jun 2020
+ *      Author: David
+ */
+
+#ifndef SRC_HARDWARE_SAME5X_ETHERNET_GMAC_H_
+#define SRC_HARDWARE_SAME5X_ETHERNET_GMAC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/err.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+
+#ifdef __cplusplus
+}
+
+err_t ethernetif_init(struct netif *netif) noexcept;		// called by LwIP to initialise the interface
+
+void ethernetif_terminate() noexcept;						// called when we shut down
+
+bool ethernetif_input(struct netif *netif) noexcept;		// checks for a new packet and returns true if one was processed
+
+void ethernetif_hardware_init() noexcept;					// initialises the low-level hardware interface
+
+bool ethernetif_establish_link() noexcept;					// attempts to establish link and returns true on success
+
+bool ethernetif_link_established() noexcept;				// asks the PHY if the link is still up
+
+void ethernetif_set_mac_address(const uint8_t macAddress[]) noexcept;
+
+#endif
+
+// Error counters
+extern unsigned int rxErrorCount;
+extern unsigned int rxBuffersNotFullyPopulatedCount;
+extern unsigned int txErrorCount;
+extern unsigned int txBufferNotFreeCount;
+extern unsigned int txBufferTooShortCount;
+
+
+
+#endif /* SRC_HARDWARE_SAME5X_ETHERNET_GMAC_H_ */
diff --git a/src/Hardware/SAME70/ksz8081rna/ethernet_phy.c b/src/Hardware/SAME70/Ethernet/Phy/ethernet_phy.c
index 0ca27033..0ca27033 100644
--- a/src/Hardware/SAME70/ksz8081rna/ethernet_phy.c
+++ b/src/Hardware/SAME70/Ethernet/Phy/ethernet_phy.c
diff --git a/src/Hardware/SAME70/ksz8081rna/ethernet_phy.h b/src/Hardware/SAME70/Ethernet/Phy/ethernet_phy.h
index 7baa3e63..7baa3e63 100644
--- a/src/Hardware/SAME70/ksz8081rna/ethernet_phy.h
+++ b/src/Hardware/SAME70/Ethernet/Phy/ethernet_phy.h
diff --git a/src/Hardware/SAME70/same70_gmac.cpp b/src/Hardware/SAME70/Ethernet/gmac.cpp
index 2232b246..2b770d68 100644
--- a/src/Hardware/SAME70/same70_gmac.cpp
+++ b/src/Hardware/SAME70/Ethernet/gmac.cpp
@@ -31,17 +31,14 @@
  *
  */
 
-#include "same70_gmac.h"
-
-#if defined(SAME70) && SAME70
+#include "gmac.h"
 #include "pmc/pmc.h"
-#endif
 
 #include "conf_eth.h"
 #include <cstring>
 
 extern "C" {
-#include "ksz8081rna/ethernet_phy.h"
+#include "Phy/ethernet_phy.h"
 #include "lwip/opt.h"
 #include "lwip/sys.h"
 #include "lwip/def.h"
diff --git a/src/Hardware/SAME70/same70_gmac.h b/src/Hardware/SAME70/Ethernet/gmac.h
index 00eae00b..c989abd6 100644
--- a/src/Hardware/SAME70/same70_gmac.h
+++ b/src/Hardware/SAME70/Ethernet/gmac.h
@@ -42,8 +42,8 @@
  *
  */
 
-#ifndef SAME70_GMAC_H_INCLUDED
-#define SAME70_GMAC_H_INCLUDED
+#ifndef SAME70_ETHERNET_GMAC_H_INCLUDED
+#define SAME70_ETHERNET_GMAC_H_INCLUDED
 
 #ifdef __cplusplus
 extern "C" {
@@ -80,4 +80,4 @@ extern unsigned int txErrorCount;
 extern unsigned int txBufferNotFreeCount;
 extern unsigned int txBufferTooShortCount;
 
-#endif /* SAME70_GMAC_H_INCLUDED */
+#endif /* SAME70_ETHERNET_GMAC_H_INCLUDED */
diff --git a/src/Movement/StepperDrivers/TMC22xx.cpp b/src/Movement/StepperDrivers/TMC22xx.cpp
index 3b489d1e..0baa6ede 100644
--- a/src/Movement/StepperDrivers/TMC22xx.cpp
+++ b/src/Movement/StepperDrivers/TMC22xx.cpp
@@ -1471,18 +1471,20 @@ extern "C" void TmcLoop(void *) noexcept
 #elif defined(DUET_5LC)
 			// To avoid having to insert delays between addressing drivers on the same multiplexer channel,
 			// address drivers on alternate multiplexer channels, i.e in the order 04152637
-			static_assert(MaxSmartDrivers == 8);
-			static_assert(!TMC22xx_VARIABLE_NUM_DRIVERS);
-			if (currentDriver == nullptr)
+			if (currentDriver == nullptr || currentDriverNumber == GetNumTmcDrivers() - 1)
 			{
 				currentDriverNumber = 0;
 			}
 			else
 			{
-				static constexpr size_t nextDriver[] = { 4, 5, 6, 7, 1, 2, 3, 0 };
-				currentDriverNumber = nextDriver[currentDriverNumber];
+				++currentDriverNumber;
 			}
-			currentDriver = &driverStates[currentDriverNumber];
+			static constexpr TmcDriverState *drivers[] =
+			{
+				&driverStates[0], &driverStates[4], &driverStates[1], &driverStates[5], &driverStates[2], &driverStates[6], &driverStates[3], &driverStates[7]
+			};
+			static_assert(ARRAY_SIZE(drivers) == MaxSmartDrivers);
+			currentDriver = drivers[currentDriverNumber];
 #else
 			currentDriver = (currentDriver == nullptr || currentDriver + 1 == driverStates + GetNumTmcDrivers())
 								? driverStates
diff --git a/src/Networking/LwipEthernet/GMAC/ethernet_sam.cpp b/src/Networking/LwipEthernet/GMAC/ethernet_sam.cpp
index e7e438b5..528977c3 100644
--- a/src/Networking/LwipEthernet/GMAC/ethernet_sam.cpp
+++ b/src/Networking/LwipEthernet/GMAC/ethernet_sam.cpp
@@ -43,7 +43,14 @@
 
 #include "ethernet_sam.h"
 
-#include <Hardware/SAME70/same70_gmac.h>
+#if defined(__SAME70Q20B__)
+# include <Hardware/SAME70/Ethernet/gmac.h>
+#elif defined(__SAME54P20A__)
+# include <Hardware/SAME5x/Ethernet/gmac.h>
+#else
+# error Unsupported processor
+#endif
+
 #include "lwip/netif.h"
 
 #include <cstring>
diff --git a/src/Networking/LwipEthernet/LwipEthernetInterface.cpp b/src/Networking/LwipEthernet/LwipEthernetInterface.cpp
index 5b9aa927..5b8a726a 100644
--- a/src/Networking/LwipEthernet/LwipEthernetInterface.cpp
+++ b/src/Networking/LwipEthernet/LwipEthernetInterface.cpp
@@ -20,7 +20,12 @@
 #include "General/IP4String.h"
 #include "Version.h"								// version is reported by MDNS
 #include "GMAC/ethernet_sam.h"
-#include <Hardware/SAME70/same70_gmac.h>			// for error counts used in function Diagnostics
+
+#if SAME70
+# include <Hardware/SAME70/Ethernet/gmac.h>
+#elif SAME5x
+# include <Hardware/SAME5x/Ethernet/gmac.h>
+#endif
 
 extern "C"
 {
diff --git a/src/Version.h b/src/Version.h
index ac6f41aa..9d475c30 100644
--- a/src/Version.h
+++ b/src/Version.h
@@ -19,7 +19,7 @@
 #endif
 
 #ifndef DATE
-# define DATE "2020-06-21b2"
+# define DATE "2020-06-22b1"
 #endif
 
 #define AUTHORS "reprappro, dc42, chrishamm, t3p3, dnewman, printm3d"