diff options
author | David Crocker <dcrocker@eschertech.com> | 2022-08-07 22:52:16 +0300 |
---|---|---|
committer | David Crocker <dcrocker@eschertech.com> | 2022-08-07 22:52:16 +0300 |
commit | 3d1875dd7f661358b0c1743b4a9f2b82724fd566 (patch) | |
tree | a1461d05a00d950eec214e8a5b846ed9d5b04a3c | |
parent | a857bc8240560bb16c35d9e355422b6745f867ac (diff) |
Duet3 Mini WiFi interface now uses end-of-transfer interrupt
-rw-r--r-- | src/Config/Pins_Duet3Mini.h | 4 | ||||
-rw-r--r-- | src/Networking/ESP8266WiFi/WiFiInterface.cpp | 33 |
2 files changed, 7 insertions, 30 deletions
diff --git a/src/Config/Pins_Duet3Mini.h b/src/Config/Pins_Duet3Mini.h index cf4f4b1e..f40ed90e 100644 --- a/src/Config/Pins_Duet3Mini.h +++ b/src/Config/Pins_Duet3Mini.h @@ -300,8 +300,8 @@ constexpr Pin EspSclkPin = PortAPin(12); constexpr Pin EspSSPin = PortAPin(14); constexpr Pin WiFiSpiSercomPins[] = { EspSclkPin, EspMisoPin, EspSSPin, EspMosiPin }; constexpr GpioPinFunction WiFiSpiSercomPinsMode = GpioPinFunction::D; -constexpr IRQn WiFiSpiSercomIRQn = SERCOM4_3_IRQn; // this is the SS Low interrupt, the only one we use -#define ESP_SPI_HANDLER SERCOM4_3_Handler +constexpr IRQn WiFiSpiSercomIRQn = SERCOM4_1_IRQn; // this is the SS Low interrupt, the only one we use +#define ESP_SPI_HANDLER SERCOM4_1_Handler constexpr Pin EspResetPin = EthernetPhyResetPin; constexpr Pin EspEnablePin = PortCPin(20); diff --git a/src/Networking/ESP8266WiFi/WiFiInterface.cpp b/src/Networking/ESP8266WiFi/WiFiInterface.cpp index 24ef7662..b4afe547 100644 --- a/src/Networking/ESP8266WiFi/WiFiInterface.cpp +++ b/src/Networking/ESP8266WiFi/WiFiInterface.cpp @@ -1802,7 +1802,7 @@ int32_t WiFiInterface::SendCommand(NetworkCommand cmd, SocketNumber socketNum, u #if SAME5x spi_slave_dma_setup(dataOutLength, dataInLength); WiFiSpiSercom->SPI.INTFLAG.reg = 0xFF; // clear any pending interrupts - WiFiSpiSercom->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; // enable the start of transfer (SS low) interrupt + WiFiSpiSercom->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; // enable the end of transmit interrupt EnableSpi(); #elif defined(__LPC17xx__) spi_slave_dma_setup(dataOutLength, dataInLength); @@ -1845,27 +1845,6 @@ int32_t WiFiInterface::SendCommand(NetworkCommand cmd, SocketNumber socketNum, u #if SAME5x { - // We don't get an end-of-transfer interrupt, just a start-of-transfer one. So wait until SS is high, then disable the SPI. - // The normal maximum block time is about 2K * 8/spi_clock_speed plus any pauses that the ESP takes, which at 26.7MHz clock rate is 620us plus pause time - // However, when we send a command that involves writing to flash memory, then the flash write occurs between sending the header and the body, so it takes much longer - const uint32_t startedWaitingAt = millis(); - const bool writingFlash = ( cmd == NetworkCommand::networkAddSsid || cmd == NetworkCommand::networkConfigureAccessPoint - || cmd == NetworkCommand::networkDeleteSsid || cmd == NetworkCommand::networkFactoryReset); - while (!digitalRead(EspSSPin)) - { - const uint32_t millisWaiting = millis() - startedWaitingAt; - if (millisWaiting >= WiFiTransferTimeoutMillis) - { - return ResponseTimeout; - } - - // The new RTOS SDK for the ESP8266 often interrupts out transfer task for long periods of time. So if the transfer is taking a while to complete, give up the CPU. - // Also give up the CPU if we are writing to flash memory, because we know that takes a long time. - if (writingFlash || millisWaiting >= 2) - { - delay(2); - } - } if (WiFiSpiSercom->SPI.STATUS.bit.BUFOVF) { ++spiRxOverruns; @@ -1978,7 +1957,7 @@ void WiFiInterface::GetNewStatus() noexcept # error ESP_SPI_HANDLER not defined # endif -// SPI interrupt handler, called when NSS goes high (SAM4E, SAME70) or low (SAME5x) +// SPI interrupt handler, called when NSS goes high (SAM4E, SAME70) or end of transfer (SAME5x) void ESP_SPI_HANDLER() noexcept { wifiInterface->SpiInterrupt(); @@ -1987,13 +1966,11 @@ void ESP_SPI_HANDLER() noexcept void WiFiInterface::SpiInterrupt() noexcept { #if SAME5x - // On the SAM5x we can't get an end-of-transfer interrupt, only a start-of-transfer interrupt. - // So we can't disable SPI or DMA in this ISR. const uint8_t status = WiFiSpiSercom->SPI.INTFLAG.reg; - if ((status & SERCOM_SPI_INTENSET_SSL) != 0) + if ((status & SERCOM_SPI_INTFLAG_TXC) != 0) { - WiFiSpiSercom->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; // disable the interrupt - WiFiSpiSercom->SPI.INTFLAG.reg = SERCOM_SPI_INTENSET_SSL; // clear the status + WiFiSpiSercom->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; // disable the interrupt + WiFiSpiSercom->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; // clear the status #else const uint32_t status = ESP_SPI->SPI_SR; // read status and clear interrupt ESP_SPI->SPI_IDR = SPI_IER_NSSR; // disable the interrupt |