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| author | David Crocker <dcrocker@eschertech.com> | 2019-03-10 16:48:57 +0300 |
|---|---|---|
| committer | David Crocker <dcrocker@eschertech.com> | 2019-03-10 16:48:57 +0300 |
| commit | d9f841aa5896567158fefca7bea95faa597c4d6b (patch) | |
| tree | 4abc24d12788a79b5cf44b0ccca83cb4ac4f377f /src/Networking/LwipEthernet/GMAC | |
| parent | 34d3b9a054aec83c1dff2f73ef9512545eb305a0 (diff) | |
Fixes for Duet 3
Fixed Duet 3 v0.5 Ethernet
Fixed TMC driver SPI
Needs new CoreNG based on ASF 3.45.0
Diffstat (limited to 'src/Networking/LwipEthernet/GMAC')
| -rw-r--r-- | src/Networking/LwipEthernet/GMAC/same70_gmac.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/Networking/LwipEthernet/GMAC/same70_gmac.c b/src/Networking/LwipEthernet/GMAC/same70_gmac.c index 0a8b18de..3250070d 100644 --- a/src/Networking/LwipEthernet/GMAC/same70_gmac.c +++ b/src/Networking/LwipEthernet/GMAC/same70_gmac.c @@ -676,12 +676,22 @@ void ethernetif_hardware_init(void) /* Clear interrupts */ gmac_get_priority_interrupt_status(GMAC, GMAC_QUE_2); gmac_get_priority_interrupt_status(GMAC, GMAC_QUE_1); +#if (SAMV71B || SAME70B) + gmac_get_priority_interrupt_status(GMAC, GMAC_QUE_3); + gmac_get_priority_interrupt_status(GMAC, GMAC_QUE_4); + gmac_get_priority_interrupt_status(GMAC, GMAC_QUE_5); +#endif /* Set Tx Priority */ gs_tx_desc_null.addr = (uint32_t)0xFFFFFFFF; gs_tx_desc_null.status.val = GMAC_TXD_WRAP | GMAC_TXD_USED; gmac_set_tx_priority_queue(GMAC, (uint32_t)&gs_tx_desc_null, GMAC_QUE_2); gmac_set_tx_priority_queue(GMAC, (uint32_t)&gs_tx_desc_null, GMAC_QUE_1); +#if (SAMV71B || SAME70B) + gmac_set_tx_priority_queue(GMAC, (uint32_t)&gs_tx_desc_null, GMAC_QUE_3); + gmac_set_tx_priority_queue(GMAC, (uint32_t)&gs_tx_desc_null, GMAC_QUE_4); + gmac_set_tx_priority_queue(GMAC, (uint32_t)&gs_tx_desc_null, GMAC_QUE_5); +#endif /* Set Rx Priority */ gs_rx_desc_null.addr.val = (uint32_t)0xFFFFFFFF & GMAC_RXD_ADDR_MASK; @@ -689,6 +699,11 @@ void ethernetif_hardware_init(void) gs_rx_desc_null.status.val = 0; gmac_set_rx_priority_queue(GMAC, (uint32_t)&gs_rx_desc_null, GMAC_QUE_2); gmac_set_rx_priority_queue(GMAC, (uint32_t)&gs_rx_desc_null, GMAC_QUE_1); +#if (SAMV71B || SAME70B) + gmac_set_rx_priority_queue(GMAC, (uint32_t)&gs_rx_desc_null, GMAC_QUE_3); + gmac_set_rx_priority_queue(GMAC, (uint32_t)&gs_rx_desc_null, GMAC_QUE_4); + gmac_set_rx_priority_queue(GMAC, (uint32_t)&gs_rx_desc_null, GMAC_QUE_5); +#endif gmac_rx_init(&gs_gmac_dev); gmac_tx_init(&gs_gmac_dev); |