diff options
| author | David Crocker <dcrocker@eschertech.com> | 2019-12-02 14:16:15 +0300 |
|---|---|---|
| committer | David Crocker <dcrocker@eschertech.com> | 2019-12-02 14:16:15 +0300 |
| commit | 9cea4d41a71b37d6487c0814bfcf491a77a45a15 (patch) | |
| tree | 52acae8162c2d71a7b119babc9c18f6558b8f13a /src/Storage/CRC32.cpp | |
| parent | 6e686e0d09c2aa7c4d1addc527c826b1e13e0c39 (diff) | |
Fixed DWC2 compatability isue
Don't suppress empty responses to HTTP because DWC2 waits for them
Diffstat (limited to 'src/Storage/CRC32.cpp')
| -rw-r--r-- | src/Storage/CRC32.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/Storage/CRC32.cpp b/src/Storage/CRC32.cpp index e8c57758..297e4c75 100644 --- a/src/Storage/CRC32.cpp +++ b/src/Storage/CRC32.cpp @@ -171,6 +171,11 @@ void CRC32::Update(char c) crc = (CRC_32_TAB[(crc ^ c) & 0xFF] ^ (crc >> 8)); } +// A note on CRC algorithms on ARM: +// Original algorithm (1 byte per loop iteration, 1K table): 7 instructions, 11 clocks (11 clocks/byte) +// Algorithm currently used on non-SAME70 processors (4 bytes per loop iteration, 1K table): 19 instructions, 26 clocks (6.5 clocks/byte) +// Slicing-by-4 using 1 dword per loop iteration: 15 instructions, 18 clocks (4.5 clocks/byte) +// Slicing-by-4 using 1 quadword per loop iteration: 28 instructions, 30 clocks (3.75 clocks/byte) void CRC32::Update(const char *s, size_t len) { // The speed of this function affects the speed of file uploads, so make it as fast as possible. Sadly the SAME70 doesn't do hardware CRC calculation. |