diff options
| -rw-r--r-- | .cproject | 5 | ||||
| -rw-r--r-- | src/Duet3_V06/Pins_Duet3_V06.cpp | 12 | ||||
| -rw-r--r-- | src/Duet3_V06/Pins_Duet3_V06.h | 189 | ||||
| -rw-r--r-- | src/Hardware/IoPorts.h | 2 | ||||
| -rw-r--r-- | src/Hardware/SAME70/Main.cpp | 20 | ||||
| -rw-r--r-- | src/Hardware/SAME70/same70q21b_flash.ld | 184 |
6 files changed, 350 insertions, 62 deletions
@@ -451,7 +451,7 @@ </extensions> </storageModule> <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - <configuration artifactExtension="elf" artifactName="Duet3Firmware_MB6HC" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.cross.exe.release.516195201.976458850.241502451.1275216290.274082366.1645191116.1852610203.289083307.712841925" name="Duet3" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="cdt.managedbuild.config.gnu.cross.exe.release" postannouncebuildStep="Generating binary file" postbuildStep="arm-none-eabi-objcopy -O binary "${workspace_loc:/${ProjName}/${ConfigName}}/${BuildArtifactFileBaseName}.elf" "${workspace_loc:/${ProjName}/${ConfigName}}/${BuildArtifactFileBaseName}.bin" && crc32appender "${workspace_loc:/${ProjName}/${ConfigName}}/${BuildArtifactFileBaseName}.bin""> + <configuration artifactName="Duet3Firmware_MB6HC" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="cdt.managedbuild.config.gnu.cross.exe.release.516195201.976458850.241502451.1275216290.274082366.1645191116.1852610203.289083307.712841925" name="Duet3" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.enablement=null,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.image=null,org.eclipse.cdt.docker.launcher.containerbuild.property.connection=null" parent="cdt.managedbuild.config.gnu.cross.exe.release" postannouncebuildStep="Generating binary file" postbuildStep="arm-none-eabi-objcopy -O binary "${workspace_loc:/${ProjName}/${ConfigName}}/${BuildArtifactFileBaseName}.elf" "${workspace_loc:/${ProjName}/${ConfigName}}/${BuildArtifactFileBaseName}.bin" && crc32appender "${workspace_loc:/${ProjName}/${ConfigName}}/${BuildArtifactFileBaseName}.bin""> <folderInfo id="cdt.managedbuild.config.gnu.cross.exe.release.516195201.976458850.241502451.1275216290.274082366.1645191116.1852610203.289083307.712841925." name="/" resourcePath=""> <toolChain id="cdt.managedbuild.toolchain.gnu.cross.exe.release.537248487" name="Cross GCC" superClass="cdt.managedbuild.toolchain.gnu.cross.exe.release"> <option id="cdt.managedbuild.option.gnu.cross.path.582108797" name="Path" superClass="cdt.managedbuild.option.gnu.cross.path" useByScannerDiscovery="false" value="${ArmGccPath}" valueType="string"/> @@ -482,6 +482,7 @@ <listOptionValue builtIn="false" value=""${workspace_loc:/CoreN2G/src/SAM4S_4E_E70/asf/sam/utils/preprocessor}""/> <listOptionValue builtIn="false" value=""${workspace_loc:/CoreN2G/src/SAM4S_4E_E70/asf/sam/utils/header_files}""/> <listOptionValue builtIn="false" value=""${workspace_loc:/CoreN2G/src/SAM4S_4E_E70/asf/sam/utils/cmsis/same70/include}""/> + <listOptionValue builtIn="false" value=""${workspace_loc:/CoreN2G/src/atmel/SAME70_DFP/2.4.166/same70b/include}""/> <listOptionValue builtIn="false" value=""${workspace_loc:/CoreN2G/src/arm/CMSIS/5.4.0/CMSIS/Core/Include}""/> <listOptionValue builtIn="false" value=""${workspace_loc:/CoreN2G/src/SAM4S_4E_E70/SAME70}""/> <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Networking/LwipEthernet/Lwip}""/> @@ -514,7 +515,7 @@ <listOptionValue builtIn="false" srcPrefixMapping="" srcRootPath="" value="CANlib"/> <listOptionValue builtIn="false" value="supc++"/> </option> - <option id="gnu.cpp.link.option.flags.951069241" name="Linker flags" superClass="gnu.cpp.link.option.flags" useByScannerDiscovery="false" value="--specs=nosys.specs -Os -Wl,--gc-sections -Wl,--fatal-warnings -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -T"${workspace_loc:/${CoreName}/variants/same70/linker_scripts/gcc/flash.ld}" -Wl,-Map,"${workspace_loc:/${ProjName}/${ConfigName}}/${BuildArtifactFileBaseName}.map"" valueType="string"/> + <option id="gnu.cpp.link.option.flags.951069241" name="Linker flags" superClass="gnu.cpp.link.option.flags" useByScannerDiscovery="false" value="--specs=nosys.specs -Os -Wl,--gc-sections -Wl,--fatal-warnings -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -T"${workspace_loc:/${ProjName}/src/Hardware/SAME70/same70q21b_flash.ld}" -Wl,-Map,"${workspace_loc:/${ProjName}/${ConfigName}}/${BuildArtifactFileBaseName}.map"" valueType="string"/> <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.180655060" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input"> <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/> <additionalInput kind="additionalinput" paths="$(LIBS)"/> diff --git a/src/Duet3_V06/Pins_Duet3_V06.cpp b/src/Duet3_V06/Pins_Duet3_V06.cpp index a96f3508..9d8cbd5f 100644 --- a/src/Duet3_V06/Pins_Duet3_V06.cpp +++ b/src/Duet3_V06/Pins_Duet3_V06.cpp @@ -9,9 +9,15 @@ // Hardware-dependent pins functions -// Function to look up a pin name pass back the corresponding index into the pin table +// Return a pointer to the pin description entry. Declared in and called from CoreN2G. +const PinDescriptionBase *AppGetPinDescription(Pin p) noexcept +{ + return (p < ARRAY_SIZE(PinTable)) ? &PinTable[p] : nullptr; +} + +// Function to look up a pin name and pass back the corresponding index into the pin table // On this platform, the mapping from pin names to pins is fixed, so this is a simple lookup -bool LookupPinName(const char*pn, LogicalPin& lpin, bool& hardwareInverted) noexcept +bool LookupPinName(const char *pn, LogicalPin &lpin, bool &hardwareInverted) noexcept { if (StringEqualsIgnoreCase(pn, NoPinName)) { @@ -22,7 +28,7 @@ bool LookupPinName(const char*pn, LogicalPin& lpin, bool& hardwareInverted) noex for (size_t lp = 0; lp < ARRAY_SIZE(PinTable); ++lp) { - const char *q = PinTable[lp].names; + const char *q = PinTable[lp].pinNames; while (*q != 0) { // Try the next alias in the list of names for this pin diff --git a/src/Duet3_V06/Pins_Duet3_V06.h b/src/Duet3_V06/Pins_Duet3_V06.h index 98a0cc47..de43b2c4 100644 --- a/src/Duet3_V06/Pins_Duet3_V06.h +++ b/src/Duet3_V06/Pins_Duet3_V06.h @@ -1,6 +1,8 @@ #ifndef PINS_DUET3_V06_H__ #define PINS_DUET3_V06_H__ +#include <PinDescription.h> + #define BOARD_SHORT_NAME "MB6HC" #define BOARD_NAME "Duet 3 MB6HC" #define DEFAULT_BOARD_TYPE BoardType::Auto @@ -174,49 +176,161 @@ constexpr Pin EthernetPhyResetPin = PortDPin(11); #define USART_SSPI USART0 #define ID_SSPI ID_USART0 -// Enum to represent allowed types of pin access -// We don't have a separate bit for servo, because Duet PWM-capable ports can be used for servos if they are on the Duet main board -enum class PinCapability: uint8_t -{ - // Individual capabilities - read = 1, - ain = 2, - write = 4, - pwm = 8, - - // Combinations - ainr = 1|2, - rw = 1|4, - wpwm = 4|8, - rwpwm = 1|4|8, - ainrw = 1|2|4, - ainrwpwm = 1|2|4|8 -}; - -constexpr inline PinCapability operator|(PinCapability a, PinCapability b) noexcept -{ - return (PinCapability)((uint8_t)a | (uint8_t)b); -} - -// Struct to represent a pin that can be assigned to various functions -// This can be varied to suit the hardware. It is a struct not a class so that it can be direct initialised in read-only memory. -struct PinEntry -{ - Pin GetPin() const noexcept { return pin; } - PinCapability GetCapability() const noexcept { return cap; } - const char* GetNames() const noexcept { return names; } - - Pin pin; - PinCapability cap; - const char *names; -}; - // List of assignable pins and their mapping from names to MPU ports. This is indexed by logical pin number. // The names must match user input that has been concerted to lowercase and had _ and - characters stripped out. // Aliases are separate by the , character. // If a pin name is prefixed by ! then this means the pin is hardware inverted. The same pin may have names for both the inverted and non-inverted cases, // for example the inverted heater pins on the expansion connector are available as non-inverted servo pins on a DueX. //TODO change the table below for the V0.6 board +constexpr PinDescription PinTable[] = +{ + // TC PWM ADC Capability PinNames + // Port A + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "io6.out" }, // PA00 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::read, "out6.tach" }, // PA01 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA02 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "io3.out" }, // PA03 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA04 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "spi.cs0,serial3.rx"}, // PA05 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "spi.cs1,serial3.tx"}, // PA06 + { TcOutput::none, PwmOutput::pwm0h3_c,AdcInput::none, PinCapability::wpwm, "out0" }, // PA07 + { TcOutput::none, PwmOutput::pwm1h3_c,AdcInput::none, PinCapability::wpwm, "out6" }, // PA08 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA09 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::write, "pson" }, // PA10 + { TcOutput::none, PwmOutput::pwm0h0_c,AdcInput::none, PinCapability::wpwm, "out3" }, // PA11 + { TcOutput::none, PwmOutput::pwm1h0_c,AdcInput::none, PinCapability::wpwm, "out9,laser,vfd" }, // PA12 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA13 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA14 + { TcOutput::tioa1, PwmOutput::none, AdcInput::none, PinCapability::wpwm, "out4" }, // PA15 + { TcOutput::none, PwmOutput::pwm0l2_c,AdcInput::none, PinCapability::wpwm, "out2" }, // PA16 + { TcOutput::none, PwmOutput::none, AdcInput::adc0_6, PinCapability::ainr, "io7.in" }, // PA17 + { TcOutput::none, PwmOutput::none, AdcInput::adc0_7, PinCapability::ainr, "io6.in" }, // PA18 + { TcOutput::none, PwmOutput::none, AdcInput::adc0_8, PinCapability::ainr, "io5.in" }, // PA19 + { TcOutput::none, PwmOutput::none, AdcInput::adc0_9, PinCapability::none, nullptr }, // PA20 + { TcOutput::none, PwmOutput::none, AdcInput::adc0_1, PinCapability::none, nullptr }, // PA21 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA22 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA23 + { TcOutput::none, PwmOutput::pwm0h1_c,AdcInput::none, PinCapability::wpwm, "out1" }, // PA24 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA25 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA26 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA27 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA28 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA29 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA30 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PA31 + + // Port B + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB00 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB01 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB02 + { TcOutput::none, PwmOutput::none, AdcInput::adc0_2, PinCapability::none, nullptr }, // PB03 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB04 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB05 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB06 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB07 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB08 Chrystal + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB09 Chrystal + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB10 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB11 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB12 Erase + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB13 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB14 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB15 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB16 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB17 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB18 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB19 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB20 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB21 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB22 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB23 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB24 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB25 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB26 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB27 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB28 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB29 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB30 not on chip + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PB31 not on chip + + // Port C + { TcOutput::none, PwmOutput::none, AdcInput::adc1_9, PinCapability::none, nullptr }, // PC00 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC01 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC02 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC03 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC04 + { TcOutput::tioa6, PwmOutput::none, AdcInput::none, PinCapability::wpwm, "out5" }, // PC05 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC06 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::read, "out4.tach" }, // PC07 + { TcOutput::tioa7, PwmOutput::none, AdcInput::none, PinCapability::wpwm, "out8" }, // PC08 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC09 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC10 + { TcOutput::tioa8, PwmOutput::none, AdcInput::none, PinCapability::wpwm, "out7" }, // PC11 + { TcOutput::none, PwmOutput::none, AdcInput::adc1_3, PinCapability::none, nullptr }, // PC12 + { TcOutput::none, PwmOutput::none, AdcInput::adc1_1, PinCapability::none, nullptr }, // PC13 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC14 + { TcOutput::none, PwmOutput::none, AdcInput::adc1_2, PinCapability::ainr, "temp0" }, // PC15 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC16 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC17 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC18 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC19 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC20 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC21 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "spi.cs3" }, // PC22 + { TcOutput::tioa3, PwmOutput::none, AdcInput::none, PinCapability::rwpwm, "io7.out" }, // PC23 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC24 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC25 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC26 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC27 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PC28 + { TcOutput::tioa5, PwmOutput::none, AdcInput::adc1_4, PinCapability::ainr, "temp1" }, // PC29 + { TcOutput::none, PwmOutput::none, AdcInput::adc1_5, PinCapability::ainr, "temp2" }, // PC30 + { TcOutput::none, PwmOutput::none, AdcInput::adc1_6, PinCapability::ainr, "temp3" }, // PC31 + + // PORT D + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD00 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD01 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD02 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD03 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD04 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD05 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD06 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD07 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD08 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD09 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD10 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD11 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD12 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD13 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD14 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::read, "io1.in,serial1.rx" }, // PD15 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "io1.out,serial1.tx"}, // PD16 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD17 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD18 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD19 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "spi.cs2" }, // PD20 + { TcOutput::tioa11, PwmOutput::none, AdcInput::none, PinCapability::rwpwm, "io5.out" }, // PD21 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD22 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::read, "out5.tach" }, // PD23 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD24 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::read, "io0.in,serial0.rx" }, // PD25 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "io0.out,serial0.tx"}, // PD26 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "io2.out,i2c0.dat" }, // PD27 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::read, "io2.in,i2c0.clk" }, // PD28 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD29 + { TcOutput::none, PwmOutput::none, AdcInput::adc0_0, PinCapability::ainr, "io4.in" }, // PD30 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PD31 + + // Port E + { TcOutput::tioa9, PwmOutput::none, AdcInput::adc1_11, PinCapability::rwpwm, "io4.out" }, // PE00 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::rw, "io8.out" }, // PE01 + { TcOutput::none, PwmOutput::none, AdcInput::none, PinCapability::none, nullptr }, // PE02 + { TcOutput::none, PwmOutput::none, AdcInput::adc1_10, PinCapability::read, "io8.in" }, // PE03 analog in not usable because it is on the wrong ADC + { TcOutput::none, PwmOutput::none, AdcInput::adc0_4, PinCapability::none, nullptr }, // PE04 + { TcOutput::none, PwmOutput::none, AdcInput::adc0_3, PinCapability::ainr, "io3.in" }, // PE05 +}; + +#if 0 constexpr PinEntry PinTable[] = { // Output connectors @@ -271,6 +385,7 @@ constexpr PinEntry PinTable[] = { PortDPin(20), PinCapability::rw, "spi.cs2" }, { PortCPin(22), PinCapability::rw, "spi.cs3" } }; +#endif constexpr unsigned int NumNamedPins = ARRAY_SIZE(PinTable); diff --git a/src/Hardware/IoPorts.h b/src/Hardware/IoPorts.h index 37a6bba0..90a832eb 100644 --- a/src/Hardware/IoPorts.h +++ b/src/Hardware/IoPorts.h @@ -79,7 +79,7 @@ protected: // Get the physical pin without checking the validity of the logical pin Pin GetPinNoCheck() const noexcept { -#if SAME5x +#if SAME5x || SAME70 // New-style pin table is indexed by pin number return logicalPin; #else diff --git a/src/Hardware/SAME70/Main.cpp b/src/Hardware/SAME70/Main.cpp index 5851ca16..4d26da64 100644 --- a/src/Hardware/SAME70/Main.cpp +++ b/src/Hardware/SAME70/Main.cpp @@ -6,29 +6,11 @@ * License: GNU GPL version 3 */ -#include <Core.h> +#include <CoreIO.h> // Program initialisation void AppInit() noexcept { } -// syscalls.h must be included by exactly one .cpp file in the project -#include <syscalls.h> - -[[noreturn]] void OutOfMemoryHandler() noexcept -{ - while (true) { } -} - -extern "C" [[noreturn]] void __cxa_pure_virtual() noexcept -{ - while (true) { } -} - -extern "C" [[noreturn]] void __cxa_deleted_virtual() noexcept -{ - while (true) { } -} - // End diff --git a/src/Hardware/SAME70/same70q21b_flash.ld b/src/Hardware/SAME70/same70q21b_flash.ld new file mode 100644 index 00000000..5cfabe2f --- /dev/null +++ b/src/Hardware/SAME70/same70q21b_flash.ld @@ -0,0 +1,184 @@ +/** + * \file + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +/* We put the non-cached RAM at the start of RAM because the CAN buffers must be within the first 64kb. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram_not_cached (rw) : ORIGIN = 0x20400000, LENGTH = 0x00018000 /* we currently allocate 96kb of non-cached RAM */ + ram (rwx) : ORIGIN = 0x20418000, LENGTH = 0x00048000 /* that leaves 288Kb of cached RAM */ +} + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > rom + + . = ALIGN(4); + _etext = .; + + .ram_nocache (NOLOAD) : + { + . = ALIGN(4); + _szero_nocache = .; + *(.CanMessage .CanMessage.*) + *(.ram_nocache .ram_nocache.*) + . = ALIGN(4); + _ezero_nocache = .; + } > ram_not_cached + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + . = ALIGN(4); + _eramfunc = .; + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + _firmware_crc = _etext + (_erelocate - _srelocate); /* We append the CRC32 to the binary file. This is its offset in memory. */ + + /* .bss section which is used for uninitialized data */ + .bss ALIGN(4) (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + . = ALIGN(4); + _end = . ; + + /* .stack_dummy section doesn't contains any symbols. It is only + used for linker to calculate size of stack sections, and assign + values to stack symbols later */ + .stack_dummy : + { + *(.stack*) + } > ram + + /* Set stack top to end of ram, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(_sstack = __StackLimit); + PROVIDE(_estack = __StackTop); + + PROVIDE(_nocache_ram_start = ORIGIN(ram_not_cached)); + PROVIDE(_nocache_ram_end = ORIGIN(ram_not_cached) + LENGTH(ram_not_cached)); +} + |