diff options
Diffstat (limited to 'src/DuetNG/DuetEthernet/Wiznet/Ethernet/W5500/w5500.h')
| -rw-r--r-- | src/DuetNG/DuetEthernet/Wiznet/Ethernet/W5500/w5500.h | 929 |
1 files changed, 535 insertions, 394 deletions
diff --git a/src/DuetNG/DuetEthernet/Wiznet/Ethernet/W5500/w5500.h b/src/DuetNG/DuetEthernet/Wiznet/Ethernet/W5500/w5500.h index 051ef753..048c47eb 100644 --- a/src/DuetNG/DuetEthernet/Wiznet/Ethernet/W5500/w5500.h +++ b/src/DuetNG/DuetEthernet/Wiznet/Ethernet/W5500/w5500.h @@ -48,12 +48,20 @@ #ifndef _W5500_H_ #define _W5500_H_ -#include <stdint.h> +#include <cstdint> +#include <cstddef> #include "../wizchip_conf.h" +#include "spi.h" + +// The following functions are defined in Network.cpp and used by this module +extern void SpiAssertSS(); +extern void SpiReleaseSS(); +extern void SpiSendAddress(uint32_t); +extern uint8_t SpiReadByte(); +extern void SpiSendByte(uint8_t b); +extern spi_status_t SpiReadBurst(uint8_t* pBuf, size_t len); +extern spi_status_t SpiSendBurst(const uint8_t* pBuf, size_t len); -/// @cond DOXY_APPLY_CODE -#if (_WIZCHIP_ == 5500) -/// @endcond #define _W5500_IO_BASE_ 0x00000000 @@ -211,42 +219,42 @@ * - \ref MR_PPPOE : PPPoE mode * - \ref MR_FARP : Force ARP mode */ -#define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3)) +const uint32_t MR = _W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief Gateway IP Register address(R/W) * @details @ref GAR configures the default gateway address. */ -#define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t GAR = _W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief Subnet mask Register address(R/W) * @details @ref SUBR configures the subnet mask address. */ -#define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t SUBR = _W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief Source MAC Register address(R/W) * @details @ref SHAR configures the source hardware address. */ -#define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t SHAR = _W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief Source IP Register address(R/W) * @details @ref SIPR configures the source IP address. */ -#define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t SIPR = _W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief Set Interrupt low level timer register address(R/W) * @details @ref INTLEVEL configures the Interrupt Assert Time. */ -#define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t INTLEVEL = _W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group @@ -263,7 +271,7 @@ * - \ref IR_PPPoE : PPPoE connection close * - \ref IR_MP : Magic packet */ -#define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t IR = _W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group @@ -281,9 +289,7 @@ * - \ref IM_IR5 : PPPoE Close Interrupt Mask * - \ref IM_IR4 : Magic Packet Interrupt Mask */ -//M20150401 : Rename SYMBOE ( Re-define error in a compile) -//#define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3)) -#define _IMR_ (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t _IMR_ = _W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group @@ -291,7 +297,7 @@ * @details @ref SIR indicates the interrupt status of Socket.\n * Each bit of @ref SIR be still until @ref Sn_IR is cleared by the host.\n * If @ref Sn_IR is not equal to x00 the n-th bit of @ref SIR is and INTn PIN is asserted until @ref SIR is x00 */ -#define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t SIR = _W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group @@ -300,7 +306,7 @@ * When a bit of @ref SIMR is and the corresponding bit of @ref SIR is Interrupt will be issued. * In other words, if a bit of @ref SIMR is an interrupt will be not issued even if the corresponding bit of @ref SIR is */ -#define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t SIMR = _W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group @@ -310,9 +316,7 @@ * to the packet that is transmitted by \ref Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). * If the peer does not respond within the @ref _RTR_ time, W5500 retransmits the packet or issues timeout. */ -//M20150401 : Rename SYMBOE ( Re-define error in a compile) -//#define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3)) -#define _RTR_ (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t _RTR_ = _W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group @@ -320,44 +324,42 @@ * @details @ref _RCR_ configures the number of time of retransmission. * When retransmission occurs as many as ref _RCR_+1 Timeout interrupt is issued (@ref Sn_IR_TIMEOUT = '1'). */ -//M20150401 : Rename SYMBOE ( Re-define error in a compile) -//#define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3)) -#define _RCR_ (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t _RCR_ = _W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief PPP LCP Request Timer register in PPPoE mode(R/W) * @details @ref PTIMER configures the time for sending LCP echo request. The unit of time is 25ms. */ -#define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t PTIMER = _W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief PPP LCP Magic number register in PPPoE mode(R/W) * @details @ref PMAGIC configures the 4bytes magic number to be used in LCP negotiation. */ -#define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t PMAGIC = _W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief PPP Destination MAC Register address(R/W) * @details @ref PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process. */ -#define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t PHAR = _W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief PPP Session Identification Register(R/W) * @details @ref PSID configures the PPPoE sever session ID acquired during PPPoE connection process. */ -#define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t PSID = _W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief PPP Maximum Segment Size(MSS) register(R/W) * @details @ref PMRU configures the maximum receive unit of PPPoE. */ -#define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t PMRU = _W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group @@ -366,7 +368,7 @@ * which socket is not open and @ref IR_UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR indicates * the destination IP address & port number respectively. */ -#define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t UIPR = _W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group @@ -375,14 +377,14 @@ * which socket is not open and @ref IR_UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR * indicates the destination IP address & port number respectively. */ -#define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t UPORTR = _W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3); /** * @ingroup Common_register_group * @brief PHY Status Register(R/W) * @details @ref PHYCFGR configures PHY operation mode and resets PHY. In addition, @ref PHYCFGR indicates the status of PHY such as duplex, Speed, Link. */ -#define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t PHYCFGR = _W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3); // Reserved (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3)) // Reserved (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3)) @@ -400,7 +402,7 @@ * @brief chip version register address(R) * @details @ref VERSIONR always indicates the W5500 version as @b 0x04. */ -#define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3)) + const uint32_t VERSIONR = _W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3); //----------------------------- W5500 Socket Registers IOMAP ----------------------------- @@ -434,7 +436,10 @@ * - @ref Sn_MR_CLOSE : Unused socket * @note MACRAW mode should be only used in Socket 0. */ -#define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_MR(uint8_t N) + { + return _W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group @@ -453,7 +458,10 @@ * - @ref Sn_CR_SEND_KEEP : Send keep alive message. * - @ref Sn_CR_RECV : Update RX buffer pointer and receive data. */ -#define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_CR(uint8_t N) + { + return _W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group @@ -471,7 +479,10 @@ * - \ref Sn_IR_DISCON : <b>DISCON Interrupt</b> * - \ref Sn_IR_CON : <b>CON Interrupt</b> */ -#define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_IR(uint8_t N) + { + return _W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group @@ -494,7 +505,10 @@ * - @ref SOCK_TIME_WAIT : Closing state * - @ref SOCK_LAST_ACK : Closing state */ -#define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_SR(uint8_t N) + { + return _W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group @@ -502,7 +516,10 @@ * @details @ref Sn_PORT configures the source port number of Socket n. * It is valid when Socket n is used in TCP/UDP mode. It should be set before OPEN command is ordered. */ -#define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_PORT(uint8_t N) + { + return _W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group @@ -510,7 +527,10 @@ * @details @ref Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or * it indicates that it is acquired in ARP-process by CONNECT/SEND command. */ -#define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_DHAR(uint8_t N) + { + return _W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group @@ -520,7 +540,10 @@ * In TCP server mode, it indicates an IP address of TCP clientafter successfully establishing connection. * In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command. */ -#define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_DIPR(uint8_t N) + { + return _W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group @@ -530,14 +553,20 @@ * In TCP Servermode, it indicates the port number of TCP client after successfully establishing connection. * In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command. */ -#define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_DPORT(uint8_t N) + { + return _W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group * @brief Maximum Segment Size(Sn_MSSR0) register address(R/W) * @details @ref Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n. */ -#define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_MSSR(uint8_t N) + { + return _W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } // Reserved (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) @@ -547,14 +576,22 @@ * @details @ref Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n. * It is set before OPEN command. */ -#define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_TOS(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} + /** * @ingroup Socket_register_group * @brief IP Time to live(TTL) Register(R/W) * @details @ref Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n. * It is set before OPEN command. */ -#define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_TTL(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} + // Reserved (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) // Reserved (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) // Reserved (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) @@ -573,7 +610,10 @@ * user can re-configure its size using @ref Sn_RXBUF_SIZE. The total sum of @ref Sn_RXBUF_SIZE can not be exceed 16Kbytes. * When exceeded, the data reception error is occurred. */ -#define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_RXBUF_SIZE(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group @@ -584,7 +624,10 @@ * user can be re-configure its size using @ref Sn_TXBUF_SIZE. The total sum of @ref Sn_TXBUF_SIZE can not be exceed 16Kbytes. * When exceeded, the data transmission error is occurred. */ -#define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_TXBUF_SIZE(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group @@ -595,7 +638,10 @@ * transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size, * transmit the data after dividing into the checked size and saving in the Socket n TX buffer. */ -#define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_TX_FSR(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group @@ -607,7 +653,10 @@ * If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), * then the carry bit is ignored and will automatically update with the lower 16bits value. */ -#define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_TX_RD(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group @@ -621,16 +670,22 @@ * then the carry bit is ignored and will automatically update with the lower 16bits value.\n * 4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command */ -#define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_TX_WR(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group * @brief Received data size register(R) * @details @ref Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer. * @ref Sn_RX_RSR does not exceed the @ref Sn_RXBUF_SIZE and is calculated as the difference between - * �Socket n RX Write Pointer (@ref Sn_RX_WR)and �Socket n RX Read Pointer (@ref Sn_RX_RD) + * Socket n RX Write Pointer (@ref Sn_RX_WR)and Socket n RX Read Pointer (@ref Sn_RX_RD) */ -#define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_RX_RSR(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group @@ -643,7 +698,10 @@ * update with the lower 16bits value ignored the carry bit.\n * 4. Order RECV command is for notifying the updated @ref Sn_RX_RD to W5500. */ -#define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_RX_RD(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group @@ -652,7 +710,10 @@ * If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), * then the carry bit is ignored and will automatically update with the lower 16bits value. */ -#define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_RX_WR(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group @@ -662,14 +723,20 @@ * the corresponding bit of @ref Sn_IR becomes When both the corresponding bit of @ref Sn_IMR and @ref Sn_IR are and the n-th bit of @ref IR is * Host is interrupted by asserted INTn PIN to low. */ -#define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_IMR(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} /** * @ingroup Socket_register_group * @brief Fragment field value in IP header register(R/W) * @details @ref Sn_FRAG configures the FRAG(Fragment field in IP header). */ -#define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) + static inline uint32_t Sn_FRAG(uint8_t N) + { + return _W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); + } /** * @ingroup Socket_register_group @@ -682,7 +749,10 @@ * and KA packet can be transmitted by SEND_KEEP command by the host (Manual-keep-alive-process). * Manual-keep-alive-process is ignored in case of '@ref Sn_KPALVTR > 0'. */ -#define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) +static inline uint32_t Sn_KPALVTR(uint8_t N) +{ + return _W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3); +} //#define Sn_TSR(N) (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) @@ -694,7 +764,7 @@ * @brief Reset * @details If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset. */ -#define MR_RST 0x80 +const uint8_t MR_RST = 0x80; /** * @brief Wake on LAN @@ -705,7 +775,7 @@ * @note The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and * 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode. */ -#define MR_WOL 0x20 +const uint8_t MR_WOL = 0x20; /** * @brief Ping block @@ -713,7 +783,7 @@ * 1 : Enable Ping block\n * If the bit is it blocks the response to a ping request. */ -#define MR_PB 0x10 +const uint8_t MR_PB = 0x10; /** * @brief Enable PPPoE @@ -721,7 +791,7 @@ * 1 : EnablePPPoE mode\n * If you use ADSL, this bit should be */ -#define MR_PPPOE 0x08 +const uint8_t MR_PPPOE = 0x08; /** * @brief Enable UDP_FORCE_ARP CHECHK @@ -729,52 +799,52 @@ * 1 : Enable Force ARP mode\n * In Force ARP mode, It forces on sending ARP Request whenever data is sent. */ -#define MR_FARP 0x02 +const uint8_t MR_FARP = 0x02; /* IR register values */ /** * @brief Check IP conflict. * @details Bit is set as when own source IP address is same with the sender IP address in the received ARP request. */ -#define IR_CONFLICT 0x80 +const uint8_t IR_CONFLICT = 0x80; /** * @brief Get the destination unreachable message in UDP sending. * @details When receiving the ICMP (Destination port unreachable) packet, this bit is set as * When this bit is Destination Information such as IP address and Port number may be checked with the corresponding @ref UIPR & @ref UPORTR. */ -#define IR_UNREACH 0x40 +const uint8_t IR_UNREACH = 0x40; /** * @brief Get the PPPoE close message. * @details When PPPoE is disconnected during PPPoE mode, this bit is set. */ -#define IR_PPPoE 0x20 +const uint8_t IR_PPPoE = 0x20; /** * @brief Get the magic packet interrupt. * @details When WOL mode is enabled and receives the magic packet over UDP, this bit is set. */ -#define IR_MP 0x10 +const uint8_t IR_MP = 0x10; /* PHYCFGR register value */ -#define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask. -#define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value -#define PHYCFGR_OPMDC_ALLA (7<<3) -#define PHYCFGR_OPMDC_PDOWN (6<<3) -#define PHYCFGR_OPMDC_NA (5<<3) -#define PHYCFGR_OPMDC_100FA (4<<3) -#define PHYCFGR_OPMDC_100F (3<<3) -#define PHYCFGR_OPMDC_100H (2<<3) -#define PHYCFGR_OPMDC_10F (1<<3) -#define PHYCFGR_OPMDC_10H (0<<3) -#define PHYCFGR_DPX_FULL (1<<2) -#define PHYCFGR_DPX_HALF (0<<2) -#define PHYCFGR_SPD_100 (1<<1) -#define PHYCFGR_SPD_10 (0<<1) -#define PHYCFGR_LNK_ON (1<<0) -#define PHYCFGR_LNK_OFF (0<<0) +const uint8_t PHYCFGR_RST = (uint8_t)~(1<<7); //< For PHY reset, must operate AND mask. +const uint8_t PHYCFGR_OPMD = (1<<6); // Configre PHY with OPMDC value +const uint8_t PHYCFGR_OPMDC_ALLA = (7<<3); +const uint8_t PHYCFGR_OPMDC_PDOWN = (6<<3); +const uint8_t PHYCFGR_OPMDC_NA = (5<<3); +const uint8_t PHYCFGR_OPMDC_100FA = (4<<3); +const uint8_t PHYCFGR_OPMDC_100F = (3<<3); +const uint8_t PHYCFGR_OPMDC_100H = (2<<3); +const uint8_t PHYCFGR_OPMDC_10F = (1<<3); +const uint8_t PHYCFGR_OPMDC_10H = (0<<3); +const uint8_t PHYCFGR_DPX_FULL = (1<<2); +const uint8_t PHYCFGR_DPX_HALF = (0<<2); +const uint8_t PHYCFGR_SPD_100 = (1<<1); +const uint8_t PHYCFGR_SPD_10 = (0<<1); +const uint8_t PHYCFGR_LNK_ON = (1<<0); +const uint8_t PHYCFGR_LNK_OFF = (0<<0); /* IMR register values */ /** @@ -782,28 +852,28 @@ * @details 0: Disable IP Conflict Interrupt\n * 1: Enable IP Conflict Interrupt */ -#define IM_IR7 0x80 +const uint8_t IM_IR7 = 0x80; /** * @brief Destination unreachable Interrupt Mask. * @details 0: Disable Destination unreachable Interrupt\n * 1: Enable Destination unreachable Interrupt */ -#define IM_IR6 0x40 +const uint8_t IM_IR6 = 0x40; /** * @brief PPPoE Close Interrupt Mask. * @details 0: Disable PPPoE Close Interrupt\n * 1: Enable PPPoE Close Interrupt */ -#define IM_IR5 0x20 +const uint8_t IM_IR5 = 0x20; /** * @brief Magic Packet Interrupt Mask. * @details 0: Disable Magic Packet Interrupt\n * 1: Enable Magic Packet Interrupt */ -#define IM_IR4 0x10 +const uint8_t IM_IR4 = 0x10; /* Sn_MR Default values */ /** @@ -814,7 +884,7 @@ * To use multicasting, @ref Sn_DIPR & @ref Sn_DPORT should be respectively configured with the multicast group IP address & port number * before Socket n is opened by OPEN command of @ref Sn_CR. */ -#define Sn_MR_MULTI 0x80 +const uint8_t Sn_MR_MULTI = 0x80; /** * @brief Broadcast block in UDP Multicasting. @@ -823,7 +893,7 @@ * This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010.\m * In addition, This bit does when MACRAW mode(P[3:0] = 100 */ -#define Sn_MR_BCASTB 0x40 +const uint8_t Sn_MR_BCASTB = 0x40; /** * @brief No Delayed Ack(TCP), Multicast flag @@ -833,7 +903,7 @@ * When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.\n * When this bit is It sends the ACK packet after waiting for the timeout time configured by @ref _RTR_. */ -#define Sn_MR_ND 0x20 +const uint8_t Sn_MR_ND = 0x20; /** * @brief Unicast Block in UDP Multicasting @@ -841,14 +911,14 @@ * 1 : enable Unicast Blocking\n * This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI = */ -#define Sn_MR_UCASTB 0x10 +const uint8_t Sn_MR_UCASTB = 0x10; /** * @brief MAC LAYER RAW SOCK * @details This configures the protocol mode of Socket n. * @note MACRAW mode should be only used in Socket 0. */ -#define Sn_MR_MACRAW 0x04 +const uint8_t Sn_MR_MACRAW = 0x04; //#define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */ @@ -856,19 +926,19 @@ * @brief UDP * @details This configures the protocol mode of Socket n. */ -#define Sn_MR_UDP 0x02 +const uint8_t Sn_MR_UDP = 0x02; /** * @brief TCP * @details This configures the protocol mode of Socket n. */ -#define Sn_MR_TCP 0x01 +const uint8_t Sn_MR_TCP = 0x01; /** * @brief Unused socket * @details This configures the protocol mode of Socket n. */ -#define Sn_MR_CLOSE 0x00 +const uint8_t Sn_MR_CLOSE = 0x00; /* Sn_MR values used with Sn_MR_MACRAW */ /** @@ -881,7 +951,7 @@ * If user wants to implement Hybrid TCP/IP stack, * it is recommended that this bit is set as for reducing host overhead to process the all received packets. */ -#define Sn_MR_MFEN Sn_MR_MULTI +const uint8_t Sn_MR_MFEN = Sn_MR_MULTI; /** * @brief Multicast Blocking in @ref Sn_MR_MACRAW mode @@ -890,7 +960,7 @@ * This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = * It configures the version for IGMP messages (Join/Leave/Report). */ -#define Sn_MR_MMB Sn_MR_ND +const uint8_t Sn_MR_MMB = Sn_MR_ND; /** * @brief IPv6 packet Blocking in @ref Sn_MR_MACRAW mode @@ -898,7 +968,7 @@ * 1 : enable IPv6 Blocking\n * This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet. */ -#define Sn_MR_MIP6B Sn_MR_UCASTB +const uint8_t Sn_MR_MIP6B = Sn_MR_UCASTB; /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */ /** @@ -907,18 +977,18 @@ * 1 : enable Multicast Blocking\n * This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address. */ -#define Sn_MR_MC Sn_MR_ND +const uint8_t Sn_MR_MC = Sn_MR_ND; /* Sn_MR alternate values */ /** * @brief For Berkeley Socket API */ -#define SOCK_STREAM Sn_MR_TCP +const uint8_t SOCK_STREAM = Sn_MR_TCP; /** * @brief For Berkeley Socket API */ -#define SOCK_DGRAM Sn_MR_UDP +const uint8_t SOCK_DGRAM = Sn_MR_UDP; /* Sn_CR values */ @@ -934,7 +1004,7 @@ * <tr> <td>S0_MR_MACRAW (100)</td> <td>SOCK_MACRAW (0x02)</td> </tr> * </table> */ -#define Sn_CR_OPEN 0x01 +const uint8_t Sn_CR_OPEN = 0x01; /** * @brief Wait connection request in TCP mode(Server mode) @@ -945,7 +1015,7 @@ * the @ref Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the @ref Sn_IR(0) becomes * But when a TCP clientconnection request is failed, @ref Sn_IR(3) becomes and the status of @ref Sn_SR changes to SOCK_CLOSED. */ -#define Sn_CR_LISTEN 0x02 +const uint8_t Sn_CR_LISTEN = 0x02; /** * @brief Send connection request in TCP mode(Client mode) @@ -957,7 +1027,7 @@ * 3. When a @b RST packet is received instead of a @b SYN/ACK packet. In these cases, @ref Sn_SR is changed to @ref SOCK_CLOSED. * @note This is valid only in TCP mode and operates when Socket n acts as <b>TCP client</b> */ -#define Sn_CR_CONNECT 0x04 +const uint8_t Sn_CR_CONNECT = 0x04; /** * @brief Send closing request in TCP mode @@ -970,13 +1040,13 @@ * Otherwise, TCPTO occurs (\ref Sn_IR(3)='1') and then @ref Sn_SR is changed to @ref SOCK_CLOSED. * @note Valid only in TCP mode. */ -#define Sn_CR_DISCON 0x08 +const uint8_t Sn_CR_DISCON = 0x08; /** * @brief Close socket * @details Sn_SR is changed to @ref SOCK_CLOSED. */ -#define Sn_CR_CLOSE 0x10 +const uint8_t Sn_CR_CLOSE = 0x10; /** * @brief Update TX buffer pointer and send data @@ -984,7 +1054,7 @@ * For more details, please refer to Socket n TX Free Size Register (@ref Sn_TX_FSR), Socket n, * TX Write Pointer Register(@ref Sn_TX_WR), and Socket n TX Read Pointer Register(@ref Sn_TX_RD). */ -#define Sn_CR_SEND 0x20 +const uint8_t Sn_CR_SEND = 0x20; /** * @brief Send data with MAC address, so without ARP process @@ -994,7 +1064,7 @@ * In this case, the destination hardware address is acquired from @ref Sn_DHAR configured by host, instead of APR-process. * @note Valid only in UDP mode. */ -#define Sn_CR_SEND_MAC 0x21 +const uint8_t Sn_CR_SEND_MAC = 0x21; /** * @brief Send keep alive message @@ -1002,7 +1072,7 @@ * If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur. * @note Valid only in TCP mode. */ -#define Sn_CR_SEND_KEEP 0x22 +const uint8_t Sn_CR_SEND_KEEP = 0x22; /** * @brief Update RX buffer pointer and receive data @@ -1010,38 +1080,38 @@ * For more details, refer to Socket n RX Received Size Register (@ref Sn_RX_RSR), Socket n RX Write Pointer Register (@ref Sn_RX_WR), * and Socket n RX Read Pointer Register (@ref Sn_RX_RD). */ -#define Sn_CR_RECV 0x40 +const uint8_t Sn_CR_RECV = 0x40; /* Sn_IR values */ /** * @brief SEND_OK Interrupt * @details This is issued when SEND command is completed. */ -#define Sn_IR_SENDOK 0x10 +const uint8_t Sn_IR_SENDOK = 0x10; /** * @brief TIMEOUT Interrupt * @details This is issued when ARPTO or TCPTO occurs. */ -#define Sn_IR_TIMEOUT 0x08 +const uint8_t Sn_IR_TIMEOUT = 0x08; /** * @brief RECV Interrupt * @details This is issued whenever data is received from a peer. */ -#define Sn_IR_RECV 0x04 +const uint8_t Sn_IR_RECV = 0x04; /** * @brief DISCON Interrupt * @details This is issued when FIN or FIN/ACK packet is received from a peer. */ -#define Sn_IR_DISCON 0x02 +const uint8_t Sn_IR_DISCON = 0x02; /** * @brief CON Interrupt * @details This is issued one time when the connection with peer is successful and then @ref Sn_SR is changed to @ref SOCK_ESTABLISHED. */ -#define Sn_IR_CON 0x01 +const uint8_t Sn_IR_CON = 0x01; /* Sn_SR values */ /** @@ -1049,7 +1119,7 @@ * @details This indicates that Socket n is released.\n * When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to @ref SOCK_CLOSED regardless of previous status. */ -#define SOCK_CLOSED 0x00 +const uint8_t SOCK_CLOSED = 0x00; /** * @brief Initiate state @@ -1057,7 +1127,7 @@ * It is changed to @ref SOCK_INIT when @ref Sn_MR(P[3:0]) = 001 and OPEN command is ordered.\n * After @ref SOCK_INIT, user can use LISTEN /CONNECT command. */ -#define SOCK_INIT 0x13 +const uint8_t SOCK_INIT = 0x13; /** * @brief Listen state @@ -1065,7 +1135,7 @@ * It will change to @ref SOCK_ESTALBLISHED when the connection-request is successfully accepted.\n * Otherwise it will change to @ref SOCK_CLOSED after TCPTO @ref Sn_IR(TIMEOUT) = '1') is occurred. */ -#define SOCK_LISTEN 0x14 +const uint8_t SOCK_LISTEN = 0x14; /** * @brief Connection state @@ -1074,7 +1144,7 @@ * If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to @ref SOCK_ESTABLISHED.\n * Otherwise, it changes to @ref SOCK_CLOSED after TCPTO (@ref Sn_IR[TIMEOUT] = '1') is occurred. */ -#define SOCK_SYNSENT 0x15 +const uint8_t SOCK_SYNSENT = 0x15; /** * @brief Connection state @@ -1082,7 +1152,7 @@ * If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to @ref SOCK_ESTABLISHED. \n * If not, it changes to @ref SOCK_CLOSED after timeout (@ref Sn_IR[TIMEOUT] = '1') is occurred. */ -#define SOCK_SYNRECV 0x16 +const uint8_t SOCK_SYNRECV = 0x16; /** * @brief Success to connect @@ -1091,7 +1161,7 @@ * when the CONNECT command is successful.\n * During @ref SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command. */ -#define SOCK_ESTABLISHED 0x17 +const uint8_t SOCK_ESTABLISHED = 0x17; /** * @brief Closing state @@ -1099,7 +1169,7 @@ * These are shown in disconnect-process such as active-close and passive-close.\n * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. */ -#define SOCK_FIN_WAIT 0x18 +const uint8_t SOCK_FIN_WAIT = 0x18; /** * @brief Closing state @@ -1107,7 +1177,7 @@ * These are shown in disconnect-process such as active-close and passive-close.\n * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. */ -#define SOCK_CLOSING 0x1A +const uint8_t SOCK_CLOSING = 0x1A; /** * @brief Closing state @@ -1115,7 +1185,7 @@ * These are shown in disconnect-process such as active-close and passive-close.\n * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. */ -#define SOCK_TIME_WAIT 0x1B +const uint8_t SOCK_TIME_WAIT = 0x1B; /** * @brief Closing state @@ -1123,14 +1193,14 @@ * This is half-closing status, and data can be transferred.\n * For full-closing, DISCON command is used. But For just-closing, CLOSE command is used. */ -#define SOCK_CLOSE_WAIT 0x1C +const uint8_t SOCK_CLOSE_WAIT = 0x1C; /** * @brief Closing state * @details This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.\n * It changes to @ref SOCK_CLOSED when Socket n received the response successfully, or when timeout(@ref Sn_IR[TIMEOUT] = '1') is occurred. */ -#define SOCK_LAST_ACK 0x1D +const uint8_t SOCK_LAST_ACK = 0x1D; /** * @brief UDP socket @@ -1138,7 +1208,7 @@ * It changes to SOCK_UDP when @ref Sn_MR(P[3:0]) = '010' and @ref Sn_CR_OPEN command is ordered.\n * Unlike TCP mode, data can be transfered without the connection-process. */ -#define SOCK_UDP 0x22 +const uint8_t SOCK_UDP = 0x22; //#define SOCK_IPRAW 0x32 /**< IP raw mode socket */ @@ -1148,7 +1218,7 @@ * It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.\n * Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process. */ -#define SOCK_MACRAW 0x42 +const uint8_t SOCK_MACRAW = 0x42; //#define SOCK_PPPOE 0x5F @@ -1176,11 +1246,7 @@ * \sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() * \sa WIZCHIP_CRITICAL_EXIT() */ -#define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter() - -#ifdef _exit -#undef _exit -#endif +static inline void WIZCHIP_CRITICAL_ENTER() {} /** * @brief Exit a critical section @@ -1193,7 +1259,7 @@ * @sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() * @sa WIZCHIP_CRITICAL_ENTER() */ -#define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit() +static inline void WIZCHIP_CRITICAL_EXIT() { } //////////////////////// @@ -1233,7 +1299,7 @@ void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param pBuf Pointer buffer to write data * @param len Data length */ -void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); +void WIZCHIP_WRITE_BUF(uint32_t AddrSel, const uint8_t* pBuf, uint16_t len); ///////////////////////////////// // Common Register I/O function // @@ -1244,9 +1310,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)mr The value to be set. * @sa getMR() */ -#define setMR(mr) \ - WIZCHIP_WRITE(MR,mr) - +static inline void setMR(uint8_t mr) +{ + WIZCHIP_WRITE(MR, mr); +} /** * @ingroup Common_register_access_function @@ -1254,8 +1321,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. The value of Mode register. * @sa setMR() */ -#define getMR() \ - WIZCHIP_READ(MR) +static inline uint8_t getMR() +{ + return WIZCHIP_READ(MR); +} + /** * @ingroup Common_register_access_function @@ -1263,8 +1333,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes. * @sa getGAR() */ -#define setGAR(gar) \ - WIZCHIP_WRITE_BUF(GAR,gar,4) +static inline void setGAR(const uint8_t *gar) +{ + WIZCHIP_WRITE_BUF(GAR, gar, 4); +} /** * @ingroup Common_register_access_function @@ -1272,8 +1344,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes. * @sa setGAR() */ -#define getGAR(gar) \ - WIZCHIP_READ_BUF(GAR,gar,4) +static inline void getGAR(uint8_t *gar) +{ + WIZCHIP_READ_BUF(GAR, gar, 4); +} /** * @ingroup Common_register_access_function @@ -1281,8 +1355,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes. * @sa getSUBR() */ -#define setSUBR(subr) \ - WIZCHIP_WRITE_BUF(SUBR, subr,4) +static inline void setSUBR(const uint8_t *subr) +{ + WIZCHIP_WRITE_BUF(SUBR, subr, 4); +} /** @@ -1291,8 +1367,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes. * @sa setSUBR() */ -#define getSUBR(subr) \ - WIZCHIP_READ_BUF(SUBR, subr, 4) +static inline void getSUBR(uint8_t* subr) +{ + WIZCHIP_READ_BUF(SUBR, subr, 4); +} /** * @ingroup Common_register_access_function @@ -1300,8 +1378,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes. * @sa getSHAR() */ -#define setSHAR(shar) \ - WIZCHIP_WRITE_BUF(SHAR, shar, 6) +static inline void setSHAR(const uint8_t *shar) +{ + WIZCHIP_WRITE_BUF(SHAR, shar, 6); +} /** * @ingroup Common_register_access_function @@ -1309,8 +1389,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes. * @sa setSHAR() */ -#define getSHAR(shar) \ - WIZCHIP_READ_BUF(SHAR, shar, 6) +static inline void getSHAR(uint8_t *shar) +{ + WIZCHIP_READ_BUF(SHAR, shar, 6); +} /** * @ingroup Common_register_access_function @@ -1318,8 +1400,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes. * @sa getSIPR() */ -#define setSIPR(sipr) \ - WIZCHIP_WRITE_BUF(SIPR, sipr, 4) +static inline void setSIPR(const uint8_t *sipr) +{ + WIZCHIP_WRITE_BUF(SIPR, sipr, 4); +} /** * @ingroup Common_register_access_function @@ -1327,8 +1411,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes. * @sa setSIPR() */ -#define getSIPR(sipr) \ - WIZCHIP_READ_BUF(SIPR, sipr, 4) +static inline void getSIPR(uint8_t *sipr) +{ + WIZCHIP_READ_BUF(SIPR, sipr, 4); +} /** * @ingroup Common_register_access_function @@ -1336,11 +1422,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint16_t)intlevel Value to set @ref INTLEVEL register. * @sa getINTLEVEL() */ -#define setINTLEVEL(intlevel) {\ - WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \ - } - +static inline void setINTLEVEL(uint16_t intlevel) +{ + WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); +} /** * @ingroup Common_register_access_function @@ -1348,13 +1434,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint16_t. Value of @ref INTLEVEL register. * @sa setINTLEVEL() */ -//M20150401 : Type explict declaration -/* -#define getINTLEVEL() \ - ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1))) -*/ -#define getINTLEVEL() \ - (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1))) +static inline uint16_t getINTLEVEL() +{ + const uint8_t msb = WIZCHIP_READ(INTLEVEL); + return ((uint16_t)msb << 8) | WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL, 1)); +} /** * @ingroup Common_register_access_function @@ -1362,8 +1446,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)ir Value to set @ref IR register. * @sa getIR() */ -#define setIR(ir) \ - WIZCHIP_WRITE(IR, (ir & 0xF0)) +static inline void setIR(uint8_t ir) +{ + WIZCHIP_WRITE(IR, (ir & 0xF0)); +} /** * @ingroup Common_register_access_function @@ -1371,16 +1457,21 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref IR register. * @sa setIR() */ -#define getIR() \ - (WIZCHIP_READ(IR) & 0xF0) +static inline uint8_t getIR() +{ + return WIZCHIP_READ(IR) & 0xF0; +} + /** * @ingroup Common_register_access_function * @brief Set @ref _IMR_ register * @param (uint8_t)imr Value to set @ref _IMR_ register. * @sa getIMR() */ -#define setIMR(imr) \ - WIZCHIP_WRITE(_IMR_, imr) +static inline void setIMR(uint8_t imr) +{ + WIZCHIP_WRITE(_IMR_, imr); +} /** * @ingroup Common_register_access_function @@ -1388,8 +1479,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref _IMR_ register. * @sa setIMR() */ -#define getIMR() \ - WIZCHIP_READ(_IMR_) +static inline uint8_t getIMR() +{ + return WIZCHIP_READ(_IMR_); +} /** * @ingroup Common_register_access_function @@ -1397,8 +1490,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)sir Value to set @ref SIR register. * @sa getSIR() */ -#define setSIR(sir) \ - WIZCHIP_WRITE(SIR, sir) +static inline void setSIR(uint8_t sir) +{ + WIZCHIP_WRITE(SIR, sir); +} /** * @ingroup Common_register_access_function @@ -1406,16 +1501,21 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref SIR register. * @sa setSIR() */ -#define getSIR() \ - WIZCHIP_READ(SIR) +static inline uint8_t getSIR() +{ + return WIZCHIP_READ(SIR); +} + /** * @ingroup Common_register_access_function * @brief Set @ref SIMR register * @param (uint8_t)simr Value to set @ref SIMR register. * @sa getSIMR() */ -#define setSIMR(simr) \ - WIZCHIP_WRITE(SIMR, simr) +static inline void setSIMR(uint8_t simr) +{ + WIZCHIP_WRITE(SIMR, simr); +} /** * @ingroup Common_register_access_function @@ -1423,8 +1523,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref SIMR register. * @sa setSIMR() */ -#define getSIMR() \ - WIZCHIP_READ(SIMR) +static inline uint8_t getSIMR() +{ + return WIZCHIP_READ(SIMR); +} /** * @ingroup Common_register_access_function @@ -1432,10 +1534,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint16_t)rtr Value to set @ref _RTR_ register. * @sa getRTR() */ -#define setRTR(rtr) {\ - WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \ - } +static inline void setRTR(uint16_t rtr) +{ + WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); +} /** * @ingroup Common_register_access_function @@ -1443,13 +1546,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint16_t. Value of @ref _RTR_ register. * @sa setRTR() */ -//M20150401 : Type explict declaration -/* -#define getRTR() \ - ((WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1))) -*/ -#define getRTR() \ - (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1))) +static inline uint16_t getRTR() +{ + const uint8_t msb = WIZCHIP_READ(_RTR_); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_, 1)); +} /** @@ -1458,8 +1559,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)rcr Value to set @ref _RCR_ register. * @sa getRCR() */ -#define setRCR(rcr) \ - WIZCHIP_WRITE(_RCR_, rcr) +static inline void setRCR(uint8_t rcr) +{ + WIZCHIP_WRITE(_RCR_, rcr); +} /** * @ingroup Common_register_access_function @@ -1467,8 +1570,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref _RCR_ register. * @sa setRCR() */ -#define getRCR() \ - WIZCHIP_READ(_RCR_) +static inline uint8_t getRCR() +{ + return WIZCHIP_READ(_RCR_); +} //================================================== test done =========================================================== @@ -1478,8 +1583,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)ptimer Value to set @ref PTIMER register. * @sa getPTIMER() */ -#define setPTIMER(ptimer) \ - WIZCHIP_WRITE(PTIMER, ptimer) +static inline void setPTIMER(uint8_t ptimer) +{ + WIZCHIP_WRITE(PTIMER, ptimer); +} /** * @ingroup Common_register_access_function @@ -1487,8 +1594,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref PTIMER register. * @sa setPTIMER() */ -#define getPTIMER() \ - WIZCHIP_READ(PTIMER) +static inline uint8_t getPTIMER() +{ + return WIZCHIP_READ(PTIMER); +} /** * @ingroup Common_register_access_function @@ -1496,8 +1605,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)pmagic Value to set @ref PMAGIC register. * @sa getPMAGIC() */ -#define setPMAGIC(pmagic) \ - WIZCHIP_WRITE(PMAGIC, pmagic) +static inline void setPMAGIC(uint8_t pmagic) +{ + WIZCHIP_WRITE(PMAGIC, pmagic); +} /** * @ingroup Common_register_access_function @@ -1505,8 +1616,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref PMAGIC register. * @sa setPMAGIC() */ -#define getPMAGIC() \ - WIZCHIP_READ(PMAGIC) +static inline uint8_t getPMAGIC() +{ + return WIZCHIP_READ(PMAGIC); +} /** * @ingroup Common_register_access_function @@ -1514,8 +1627,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)phar Pointer variable to set PPP destination MAC register address. It should be allocated 6 bytes. * @sa getPHAR() */ -#define setPHAR(phar) \ - WIZCHIP_WRITE_BUF(PHAR, phar, 6) +static inline void setPHAR(const uint8_t *phar) +{ + WIZCHIP_WRITE_BUF(PHAR, phar, 6); +} /** * @ingroup Common_register_access_function @@ -1523,8 +1638,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)phar Pointer variable to PPP destination MAC register address. It should be allocated 6 bytes. * @sa setPHAR() */ -#define getPHAR(phar) \ - WIZCHIP_READ_BUF(PHAR, phar, 6) +static inline void getPHAR(uint8_t *phar) +{ + WIZCHIP_READ_BUF(PHAR, phar, 6); +} /** * @ingroup Common_register_access_function @@ -1532,10 +1649,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint16_t)psid Value to set @ref PSID register. * @sa getPSID() */ -#define setPSID(psid) {\ - WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \ - } +static inline void setPSID(uint16_t psid) +{ + WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); +} /** * @ingroup Common_register_access_function @@ -1543,14 +1661,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint16_t. Value of @ref PSID register. * @sa setPSID() */ -//uint16_t getPSID(void); -//M20150401 : Type explict declaration -/* -#define getPSID() \ - ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1))) -*/ -#define getPSID() \ - (((uint16_t)WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1))) +static inline uint16_t getPSID() +{ + const uint8_t msb = WIZCHIP_READ(PSID); + return ((uint16_t)msb << 8) | WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)); +} /** * @ingroup Common_register_access_function @@ -1558,10 +1673,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint16_t)pmru Value to set @ref PMRU register. * @sa getPMRU() */ -#define setPMRU(pmru) { \ - WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \ - } +static inline void setPMRU(uint16_t pmru) +{ + WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); +} /** * @ingroup Common_register_access_function @@ -1569,39 +1685,32 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint16_t. Value of @ref PMRU register. * @sa setPMRU() */ -//M20150401 : Type explict declaration -/* -#define getPMRU() \ - ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1))) -*/ -#define getPMRU() \ - (((uint16_t)WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1))) +static inline uint16_t getPMRU() +{ + const uint8_t msb = WIZCHIP_READ(PMRU); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU, 1)); +} /** * @ingroup Common_register_access_function * @brief Get unreachable IP address * @param (uint8_t*)uipr Pointer variable to get unreachable IP address. It should be allocated 4 bytes. */ -//M20150401 : Size Error of UIPR (6 -> 4) -/* -#define getUIPR(uipr) \ - WIZCHIP_READ_BUF(UIPR,uipr,6) -*/ -#define getUIPR(uipr) \ - WIZCHIP_READ_BUF(UIPR,uipr,4) +static inline void getUIPR(uint8_t *uipr) +{ + WIZCHIP_READ_BUF(UIPR, uipr, 4); +} /** * @ingroup Common_register_access_function * @brief Get @ref UPORTR register * @return uint16_t. Value of @ref UPORTR register. */ -//M20150401 : Type explict declaration -/* -#define getUPORTR() \ - ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1))) -*/ -#define getUPORTR() \ - (((uint16_t)WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1))) +static inline uint16_t getUPORTR() +{ + const uint8_t msb = WIZCHIP_READ(UPORTR); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR, 1)); +} /** * @ingroup Common_register_access_function @@ -1609,8 +1718,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)phycfgr Value to set @ref PHYCFGR register. * @sa getPHYCFGR() */ -#define setPHYCFGR(phycfgr) \ - WIZCHIP_WRITE(PHYCFGR, phycfgr) +static inline void setPHYCFGR(uint8_t phycfgr) +{ + WIZCHIP_WRITE(PHYCFGR, phycfgr); +} /** * @ingroup Common_register_access_function @@ -1618,16 +1729,20 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref PHYCFGR register. * @sa setPHYCFGR() */ -#define getPHYCFGR() \ - WIZCHIP_READ(PHYCFGR) +static inline uint8_t getPHYCFGR() +{ + return WIZCHIP_READ(PHYCFGR); +} /** * @ingroup Common_register_access_function * @brief Get @ref VERSIONR register * @return uint8_t. Value of @ref VERSIONR register. */ -#define getVERSIONR() \ - WIZCHIP_READ(VERSIONR) +static inline uint8_t getVERSIONR() +{ + return WIZCHIP_READ(VERSIONR); +} ///////////////////////////////////// @@ -1641,8 +1756,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)mr Value to set @ref Sn_MR * @sa getSn_MR() */ -#define setSn_MR(sn, mr) \ - WIZCHIP_WRITE(Sn_MR(sn),mr) +static inline void setSn_MR(uint8_t sn, uint8_t mr) +{ + WIZCHIP_WRITE(Sn_MR(sn), mr); +} /** * @ingroup Socket_register_access_function @@ -1651,8 +1768,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref Sn_MR. * @sa setSn_MR() */ -#define getSn_MR(sn) \ - WIZCHIP_READ(Sn_MR(sn)) +static inline uint8_t getSn_MR(uint8_t sn) +{ + return WIZCHIP_READ(Sn_MR(sn)); +} /** * @ingroup Socket_register_access_function @@ -1661,8 +1780,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)cr Value to set @ref Sn_CR * @sa getSn_CR() */ -#define setSn_CR(sn, cr) \ - WIZCHIP_WRITE(Sn_CR(sn), cr) +static inline void setSn_CR(uint8_t sn, uint8_t cr) +{ + WIZCHIP_WRITE(Sn_CR(sn), cr); +} /** * @ingroup Socket_register_access_function @@ -1671,8 +1792,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref Sn_CR. * @sa setSn_CR() */ -#define getSn_CR(sn) \ - WIZCHIP_READ(Sn_CR(sn)) +static inline uint8_t getSn_CR(uint8_t sn) +{ + return WIZCHIP_READ(Sn_CR(sn)); +} /** * @ingroup Socket_register_access_function @@ -1681,8 +1804,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)ir Value to set @ref Sn_IR * @sa getSn_IR() */ -#define setSn_IR(sn, ir) \ - WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F)) +static inline void setSn_IR(uint8_t sn, uint8_t ir) +{ + WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F)); +} /** * @ingroup Socket_register_access_function @@ -1691,8 +1816,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref Sn_IR. * @sa setSn_IR() */ -#define getSn_IR(sn) \ - (WIZCHIP_READ(Sn_IR(sn)) & 0x1F) +static inline uint8_t getSn_IR(uint8_t sn) +{ + return WIZCHIP_READ(Sn_IR(sn)) & 0x1F; +} /** * @ingroup Socket_register_access_function @@ -1701,8 +1828,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)imr Value to set @ref Sn_IMR * @sa getSn_IMR() */ -#define setSn_IMR(sn, imr) \ - WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F)) +static inline void setSn_IMR(uint8_t sn, uint8_t imr) +{ + WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F)); +} /** * @ingroup Socket_register_access_function @@ -1711,8 +1840,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref Sn_IMR. * @sa setSn_IMR() */ -#define getSn_IMR(sn) \ - (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F) +static inline uint8_t getSn_IMR(uint8_t sn) +{ + return WIZCHIP_READ(Sn_IMR(sn)) & 0x1F; +} /** * @ingroup Socket_register_access_function @@ -1720,8 +1851,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. * @return uint8_t. Value of @ref Sn_SR. */ -#define getSn_SR(sn) \ - WIZCHIP_READ(Sn_SR(sn)) +static inline uint8_t getSn_SR(uint8_t sn) +{ + return WIZCHIP_READ(Sn_SR(sn)); +} /** * @ingroup Socket_register_access_function @@ -1730,10 +1863,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint16_t)port Value to set @ref Sn_PORT. * @sa getSn_PORT() */ -#define setSn_PORT(sn, port) { \ - WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \ - } +static inline void setSn_PORT(uint8_t sn, uint16_t port) +{ + WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn), 1), (uint8_t) port); +} /** * @ingroup Socket_register_access_function @@ -1742,13 +1876,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint16_t. Value of @ref Sn_PORT. * @sa setSn_PORT() */ -//M20150401 : Type explict declaration -/* -#define getSn_PORT(sn) \ - ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1))) -*/ -#define getSn_PORT(sn) \ - (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1))) +static inline uint16_t getSn_PORT(uint8_t sn) +{ + const uint8_t msb = WIZCHIP_READ(Sn_PORT(sn)); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn), 1)); +} /** * @ingroup Socket_register_access_function @@ -1757,8 +1889,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)dhar Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes. * @sa getSn_DHAR() */ -#define setSn_DHAR(sn, dhar) \ - WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6) +static inline void setSn_DHAR(uint8_t sn, const uint8_t *dhar) +{ + WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6); +} /** * @ingroup Socket_register_access_function @@ -1767,8 +1901,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)dhar Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes. * @sa setSn_DHAR() */ -#define getSn_DHAR(sn, dhar) \ - WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6) +static inline void getSn_DHAR(uint8_t sn, uint8_t *dhar) +{ + WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6); +} /** * @ingroup Socket_register_access_function @@ -1777,8 +1913,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)dipr Pointer variable to set socket n destination IP address. It should be allocated 4 bytes. * @sa getSn_DIPR() */ -#define setSn_DIPR(sn, dipr) \ - WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4) +static inline void setSn_DIPR(uint8_t sn, const uint8_t *dipr) +{ + WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4); +} /** * @ingroup Socket_register_access_function @@ -1787,8 +1925,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t*)dipr Pointer variable to get socket n destination IP address. It should be allocated 4 bytes. * @sa setSn_DIPR() */ -#define getSn_DIPR(sn, dipr) \ - WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4) +static inline void getSn_DIPR(uint8_t sn, uint8_t *dipr) +{ + WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4); +} /** * @ingroup Socket_register_access_function @@ -1797,10 +1937,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint16_t)dport Value to set @ref Sn_DPORT * @sa getSn_DPORT() */ -#define setSn_DPORT(sn, dport) { \ - WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \ - } +static inline void setSn_DPORT(uint8_t sn, uint16_t dport) +{ + WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn), 1), (uint8_t) dport); +} /** * @ingroup Socket_register_access_function @@ -1809,13 +1950,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint16_t. Value of @ref Sn_DPORT. * @sa setSn_DPORT() */ -//M20150401 : Type explict declaration -/* -#define getSn_DPORT(sn) \ - ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1))) -*/ -#define getSn_DPORT(sn) \ - (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1))) +static inline uint16_t getSn_DPORT(uint8_t sn) +{ + const uint8_t msb = WIZCHIP_READ(Sn_DPORT(sn)); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)); +} /** * @ingroup Socket_register_access_function @@ -1824,10 +1963,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint16_t)mss Value to set @ref Sn_MSSR * @sa setSn_MSSR() */ -#define setSn_MSSR(sn, mss) { \ - WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \ - } +static inline void setSn_MSSR(uint8_t sn, uint16_t mss) +{ + WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn), 1), (uint8_t) mss); +} /** * @ingroup Socket_register_access_function @@ -1836,13 +1976,11 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint16_t. Value of @ref Sn_MSSR. * @sa setSn_MSSR() */ -//M20150401 : Type explict declaration -/* -#define getSn_MSSR(sn) \ - ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1))) -*/ -#define getSn_MSSR(sn) \ - (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1))) +static inline uint16_t getSn_MSSR(uint8_t sn) +{ + const uint8_t msb = WIZCHIP_READ(Sn_MSSR(sn)); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn), 1)); +} /** * @ingroup Socket_register_access_function @@ -1851,8 +1989,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)tos Value to set @ref Sn_TOS * @sa getSn_TOS() */ -#define setSn_TOS(sn, tos) \ - WIZCHIP_WRITE(Sn_TOS(sn), tos) +static inline void setSn_TOS(uint8_t sn, uint8_t tos) +{ + WIZCHIP_WRITE(Sn_TOS(sn), tos); +} /** * @ingroup Socket_register_access_function @@ -1861,8 +2001,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of Sn_TOS. * @sa setSn_TOS() */ -#define getSn_TOS(sn) \ - WIZCHIP_READ(Sn_TOS(sn)) +static inline uint8_t getSn_TOS(uint8_t sn) +{ + return WIZCHIP_READ(Sn_TOS(sn)); +} /** * @ingroup Socket_register_access_function @@ -1871,8 +2013,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)ttl Value to set @ref Sn_TTL * @sa getSn_TTL() */ -#define setSn_TTL(sn, ttl) \ - WIZCHIP_WRITE(Sn_TTL(sn), ttl) +static inline void setSn_TTL(uint8_t sn, uint8_t ttl) +{ + WIZCHIP_WRITE(Sn_TTL(sn), ttl); +} /** @@ -1882,8 +2026,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref Sn_TTL. * @sa setSn_TTL() */ -#define getSn_TTL(sn) \ - WIZCHIP_READ(Sn_TTL(sn)) +static inline uint8_t getSn_TTL(uint8_t sn) +{ + return WIZCHIP_READ(Sn_TTL(sn)); +} /** @@ -1893,8 +2039,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)rxbufsize Value to set @ref Sn_RXBUF_SIZE * @sa getSn_RXBUF_SIZE() */ -#define setSn_RXBUF_SIZE(sn, rxbufsize) \ - WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize) +static inline void setSn_RXBUF_SIZE(uint8_t sn, uint8_t rxbufsize) +{ + WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize); +} /** @@ -1904,8 +2052,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref Sn_RXBUF_SIZE. * @sa setSn_RXBUF_SIZE() */ -#define getSn_RXBUF_SIZE(sn) \ - WIZCHIP_READ(Sn_RXBUF_SIZE(sn)) +static inline uint8_t getSn_RXBUF_SIZE(uint8_t sn) +{ + return WIZCHIP_READ(Sn_RXBUF_SIZE(sn)); +} /** * @ingroup Socket_register_access_function @@ -1914,8 +2064,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @param (uint8_t)txbufsize Value to set @ref Sn_TXBUF_SIZE * @sa getSn_TXBUF_SIZE() */ -#define setSn_TXBUF_SIZE(sn, txbufsize) \ - WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize) +static inline void setSn_TXBUF_SIZE(uint8_t sn, uint8_t txbufsize) +{ + WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize); +} /** * @ingroup Socket_register_access_function @@ -1924,8 +2076,10 @@ void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); * @return uint8_t. Value of @ref Sn_TXBUF_SIZE. * @sa setSn_TXBUF_SIZE() */ -#define getSn_TXBUF_SIZE(sn) \ - WIZCHIP_READ(Sn_TXBUF_SIZE(sn)) +static inline uint8_t getSn_TXBUF_SIZE(uint8_t sn) +{ + return WIZCHIP_READ(Sn_TXBUF_SIZE(sn)); +} /** * @ingroup Socket_register_access_function @@ -1941,13 +2095,11 @@ uint16_t getSn_TX_FSR(uint8_t sn); * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. * @return uint16_t. Value of @ref Sn_TX_RD. */ -//M20150401 : Type explict declaration -/* -#define getSn_TX_RD(sn) \ - ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1))) -*/ -#define getSn_TX_RD(sn) \ - (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1))) +static inline uint16_t getSn_TX_RD(uint8_t sn) +{ + const uint8_t msb = WIZCHIP_READ(Sn_TX_RD(sn)); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)); +} /** * @ingroup Socket_register_access_function @@ -1956,10 +2108,11 @@ uint16_t getSn_TX_FSR(uint8_t sn); * @param (uint16_t)txwr Value to set @ref Sn_TX_WR * @sa GetSn_TX_WR() */ -#define setSn_TX_WR(sn, txwr) { \ - WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \ - } +static inline void setSn_TX_WR(uint8_t sn, uint16_t txwr) +{ + WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn), 1), (uint8_t) txwr); +} /** * @ingroup Socket_register_access_function @@ -1968,13 +2121,11 @@ uint16_t getSn_TX_FSR(uint8_t sn); * @return uint16_t. Value of @ref Sn_TX_WR. * @sa setSn_TX_WR() */ -//M20150401 : Type explict declaration -/* -#define getSn_TX_WR(sn) \ - ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1))) -*/ -#define getSn_TX_WR(sn) \ - (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1))) +static inline uint16_t getSn_TX_WR(uint8_t sn) +{ + const uint8_t msb = WIZCHIP_READ(Sn_TX_WR(sn)); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)); +} /** @@ -1993,10 +2144,11 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @param (uint16_t)rxrd Value to set @ref Sn_RX_RD * @sa getSn_RX_RD() */ -#define setSn_RX_RD(sn, rxrd) { \ - WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \ - } +static inline void setSn_RX_RD(uint8_t sn, uint16_t rxrd) +{ + WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); +} /** * @ingroup Socket_register_access_function @@ -2005,13 +2157,11 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @return uint16_t. Value of @ref Sn_RX_RD. * @sa setSn_RX_RD() */ -//M20150401 : Type explict declaration -/* -#define getSn_RX_RD(sn) \ - ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1))) -*/ -#define getSn_RX_RD(sn) \ - (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1))) +static inline uint16_t getSn_RX_RD(uint8_t sn) +{ + const uint8_t msb = WIZCHIP_READ(Sn_RX_RD(sn)); + return ((uint16_t)msb << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn), 1)); +} /** * @ingroup Socket_register_access_function @@ -2019,13 +2169,11 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. * @return uint16_t. Value of @ref Sn_RX_WR. */ -//M20150401 : Type explict declaration -/* -#define getSn_RX_WR(sn) \ - ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1))) -*/ -#define getSn_RX_WR(sn) \ - (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1))) +static inline uint16_t getSn_RX_WR(uint8_t sn) +{ + const uint8_t msb = WIZCHIP_READ(Sn_RX_WR(sn)); + return ((uint16_t)msb << 8) | WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn), 1)); +} /** * @ingroup Socket_register_access_function @@ -2034,10 +2182,11 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @param (uint16_t)frag Value to set @ref Sn_FRAG * @sa getSn_FRAD() */ -#define setSn_FRAG(sn, frag) { \ - WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \ - WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \ - } +static inline void setSn_FRAG(uint8_t sn, uint16_t frag) +{ + WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >> 8)); + WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); +} /** * @ingroup Socket_register_access_function @@ -2046,13 +2195,11 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @return uint16_t. Value of @ref Sn_FRAG. * @sa setSn_FRAG() */ -//M20150401 : Type explict declaration -/* -#define getSn_FRAG(sn) \ - ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1))) -*/ -#define getSn_FRAG(sn) \ - (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1))) +static inline uint16_t getSn_FRAG(uint8_t sn) +{ + const uint8_t msb = WIZCHIP_READ(Sn_FRAG(sn)); + return ((uint16_t)msb << 8) | WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)); +} /** * @ingroup Socket_register_access_function @@ -2061,8 +2208,10 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @param (uint8_t)kpalvt Value to set @ref Sn_KPALVTR * @sa getSn_KPALVTR() */ -#define setSn_KPALVTR(sn, kpalvt) \ - WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt) +static inline void setSn_KPALVTR(uint8_t sn, uint8_t kpalvt) +{ + WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt); +} /** * @ingroup Socket_register_access_function @@ -2071,8 +2220,10 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @return uint8_t. Value of @ref Sn_KPALVTR. * @sa setSn_KPALVTR() */ -#define getSn_KPALVTR(sn) \ - WIZCHIP_READ(Sn_KPALVTR(sn)) +static inline uint8_t getSn_KPALVTR(uint8_t sn) +{ + return WIZCHIP_READ(Sn_KPALVTR(sn)); +} ////////////////////////////////////// @@ -2085,13 +2236,10 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. * @return uint16_t. Value of Socket n RX max buffer size. */ -//M20150401 : Type explict declaration -/* -#define getSn_RxMAX(sn) \ - (getSn_RXBUF_SIZE(sn) << 10) -*/ -#define getSn_RxMAX(sn) \ - (((uint16_t)getSn_RXBUF_SIZE(sn)) << 10) +static inline uint16_t getSn_RxMAX(uint8_t sn) +{ + return ((uint16_t)getSn_RXBUF_SIZE(sn)) << 10; +} /** * @brief Socket_register_access_function @@ -2099,13 +2247,10 @@ uint16_t getSn_RX_RSR(uint8_t sn); * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. * @return uint16_t. Value of Socket n TX max buffer size. */ -//M20150401 : Type explict declaration -/* -#define getSn_TxMAX(sn) \ - (getSn_TXBUF_SIZE(sn) << 10) -*/ -#define getSn_TxMAX(sn) \ - (((uint16_t)getSn_TXBUF_SIZE(sn)) << 10) +static inline uint16_t getSn_TxMAX(uint8_t sn) +{ + return ((uint16_t)getSn_TXBUF_SIZE(sn)) << 10; +} /** * @ingroup Basic_IO_function @@ -2148,8 +2293,4 @@ void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len); */ void wiz_recv_ignore(uint8_t sn, uint16_t len); -/// @cond DOXY_APPLY_CODE -#endif -/// @endcond - #endif // _W5500_H_ |