Attempted to merge in changes from upstream. Scary\!

48 files changed, 1790 insertions, 821 deletions

diff --git a/FastLED.h b/FastLED.h
index 8fe2b55c..d2d4b649 100644
--- a/FastLED.h
+++ b/FastLED.h
@@ -8,12 +8,12 @@
 #define FASTLED_HAS_PRAGMA_MESSAGE
 #endif
 
-#define FASTLED_VERSION 3002009
+#define FASTLED_VERSION 3003002
 #ifndef FASTLED_INTERNAL
 #  ifdef FASTLED_HAS_PRAGMA_MESSAGE
-#    pragma message "FastLED version 3.002.009"
+#    pragma message "FastLED version 3.003.002"
 #  else
-#    warning FastLED version 3.002.009  (Not really a warning, just telling you here.)
+#    warning FastLED version 3.003.002  (Not really a warning, just telling you here.)
 #  endif
 #endif
 
@@ -315,6 +315,14 @@ public:
 		return addLeds(&c, data, nLedsOrOffset, nLedsIfOffset);
 	}
 
+#if defined(__FASTLED_HAS_FIBCC) && (__FASTLED_HAS_FIBCC == 1)
+  template<uint8_t NUM_LANES, template<uint8_t DATA_PIN, EOrder RGB_ORDER> class CHIPSET, uint8_t DATA_PIN, EOrder RGB_ORDER=RGB>
+  static CLEDController &addLeds(struct CRGB *data, int nLeds) {
+    static __FIBCC<CHIPSET, DATA_PIN, NUM_LANES, RGB_ORDER> c;
+    return addLeds(&c, data, nLeds);
+  }
+#endif
+
 	#ifdef FASTSPI_USE_DMX_SIMPLE
 	template<EClocklessChipsets CHIPSET, uint8_t DATA_PIN, EOrder RGB_ORDER=RGB>
 	static CLEDController &addLeds(struct CRGB *data, int nLedsOrOffset, int nLedsIfOffset = 0)
diff --git a/PORTING.md b/PORTING.md
index 2b4ade2e..2f925ab2 100644
--- a/PORTING.md
+++ b/PORTING.md
@@ -1,5 +1,31 @@
 =New platform porting guide=
 
+== Fast porting for a new board on existing hardware ==
+
+Sometimes "porting" FastLED simply consists of supplying new pin definitions for the given platform.  For example, platforms/avr/fastpin_avr.h contains various pin definitions for all the AVR variant chipsets/boards that FastLED supports.  Defining a set of pins involves setting up a set of definitions - for example here's one full set from the avr fastpin file:
+
+```
+#elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__)
+
+_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D);
+
+#define MAX_PIN 31
+_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B); _FL_DEFPIN(3, 3, B);
+_FL_DEFPIN(4, 4, B); _FL_DEFPIN(5, 5, B); _FL_DEFPIN(6, 6, B); _FL_DEFPIN(7, 7, B);
+_FL_DEFPIN(8, 0, D); _FL_DEFPIN(9, 1, D); _FL_DEFPIN(10, 2, D); _FL_DEFPIN(11, 3, D);
+_FL_DEFPIN(12, 4, D); _FL_DEFPIN(13, 5, D); _FL_DEFPIN(14, 6, D); _FL_DEFPIN(15, 7, D);
+_FL_DEFPIN(16, 0, C); _FL_DEFPIN(17, 1, C); _FL_DEFPIN(18, 2, C); _FL_DEFPIN(19, 3, C);
+_FL_DEFPIN(20, 4, C); _FL_DEFPIN(21, 5, C); _FL_DEFPIN(22, 6, C); _FL_DEFPIN(23, 7, C);
+_FL_DEFPIN(24, 0, A); _FL_DEFPIN(25, 1, A); _FL_DEFPIN(26, 2, A); _FL_DEFPIN(27, 3, A);
+_FL_DEFPIN(28, 4, A); _FL_DEFPIN(29, 5, A); _FL_DEFPIN(30, 6, A); _FL_DEFPIN(31, 7, A);
+
+#define HAS_HARDWARE_PIN_SUPPORT 1
+```
+
+The ```_FL_IO``` macro is used to define the port registers for the platform while the ```_FL_DEFPIN``` macro is used to define pins.  The parameters to the macro are the pin number, the bit on the port that represents that pin, and the port identifier itself.  On some platforms, like the AVR, ports are identified by letter.  On other platforms, like arm, ports are identified by number.
+
+The ```HAS_HARDWARE_PIN_SUPPORT``` define tells the rest of the FastLED library that there is hardware pin support available.  There may be other platform specific defines for things like hardware SPI ports and such.
+
 == Setting up the basic files/folders ==
 
 * Create platform directory (e.g. platforms/arm/kl26)
diff --git a/README.md b/README.md
index 11a4fd71..0069329e 100644
--- a/README.md
+++ b/README.md
@@ -4,7 +4,7 @@
 IMPORTANT NOTE: For AVR based systems, avr-gcc 4.8.x is supported and tested.  This means Arduino 1.6.5 and later.
 
 
-FastLED 3.2
+FastLED 3.3
 ===========
 
 This is a library for easily & efficiently controlling a wide variety of LED chipsets, like the ones
@@ -68,13 +68,14 @@ Right now the library is supported on a variety of arduino compatable platforms.
 * Arduino & compatibles - straight up arduino devices, uno, duo, leonardo, mega, nano, etc...
 * Arduino Yún
 * Adafruit Trinket & Gemma - Trinket Pro may be supported, but haven't tested to confirm yet
-* Teensy 2, Teensy++ 2, Teensy 3.0, Teensy 3.1/3.2, Teensy LC - arduino compataible from pjrc.com with some extra goodies (note the teensy 3, 3.1, and LC are ARM, not AVR!)
+* Teensy 2, Teensy++ 2, Teensy 3.0, Teensy 3.1/3.2, Teensy LC, Teensy 3.5, Teensy 3.6, and Teensy 4.0 - arduino compataible from pjrc.com with some extra goodies (note the teensy 3, 3.1, and LC are ARM, not AVR!)
 * Arduino Due and the digistump DigiX
 * RFDuino
 * SparkCore
 * Arduino Zero
 * ESP8266 using the arduino board definitions from http://arduino.esp8266.com/stable/package_esp8266com_index.json - please be sure to also read https://github.com/FastLED/FastLED/wiki/ESP8266-notes for information specific to the 8266.
 * The wino board - http://wino-board.com
+* ESP32 based boards
 
 What types of platforms are we thinking about supporting in the future?  Here's a short list:  ChipKit32, Maple, Beagleboard
 
diff --git a/chipsets.h b/chipsets.h
index d452abfe..8e9051d5 100644
--- a/chipsets.h
+++ b/chipsets.h
@@ -77,7 +77,7 @@ protected:
 /// @tparam CLOCK_PIN the clock pin for these leds
 /// @tparam RGB_ORDER the RGB ordering for these leds
 /// @tparam SPI_SPEED the clock divider used for these leds.  Set using the DATA_RATE_MHZ/DATA_RATE_KHZ macros.  Defaults to DATA_RATE_MHZ(12)
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB,  uint8_t SPI_SPEED = DATA_RATE_MHZ(12) >
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB,  uint32_t SPI_SPEED = DATA_RATE_MHZ(12) >
 class LPD8806Controller : public CPixelLEDController<RGB_ORDER> {
 	typedef SPIOutput<DATA_PIN, CLOCK_PIN, SPI_SPEED> SPI;
 
@@ -118,7 +118,7 @@ protected:
 /// @tparam CLOCK_PIN the clock pin for these leds
 /// @tparam RGB_ORDER the RGB ordering for these leds
 /// @tparam SPI_SPEED the clock divider used for these leds.  Set using the DATA_RATE_MHZ/DATA_RATE_KHZ macros.  Defaults to DATA_RATE_MHZ(1)
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint8_t SPI_SPEED = DATA_RATE_MHZ(1)>
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint32_t SPI_SPEED = DATA_RATE_MHZ(1)>
 class WS2801Controller : public CPixelLEDController<RGB_ORDER> {
 	typedef SPIOutput<DATA_PIN, CLOCK_PIN, SPI_SPEED> SPI;
 	SPI mSPI;
@@ -140,7 +140,7 @@ protected:
 	}
 };
 
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint8_t SPI_SPEED = DATA_RATE_MHZ(25)>
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint32_t SPI_SPEED = DATA_RATE_MHZ(25)>
 class WS2803Controller : public WS2801Controller<DATA_PIN, CLOCK_PIN, RGB_ORDER, SPI_SPEED> {};
 
 /// LPD6803 controller class (LPD1101).
@@ -151,7 +151,7 @@ class WS2803Controller : public WS2801Controller<DATA_PIN, CLOCK_PIN, RGB_ORDER,
 /// @tparam CLOCK_PIN the clock pin for these leds
 /// @tparam RGB_ORDER the RGB ordering for these leds
 /// @tparam SPI_SPEED the clock divider used for these leds.  Set using the DATA_RATE_MHZ/DATA_RATE_KHZ macros.  Defaults to DATA_RATE_MHZ(12)
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint8_t SPI_SPEED = DATA_RATE_MHZ(12)>
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint32_t SPI_SPEED = DATA_RATE_MHZ(12)>
 class LPD6803Controller : public CPixelLEDController<RGB_ORDER> {
 	typedef SPIOutput<DATA_PIN, CLOCK_PIN, SPI_SPEED> SPI;
 	SPI mSPI;
@@ -201,7 +201,7 @@ protected:
 /// @tparam CLOCK_PIN the clock pin for these leds
 /// @tparam RGB_ORDER the RGB ordering for these leds
 /// @tparam SPI_SPEED the clock divider used for these leds.  Set using the DATA_RATE_MHZ/DATA_RATE_KHZ macros.  Defaults to DATA_RATE_MHZ(12)
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint8_t SPI_SPEED = DATA_RATE_MHZ(12)>
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint32_t SPI_SPEED = DATA_RATE_MHZ(12)>
 class APA102Controller : public CPixelLEDController<RGB_ORDER> {
 	typedef SPIOutput<DATA_PIN, CLOCK_PIN, SPI_SPEED> SPI;
 	SPI mSPI;
@@ -266,7 +266,7 @@ protected:
 /// @tparam CLOCK_PIN the clock pin for these leds
 /// @tparam RGB_ORDER the RGB ordering for these leds
 /// @tparam SPI_SPEED the clock divider used for these leds.  Set using the DATA_RATE_MHZ/DATA_RATE_KHZ macros.  Defaults to DATA_RATE_MHZ(24)
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint8_t SPI_SPEED = DATA_RATE_MHZ(24)>
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint32_t SPI_SPEED = DATA_RATE_MHZ(24)>
 class SK9822Controller : public CPixelLEDController<RGB_ORDER> {
 	typedef SPIOutput<DATA_PIN, CLOCK_PIN, SPI_SPEED> SPI;
 	SPI mSPI;
@@ -340,7 +340,7 @@ protected:
 /// @tparam CLOCK_PIN the clock pin for these leds
 /// @tparam RGB_ORDER the RGB ordering for these leds
 /// @tparam SPI_SPEED the clock divider used for these leds.  Set using the DATA_RATE_MHZ/DATA_RATE_KHZ macros.  Defaults to DATA_RATE_MHZ(10)
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint8_t SPI_SPEED = DATA_RATE_MHZ(10)>
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint32_t SPI_SPEED = DATA_RATE_MHZ(10)>
 class P9813Controller : public CPixelLEDController<RGB_ORDER> {
 	typedef SPIOutput<DATA_PIN, CLOCK_PIN, SPI_SPEED> SPI;
 	SPI mSPI;
@@ -390,7 +390,7 @@ protected:
 /// @tparam CLOCK_PIN the clock pin for these leds
 /// @tparam RGB_ORDER the RGB ordering for these leds
 /// @tparam SPI_SPEED the clock divider used for these leds.  Set using the DATA_RATE_MHZ/DATA_RATE_KHZ macros.  Defaults to DATA_RATE_MHZ(16)
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint8_t SPI_SPEED = DATA_RATE_MHZ(16)>
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, EOrder RGB_ORDER = RGB, uint32_t SPI_SPEED = DATA_RATE_MHZ(16)>
 class SM16716Controller : public CPixelLEDController<RGB_ORDER> {
 	typedef SPIOutput<DATA_PIN, CLOCK_PIN, SPI_SPEED> SPI;
 	SPI mSPI;
@@ -398,10 +398,15 @@ class SM16716Controller : public CPixelLEDController<RGB_ORDER> {
 	void writeHeader() {
 		// Write out 50 zeros to the spi line (6 blocks of 8 followed by two single bit writes)
 		mSPI.select();
-		mSPI.writeBytesValueRaw(0, 6);
-		mSPI.waitFully();
 		mSPI.template writeBit<0>(0);
+		mSPI.writeByte(0);
+		mSPI.writeByte(0);
+		mSPI.writeByte(0);
 		mSPI.template writeBit<0>(0);
+		mSPI.writeByte(0);
+		mSPI.writeByte(0);
+		mSPI.writeByte(0);
+		mSPI.waitFully();
 		mSPI.release();
 	}
 
@@ -524,7 +529,13 @@ class PL9823Controller : public ClocklessController<DATA_PIN, 3 * FMUL, 8 * FMUL
 
 // Similar to NS() macro, this calculates the number of cycles for
 // the clockless chipset (which may differ from CPU cycles)
+
+#ifdef FASTLED_TEENSY4
+// just use raw nanosecond values for the teensy4
+#define C_NS(_NS) _NS
+#else
 #define C_NS(_NS) (((_NS * ((CLOCKLESS_FREQUENCY / 1000000L)) + 999)) / 1000)
+#endif
 
 // GE8822 - 350ns 660ns 350ns
 template <uint8_t DATA_PIN, EOrder RGB_ORDER = RGB>
diff --git a/examples/Multiple/MultiArrays/MultiArrays.ino b/examples/Multiple/MultiArrays/MultiArrays.ino
index 50241c39..9d3cbb6b 100644
--- a/examples/Multiple/MultiArrays/MultiArrays.ino
+++ b/examples/Multiple/MultiArrays/MultiArrays.ino
@@ -33,7 +33,7 @@ void loop() {
     // clear our current dot before we move on
     redLeds[i] = CRGB::Black;
     greenLeds[i] = CRGB::Black;
-    blueLeds[i] = CRGB::Blue;
+    blueLeds[i] = CRGB::Black;
     delay(100);
   }
 
@@ -46,7 +46,7 @@ void loop() {
     // clear our current dot before we move on
     redLeds[i] = CRGB::Black;
     greenLeds[i] = CRGB::Black;
-    blueLeds[i] = CRGB::Blue;
+    blueLeds[i] = CRGB::Black;
     delay(100);
   }
 }
diff --git a/examples/Multiple/ParallelOutputDemo/ParallelOutputDemo.ino b/examples/Multiple/ParallelOutputDemo/ParallelOutputDemo.ino
index fc7c9e77..8c447b54 100644
--- a/examples/Multiple/ParallelOutputDemo/ParallelOutputDemo.ino
+++ b/examples/Multiple/ParallelOutputDemo/ParallelOutputDemo.ino
@@ -1,6 +1,6 @@
 #include <FastLED.h>
 
-#define NUM_LEDS_PER_STRIP 64
+#define NUM_LEDS_PER_STRIP 16
 // Note: this can be 12 if you're using a teensy 3 and don't mind soldering the pads on the back
 #define NUM_STRIPS 16
 
@@ -17,15 +17,24 @@ CRGB leds[NUM_STRIPS * NUM_LEDS_PER_STRIP];
 // WS2811_PORTD: 25,26,27,28,14,15,29,11
 //
 
+
+// IBCC<WS2811, 1, 16> outputs;
+
 void setup() {
+  delay(5000);
+  Serial.begin(57600);
+  Serial.println("Starting...");
   // LEDS.addLeds<WS2811_PORTA,NUM_STRIPS>(leds, NUM_LEDS_PER_STRIP);
   // LEDS.addLeds<WS2811_PORTB,NUM_STRIPS>(leds, NUM_LEDS_PER_STRIP);
   // LEDS.addLeds<WS2811_PORTD,NUM_STRIPS>(leds, NUM_LEDS_PER_STRIP).setCorrection(TypicalLEDStrip);
   LEDS.addLeds<WS2811_PORTDC,NUM_STRIPS>(leds, NUM_LEDS_PER_STRIP);
-  LEDS.setBrightness(32);
+
+  // Teensy 4 parallel output example
+  // LEDS.addLeds<NUM_STRIPS, WS2811, 1>(leds,NUM_LEDS_PER_STRIP);
 }
 
 void loop() {
+  Serial.println("Loop....");
   static uint8_t hue = 0;
   for(int i = 0; i < NUM_STRIPS; i++) {
     for(int j = 0; j < NUM_LEDS_PER_STRIP; j++) {
@@ -43,5 +52,5 @@ void loop() {
   hue++;
 
   LEDS.show();
-  LEDS.delay(10);
+  // LEDS.delay(100);
 }
diff --git a/examples/Pintest/Pintest.ino b/examples/Pintest/Pintest.ino
index a63f0d46..a8141520 100644
--- a/examples/Pintest/Pintest.ino
+++ b/examples/Pintest/Pintest.ino
@@ -1,7 +1,10 @@
 
-#include <FastSPI_LED.h>
+#include <FastLED.h>
+
+char fullstrBuffer[64];
 
 const char *getPort(void *portPtr) {
+// AVR port checks
 #ifdef PORTA
 	if(portPtr == (void*)&PORTA) { return "PORTA"; }
 #endif
@@ -38,6 +41,8 @@ const char *getPort(void *portPtr) {
 #ifdef PORTL
 	if(portPtr == (void*)&PORTL) { return "PORTL"; }
 #endif
+
+// Teensy 3.x port checks
 #ifdef GPIO_A_PDOR
 	if(portPtr == (void*)&GPIO_A_PDOR) { return "GPIO_A_PDOR"; }
 #endif
@@ -65,41 +70,130 @@ const char *getPort(void *portPtr) {
 #ifdef REG_PIO_D_ODSR
 	if(portPtr == (void*)&REG_PIO_D_ODSR) { return "REG_PIO_D_ODSR"; }
 #endif
-	return "unknown";
+
+// Teensy 4 port checks
+#ifdef GPIO1_DR
+	if(portPtr == (void*)&GPIO1_DR) { return "GPIO1_DR"; }
+#endif
+#ifdef GPIO2_DR
+if(portPtr == (void*)&GPIO2_DR) { return "GPIO21_DR"; }
+#endif
+#ifdef GPIO3_DR
+if(portPtr == (void*)&GPIO3_DR) { return "GPIO3_DR"; }
+#endif
+#ifdef GPIO4_DR
+if(portPtr == (void*)&GPIO4_DR) { return "GPIO4_DR"; }
+#endif
+  String unknown_str = "Unknown: " + String((size_t)portPtr, HEX);
+	strncpy(fullstrBuffer, unknown_str.c_str(), unknown_str.length());
+	fullstrBuffer[sizeof(fullstrBuffer)-1] = '\0';
+	return fullstrBuffer;
 }
 
 template<uint8_t PIN> void CheckPin()
 {
 	CheckPin<PIN - 1>();
 
-	RwReg *systemThinksPortIs = portOutputRegister(digitalPinToPort(PIN));
+	void *systemThinksPortIs = (void*)portOutputRegister(digitalPinToPort(PIN));
 	RwReg systemThinksMaskIs = digitalPinToBitMask(PIN);
-	
+
 	Serial.print("Pin "); Serial.print(PIN); Serial.print(": Port ");
-	
-	if(systemThinksPortIs == FastPin<PIN>::port()) { 
+
+	if(systemThinksPortIs == (void*)FastPin<PIN>::port()) {
 		Serial.print("valid & mask ");
-	} else { 
-		Serial.print("invalid, is "); Serial.print(getPort((void*)FastPin<PIN>::port())); Serial.print(" should be "); 
+	} else {
+		Serial.print("invalid, is "); Serial.print(getPort((void*)FastPin<PIN>::port())); Serial.print(" should be ");
 		Serial.print(getPort((void*)systemThinksPortIs));
 		Serial.print(" & mask ");
 	}
 
 	if(systemThinksMaskIs == FastPin<PIN>::mask()) {
 		Serial.println("valid.");
-	} else { 
+	} else {
 		Serial.print("invalid, is "); Serial.print(FastPin<PIN>::mask()); Serial.print(" should be "); Serial.println(systemThinksMaskIs);
 	}
-}	
+}
+
+template<> void CheckPin<255> () {}
+
+
+template<uint8_t _PORT> const char *_GetPinPort(void *ptr) {
+	if (__FL_PORT_INFO<_PORT>::hasPort() && (ptr == (void*)__FL_PORT_INFO<_PORT>::portAddr())) {
+		return __FL_PORT_INFO<_PORT>::portName();
+	} else {
+		return _GetPinPort<_PORT - 1>(ptr);
+	}
+}
+template<> const char *_GetPinPort<-1>(void *ptr) {
+	return NULL;
+}
+
+const char *GetPinPort(void *ptr) {
+	return _GetPinPort<'Z'>(ptr);
+}
+
+static uint8_t pcount = 0;
+
+
+template<uint8_t PIN> void PrintPins() {
+	PrintPins<PIN - 1>();
+
+	RwReg *systemThinksPortIs = portOutputRegister(digitalPinToPort(PIN));
+	RwReg systemThinksMaskIs = digitalPinToBitMask(PIN);
+
+	int maskBit = 0;
+	while(systemThinksMaskIs > 1) { systemThinksMaskIs >>= 1; maskBit++; }
+
+	const char *pinport = GetPinPort((void*)systemThinksPortIs);
+	if (pinport) {
+		Serial.print("__FL_DEFPIN("); Serial.print(PIN);
+		Serial.print(","); Serial.print(maskBit);
+		Serial.print(","); Serial.print(pinport);
+		Serial.print("); ");
+		pcount++;
+		if(pcount == 4) { pcount = 0; Serial.println(""); }
+	} else {
+		// Serial.print("Not found for pin "); Serial.println(PIN);
+	}
+}
 
-template<> void CheckPin<-1> () {}
+template<> void PrintPins<0>() {
+	RwReg *systemThinksPortIs = portOutputRegister(digitalPinToPort(0));
+	RwReg systemThinksMaskIs = digitalPinToBitMask(0);
 
-void setup() { 
+	int maskBit = 0;
+	while(systemThinksMaskIs > 1) { systemThinksMaskIs >>= 1; maskBit++; }
+
+	const char *pinport = GetPinPort((void*)systemThinksPortIs);
+	if (pinport) {
+		Serial.print("__FL_DEFPIN("); Serial.print(0);
+		Serial.print(","); Serial.print(maskBit);
+		Serial.print(","); Serial.print(pinport);
+		Serial.print("); ");
+		pcount++;
+		if(pcount == 4) { pcount = 0; Serial.println(""); }
+	}
+}
+
+int counter = 0;
+void setup() {
+	delay(5000);
     Serial.begin(38400);
     Serial.println("resetting!");
 }
 
-void loop() { 
+void loop() {
+	Serial.println(counter);
+
+#ifdef MAX_PIN
 	CheckPin<MAX_PIN>();
-	delay(10000);
+#endif
+
+	Serial.println("-----");
+#ifdef NUM_DIGITAL_PINS
+	PrintPins<NUM_DIGITAL_PINS>();
+#endif
+	Serial.println("------");
+
+	delay(100000);
 }
diff --git a/fastpin.h b/fastpin.h
index beb3a2d8..ed2b8e7e 100644
--- a/fastpin.h
+++ b/fastpin.h
@@ -241,6 +241,28 @@ template<uint8_t PIN> class FastPinBB : public FastPin<PIN> {};
 typedef volatile uint32_t & reg32_t;
 typedef volatile uint32_t * ptr_reg32_t;
 
+// Utility templates for tracking down information about pins and ports
+template<uint8_t port> struct __FL_PORT_INFO {
+	static bool hasPort() { return 0; }
+	static const char *portName() { return "--"; }
+	static const void *portAddr() { return NULL; }
+};
+
+// Give us our instantiations for defined ports - we're going to abuse this later for
+// auto discovery of pin/port mappings for new variants.  Use _FL_DEFINE_PORT for ports that
+// are numeric in nature, e.g. GPIO0, GPIO1.  Use _FL_DEFINE_PORT3 for ports that are letters.
+// The first parameter will be the letter, the second parameter will be an integer/counter of smoe kind
+// (this is because attempts to turn macro parameters into character constants break in some compilers)
+#define _FL_DEFINE_PORT(L, BASE) template<> struct __FL_PORT_INFO<L> { static bool hasPort() { return 1; } \
+										static const char *portName() { return #L; } \
+										typedef BASE __t_baseType;  \
+										static const void *portAddr() { return (void*)&__t_baseType::r(); } };
+
+#define _FL_DEFINE_PORT3(L, LC, BASE) template<> struct __FL_PORT_INFO<LC> { static bool hasPort() { return 1; } \
+										static const char *portName() { return #L; } \
+										typedef BASE __t_baseType;  \
+										static const void *portAddr() { return (void*)&__t_baseType::r(); } };
+
 FASTLED_NAMESPACE_END
 
 #pragma GCC diagnostic pop
diff --git a/fastspi.h b/fastspi.h
index fc0843be..38e8eabf 100644
--- a/fastspi.h
+++ b/fastspi.h
@@ -13,6 +13,10 @@ FASTLED_NAMESPACE_BEGIN
 #if defined(FASTLED_TEENSY3) && (F_CPU > 48000000)
 #define DATA_RATE_MHZ(X) (((48000000L / 1000000L) / X))
 #define DATA_RATE_KHZ(X) (((48000000L / 1000L) / X))
+#elif defined(FASTLED_TEENSY4) // && (ARM_HARDWARE_SPI)
+// just use clocks
+#define DATA_RATE_MHZ(X) (1000000 * (X))
+#define DATA_RATE_KHZ(X) (1000 * (X))
 #else
 #define DATA_RATE_MHZ(X) ((F_CPU / 1000000L) / X)
 #define DATA_RATE_KHZ(X) ((F_CPU / 1000L) / X)
@@ -26,22 +30,22 @@ FASTLED_NAMESPACE_BEGIN
 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 
 #if !defined(FASTLED_ALL_PINS_HARDWARE_SPI)
-template<uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template<uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class SPIOutput : public AVRSoftwareSPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDER> {};
 #endif
 
-template<uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template<uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class SoftwareSPIOutput : public AVRSoftwareSPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDER> {};
 
 #ifndef FASTLED_FORCE_SOFTWARE_SPI
 
 #if defined(NRF51) && defined(FASTLED_ALL_PINS_HARDWARE_SPI)
-template<uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template<uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class SPIOutput : public NRF51SPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDER> {};
 #endif
 
 #if defined(NRF52_SERIES) && defined(FASTLED_ALL_PINS_HARDWARE_SPI)
-template<uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template<uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class SPIOutput : public NRF52SPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDER> {};
 #endif
 
@@ -49,26 +53,37 @@ class SPIOutput : public NRF52SPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDE
 
 #if defined(FASTLED_TEENSY3) && defined(ARM_HARDWARE_SPI)
 
-template<uint8_t SPI_SPEED>
+template<uint32_t SPI_SPEED>
 class SPIOutput<SPI_DATA, SPI_CLOCK, SPI_SPEED> : public ARMHardwareSPIOutput<SPI_DATA, SPI_CLOCK, SPI_SPEED, 0x4002C000> {};
 
 #if defined(SPI2_DATA)
 
-template<uint8_t SPI_SPEED>
+template<uint32_t SPI_SPEED>
 class SPIOutput<SPI2_DATA, SPI2_CLOCK, SPI_SPEED> : public ARMHardwareSPIOutput<SPI2_DATA, SPI2_CLOCK, SPI_SPEED, 0x4002C000> {};
 
-template<uint8_t SPI_SPEED>
+template<uint32_t SPI_SPEED>
 class SPIOutput<SPI_DATA, SPI2_CLOCK, SPI_SPEED> : public ARMHardwareSPIOutput<SPI_DATA, SPI2_CLOCK, SPI_SPEED, 0x4002C000> {};
 
-template<uint8_t SPI_SPEED>
+template<uint32_t SPI_SPEED>
 class SPIOutput<SPI2_DATA, SPI_CLOCK, SPI_SPEED> : public ARMHardwareSPIOutput<SPI2_DATA, SPI_CLOCK, SPI_SPEED, 0x4002C000> {};
 #endif
 
+#elif defined(FASTLED_TEENSY4) && defined(ARM_HARDWARE_SPI)
+
+template<uint32_t SPI_SPEED>
+class SPIOutput<SPI_DATA, SPI_CLOCK, SPI_SPEED> : public Teesy4HardwareSPIOutput<SPI_DATA, SPI_CLOCK, SPI_SPEED, SPI, 0> {};
+
+template<uint32_t SPI_SPEED>
+class SPIOutput<SPI1_DATA, SPI_CLOCK, SPI_SPEED> : public Teesy4HardwareSPIOutput<SPI1_DATA, SPI1_CLOCK, SPI_SPEED, SPI1, 1> {};
+
+template<uint32_t SPI_SPEED>
+class SPIOutput<SPI2_DATA, SPI2_CLOCK, SPI_SPEED> : public Teesy4HardwareSPIOutput<SPI2_DATA, SPI2_CLOCK, SPI_SPEED, SPI2, 2> {};
+
 #elif defined(FASTLED_TEENSYLC) && defined(ARM_HARDWARE_SPI)
 
-#define DECLARE_SPI0(__DATA,__CLOCK) template<uint8_t SPI_SPEED>\
+#define DECLARE_SPI0(__DATA,__CLOCK) template<uint32_t SPI_SPEED>\
  class SPIOutput<__DATA, __CLOCK, SPI_SPEED> : public ARMHardwareSPIOutput<__DATA, __CLOCK, SPI_SPEED, 0x40076000> {};
- #define DECLARE_SPI1(__DATA,__CLOCK) template<uint8_t SPI_SPEED>\
+ #define DECLARE_SPI1(__DATA,__CLOCK) template<uint32_t SPI_SPEED>\
   class SPIOutput<__DATA, __CLOCK, SPI_SPEED> : public ARMHardwareSPIOutput<__DATA, __CLOCK, SPI_SPEED, 0x40077000> {};
 
 DECLARE_SPI0(7,13);
@@ -85,24 +100,24 @@ DECLARE_SPI1(21,20);
 
 #elif defined(__SAM3X8E__)
 
-template<uint8_t SPI_SPEED>
+template<uint32_t SPI_SPEED>
 class SPIOutput<SPI_DATA, SPI_CLOCK, SPI_SPEED> : public SAMHardwareSPIOutput<SPI_DATA, SPI_CLOCK, SPI_SPEED> {};
 
 #elif defined(AVR_HARDWARE_SPI)
 
-template<uint8_t SPI_SPEED>
+template<uint32_t SPI_SPEED>
 class SPIOutput<SPI_DATA, SPI_CLOCK, SPI_SPEED> : public AVRHardwareSPIOutput<SPI_DATA, SPI_CLOCK, SPI_SPEED> {};
 
 #if defined(SPI_UART0_DATA)
 
-template<uint8_t SPI_SPEED>
+template<uint32_t SPI_SPEED>
 class SPIOutput<SPI_UART0_DATA, SPI_UART0_CLOCK, SPI_SPEED> : public AVRUSART0SPIOutput<SPI_UART0_DATA, SPI_UART0_CLOCK, SPI_SPEED> {};
 
 #endif
 
 #if defined(SPI_UART1_DATA)
 
-template<uint8_t SPI_SPEED>
+template<uint32_t SPI_SPEED>
 class SPIOutput<SPI_UART1_DATA, SPI_UART1_CLOCK, SPI_SPEED> : public AVRUSART1SPIOutput<SPI_UART1_DATA, SPI_UART1_CLOCK, SPI_SPEED> {};
 
 #endif
@@ -120,7 +135,7 @@ class SPIOutput<SPI_UART1_DATA, SPI_UART1_CLOCK, SPI_SPEED> : public AVRUSART1SP
 #endif
 
 // #if defined(USART_DATA) && defined(USART_CLOCK)
-// template<uint8_t SPI_SPEED>
+// template<uint32_t SPI_SPEED>
 // class AVRSPIOutput<USART_DATA, USART_CLOCK, SPI_SPEED> : public AVRUSARTSPIOutput<USART_DATA, USART_CLOCK, SPI_SPEED> {};
 // #endif
 
diff --git a/fastspi_bitbang.h b/fastspi_bitbang.h
index d48e32bc..019b6dc0 100644
--- a/fastspi_bitbang.h
+++ b/fastspi_bitbang.h
@@ -15,7 +15,7 @@ FASTLED_NAMESPACE_BEGIN
 //
 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 
-template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, uint8_t SPI_SPEED>
+template <uint8_t DATA_PIN, uint8_t CLOCK_PIN, uint32_t SPI_SPEED>
 class AVRSoftwareSPIOutput {
 	// The data types for pointers to the pin port - typedef'd here from the Pin definition because on avr these
 	// are pointers to 8 bit values, while on arm they are 32 bit
@@ -113,10 +113,16 @@ private:
 public:
 
 	// We want to make sure that the clock pulse is held high for a nininum of 35ns.
-	#define MIN_DELAY (NS(35) - 3)
+#if defined(FASTLED_TEENSY4)
+	#define DELAY_NS (1000 / (SPI_SPEED/1000000))
+	#define CLOCK_HI_DELAY do { delayNanoseconds((DELAY_NS/4)); } while(0);
+	#define CLOCK_LO_DELAY do { delayNanoseconds((DELAY_NS/4)); } while(0);
+#else
+	#define MIN_DELAY ((NS(35)>3) ? (NS(35) - 3) : 1)
 
-  #define CLOCK_HI_DELAY delaycycles<MIN_DELAY>(); delaycycles<(((SPI_SPEED-6) / 2) - MIN_DELAY)>();
-	#define CLOCK_LO_DELAY delaycycles<(((SPI_SPEED-6) / 4))>();
+	#define CLOCK_HI_DELAY do { delaycycles<MIN_DELAY>(); delaycycles<((SPI_SPEED > 10) ? (((SPI_SPEED-6) / 2) - MIN_DELAY) : (SPI_SPEED))>(); } while(0);
+	#define CLOCK_LO_DELAY do { delaycycles<((SPI_SPEED > 10) ? ((SPI_SPEED-6) / 2) : (SPI_SPEED))>(); } while(0);
+#endif
 
 	// write the BIT'th bit out via spi, setting the data pin then strobing the clcok
 	template <uint8_t BIT> __attribute__((always_inline, hot)) inline static void writeBit(uint8_t b) {
@@ -126,8 +132,8 @@ public:
 #ifdef ESP32
 			// try to ensure we never have adjacent write opcodes to the same register
 			FastPin<CLOCK_PIN>::lo();
-			FastPin<CLOCK_PIN>::hi(); CLOCK_HI_DELAY; 
-			FastPin<CLOCK_PIN>::toggle(); CLOCK_LO_DELAY; 
+			FastPin<CLOCK_PIN>::hi(); CLOCK_HI_DELAY;
+			FastPin<CLOCK_PIN>::toggle(); CLOCK_LO_DELAY;
 #else
 			FastPin<CLOCK_PIN>::hi(); CLOCK_HI_DELAY;
 			FastPin<CLOCK_PIN>::lo(); CLOCK_LO_DELAY;
@@ -137,7 +143,7 @@ public:
 			FastPin<CLOCK_PIN>::hi(); CLOCK_HI_DELAY;
 #ifdef ESP32
 			// try to ensure we never have adjacent write opcodes to the same register
-			FastPin<CLOCK_PIN>::toggle(); CLOCK_HI_DELAY; 
+			FastPin<CLOCK_PIN>::toggle(); CLOCK_HI_DELAY;
 #else
 			FastPin<CLOCK_PIN>::lo(); CLOCK_LO_DELAY;
 #endif
diff --git a/fastspi_nop.h b/fastspi_nop.h
index 5c5da010..1dcd2961 100644
--- a/fastspi_nop.h
+++ b/fastspi_nop.h
@@ -10,7 +10,7 @@ FASTLED_NAMESPACE_BEGIN
 /// A nop/stub class, mostly to show the SPI methods that are needed/used by the various SPI chipset implementations.  Should
 /// be used as a definition for the set of methods that the spi implementation classes should use (since C++ doesn't support the
 /// idea of interfaces - it's possible this could be done with virtual classes, need to decide if i want that overhead)
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class NOPSPIOutput {
 	Selectable *m_pSelect;
 
diff --git a/fastspi_ref.h b/fastspi_ref.h
index f68e63ef..00c41d34 100644
--- a/fastspi_ref.h
+++ b/fastspi_ref.h
@@ -8,7 +8,7 @@ FASTLED_NAMESPACE_BEGIN
 
 // A skeletal implementation of hardware SPI support.  Fill in the necessary code for init, waiting, and writing.  The rest of
 // the method implementations should provide a starting point, even if not hte most efficient to start with
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class REFHardwareSPIOutput {
 	Selectable *m_pSelect;
 public:
diff --git a/keywords.txt b/keywords.txt
index c30552d8..75df500c 100644
--- a/keywords.txt
+++ b/keywords.txt
@@ -294,41 +294,52 @@ CRGB::YellowGreen	KEYWORD2
 #######################################
 
 # Chipsets
-LPD6803	LITERAL1
-LPD8806	LITERAL1
-WS2801	LITERAL1
-WS2803	LITERAL1
-P9813	LITERAL1
-SM16716	LITERAL1
 APA102	LITERAL1
+APA104	LITERAL1
+APA106	LITERAL1
 DMXSERIAL	LITERAL1
 DMXSIMPLE	LITERAL1
-TM1829	LITERAL1
-TM1809	LITERAL1
-TM1804	LITERAL1
-TM1803	LITERAL1
-APA104	LITERAL1
-WS2811	LITERAL1
-WS2812	LITERAL1
-WS2812B	LITERAL1
-WS2811_400	LITERAL1
-WS2813	LITERAL1
-NEOPIXEL	LITERAL1
-UCS1903	LITERAL1
-UCS1903B	LITERAL1
+DOTSTAR	LITERAL1
+GE8822	LITERAL1
+GS1903	LITERAL1
 GW6205	LITERAL1
 GW6205B	LITERAL1
+GW6205_400	LITERAL1
 LPD1886	LITERAL1
+LPD1886_8BIT	LITERAL1
+LPD6803	LITERAL1
+LPD8806	LITERAL1
+NEOPIXEL	LITERAL1
 OCTOWS2811	LITERAL1
 OCTOWS2811_400	LITERAL1
 OCTOWS2813	LITERAL1
-WS2812SERIAL	LITERAL1
-SMART_MATRIX	LITERAL1
-GE8822	LITERAL1
+P9813	LITERAL1
+PIXIE	LITERAL1
+PL9823	LITERAL1
+SK6812	LITERAL1
+SK6822	LITERAL1
+SK9822	LITERAL1
 SM16703 LITERAL1
-GS1903	LITERAL1
-LPD6803	LITERAL1
-
+SM16716	LITERAL1
+SMART_MATRIX	LITERAL1
+TM1803	LITERAL1
+TM1804	LITERAL1
+TM1809	LITERAL1
+TM1812	LITERAL1
+TM1829	LITERAL1
+UCS1903	LITERAL1
+UCS1903B	LITERAL1
+UCS1904	LITERAL1
+UCS2903	LITERAL1
+WS2801	LITERAL1
+WS2803	LITERAL1
+WS2811	LITERAL1
+WS2811_400	LITERAL1
+WS2812	LITERAL1
+WS2812B	LITERAL1
+WS2812SERIAL	LITERAL1
+WS2813	LITERAL1
+WS2852	LITERAL1
 
 # RGB orderings
 RGB	LITERAL1
diff --git a/led_sysdefs.h b/led_sysdefs.h
index 7abcd15e..27da24a0 100644
--- a/led_sysdefs.h
+++ b/led_sysdefs.h
@@ -18,6 +18,9 @@
 #elif defined(__MKL26Z64__)
 // Include kl26/T-LC headers
 #include "platforms/arm/kl26/led_sysdefs_arm_kl26.h"
+#elif defined(__IMXRT1062__)
+// teensy4
+#include "platforms/arm/mxrt1062/led_sysdefs_arm_mxrt1062.h"
 #elif defined(__SAM3X8E__)
 // Include sam/due headers
 #include "platforms/arm/sam/led_sysdefs_arm_sam.h"
diff --git a/library.json b/library.json
index ca8f09e8..c7075be7 100644
--- a/library.json
+++ b/library.json
@@ -18,7 +18,7 @@
         "type": "git",
         "url": "https://github.com/FastLED/FastLED.git"
     },
-    "version": "3.2.9",
+    "version": "3.3.2",
     "license": "MIT",
     "homepage": "http://fastled.io",
     "frameworks": "arduino",
diff --git a/library.properties b/library.properties
index 25460b1e..31175c55 100644
--- a/library.properties
+++ b/library.properties
@@ -1,5 +1,5 @@
 name=FastLED
-version=3.2.9
+version=3.3.2
 author=Daniel Garcia
 maintainer=Daniel Garcia <dgarcia@fastled.io>
 sentence=Multi-platform library for controlling dozens of different types of LEDs along with optimized math, effect, and noise functions.
diff --git a/platforms.h b/platforms.h
index 82d7d993..f66599fd 100644
--- a/platforms.h
+++ b/platforms.h
@@ -18,6 +18,9 @@
 #elif defined(__MKL26Z64__)
 // Include kl26/T-LC headers
 #include "platforms/arm/kl26/fastled_arm_kl26.h"
+#elif defined(__IMXRT1062__)
+// teensy4
+#include "platforms/arm/mxrt1062/fastled_arm_mxrt1062.h"
 #elif defined(__SAM3X8E__)
 // Include sam/due headers
 #include "platforms/arm/sam/fastled_arm_sam.h"
diff --git a/platforms/arm/d21/fastpin_arm_d21.h b/platforms/arm/d21/fastpin_arm_d21.h
index 1606d650..84b0738c 100644
--- a/platforms/arm/d21/fastpin_arm_d21.h
+++ b/platforms/arm/d21/fastpin_arm_d21.h
@@ -57,19 +57,19 @@ public:
 #define _R(T) struct __gen_struct_ ## T
 #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile PortGroup * r() { return T; } };
 
-#define _IO32(L) _RD32(GPIO ## L)
+#define _FL_IO(L) _RD32(GPIO ## L)
 
-#define _DEFPIN_ARM(PIN, L, BIT) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, L> {};
+#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, L> {};
 
 // Actual pin definitions
 #if defined(ARDUINO_SAMD_CIRCUITPLAYGROUND_EXPRESS)
 
 #define MAX_PIN 17
-_DEFPIN_ARM( 8,1,23);
-_DEFPIN_ARM( 0,1, 9); _DEFPIN_ARM( 1,1, 8); _DEFPIN_ARM( 2,1, 2); _DEFPIN_ARM( 3,1, 3);
-_DEFPIN_ARM( 6,0, 5); _DEFPIN_ARM( 9,0, 6); _DEFPIN_ARM(10,0, 7); _DEFPIN_ARM(12,0, 2);
-_DEFPIN_ARM(A6,1, 9); _DEFPIN_ARM(A7,1, 8); _DEFPIN_ARM(A5,1, 2); _DEFPIN_ARM(A4,1, 3);
-_DEFPIN_ARM(A1,0, 5); _DEFPIN_ARM(A2,0, 6); _DEFPIN_ARM(A3,0, 7); _DEFPIN_ARM(A0,0, 2);
+_FL_DEFPIN( 8,23,1);
+_FL_DEFPIN( 0, 9,1); _FL_DEFPIN( 1, 8,1); _FL_DEFPIN( 2, 2,1); _FL_DEFPIN( 3, 3,1);
+_FL_DEFPIN( 6, 5,0); _FL_DEFPIN( 9, 6,0); _FL_DEFPIN(10, 7,0); _FL_DEFPIN(12, 2,0);
+_FL_DEFPIN(A6, 9,1); _FL_DEFPIN(A7, 8,1); _FL_DEFPIN(A5, 2,1); _FL_DEFPIN(A4, 3,1);
+_FL_DEFPIN(A1, 5,0); _FL_DEFPIN(A2, 6,0); _FL_DEFPIN(A3, 7,0); _FL_DEFPIN(A0, 2,0);
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 
@@ -78,19 +78,19 @@ _DEFPIN_ARM(A1,0, 5); _DEFPIN_ARM(A2,0, 6); _DEFPIN_ARM(A3,0, 7); _DEFPIN_ARM(A0
 
 #define MAX_PIN 20
 // 0 & 1
-_DEFPIN_ARM( 0, 0, 9);    _DEFPIN_ARM( 1, 0, 10);
+_FL_DEFPIN( 0, 9, 0);    _FL_DEFPIN( 1, 10, 0);
 // 2, 3, 4
-_DEFPIN_ARM( 2, 0, 14);   _DEFPIN_ARM( 3, 0, 11);   _DEFPIN_ARM( 4, 0, 8);
+_FL_DEFPIN( 2, 14, 0);   _FL_DEFPIN( 3, 11, 0);   _FL_DEFPIN( 4, 8, 0);
 // 5, 6, 7
-_DEFPIN_ARM( 5, 0, 15);   _DEFPIN_ARM( 6, 0, 18);   _DEFPIN_ARM( 7, 0, 0);
+_FL_DEFPIN( 5, 15, 0);   _FL_DEFPIN( 6, 18, 0);   _FL_DEFPIN( 7, 0, 0);
 // 8, 9, 10
-_DEFPIN_ARM( 8, 0, 12);   _DEFPIN_ARM( 9, 0, 19);   _DEFPIN_ARM(10, 0, 20);
+_FL_DEFPIN( 8, 12, 0);   _FL_DEFPIN( 9, 19, 0);   _FL_DEFPIN(10, 20, 0);
 // 11, 12, 13
-_DEFPIN_ARM(11, 0, 21);   _DEFPIN_ARM(12, 0, 22);   _DEFPIN_ARM(13, 0, 23);
+_FL_DEFPIN(11, 21, 0);   _FL_DEFPIN(12, 22, 0);   _FL_DEFPIN(13, 23, 0);
 // 14, 15, 16 (A0 - A2)
-_DEFPIN_ARM(14, 0,  2);   _DEFPIN_ARM(15, 1,  8);   _DEFPIN_ARM(16, 1, 9);
+_FL_DEFPIN(14,  2, 0);   _FL_DEFPIN(15,  8, 1);   _FL_DEFPIN(16, 9, 1);
 // 17, 18, 19 (A3 - A5)
-_DEFPIN_ARM(17, 0,  4);   _DEFPIN_ARM(18, 0,  5);   _DEFPIN_ARM(19, 0, 6);
+_FL_DEFPIN(17,  4, 0);   _FL_DEFPIN(18,  5, 0);   _FL_DEFPIN(19, 6, 0);
 
 #define SPI_DATA  PIN_SPI_MOSI
 #define SPI_CLOCK PIN_SPI_SCK
@@ -101,17 +101,17 @@ _DEFPIN_ARM(17, 0,  4);   _DEFPIN_ARM(18, 0,  5);   _DEFPIN_ARM(19, 0, 6);
 #elif defined(ARDUINO_SAMD_ZERO)
 
 #define MAX_PIN 42
-_DEFPIN_ARM( 0,0,10); _DEFPIN_ARM( 1,0,11); _DEFPIN_ARM( 2,0, 8); _DEFPIN_ARM( 3,0, 9);
-_DEFPIN_ARM( 4,0,14); _DEFPIN_ARM( 5,0,15); _DEFPIN_ARM( 6,0,20); _DEFPIN_ARM( 7,0,21);
-_DEFPIN_ARM( 8,0, 6); _DEFPIN_ARM( 9,0, 7); _DEFPIN_ARM(10,0,18); _DEFPIN_ARM(11,0,16);
-_DEFPIN_ARM(12,0,19); _DEFPIN_ARM(13,0,17); _DEFPIN_ARM(14,0, 2); _DEFPIN_ARM(15,1, 8);
-_DEFPIN_ARM(16,1, 9); _DEFPIN_ARM(17,0, 4); _DEFPIN_ARM(18,0, 5); _DEFPIN_ARM(19,1, 2);
-_DEFPIN_ARM(20,0,22); _DEFPIN_ARM(21,0,23); _DEFPIN_ARM(22,0,12); _DEFPIN_ARM(23,1,11);
-_DEFPIN_ARM(24,1,10); _DEFPIN_ARM(25,1, 3); _DEFPIN_ARM(26,0,27); _DEFPIN_ARM(27,0,28);
-_DEFPIN_ARM(28,0,24); _DEFPIN_ARM(29,0,25); _DEFPIN_ARM(30,1,22); _DEFPIN_ARM(31,1,23);
-_DEFPIN_ARM(32,0,22); _DEFPIN_ARM(33,0,23); _DEFPIN_ARM(34,0,19); _DEFPIN_ARM(35,0,16);
-_DEFPIN_ARM(36,0,18); _DEFPIN_ARM(37,0,17); _DEFPIN_ARM(38,0,13); _DEFPIN_ARM(39,0,21);
-_DEFPIN_ARM(40,0, 6); _DEFPIN_ARM(41,0, 7); _DEFPIN_ARM(42,0, 3);
+_FL_DEFPIN( 0,10,0); _FL_DEFPIN( 1,11,0); _FL_DEFPIN( 2, 8,0); _FL_DEFPIN( 3, 9,0);
+_FL_DEFPIN( 4,14,0); _FL_DEFPIN( 5,15,0); _FL_DEFPIN( 6,20,0); _FL_DEFPIN( 7,21,0);
+_FL_DEFPIN( 8, 6,0); _FL_DEFPIN( 9, 7,0); _FL_DEFPIN(10,18,0); _FL_DEFPIN(11,16,0);
+_FL_DEFPIN(12,19,0); _FL_DEFPIN(13,17,0); _FL_DEFPIN(14, 2,0); _FL_DEFPIN(15, 8,1);
+_FL_DEFPIN(16, 9,1); _FL_DEFPIN(17, 4,0); _FL_DEFPIN(18, 5,0); _FL_DEFPIN(19, 2,1);
+_FL_DEFPIN(20,22,0); _FL_DEFPIN(21,23,0); _FL_DEFPIN(22,12,0); _FL_DEFPIN(23,11,1);
+_FL_DEFPIN(24,10,1); _FL_DEFPIN(25, 3,1); _FL_DEFPIN(26,27,0); _FL_DEFPIN(27,28,0);
+_FL_DEFPIN(28,24,0); _FL_DEFPIN(29,25,0); _FL_DEFPIN(30,22,1); _FL_DEFPIN(31,23,1);
+_FL_DEFPIN(32,22,0); _FL_DEFPIN(33,23,0); _FL_DEFPIN(34,19,0); _FL_DEFPIN(35,16,0);
+_FL_DEFPIN(36,18,0); _FL_DEFPIN(37,17,0); _FL_DEFPIN(38,13,0); _FL_DEFPIN(39,21,0);
+_FL_DEFPIN(40, 6,0); _FL_DEFPIN(41, 7,0); _FL_DEFPIN(42, 3,0);
 
 #define SPI_DATA 24
 #define SPI_CLOCK 23
@@ -121,21 +121,21 @@ _DEFPIN_ARM(40,0, 6); _DEFPIN_ARM(41,0, 7); _DEFPIN_ARM(42,0, 3);
 #elif defined(ARDUINO_SODAQ_AUTONOMO)
 
 #define MAX_PIN 56
-_DEFPIN_ARM( 0,0, 9); _DEFPIN_ARM( 1,0,10); _DEFPIN_ARM( 2,0,11); _DEFPIN_ARM( 3,1,10);
-_DEFPIN_ARM( 4,1,11); _DEFPIN_ARM( 5,1,12); _DEFPIN_ARM( 6,1,13); _DEFPIN_ARM( 7,1,14);
-_DEFPIN_ARM( 8,1,15); _DEFPIN_ARM( 9,0,14); _DEFPIN_ARM(10,0,15); _DEFPIN_ARM(11,0,16);
-_DEFPIN_ARM(12,0,17); _DEFPIN_ARM(13,0,18); _DEFPIN_ARM(14,0,19); _DEFPIN_ARM(15,1,16);
-_DEFPIN_ARM(16,0, 8); _DEFPIN_ARM(17,0,28); _DEFPIN_ARM(18,1,17); _DEFPIN_ARM(19,0, 2);
-_DEFPIN_ARM(20,0, 6); _DEFPIN_ARM(21,0, 5); _DEFPIN_ARM(22,0, 4); _DEFPIN_ARM(23,1, 9);
-_DEFPIN_ARM(24,1, 8); _DEFPIN_ARM(25,1, 7); _DEFPIN_ARM(26,1, 6); _DEFPIN_ARM(27,1, 5);
-_DEFPIN_ARM(28,1, 4); _DEFPIN_ARM(29,0, 7); _DEFPIN_ARM(30,1, 3); _DEFPIN_ARM(31,1, 2);
-_DEFPIN_ARM(32,1, 1); _DEFPIN_ARM(33,1, 0); _DEFPIN_ARM(34,0, 3); _DEFPIN_ARM(35,0, 3);
-_DEFPIN_ARM(36,1,30); _DEFPIN_ARM(37,1,31); _DEFPIN_ARM(38,1,22); _DEFPIN_ARM(39,1,23);
-_DEFPIN_ARM(40,0,12); _DEFPIN_ARM(41,0,13); _DEFPIN_ARM(42,0,22); _DEFPIN_ARM(43,0,23);
-_DEFPIN_ARM(44,0,20); _DEFPIN_ARM(45,0,21); _DEFPIN_ARM(46,0,27); _DEFPIN_ARM(47,0,24);
-_DEFPIN_ARM(48,0,25); _DEFPIN_ARM(49,1,13); _DEFPIN_ARM(50,1,14); _DEFPIN_ARM(51,0,17);
-_DEFPIN_ARM(52,0,18); _DEFPIN_ARM(53,1,12); _DEFPIN_ARM(54,1,13); _DEFPIN_ARM(55,1,14);
-_DEFPIN_ARM(56,1,15);
+_FL_DEFPIN( 0, 9,0); _FL_DEFPIN( 1,10,0); _FL_DEFPIN( 2,11,0); _FL_DEFPIN( 3,10,1);
+_FL_DEFPIN( 4,11,1); _FL_DEFPIN( 5,12,1); _FL_DEFPIN( 6,13,1); _FL_DEFPIN( 7,14,1);
+_FL_DEFPIN( 8,15,1); _FL_DEFPIN( 9,14,0); _FL_DEFPIN(10,15,0); _FL_DEFPIN(11,16,0);
+_FL_DEFPIN(12,17,0); _FL_DEFPIN(13,18,0); _FL_DEFPIN(14,19,0); _FL_DEFPIN(15,16,1);
+_FL_DEFPIN(16, 8,0); _FL_DEFPIN(17,28,0); _FL_DEFPIN(18,17,1); _FL_DEFPIN(19, 2,0);
+_FL_DEFPIN(20, 6,0); _FL_DEFPIN(21, 5,0); _FL_DEFPIN(22, 4,0); _FL_DEFPIN(23, 9,1);
+_FL_DEFPIN(24, 8,1); _FL_DEFPIN(25, 7,1); _FL_DEFPIN(26, 6,1); _FL_DEFPIN(27, 5,1);
+_FL_DEFPIN(28, 4,1); _FL_DEFPIN(29, 7,0); _FL_DEFPIN(30, 3,1); _FL_DEFPIN(31, 2,1);
+_FL_DEFPIN(32, 1,1); _FL_DEFPIN(33, 0,1); _FL_DEFPIN(34, 3,0); _FL_DEFPIN(35, 3,0);
+_FL_DEFPIN(36,30,1); _FL_DEFPIN(37,31,1); _FL_DEFPIN(38,22,1); _FL_DEFPIN(39,23,1);
+_FL_DEFPIN(40,12,0); _FL_DEFPIN(41,13,0); _FL_DEFPIN(42,22,0); _FL_DEFPIN(43,23,0);
+_FL_DEFPIN(44,20,0); _FL_DEFPIN(45,21,0); _FL_DEFPIN(46,27,0); _FL_DEFPIN(47,24,0);
+_FL_DEFPIN(48,25,0); _FL_DEFPIN(49,13,1); _FL_DEFPIN(50,14,1); _FL_DEFPIN(51,17,0);
+_FL_DEFPIN(52,18,0); _FL_DEFPIN(53,12,1); _FL_DEFPIN(54,13,1); _FL_DEFPIN(55,14,1);
+_FL_DEFPIN(56,15,1);
 
 #define SPI_DATA 44
 #define SPI_CLOCK 45
@@ -145,43 +145,59 @@ _DEFPIN_ARM(56,1,15);
 #elif defined(ARDUINO_SAMD_WINO)
 
 #define MAX_PIN 22
-_DEFPIN_ARM(  0, 0, 23); _DEFPIN_ARM(  1, 0, 22); _DEFPIN_ARM(  2, 0, 16); _DEFPIN_ARM(  3, 0, 17);
-_DEFPIN_ARM(  4, 0, 18); _DEFPIN_ARM(  5, 0, 19); _DEFPIN_ARM(  6, 0, 24); _DEFPIN_ARM(  7, 0, 25);
-_DEFPIN_ARM(  8, 0, 27); _DEFPIN_ARM(  9, 0, 28); _DEFPIN_ARM( 10, 0, 30); _DEFPIN_ARM( 11, 0, 31);
-_DEFPIN_ARM( 12, 0, 15); _DEFPIN_ARM( 13, 0, 14); _DEFPIN_ARM( 14, 0,  2); _DEFPIN_ARM( 15, 0,  3);
-_DEFPIN_ARM( 16, 0,  4); _DEFPIN_ARM( 17, 0,  5); _DEFPIN_ARM( 18, 0,  6); _DEFPIN_ARM( 19, 0,  7);
-_DEFPIN_ARM( 20, 0,  8); _DEFPIN_ARM( 21, 0,  9); _DEFPIN_ARM( 22, 0, 10); _DEFPIN_ARM( 23, 0, 11);
+_FL_DEFPIN(  0, 23, 0); _FL_DEFPIN(  1, 22, 0); _FL_DEFPIN(  2, 16, 0); _FL_DEFPIN(  3, 17, 0);
+_FL_DEFPIN(  4, 18, 0); _FL_DEFPIN(  5, 19, 0); _FL_DEFPIN(  6, 24, 0); _FL_DEFPIN(  7, 25, 0);
+_FL_DEFPIN(  8, 27, 0); _FL_DEFPIN(  9, 28, 0); _FL_DEFPIN( 10, 30, 0); _FL_DEFPIN( 11, 31, 0);
+_FL_DEFPIN( 12, 15, 0); _FL_DEFPIN( 13, 14, 0); _FL_DEFPIN( 14,  2, 0); _FL_DEFPIN( 15,  3, 0);
+_FL_DEFPIN( 16,  4, 0); _FL_DEFPIN( 17,  5, 0); _FL_DEFPIN( 18,  6, 0); _FL_DEFPIN( 19,  7, 0);
+_FL_DEFPIN( 20,  8, 0); _FL_DEFPIN( 21,  9, 0); _FL_DEFPIN( 22, 10, 0); _FL_DEFPIN( 23, 11, 0);
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 
 #elif defined(ARDUINO_SAMD_MKR1000)
 
 #define MAX_PIN 22
-_DEFPIN_ARM(  0, 0, 22); _DEFPIN_ARM(  1, 0, 23); _DEFPIN_ARM(  2, 0, 10); _DEFPIN_ARM(  3, 0, 11);
-_DEFPIN_ARM(  4, 1, 10); _DEFPIN_ARM(  5, 1, 11); _DEFPIN_ARM(  6, 0, 20); _DEFPIN_ARM(  7, 0, 21);
-_DEFPIN_ARM(  8, 0, 16); _DEFPIN_ARM(  9, 0, 17); _DEFPIN_ARM( 10, 0, 19); _DEFPIN_ARM( 11, 0,  8);
-_DEFPIN_ARM( 12, 0,  9); _DEFPIN_ARM( 13, 1, 23); _DEFPIN_ARM( 14, 1, 22); _DEFPIN_ARM( 15, 0,  2);
-_DEFPIN_ARM( 16, 1,  2); _DEFPIN_ARM( 17, 1,  3); _DEFPIN_ARM( 18, 0,  4); _DEFPIN_ARM( 19, 0,  5);
-_DEFPIN_ARM( 20, 0,  6); _DEFPIN_ARM( 21, 0,  7);
+_FL_DEFPIN(  0, 22, 0); _FL_DEFPIN(  1, 23, 0); _FL_DEFPIN(  2, 10, 0); _FL_DEFPIN(  3, 11, 0);
+_FL_DEFPIN(  4, 10, 1); _FL_DEFPIN(  5, 11, 1); _FL_DEFPIN(  6, 20, 0); _FL_DEFPIN(  7, 21, 0);
+_FL_DEFPIN(  8, 16, 0); _FL_DEFPIN(  9, 17, 0); _FL_DEFPIN( 10, 19, 0); _FL_DEFPIN( 11,  8, 0);
+_FL_DEFPIN( 12,  9, 0); _FL_DEFPIN( 13, 23, 1); _FL_DEFPIN( 14, 22, 1); _FL_DEFPIN( 15,  2, 0);
+_FL_DEFPIN( 16,  2, 1); _FL_DEFPIN( 17,  3, 1); _FL_DEFPIN( 18,  4, 0); _FL_DEFPIN( 19,  5, 0);
+_FL_DEFPIN( 20,  6, 0); _FL_DEFPIN( 21,  7, 0);
 
 #define SPI_DATA 8
 #define SPI_CLOCK 9
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 
+#elif defined(ARDUINO_SAMD_NANO_33_IOT)
+
+#define MAX_PIN 25
+_FL_DEFPIN(  0, 11, 0); _FL_DEFPIN(  1, 10, 0); _FL_DEFPIN(  2, 14, 0); _FL_DEFPIN(  3,  9, 0);
+_FL_DEFPIN(  4,  8, 0); _FL_DEFPIN(  5, 15, 0); _FL_DEFPIN(  6, 20, 0); _FL_DEFPIN(  7, 21, 0);
+_FL_DEFPIN(  8,  6, 0); _FL_DEFPIN(  9,  7, 0); _FL_DEFPIN( 10, 18, 0); _FL_DEFPIN( 11, 16, 0);
+_FL_DEFPIN( 12, 19, 0); _FL_DEFPIN( 13, 17, 0); _FL_DEFPIN( 14,  2, 0); _FL_DEFPIN( 15,  8, 1);
+_FL_DEFPIN( 16,  9, 1); _FL_DEFPIN( 17,  4, 0); _FL_DEFPIN( 18,  5, 0); _FL_DEFPIN( 19,  2, 1);
+_FL_DEFPIN( 20, 22, 0); _FL_DEFPIN( 21, 23, 0); _FL_DEFPIN( 22, 12, 0); _FL_DEFPIN( 23, 10, 1);
+_FL_DEFPIN( 24, 11, 1);
+
+#define SPI_DATA 23
+#define SPI_CLOCK 24
+
+#define HAS_HARDWARE_PIN_SUPPORT 1
+
 #elif defined(ARDUINO_GEMMA_M0)
 
 #define MAX_PIN 4
-_DEFPIN_ARM( 0, 0, 4); _DEFPIN_ARM( 1, 0, 2); _DEFPIN_ARM( 2, 0, 5);
-_DEFPIN_ARM( 3, 0, 0); _DEFPIN_ARM( 4, 0, 1);
+_FL_DEFPIN( 0, 4, 0); _FL_DEFPIN( 1, 2, 0); _FL_DEFPIN( 2, 5, 0);
+_FL_DEFPIN( 3, 0, 0); _FL_DEFPIN( 4, 1, 0);
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 
 #elif defined(ADAFRUIT_TRINKET_M0)
 
 #define MAX_PIN 7
-_DEFPIN_ARM( 0, 0, 8); _DEFPIN_ARM( 1, 0, 2); _DEFPIN_ARM( 2, 0, 9);
-_DEFPIN_ARM( 3, 0, 7); _DEFPIN_ARM( 4, 0, 6); _DEFPIN_ARM( 7, 0, 0); _DEFPIN_ARM( 8, 0, 1);
+_FL_DEFPIN( 0, 8, 0); _FL_DEFPIN( 1, 2, 0); _FL_DEFPIN( 2, 9, 0);
+_FL_DEFPIN( 3, 7, 0); _FL_DEFPIN( 4, 6, 0); _FL_DEFPIN( 7, 0, 0); _FL_DEFPIN( 8, 1, 0);
 
 #define SPI_DATA  4
 #define SPI_CLOCK 3
@@ -191,14 +207,14 @@ _DEFPIN_ARM( 3, 0, 7); _DEFPIN_ARM( 4, 0, 6); _DEFPIN_ARM( 7, 0, 0); _DEFPIN_ARM
 #elif defined(ADAFRUIT_ITSYBITSY_M0)
 
 #define MAX_PIN 16
-_DEFPIN_ARM( 2, 0, 14); _DEFPIN_ARM( 3, 0, 9); _DEFPIN_ARM( 4, 0, 8);
-_DEFPIN_ARM( 5, 0, 15); _DEFPIN_ARM( 6, 0, 20); _DEFPIN_ARM( 7, 0, 21);
-_DEFPIN_ARM( 8, 0, 6); _DEFPIN_ARM( 9, 0, 7); _DEFPIN_ARM( 10, 0, 18);
-_DEFPIN_ARM( 11, 0, 16); _DEFPIN_ARM( 12, 0, 19); _DEFPIN_ARM( 13, 0, 17);
-_DEFPIN_ARM( 29, 0, 10); // MOSI
-_DEFPIN_ARM( 30, 0, 11); // SCK
-_DEFPIN_ARM( 40, 0, 0); //APA102 Clock
-_DEFPIN_ARM( 41, 0, 1) //APA102 Data
+_FL_DEFPIN( 2, 14, 0); _FL_DEFPIN( 3, 9, 0); _FL_DEFPIN( 4, 8, 0);
+_FL_DEFPIN( 5, 15, 0); _FL_DEFPIN( 6, 20, 0); _FL_DEFPIN( 7, 21, 0);
+_FL_DEFPIN( 8, 6, 0); _FL_DEFPIN( 9, 7, 0); _FL_DEFPIN( 10, 18, 0);
+_FL_DEFPIN( 11, 16, 0); _FL_DEFPIN( 12, 19, 0); _FL_DEFPIN( 13, 17, 0);
+_FL_DEFPIN( 29, 10, 0); // MOSI
+_FL_DEFPIN( 30, 11, 0); // SCK
+_FL_DEFPIN( 40, 0, 0); //APA102 Clock
+_FL_DEFPIN( 41, 0, 1) //APA102 Data
 
 #define SPI_DATA  29
 #define SPI_CLOCK 30
diff --git a/platforms/arm/d51/fastpin_arm_d51.h b/platforms/arm/d51/fastpin_arm_d51.h
index 6d14c633..dd40dbfd 100644
--- a/platforms/arm/d51/fastpin_arm_d51.h
+++ b/platforms/arm/d51/fastpin_arm_d51.h
@@ -57,48 +57,71 @@ public:
 #define _R(T) struct __gen_struct_ ## T
 #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile PortGroup * r() { return T; } };
 
-#define _IO32(L) _RD32(GPIO ## L)
+#define _FL_IO(L) _RD32(GPIO ## L)
 
-#define _DEFPIN_ARM(PIN, L, BIT) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, L> {};
+#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, L> {};
 
 // Actual pin definitions
 #if defined(ADAFRUIT_ITSYBITSY_M4_EXPRESS)
 
 #define MAX_PIN 19
 // D0-D13, including D6+D8 (DotStar CLK + DATA)
-_DEFPIN_ARM( 0, 0, 16); _DEFPIN_ARM( 1, 0, 17); _DEFPIN_ARM( 2, 0,  7); _DEFPIN_ARM( 3, 1, 22);
-_DEFPIN_ARM( 4, 0, 14); _DEFPIN_ARM( 5, 0, 15); _DEFPIN_ARM( 6, 1,  2); _DEFPIN_ARM( 7, 0, 18);
-_DEFPIN_ARM( 8, 1,  3); _DEFPIN_ARM( 9, 0, 19); _DEFPIN_ARM(10, 0, 20); _DEFPIN_ARM(11, 0, 21);
-_DEFPIN_ARM(12, 0, 23); _DEFPIN_ARM(13, 0, 22);
+_FL_DEFPIN( 0, 16, 0); _FL_DEFPIN( 1, 17, 0); _FL_DEFPIN( 2,  7, 0); _FL_DEFPIN( 3, 22, 1);
+_FL_DEFPIN( 4, 14, 0); _FL_DEFPIN( 5, 15, 0); _FL_DEFPIN( 6,  2, 1); _FL_DEFPIN( 7, 18, 0);
+_FL_DEFPIN( 8,  3, 1); _FL_DEFPIN( 9, 19, 0); _FL_DEFPIN(10, 20, 0); _FL_DEFPIN(11, 21, 0);
+_FL_DEFPIN(12, 23, 0); _FL_DEFPIN(13, 22, 0);
 // A0-A5
-_DEFPIN_ARM(14, 0,  2); _DEFPIN_ARM(15, 0,  5); _DEFPIN_ARM(16, 1,  8); _DEFPIN_ARM(17, 1,  9);
-_DEFPIN_ARM(18, 0,  4); _DEFPIN_ARM(19, 0,  6); /* A6 is present in variant.h but couldn't find it on the schematic */
+_FL_DEFPIN(14,  2, 0); _FL_DEFPIN(15,  5, 0); _FL_DEFPIN(16,  8, 1); _FL_DEFPIN(17,  9, 1);
+_FL_DEFPIN(18,  4, 0); _FL_DEFPIN(19,  6, 0); /* A6 is present in variant.h but couldn't find it on the schematic */
 // SDA/SCL
-_DEFPIN_ARM(21, 0, 12); _DEFPIN_ARM(22, 0, 13);
+_FL_DEFPIN(21, 12, 0); _FL_DEFPIN(22, 13, 0);
 
 // 23..25  MISO/SCK/MOSI
-_DEFPIN_ARM(23, 1, 23); _DEFPIN_ARM(24, 0,  1); _DEFPIN_ARM(25, 0,  0);
+_FL_DEFPIN(23, 23, 1); _FL_DEFPIN(24,  1, 0); _FL_DEFPIN(25,  0, 0);
 
 #define SPI_DATA 25
 #define SPI_CLOCK 24
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 
+// Actual pin definitions
+#elif defined(ADAFRUIT_METRO_M4_AIRLIFT_LITE)
+
+#define MAX_PIN 20
+// D0-D13, including D6+D8 (DotStar CLK + DATA)
+_FL_DEFPIN( 0, 23, 0); _FL_DEFPIN( 1, 22, 0); _FL_DEFPIN( 2,  17, 1); _FL_DEFPIN( 3, 16, 1);
+_FL_DEFPIN( 4, 13, 1); _FL_DEFPIN( 5, 14, 1); _FL_DEFPIN( 6,  15, 1); _FL_DEFPIN( 7, 12, 1);
+_FL_DEFPIN( 8,  21, 0); _FL_DEFPIN( 9, 20, 0); _FL_DEFPIN(10, 18, 0); _FL_DEFPIN(11, 19, 0);
+_FL_DEFPIN(12, 17, 0); _FL_DEFPIN(13, 16, 0);
+// A0-A5
+_FL_DEFPIN(14,  2, 0); _FL_DEFPIN(15,  5, 0); _FL_DEFPIN(16,  6, 0); _FL_DEFPIN(17,  0, 1);
+_FL_DEFPIN(18,  8, 1); _FL_DEFPIN(19,  9, 1);
+// SDA/SCL
+_FL_DEFPIN(22, 2, 1); _FL_DEFPIN(23, 3, 1);
+
+// 23..25  MISO/SCK/MOSI
+_FL_DEFPIN(24, 14, 0); _FL_DEFPIN(25,  13, 0); _FL_DEFPIN(26,  12, 0);
+
+#define SPI_DATA 26
+#define SPI_CLOCK 25
+
+#define HAS_HARDWARE_PIN_SUPPORT 1
+
 #elif defined(ADAFRUIT_FEATHER_M4_EXPRESS)
 
 #define MAX_PIN 19
 // D0-D13, including D8 (neopixel)  no pins 2 3
-_DEFPIN_ARM( 0, 1, 17); _DEFPIN_ARM( 1, 1, 16);
-_DEFPIN_ARM( 4, 0, 14); _DEFPIN_ARM( 5, 0, 16); _DEFPIN_ARM( 6, 0,  18);
-_DEFPIN_ARM( 8, 1,  3); _DEFPIN_ARM( 9, 0, 19); _DEFPIN_ARM(10, 0, 20); _DEFPIN_ARM(11, 0, 21);
-_DEFPIN_ARM(12, 0, 22); _DEFPIN_ARM(13, 0, 23);
+_FL_DEFPIN( 0, 17, 1); _FL_DEFPIN( 1, 16, 1);
+_FL_DEFPIN( 4, 14, 0); _FL_DEFPIN( 5, 16, 0); _FL_DEFPIN( 6,  18, 0);
+_FL_DEFPIN( 8,  3, 1); _FL_DEFPIN( 9, 19, 0); _FL_DEFPIN(10, 20, 0); _FL_DEFPIN(11, 21, 0);
+_FL_DEFPIN(12, 22, 0); _FL_DEFPIN(13, 23, 0);
 // A0-A5
-_DEFPIN_ARM(14, 0,  2); _DEFPIN_ARM(15, 0,  5); _DEFPIN_ARM(16, 1,  8); _DEFPIN_ARM(17, 1,  9);
-_DEFPIN_ARM(18, 0,  4); _DEFPIN_ARM(19, 0,  6); /* A6 is present in variant.h but couldn't find it on the schematic */
+_FL_DEFPIN(14,  2, 0); _FL_DEFPIN(15,  5, 0); _FL_DEFPIN(16,  8, 1); _FL_DEFPIN(17,  9, 1);
+_FL_DEFPIN(18,  4, 0); _FL_DEFPIN(19,  6, 0); /* A6 is present in variant.h but couldn't find it on the schematic */
 // SDA/SCL
-_DEFPIN_ARM(21, 0, 12); _DEFPIN_ARM(22, 0, 13);
+_FL_DEFPIN(21, 12, 0); _FL_DEFPIN(22, 13, 0);
 // 23..25  MISO/MOSI/SCK
-_DEFPIN_ARM(23, 1, 22); _DEFPIN_ARM(24, 1,  23); _DEFPIN_ARM(25, 0,  17);
+_FL_DEFPIN(23, 22, 1); _FL_DEFPIN(24,  23, 1); _FL_DEFPIN(25,  17, 0);
 
 #define SPI_DATA 24
 #define SPI_CLOCK 25
diff --git a/platforms/arm/k20/fastpin_arm_k20.h b/platforms/arm/k20/fastpin_arm_k20.h
index b26e5607..736bd461 100644
--- a/platforms/arm/k20/fastpin_arm_k20.h
+++ b/platforms/arm/k20/fastpin_arm_k20.h
@@ -78,28 +78,28 @@ public:
 #define _R(T) struct __gen_struct_ ## T
 #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
 	template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
-#define _IO32(L) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR);
+#define _FL_IO(L,C) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR); _FL_DEFINE_PORT3(L,C,_R(GPIO ## L ## _PDOR));
 
-#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
+#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
 																			_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; \
 									template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
  																			_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {};
 
 // Actual pin definitions
-#if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY)
+_FL_IO(A,0); _FL_IO(B,1); _FL_IO(C,2); _FL_IO(D,3); _FL_IO(E,4);
 
-_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E);
+#if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY)
 
 #define MAX_PIN 33
-_DEFPIN_ARM(0, 16, B); _DEFPIN_ARM(1, 17, B); _DEFPIN_ARM(2, 0, D); _DEFPIN_ARM(3, 12, A);
-_DEFPIN_ARM(4, 13, A); _DEFPIN_ARM(5, 7, D); _DEFPIN_ARM(6, 4, D); _DEFPIN_ARM(7, 2, D);
-_DEFPIN_ARM(8, 3, D); _DEFPIN_ARM(9, 3, C); _DEFPIN_ARM(10, 4, C); _DEFPIN_ARM(11, 6, C);
-_DEFPIN_ARM(12, 7, C); _DEFPIN_ARM(13, 5, C); _DEFPIN_ARM(14, 1, D); _DEFPIN_ARM(15, 0, C);
-_DEFPIN_ARM(16, 0, B); _DEFPIN_ARM(17, 1, B); _DEFPIN_ARM(18, 3, B); _DEFPIN_ARM(19, 2, B);
-_DEFPIN_ARM(20, 5, D); _DEFPIN_ARM(21, 6, D); _DEFPIN_ARM(22, 1, C); _DEFPIN_ARM(23, 2, C);
-_DEFPIN_ARM(24, 5, A); _DEFPIN_ARM(25, 19, B); _DEFPIN_ARM(26, 1, E); _DEFPIN_ARM(27, 9, C);
-_DEFPIN_ARM(28, 8, C); _DEFPIN_ARM(29, 10, C); _DEFPIN_ARM(30, 11, C); _DEFPIN_ARM(31, 0, E);
-_DEFPIN_ARM(32, 18, B); _DEFPIN_ARM(33, 4, A);
+_FL_DEFPIN(0, 16, B); _FL_DEFPIN(1, 17, B); _FL_DEFPIN(2, 0, D); _FL_DEFPIN(3, 12, A);
+_FL_DEFPIN(4, 13, A); _FL_DEFPIN(5, 7, D); _FL_DEFPIN(6, 4, D); _FL_DEFPIN(7, 2, D);
+_FL_DEFPIN(8, 3, D); _FL_DEFPIN(9, 3, C); _FL_DEFPIN(10, 4, C); _FL_DEFPIN(11, 6, C);
+_FL_DEFPIN(12, 7, C); _FL_DEFPIN(13, 5, C); _FL_DEFPIN(14, 1, D); _FL_DEFPIN(15, 0, C);
+_FL_DEFPIN(16, 0, B); _FL_DEFPIN(17, 1, B); _FL_DEFPIN(18, 3, B); _FL_DEFPIN(19, 2, B);
+_FL_DEFPIN(20, 5, D); _FL_DEFPIN(21, 6, D); _FL_DEFPIN(22, 1, C); _FL_DEFPIN(23, 2, C);
+_FL_DEFPIN(24, 5, A); _FL_DEFPIN(25, 19, B); _FL_DEFPIN(26, 1, E); _FL_DEFPIN(27, 9, C);
+_FL_DEFPIN(28, 8, C); _FL_DEFPIN(29, 10, C); _FL_DEFPIN(30, 11, C); _FL_DEFPIN(31, 0, E);
+_FL_DEFPIN(32, 18, B); _FL_DEFPIN(33, 4, A);
 
 #define SPI_DATA 11
 #define SPI_CLOCK 13
diff --git a/platforms/arm/k20/fastspi_arm_k20.h b/platforms/arm/k20/fastspi_arm_k20.h
index 70210a39..05123243 100644
--- a/platforms/arm/k20/fastspi_arm_k20.h
+++ b/platforms/arm/k20/fastspi_arm_k20.h
@@ -94,7 +94,7 @@ template <int VAL> void getScalars(uint32_t & preScalar, uint32_t & scalar, uint
 
 #define SPIX (*(SPI_t*)pSPIX)
 
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER, uint32_t pSPIX>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER, uint32_t pSPIX>
 class ARMHardwareSPIOutput {
 	Selectable *m_pSelect;
 	SPIState gState;
diff --git a/platforms/arm/k20/octows2811_controller.h b/platforms/arm/k20/octows2811_controller.h
index 63f6d8f6..84c28667 100644
--- a/platforms/arm/k20/octows2811_controller.h
+++ b/platforms/arm/k20/octows2811_controller.h
@@ -28,7 +28,7 @@ class COctoWS2811Controller : public CPixelLEDController<RGB_ORDER, 8, 0xFF> {
   }
 public:
   COctoWS2811Controller() { pocto = NULL; }
-
+  virtual int size() { return CLEDController::size() * 8; }
 
   virtual void init() { /* do nothing yet */ }
 
diff --git a/platforms/arm/k66/fastpin_arm_k66.h b/platforms/arm/k66/fastpin_arm_k66.h
index e201096c..ef48396c 100644
--- a/platforms/arm/k66/fastpin_arm_k66.h
+++ b/platforms/arm/k66/fastpin_arm_k66.h
@@ -78,35 +78,35 @@ public:
 #define _R(T) struct __gen_struct_ ## T
 #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
 	template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
-#define _IO32(L) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR);
+#define _FL_IO(L,C) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR); _FL_DEFINE_PORT3(L,C,_R(GPIO ## L ## _PDOR));
 
-#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
+#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
 																			_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; \
 									template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
  																			_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {};
 
+_FL_IO(A,0); _FL_IO(B,1); _FL_IO(C,2); _FL_IO(D,3); _FL_IO(E,4);
+
 // Actual pin definitions
 #if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY)
 
-_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E);
-
 #define MAX_PIN 63
-_DEFPIN_ARM( 0, 16, B); _DEFPIN_ARM( 1, 17, B); _DEFPIN_ARM( 2,  0, D); _DEFPIN_ARM( 3, 12, A);
-_DEFPIN_ARM( 4, 13, A); _DEFPIN_ARM( 5,  7, D); _DEFPIN_ARM( 6,  4, D); _DEFPIN_ARM( 7,  2, D);
-_DEFPIN_ARM( 8,  3, D); _DEFPIN_ARM( 9,  3, C); _DEFPIN_ARM(10,  4, C); _DEFPIN_ARM(11,  6, C);
-_DEFPIN_ARM(12,  7, C); _DEFPIN_ARM(13,  5, C); _DEFPIN_ARM(14,  1, D); _DEFPIN_ARM(15,  0, C);
-_DEFPIN_ARM(16,  0, B); _DEFPIN_ARM(17,  1, B); _DEFPIN_ARM(18,  3, B); _DEFPIN_ARM(19,  2, B);
-_DEFPIN_ARM(20,  5, D); _DEFPIN_ARM(21,  6, D); _DEFPIN_ARM(22,  1, C); _DEFPIN_ARM(23,  2, C);
-_DEFPIN_ARM(24, 26, E); _DEFPIN_ARM(25,  5, A); _DEFPIN_ARM(26, 14, A); _DEFPIN_ARM(27, 15, A);
-_DEFPIN_ARM(28, 16, A); _DEFPIN_ARM(29, 18, B); _DEFPIN_ARM(30, 19, B); _DEFPIN_ARM(31, 10, B);
-_DEFPIN_ARM(32, 11, B); _DEFPIN_ARM(33, 24, E); _DEFPIN_ARM(34, 25, E); _DEFPIN_ARM(35,  8, C);
-_DEFPIN_ARM(36,  9, C); _DEFPIN_ARM(37, 10, C); _DEFPIN_ARM(38, 11, C); _DEFPIN_ARM(39, 17, A);
-_DEFPIN_ARM(40, 28, A); _DEFPIN_ARM(41, 29, A); _DEFPIN_ARM(42, 26, A); _DEFPIN_ARM(43, 20, B);
-_DEFPIN_ARM(44, 22, B); _DEFPIN_ARM(45, 23, B); _DEFPIN_ARM(46, 21, B); _DEFPIN_ARM(47,  8, D);
-_DEFPIN_ARM(48,  9, D); _DEFPIN_ARM(49,  4, B); _DEFPIN_ARM(50,  5, B); _DEFPIN_ARM(51, 14, D);
-_DEFPIN_ARM(52, 13, D); _DEFPIN_ARM(53, 12, D); _DEFPIN_ARM(54, 15, D); _DEFPIN_ARM(55, 11, D);
-_DEFPIN_ARM(56, 10, E); _DEFPIN_ARM(57, 11, E); _DEFPIN_ARM(58,  0, E); _DEFPIN_ARM(59,  1, E);
-_DEFPIN_ARM(60,  2, E); _DEFPIN_ARM(61,  3, E); _DEFPIN_ARM(62,  4, E); _DEFPIN_ARM(63,  5, E);
+_FL_DEFPIN( 0, 16, B); _FL_DEFPIN( 1, 17, B); _FL_DEFPIN( 2,  0, D); _FL_DEFPIN( 3, 12, A);
+_FL_DEFPIN( 4, 13, A); _FL_DEFPIN( 5,  7, D); _FL_DEFPIN( 6,  4, D); _FL_DEFPIN( 7,  2, D);
+_FL_DEFPIN( 8,  3, D); _FL_DEFPIN( 9,  3, C); _FL_DEFPIN(10,  4, C); _FL_DEFPIN(11,  6, C);
+_FL_DEFPIN(12,  7, C); _FL_DEFPIN(13,  5, C); _FL_DEFPIN(14,  1, D); _FL_DEFPIN(15,  0, C);
+_FL_DEFPIN(16,  0, B); _FL_DEFPIN(17,  1, B); _FL_DEFPIN(18,  3, B); _FL_DEFPIN(19,  2, B);
+_FL_DEFPIN(20,  5, D); _FL_DEFPIN(21,  6, D); _FL_DEFPIN(22,  1, C); _FL_DEFPIN(23,  2, C);
+_FL_DEFPIN(24, 26, E); _FL_DEFPIN(25,  5, A); _FL_DEFPIN(26, 14, A); _FL_DEFPIN(27, 15, A);
+_FL_DEFPIN(28, 16, A); _FL_DEFPIN(29, 18, B); _FL_DEFPIN(30, 19, B); _FL_DEFPIN(31, 10, B);
+_FL_DEFPIN(32, 11, B); _FL_DEFPIN(33, 24, E); _FL_DEFPIN(34, 25, E); _FL_DEFPIN(35,  8, C);
+_FL_DEFPIN(36,  9, C); _FL_DEFPIN(37, 10, C); _FL_DEFPIN(38, 11, C); _FL_DEFPIN(39, 17, A);
+_FL_DEFPIN(40, 28, A); _FL_DEFPIN(41, 29, A); _FL_DEFPIN(42, 26, A); _FL_DEFPIN(43, 20, B);
+_FL_DEFPIN(44, 22, B); _FL_DEFPIN(45, 23, B); _FL_DEFPIN(46, 21, B); _FL_DEFPIN(47,  8, D);
+_FL_DEFPIN(48,  9, D); _FL_DEFPIN(49,  4, B); _FL_DEFPIN(50,  5, B); _FL_DEFPIN(51, 14, D);
+_FL_DEFPIN(52, 13, D); _FL_DEFPIN(53, 12, D); _FL_DEFPIN(54, 15, D); _FL_DEFPIN(55, 11, D);
+_FL_DEFPIN(56, 10, E); _FL_DEFPIN(57, 11, E); _FL_DEFPIN(58,  0, E); _FL_DEFPIN(59,  1, E);
+_FL_DEFPIN(60,  2, E); _FL_DEFPIN(61,  3, E); _FL_DEFPIN(62,  4, E); _FL_DEFPIN(63,  5, E);
 
 
 
diff --git a/platforms/arm/k66/fastspi_arm_k66.h b/platforms/arm/k66/fastspi_arm_k66.h
index 7e598cff..a40e5985 100644
--- a/platforms/arm/k66/fastspi_arm_k66.h
+++ b/platforms/arm/k66/fastspi_arm_k66.h
@@ -102,7 +102,7 @@ template <int VAL> void getScalars(uint32_t & preScalar, uint32_t & scalar, uint
 
 #define SPIX (*(SPI_t*)pSPIX)
 
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER, uint32_t pSPIX>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER, uint32_t pSPIX>
 class ARMHardwareSPIOutput {
 	Selectable *m_pSelect;
 	SPIState gState;
diff --git a/platforms/arm/kl26/fastpin_arm_kl26.h b/platforms/arm/kl26/fastpin_arm_kl26.h
index 4c30cd78..8b3cbdfe 100644
--- a/platforms/arm/kl26/fastpin_arm_kl26.h
+++ b/platforms/arm/kl26/fastpin_arm_kl26.h
@@ -50,26 +50,26 @@ public:
 #define _R(T) struct __gen_struct_ ## T
 #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
 template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
-#define _IO32(L) _RD32(FGPIO ## L ## _PDOR); _RD32(FGPIO ## L ## _PSOR); _RD32(FGPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(FGPIO ## L ## _PDIR); _RD32(FGPIO ## L ## _PDDR);
+#define _FL_IO(L,C) _RD32(FGPIO ## L ## _PDOR); _RD32(FGPIO ## L ## _PSOR); _RD32(FGPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(FGPIO ## L ## _PDIR); _RD32(FGPIO ## L ## _PDDR); _FL_DEFINE_PORT3(L,C,_R(FGPIO ## L ## _PDOR));
 
-#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(FGPIO ## L ## _PDOR), _R(FGPIO ## L ## _PSOR), _R(FGPIO ## L ## _PCOR), \
+#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(FGPIO ## L ## _PDOR), _R(FGPIO ## L ## _PSOR), _R(FGPIO ## L ## _PCOR), \
 _R(GPIO ## L ## _PTOR), _R(FGPIO ## L ## _PDIR), _R(FGPIO ## L ## _PDDR)> {}; \
 /* template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
 _R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; */
 
+_FL_IO(A,0); _FL_IO(B,1); _FL_IO(C,2); _FL_IO(D,3); _FL_IO(E,4);
+
 // Actual pin definitions
 #if defined(FASTLED_TEENSYLC) && defined(CORE_TEENSY)
 
-_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E);
-
 #define MAX_PIN 26
-_DEFPIN_ARM(0, 16, B); _DEFPIN_ARM(1, 17, B); _DEFPIN_ARM(2, 0, D); _DEFPIN_ARM(3, 1, A);
-_DEFPIN_ARM(4, 2, A); _DEFPIN_ARM(5, 7, D); _DEFPIN_ARM(6, 4, D); _DEFPIN_ARM(7, 2, D);
-_DEFPIN_ARM(8, 3, D); _DEFPIN_ARM(9, 3, C); _DEFPIN_ARM(10, 4, C); _DEFPIN_ARM(11, 6, C);
-_DEFPIN_ARM(12, 7, C); _DEFPIN_ARM(13, 5, C); _DEFPIN_ARM(14, 1, D); _DEFPIN_ARM(15, 0, C);
-_DEFPIN_ARM(16, 0, B); _DEFPIN_ARM(17, 1, B); _DEFPIN_ARM(18, 3, B); _DEFPIN_ARM(19, 2, B);
-_DEFPIN_ARM(20, 5, D); _DEFPIN_ARM(21, 6, D); _DEFPIN_ARM(22, 1, C); _DEFPIN_ARM(23, 2, C);
-_DEFPIN_ARM(24, 20, E); _DEFPIN_ARM(25, 21, E); _DEFPIN_ARM(26, 30, E);
+_FL_DEFPIN(0, 16, B); _FL_DEFPIN(1, 17, B); _FL_DEFPIN(2, 0, D); _FL_DEFPIN(3, 1, A);
+_FL_DEFPIN(4, 2, A); _FL_DEFPIN(5, 7, D); _FL_DEFPIN(6, 4, D); _FL_DEFPIN(7, 2, D);
+_FL_DEFPIN(8, 3, D); _FL_DEFPIN(9, 3, C); _FL_DEFPIN(10, 4, C); _FL_DEFPIN(11, 6, C);
+_FL_DEFPIN(12, 7, C); _FL_DEFPIN(13, 5, C); _FL_DEFPIN(14, 1, D); _FL_DEFPIN(15, 0, C);
+_FL_DEFPIN(16, 0, B); _FL_DEFPIN(17, 1, B); _FL_DEFPIN(18, 3, B); _FL_DEFPIN(19, 2, B);
+_FL_DEFPIN(20, 5, D); _FL_DEFPIN(21, 6, D); _FL_DEFPIN(22, 1, C); _FL_DEFPIN(23, 2, C);
+_FL_DEFPIN(24, 20, E); _FL_DEFPIN(25, 21, E); _FL_DEFPIN(26, 30, E);
 
 #define SPI_DATA 11
 #define SPI_CLOCK 13
diff --git a/platforms/arm/kl26/fastspi_arm_kl26.h b/platforms/arm/kl26/fastspi_arm_kl26.h
index 869b6054..b1e76677 100644
--- a/platforms/arm/kl26/fastspi_arm_kl26.h
+++ b/platforms/arm/kl26/fastspi_arm_kl26.h
@@ -82,7 +82,7 @@ template <int VAL> void getScalars(uint8_t & sppr, uint8_t & spr) {
 #define SPIX (*(KINETISL_SPI_t*)pSPIX)
 #define ARM_HARDWARE_SPI
 
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER, uint32_t pSPIX>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER, uint32_t pSPIX>
 class ARMHardwareSPIOutput {
   Selectable *m_pSelect;
 
diff --git a/platforms/arm/kl26/led_sysdefs_arm_kl26.h b/platforms/arm/kl26/led_sysdefs_arm_kl26.h
index 466d7295..575e6399 100644
--- a/platforms/arm/kl26/led_sysdefs_arm_kl26.h
+++ b/platforms/arm/kl26/led_sysdefs_arm_kl26.h
@@ -13,7 +13,7 @@
 
 // Default to allowing interrupts
 #ifndef FASTLED_ALLOW_INTERRUPTS
-#define FASTLED_ALLOW_INTERRUPTS 1
+// #define FASTLED_ALLOW_INTERRUPTS 1
 #endif
 
 #if FASTLED_ALLOW_INTERRUPTS == 1
diff --git a/platforms/arm/mxrt1062/block_clockless_arm_mxrt1062.h b/platforms/arm/mxrt1062/block_clockless_arm_mxrt1062.h
new file mode 100644
index 00000000..694297e2
--- /dev/null
+++ b/platforms/arm/mxrt1062/block_clockless_arm_mxrt1062.h
@@ -0,0 +1,214 @@
+#ifndef __INC_BLOCK_CLOCKLESS_ARM_MXRT1062_H
+#define __INC_BLOCK_CLOCKLESS_ARM_MXRT1062_H
+
+FASTLED_NAMESPACE_BEGIN
+
+// Definition for a single channel clockless controller for the teensy4
+// See clockless.h for detailed info on how the template parameters are used.
+#if defined(FASTLED_TEENSY4)
+
+#define __FL_T4_MASK ((1<<(LANES))-1)
+template <uint8_t LANES, int FIRST_PIN, int T1, int T2, int T3, EOrder RGB_ORDER = GRB, int XTRA0 = 0, bool FLIP = false, int WAIT_TIME = 50>
+class FlexibleInlineBlockClocklessController : public CPixelLEDController<RGB_ORDER, LANES, __FL_T4_MASK> {
+
+  uint8_t m_bitOffsets[16];
+  uint8_t m_nActualLanes;
+  uint8_t m_nLowBit;
+  uint8_t m_nHighBit;
+  uint32_t m_nWriteMask;
+  uint8_t m_nOutBlocks;
+  uint32_t m_offsets[3];
+  CMinWait<WAIT_TIME> mWait;
+public:
+
+  virtual int size() { return CLEDController::size() * m_nActualLanes; }
+
+// For each pin, if we've hit our lane count, break, otherwise set the pin to output,
+// store the bit offset in our offset array, add this pin to the write mask, and if this
+// pin ends a block sequence, then break out of the switch as well
+#define _BLOCK_PIN(P) case P: {                           \
+  if(m_nActualLanes == LANES) break;                      \
+  FastPin<P>::setOutput();                                \
+  m_bitOffsets[m_nActualLanes++] = FastPin<P>::pinbit();  \
+  m_nWriteMask |= FastPin<P>::mask();                     \
+  if( P == 27 || P == 7 || P == 30) break;                \
+}
+
+  virtual void init() {
+    // pre-initialize
+    memset(m_bitOffsets,0,16);
+    m_nActualLanes = 0;
+    m_nLowBit = 33;
+    m_nHighBit = 0;
+    m_nWriteMask = 0;
+
+    // setup the bits and data tracking for parallel output
+    switch(FIRST_PIN) {
+      // GPIO6 block output
+      _BLOCK_PIN( 1);
+			_BLOCK_PIN( 0);
+			_BLOCK_PIN(24);
+			_BLOCK_PIN(25);
+			_BLOCK_PIN(19);
+			_BLOCK_PIN(18);
+			_BLOCK_PIN(14);
+			_BLOCK_PIN(15);
+			_BLOCK_PIN(17);
+			_BLOCK_PIN(16);
+			_BLOCK_PIN(22);
+			_BLOCK_PIN(23);
+			_BLOCK_PIN(20);
+			_BLOCK_PIN(21);
+			_BLOCK_PIN(26);
+			_BLOCK_PIN(27);
+      // GPIO7 block output
+			_BLOCK_PIN(10);
+			_BLOCK_PIN(12);
+			_BLOCK_PIN(11);
+			_BLOCK_PIN(13);
+			_BLOCK_PIN( 6);
+			_BLOCK_PIN( 9);
+			_BLOCK_PIN(32);
+			_BLOCK_PIN( 8);
+			_BLOCK_PIN( 7);
+      // GPIO 37 block output
+			_BLOCK_PIN(37);
+			_BLOCK_PIN(36);
+			_BLOCK_PIN(35);
+			_BLOCK_PIN(34);
+			_BLOCK_PIN(39);
+			_BLOCK_PIN(38);
+			_BLOCK_PIN(28);
+			_BLOCK_PIN(31);
+			_BLOCK_PIN(30);
+    }
+
+    for(int i = 0; i < m_nActualLanes; i++) {
+      if(m_bitOffsets[i] < m_nLowBit) { m_nLowBit = m_bitOffsets[i]; }
+      if(m_bitOffsets[i] > m_nHighBit) { m_nHighBit = m_bitOffsets[i]; }
+    }
+
+    m_nOutBlocks = (m_nHighBit + 8)/8;
+
+  }
+
+
+  virtual void showPixels(PixelController<RGB_ORDER, LANES, __FL_T4_MASK> & pixels) {
+		mWait.wait();
+    #if FASTLED_ALLOW_INTERRUPTS == 0
+		uint32_t clocks = showRGBInternal(pixels);
+		// Adjust the timer
+		long microsTaken = CLKS_TO_MICROS(clocks);
+		MS_COUNTER += (1 + (microsTaken / 1000));
+		#else
+      showRGBInternal(pixels);
+    #endif
+
+		mWait.mark();
+	}
+
+  typedef union {
+    uint8_t bytes[32];
+    uint8_t bg[4][8];
+    uint16_t shorts[16];
+    uint32_t raw[8];
+  } _outlines;
+
+
+  template<int BITS,int PX> __attribute__ ((always_inline)) inline void writeBits(register uint32_t & next_mark, register _outlines & b, PixelController<RGB_ORDER, LANES, __FL_T4_MASK> &pixels) {
+    _outlines b2;
+    transpose8x1(b.bg[3], b2.bg[3]);
+    transpose8x1(b.bg[2], b2.bg[2]);
+    transpose8x1(b.bg[1], b2.bg[1]);
+    transpose8x1(b.bg[0], b2.bg[0]);
+
+    register uint8_t d = pixels.template getd<PX>(pixels);
+    register uint8_t scale = pixels.template getscale<PX>(pixels);
+
+    int x = 0;
+    for(uint32_t i = 8; i > 0;) {
+      i--;
+      while(ARM_DWT_CYCCNT < next_mark);
+      *FastPin<FIRST_PIN>::sport() = m_nWriteMask;
+      next_mark = ARM_DWT_CYCCNT + m_offsets[0];
+
+      uint32_t out = (b2.bg[3][i] << 24) | (b2.bg[2][i] << 16) | (b2.bg[1][i] << 8) | b2.bg[0][i];
+
+      out = ((~out) & m_nWriteMask);
+      while((next_mark - ARM_DWT_CYCCNT) > m_offsets[1]);
+      *FastPin<FIRST_PIN>::cport() = out;
+
+      out = m_nWriteMask;
+      while((next_mark - ARM_DWT_CYCCNT) > m_offsets[2]);
+      *FastPin<FIRST_PIN>::cport() = out;
+
+      // Read and store up to two bytes
+      if (x < m_nActualLanes) {
+        b.bytes[m_bitOffsets[x]] = pixels.template loadAndScale<PX>(pixels,x,d,scale);
+        x++;
+        if (x < m_nActualLanes) {
+          b.bytes[m_bitOffsets[x]] = pixels.template loadAndScale<PX>(pixels,x,d,scale);
+          x++;
+        }
+      }
+    }
+  }
+
+  uint32_t showRGBInternal(PixelController<RGB_ORDER,LANES, __FL_T4_MASK> &allpixels) {
+    allpixels.preStepFirstByteDithering();
+    _outlines b0;
+    uint32_t start = ARM_DWT_CYCCNT;
+
+    for(int i = 0; i < m_nActualLanes; i++) {
+      b0.bytes[m_bitOffsets[i]] = allpixels.loadAndScale0(i);
+    }
+
+    cli();
+    m_offsets[0] = _FASTLED_NS_TO_DWT(T1+T2+T3);
+    m_offsets[1] = _FASTLED_NS_TO_DWT(T2+T3);
+    m_offsets[2] = _FASTLED_NS_TO_DWT(T3);
+    uint32_t wait_off = _FASTLED_NS_TO_DWT((WAIT_TIME-INTERRUPT_THRESHOLD));
+
+    uint32_t next_mark = ARM_DWT_CYCCNT + m_offsets[0];
+
+    while(allpixels.has(1)) {
+      allpixels.stepDithering();
+      #if (FASTLED_ALLOW_INTERRUPTS == 1)
+			cli();
+			// if interrupts took longer than 45µs, punt on the current frame
+			if(ARM_DWT_CYCCNT > next_mark) {
+				if((ARM_DWT_CYCCNT-next_mark) > wait_off) { sei(); return ARM_DWT_CYCCNT - start; }
+			}
+			#endif
+
+			// Write first byte, read next byte
+			writeBits<8+XTRA0,1>(next_mark, b0, allpixels);
+
+			// Write second byte, read 3rd byte
+			writeBits<8+XTRA0,2>(next_mark, b0, allpixels);
+			allpixels.advanceData();
+
+			// Write third byte
+			writeBits<8+XTRA0,0>(next_mark, b0, allpixels);
+
+			#if (FASTLED_ALLOW_INTERRUPTS == 1)
+			sei();
+			#endif
+    }
+
+    sei();
+
+    return ARM_DWT_CYCCNT - start;
+  }
+};
+
+template<template<uint8_t DATA_PIN, EOrder RGB_ORDER> class CHIPSET, uint8_t DATA_PIN, int NUM_LANES, EOrder RGB_ORDER=GRB>
+class __FIBCC : public FlexibleInlineBlockClocklessController<NUM_LANES,DATA_PIN,CHIPSET<DATA_PIN,RGB_ORDER>::__T1(),CHIPSET<DATA_PIN,RGB_ORDER>::__T2(),CHIPSET<DATA_PIN,RGB_ORDER>::__T3(),RGB_ORDER,CHIPSET<DATA_PIN,RGB_ORDER>::__XTRA0(),CHIPSET<DATA_PIN,RGB_ORDER>::__FLIP(),CHIPSET<DATA_PIN,RGB_ORDER>::__WAIT_TIME()> {};
+
+#define __FASTLED_HAS_FIBCC 1
+
+#endif //defined(FASTLED_TEENSY4)
+
+FASTLED_NAMESPACE_END
+
+#endif
diff --git a/platforms/arm/mxrt1062/clockless_arm_mxrt1062.h b/platforms/arm/mxrt1062/clockless_arm_mxrt1062.h
new file mode 100644
index 00000000..468c15dd
--- /dev/null
+++ b/platforms/arm/mxrt1062/clockless_arm_mxrt1062.h
@@ -0,0 +1,128 @@
+#ifndef __INC_CLOCKLESS_ARM_MXRT1062_H
+#define __INC_CLOCKLESS_ARM_MXRT1062_H
+
+FASTLED_NAMESPACE_BEGIN
+
+// Definition for a single channel clockless controller for the teensy4
+// See clockless.h for detailed info on how the template parameters are used.
+#if defined(FASTLED_TEENSY4)
+
+#define FASTLED_HAS_CLOCKLESS 1
+
+#define _FASTLED_NS_TO_DWT(_NS) (((F_CPU_ACTUAL>>16)*(_NS)) / (1000000000UL>>16))
+
+template <int DATA_PIN, int T1, int T2, int T3, EOrder RGB_ORDER = RGB, int XTRA0 = 0, bool FLIP = false, int WAIT_TIME = 50>
+class ClocklessController : public CPixelLEDController<RGB_ORDER> {
+	typedef typename FastPin<DATA_PIN>::port_ptr_t data_ptr_t;
+	typedef typename FastPin<DATA_PIN>::port_t data_t;
+
+	data_t mPinMask;
+	data_ptr_t mPort;
+	CMinWait<WAIT_TIME> mWait;
+	uint32_t off[3];
+
+public:
+	static constexpr int __DATA_PIN() { return DATA_PIN; }
+	static constexpr int __T1() { return T1; }
+	static constexpr int __T2() { return T2; }
+	static constexpr int __T3() { return T3; }
+	static constexpr EOrder __RGB_ORDER() { return RGB_ORDER; }
+	static constexpr int __XTRA0() { return XTRA0; }
+	static constexpr bool __FLIP() { return FLIP; }
+	static constexpr int __WAIT_TIME() { return WAIT_TIME; }
+
+	virtual void init() {
+		FastPin<DATA_PIN>::setOutput();
+		mPinMask = FastPin<DATA_PIN>::mask();
+		mPort = FastPin<DATA_PIN>::port();
+    FastPin<DATA_PIN>::lo();
+	}
+
+protected:
+
+	virtual void showPixels(PixelController<RGB_ORDER> & pixels) {
+    mWait.wait();
+		if(!showRGBInternal(pixels)) {
+      sei(); delayMicroseconds(WAIT_TIME); cli();
+      showRGBInternal(pixels);
+    }
+    mWait.mark();
+  }
+
+	template<int BITS> __attribute__ ((always_inline)) inline void writeBits(register uint32_t & next_mark, register uint32_t & b)  {
+		for(register uint32_t i = BITS-1; i > 0; i--) {
+			while(ARM_DWT_CYCCNT < next_mark);
+			next_mark = ARM_DWT_CYCCNT + off[0];
+			FastPin<DATA_PIN>::hi();
+			if(b&0x80) {
+				while((next_mark - ARM_DWT_CYCCNT) > off[1]);
+				FastPin<DATA_PIN>::lo();
+			} else {
+				while((next_mark - ARM_DWT_CYCCNT) > off[2]);
+				FastPin<DATA_PIN>::lo();
+			}
+			b <<= 1;
+		}
+
+		while(ARM_DWT_CYCCNT < next_mark);
+		next_mark = ARM_DWT_CYCCNT + off[1];
+		FastPin<DATA_PIN>::hi();
+
+		if(b&0x80) {
+			while((next_mark - ARM_DWT_CYCCNT) > off[2]);
+			FastPin<DATA_PIN>::lo();
+		} else {
+			while((next_mark - ARM_DWT_CYCCNT) > off[2]);
+			FastPin<DATA_PIN>::lo();
+		}
+	}
+
+	uint32_t showRGBInternal(PixelController<RGB_ORDER> pixels) {
+		uint32_t start = ARM_DWT_CYCCNT;
+
+		// Setup the pixel controller and load/scale the first byte
+		pixels.preStepFirstByteDithering();
+		register uint32_t b = pixels.loadAndScale0();
+
+		cli();
+    off[0] = _FASTLED_NS_TO_DWT(T1+T2+T3);
+    off[1] = _FASTLED_NS_TO_DWT(T2+T3);
+		off[2] = _FASTLED_NS_TO_DWT(T3);
+    uint32_t wait_off = _FASTLED_NS_TO_DWT((WAIT_TIME-INTERRUPT_THRESHOLD));
+
+    uint32_t next_mark = ARM_DWT_CYCCNT + off[0];
+
+		while(pixels.has(1)) {
+			pixels.stepDithering();
+			#if (FASTLED_ALLOW_INTERRUPTS == 1)
+			cli();
+			// if interrupts took longer than 45µs, punt on the current frame
+			if(ARM_DWT_CYCCNT > next_mark) {
+				if((ARM_DWT_CYCCNT-next_mark) > wait_off) { sei(); return ARM_DWT_CYCCNT - start; }
+			}
+			#endif
+			// Write first byte, read next byte
+			writeBits<8+XTRA0>(next_mark, b);
+			b = pixels.loadAndScale1();
+
+			// Write second byte, read 3rd byte
+			writeBits<8+XTRA0>(next_mark, b);
+			b = pixels.loadAndScale2();
+
+			// Write third byte, read 1st byte of next pixel
+			writeBits<8+XTRA0>(next_mark, b);
+			b = pixels.advanceAndLoadAndScale0();
+			#if (FASTLED_ALLOW_INTERRUPTS == 1)
+			sei();
+			#endif
+		};
+
+		sei();
+		return ARM_DWT_CYCCNT - start;
+	}
+};
+#endif
+
+FASTLED_NAMESPACE_END
+
+#endif
diff --git a/platforms/arm/mxrt1062/fastled_arm_mxrt1062.h b/platforms/arm/mxrt1062/fastled_arm_mxrt1062.h
new file mode 100644
index 00000000..0814c7fa
--- /dev/null
+++ b/platforms/arm/mxrt1062/fastled_arm_mxrt1062.h
@@ -0,0 +1,9 @@
+#ifndef __INC_FASTLED_ARM_MXRT1062_H
+#define __INC_FASTLED_ARM_MXRT1062_H
+
+#include "fastpin_arm_mxrt1062.h"
+#include "fastspi_arm_mxrt1062.h"
+#include "clockless_arm_mxrt1062.h"
+#include "block_clockless_arm_mxrt1062.h"
+
+#endif
diff --git a/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h b/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h
new file mode 100644
index 00000000..38c88410
--- /dev/null
+++ b/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h
@@ -0,0 +1,91 @@
+#ifndef __FASTPIN_ARM_MXRT1062_H
+#define __FASTPIN_ARM_MXRT1062_H
+
+FASTLED_NAMESPACE_BEGIN
+
+#if defined(FASTLED_FORCE_SOFTWARE_PINS)
+#warning "Software pin support forced, pin access will be slightly slower."
+#define NO_HARDWARE_PIN_SUPPORT
+#undef HAS_HARDWARE_PIN_SUPPORT
+
+#else
+
+/// Template definition for teensy 4.0 style ARM pins, providing direct access to the various GPIO registers.  Note that this
+/// uses the full port GPIO registers.  It calls through to pinMode for setting input/output on pins
+/// The registers are data output, set output, clear output, toggle output, input, and direction
+template<uint8_t PIN, uint32_t _BIT, uint32_t _MASK, typename _GPIO_DR, typename _GPIO_DR_SET, typename _GPIO_DR_CLEAR, typename _GPIO_DR_TOGGLE> class _ARMPIN {
+public:
+	typedef volatile uint32_t * port_ptr_t;
+	typedef uint32_t port_t;
+
+	inline static void setOutput() { pinMode(PIN, OUTPUT); } // TODO: perform MUX config { _PDDR::r() |= _MASK; }
+	inline static void setInput() { pinMode(PIN, INPUT); } // TODO: preform MUX config { _PDDR::r() &= ~_MASK; }
+
+	inline static void hi() __attribute__ ((always_inline)) { _GPIO_DR_SET::r() = _MASK; }
+	inline static void lo() __attribute__ ((always_inline)) { _GPIO_DR_CLEAR::r() = _MASK; }
+	inline static void set(register port_t val) __attribute__ ((always_inline)) { _GPIO_DR::r() = val; }
+
+	inline static void strobe() __attribute__ ((always_inline)) { toggle(); toggle(); }
+
+	inline static void toggle() __attribute__ ((always_inline)) { _GPIO_DR_TOGGLE::r() = _MASK; }
+
+	inline static void hi(register port_ptr_t port) __attribute__ ((always_inline)) { hi(); }
+	inline static void lo(register port_ptr_t port) __attribute__ ((always_inline)) { lo(); }
+	inline static void fastset(register port_ptr_t port, register port_t val) __attribute__ ((always_inline)) { *port = val; }
+
+	inline static port_t hival() __attribute__ ((always_inline)) { return _GPIO_DR::r() | _MASK; }
+	inline static port_t loval() __attribute__ ((always_inline)) { return _GPIO_DR::r() & ~_MASK; }
+	inline static port_ptr_t port() __attribute__ ((always_inline)) { return &_GPIO_DR::r(); }
+	inline static port_ptr_t sport() __attribute__ ((always_inline)) { return &_GPIO_DR_SET::r(); }
+	inline static port_ptr_t cport() __attribute__ ((always_inline)) { return &_GPIO_DR_CLEAR::r(); }
+	inline static port_t mask() __attribute__ ((always_inline)) { return _MASK; }
+  inline static uint32_t pinbit() __attribute__ ((always_inline)) { return _BIT; }
+};
+
+
+#define _R(T) struct __gen_struct_ ## T
+#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } };
+#define _FL_IO(L) _RD32(GPIO ## L ## _DR); _RD32(GPIO ## L ## _DR_SET); _RD32(GPIO ## L ## _DR_CLEAR); _RD32(GPIO ## L ## _DR_TOGGLE); _FL_DEFINE_PORT(L, _R(GPIO ## L ## _DR));
+
+// From the teensy core - it looks like there's the "default set" of port registers at GPIO1-5 - but then there
+// are a mirrored set for GPIO1-4 at GPIO6-9, which in the teensy core is referred to as "fast" - while the pin definitiosn
+// at https://forum.pjrc.com/threads/54711-Teensy-4-0-First-Beta-Test?p=193716&viewfull=1#post193716
+// refer to GPIO1-4, we're going to use GPIO6-9 in the definitions below because the fast registers are what
+// the teensy core is using internally
+#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L ## _DR), _R(GPIO ## L ## _DR_SET), _R(GPIO ## L ## _DR_CLEAR), _R(GPIO ## L ## _DR_TOGGLE)> {};
+
+#if defined(FASTLED_TEENSY4) && defined(CORE_TEENSY)
+_FL_IO(1); _FL_IO(2); _FL_IO(3); _FL_IO(4); _FL_IO(5);
+_FL_IO(6); _FL_IO(7); _FL_IO(8); _FL_IO(9);
+
+#define MAX_PIN 39
+_FL_DEFPIN( 0, 3,6); _FL_DEFPIN( 1, 2,6); _FL_DEFPIN( 2, 4,9); _FL_DEFPIN( 3, 5,9);
+_FL_DEFPIN( 4, 6,9); _FL_DEFPIN( 5, 8,9); _FL_DEFPIN( 6,10,7); _FL_DEFPIN( 7,17,7);
+_FL_DEFPIN( 8,16,7); _FL_DEFPIN( 9,11,7); _FL_DEFPIN(10, 0,7); _FL_DEFPIN(11, 2,7);
+_FL_DEFPIN(12, 1,7); _FL_DEFPIN(13, 3,7); _FL_DEFPIN(14,18,6); _FL_DEFPIN(15,19,6);
+_FL_DEFPIN(16,23,6); _FL_DEFPIN(17,22,6); _FL_DEFPIN(18,17,6); _FL_DEFPIN(19,16,6);
+_FL_DEFPIN(20,26,6); _FL_DEFPIN(21,27,6); _FL_DEFPIN(22,24,6); _FL_DEFPIN(23,25,6);
+_FL_DEFPIN(24,12,6); _FL_DEFPIN(25,13,6); _FL_DEFPIN(26,30,6); _FL_DEFPIN(27,31,6);
+_FL_DEFPIN(28,18,8); _FL_DEFPIN(29,31,9); _FL_DEFPIN(30,23,8); _FL_DEFPIN(31,22,8);
+_FL_DEFPIN(32,12,7); _FL_DEFPIN(33, 7,9); _FL_DEFPIN(34,15,8); _FL_DEFPIN(35,14,8);
+_FL_DEFPIN(36,13,8); _FL_DEFPIN(37,12,8); _FL_DEFPIN(38,17,8); _FL_DEFPIN(39,16,8);
+
+#define HAS_HARDWARE_PIN_SUPPORT
+
+#define ARM_HARDWARE_SPI
+#define SPI_DATA 11
+#define SPI_CLOCK 13
+
+#define SPI1_DATA 26
+#define SPI1_CLOCK 27
+
+#define SPI2_DATA 35
+#define SPI2_CLOCK 37
+
+#endif // defined FASTLED_TEENSY4
+
+#endif // FASTLED_FORCE_SOFTWARE_PINSs
+
+FASTLED_NAMESPACE_END
+
+#endif
diff --git a/platforms/arm/mxrt1062/fastspi_arm_mxrt1062.h b/platforms/arm/mxrt1062/fastspi_arm_mxrt1062.h
new file mode 100644
index 00000000..fa6b81ff
--- /dev/null
+++ b/platforms/arm/mxrt1062/fastspi_arm_mxrt1062.h
@@ -0,0 +1,140 @@
+#ifndef __INC_FASTSPI_ARM_MXRT1062_H
+#define __INC_FASTSPI_ARM_MXRT1062_H
+
+FASTLED_NAMESPACE_BEGIN
+
+#if defined (FASTLED_TEENSY4) && defined(ARM_HARDWARE_SPI)
+#include <SPI.h>
+
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_RATE, SPIClass & _SPIObject, int _SPI_INDEX>
+class Teesy4HardwareSPIOutput {
+	Selectable *m_pSelect;
+  uint32_t  m_bitCount;
+  uint32_t m_bitData;
+  inline IMXRT_LPSPI_t & port() __attribute__((always_inline)) {
+    switch(_SPI_INDEX) {
+      case 0:
+        return IMXRT_LPSPI4_S;
+      case 1:
+        return IMXRT_LPSPI3_S;
+      case 2:
+        return IMXRT_LPSPI1_S;
+    }
+  }
+
+public:
+	Teesy4HardwareSPIOutput() { m_pSelect = NULL; m_bitCount = 0;}
+	Teesy4HardwareSPIOutput(Selectable *pSelect) { m_pSelect = pSelect; m_bitCount = 0;}
+
+	// set the object representing the selectable -- ignore for now
+	void setSelect(Selectable *pSelect) { /* TODO */ }
+
+	// initialize the SPI subssytem
+	void init() { _SPIObject.begin(); }
+
+	// latch the CS select
+	void inline select() __attribute__((always_inline)) {
+    // begin the SPI transaction
+    _SPIObject.beginTransaction(SPISettings(_SPI_CLOCK_RATE, MSBFIRST, SPI_MODE0));
+    if(m_pSelect != NULL) { m_pSelect->select(); }
+  }
+
+	// release the CS select
+	void inline release() __attribute__((always_inline)) {
+    if(m_pSelect != NULL) { m_pSelect->release(); }
+    _SPIObject.endTransaction();
+  }
+
+	// wait until all queued up data has been written
+	static void waitFully() { /* TODO */ }
+
+	// write a byte out via SPI (returns immediately on writing register) -
+	void inline writeByte(uint8_t b) __attribute__((always_inline)) {
+    if(m_bitCount == 0) {
+      _SPIObject.transfer(b);
+    } else {
+      // There's been a bit of data written, add that to the output as well
+      uint32_t outData = (m_bitData << 8) | b;
+      uint32_t tcr = port().TCR;
+      port().TCR = (tcr & 0xfffff000) | LPSPI_TCR_FRAMESZ((8+m_bitCount) - 1);  // turn on 9 bit mode
+      port().TDR = outData;		// output 9 bit data.
+      while ((port().RSR & LPSPI_RSR_RXEMPTY)) ;	// wait while the RSR fifo is empty...
+			port().TCR = (tcr & 0xfffff000) | LPSPI_TCR_FRAMESZ((8) - 1);  // turn back on 8 bit mode
+      port().RDR;
+      m_bitCount = 0;
+    }
+  }
+
+	// write a word out via SPI (returns immediately on writing register)
+	void inline writeWord(uint16_t w) __attribute__((always_inline)) {
+    writeByte(((w>>8) & 0xFF));
+    _SPIObject.transfer(w & 0xFF);
+  }
+
+	// A raw set of writing byte values, assumes setup/init/waiting done elsewhere
+	static void writeBytesValueRaw(uint8_t value, int len) {
+		while(len--) { _SPIObject.transfer(value); }
+	}
+
+	// A full cycle of writing a value for len bytes, including select, release, and waiting
+	void writeBytesValue(uint8_t value, int len) {
+		select(); writeBytesValueRaw(value, len); release();
+	}
+
+	// A full cycle of writing a value for len bytes, including select, release, and waiting
+	template <class D> void writeBytes(register uint8_t *data, int len) {
+		uint8_t *end = data + len;
+		select();
+		// could be optimized to write 16bit words out instead of 8bit bytes
+		while(data != end) {
+			writeByte(D::adjust(*data++));
+		}
+		D::postBlock(len);
+		waitFully();
+		release();
+	}
+
+	// A full cycle of writing a value for len bytes, including select, release, and waiting
+	void writeBytes(register uint8_t *data, int len) { writeBytes<DATA_NOP>(data, len); }
+
+	// write a single bit out, which bit from the passed in byte is determined by template parameter
+	template <uint8_t BIT> inline void writeBit(uint8_t b) {
+    m_bitData = (m_bitData<<1) | ((b&(1<<BIT)) != 0);
+    // If this is the 8th bit we've collected, just write it out raw
+    register uint32_t bc = m_bitCount;
+    bc = (bc + 1) & 0x07;
+    if (!bc) {
+      m_bitCount = 0;
+      _SPIObject.transfer(m_bitData);
+    }
+    m_bitCount = bc;
+  }
+
+	// write a block of uint8_ts out in groups of three.  len is the total number of uint8_ts to write out.  The template
+	// parameters indicate how many uint8_ts to skip at the beginning and/or end of each grouping
+	template <uint8_t FLAGS, class D, EOrder RGB_ORDER> void writePixels(PixelController<RGB_ORDER> pixels) {
+		select();
+    int len = pixels.mLen;
+
+		while(pixels.has(1)) {
+			if(FLAGS & FLAG_START_BIT) {
+				writeBit<0>(1);
+			}
+			writeByte(D::adjust(pixels.loadAndScale0()));
+			writeByte(D::adjust(pixels.loadAndScale1()));
+			writeByte(D::adjust(pixels.loadAndScale2()));
+
+			pixels.advanceData();
+			pixels.stepDithering();
+		}
+		D::postBlock(len);
+		release();
+	}
+
+};
+
+
+#endif
+
+FASTLED_NAMESPACE_END
+#endif
diff --git a/platforms/arm/mxrt1062/led_sysdefs_arm_mxrt1062.h b/platforms/arm/mxrt1062/led_sysdefs_arm_mxrt1062.h
new file mode 100644
index 00000000..ac490825
--- /dev/null
+++ b/platforms/arm/mxrt1062/led_sysdefs_arm_mxrt1062.h
@@ -0,0 +1,43 @@
+#ifndef __INC_LED_SYSDEFS_ARM_MXRT1062_H
+#define __INC_LED_SYSDEFS_ARM_MXRT1062_H
+
+#define FASTLED_TEENSY4
+#define FASTLED_ARM
+
+#ifndef INTERRUPT_THRESHOLD
+#define INTERRUPT_THRESHOLD 1
+#endif
+
+// Default to allowing interrupts
+#ifndef FASTLED_ALLOW_INTERRUPTS
+#define FASTLED_ALLOW_INTERRUPTS 1
+#endif
+
+#if FASTLED_ALLOW_INTERRUPTS == 1
+#define FASTLED_ACCURATE_CLOCK
+#endif
+
+#if (F_CPU == 96000000)
+#define CLK_DBL 1
+#endif
+
+// Get some system include files
+#include <avr/io.h>
+#include <avr/interrupt.h> // for cli/se definitions
+
+// Define the register types
+#if defined(ARDUINO) // && ARDUINO < 150
+typedef volatile       uint32_t RoReg; /**< Read only 8-bit register (volatile const unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 8-bit register (volatile unsigned int) */
+#endif
+
+// extern volatile uint32_t systick_millis_count;
+// #  define MS_COUNTER systick_millis_count
+
+// Teensy4 provides progmem
+#ifndef FASTLED_USE_PROGMEM
+#define FASTLED_USE_PROGMEM 1
+#endif
+
+
+#endif
diff --git a/platforms/arm/nrf51/fastpin_arm_nrf51.h b/platforms/arm/nrf51/fastpin_arm_nrf51.h
index 4125f9a3..3d02edc1 100644
--- a/platforms/arm/nrf51/fastpin_arm_nrf51.h
+++ b/platforms/arm/nrf51/fastpin_arm_nrf51.h
@@ -49,7 +49,7 @@ _RD32_NRF(NR_OUTSET);
 _RD32_NRF(NR_OUTCLR);
 _RD32_NRF(NR_OUT);
 
-#define _DEFPIN_ARM(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN, \
+#define _FL_DEFPIN(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN, \
   _R(NR_DIRSET), _R(NR_DIRCLR), _R(NR_OUTSET), _R(NR_OUTCLR), _R(NR_OUT)> {};
 #else
 
@@ -98,19 +98,19 @@ public:
 };
 
 
-#define _DEFPIN_ARM(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN> {};
+#define _FL_DEFPIN(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN> {};
 #endif
 
 // Actual pin definitions
 #define MAX_PIN 31
-_DEFPIN_ARM(0); _DEFPIN_ARM(1); _DEFPIN_ARM(2); _DEFPIN_ARM(3);
-_DEFPIN_ARM(4); _DEFPIN_ARM(5); _DEFPIN_ARM(6); _DEFPIN_ARM(7);
-_DEFPIN_ARM(8); _DEFPIN_ARM(9); _DEFPIN_ARM(10); _DEFPIN_ARM(11);
-_DEFPIN_ARM(12); _DEFPIN_ARM(13); _DEFPIN_ARM(14); _DEFPIN_ARM(15);
-_DEFPIN_ARM(16); _DEFPIN_ARM(17); _DEFPIN_ARM(18); _DEFPIN_ARM(19);
-_DEFPIN_ARM(20); _DEFPIN_ARM(21); _DEFPIN_ARM(22); _DEFPIN_ARM(23);
-_DEFPIN_ARM(24); _DEFPIN_ARM(25); _DEFPIN_ARM(26); _DEFPIN_ARM(27);
-_DEFPIN_ARM(28); _DEFPIN_ARM(29); _DEFPIN_ARM(30); _DEFPIN_ARM(31);
+_FL_DEFPIN(0); _FL_DEFPIN(1); _FL_DEFPIN(2); _FL_DEFPIN(3);
+_FL_DEFPIN(4); _FL_DEFPIN(5); _FL_DEFPIN(6); _FL_DEFPIN(7);
+_FL_DEFPIN(8); _FL_DEFPIN(9); _FL_DEFPIN(10); _FL_DEFPIN(11);
+_FL_DEFPIN(12); _FL_DEFPIN(13); _FL_DEFPIN(14); _FL_DEFPIN(15);
+_FL_DEFPIN(16); _FL_DEFPIN(17); _FL_DEFPIN(18); _FL_DEFPIN(19);
+_FL_DEFPIN(20); _FL_DEFPIN(21); _FL_DEFPIN(22); _FL_DEFPIN(23);
+_FL_DEFPIN(24); _FL_DEFPIN(25); _FL_DEFPIN(26); _FL_DEFPIN(27);
+_FL_DEFPIN(28); _FL_DEFPIN(29); _FL_DEFPIN(30); _FL_DEFPIN(31);
 
 #define HAS_HARDWARE_PIN_SUPPORT
 
diff --git a/platforms/arm/nrf51/fastspi_arm_nrf51.h b/platforms/arm/nrf51/fastspi_arm_nrf51.h
index 539fd656..6299e89d 100644
--- a/platforms/arm/nrf51/fastspi_arm_nrf51.h
+++ b/platforms/arm/nrf51/fastspi_arm_nrf51.h
@@ -9,7 +9,7 @@
 // A nop/stub class, mostly to show the SPI methods that are needed/used by the various SPI chipset implementations.  Should
 // be used as a definition for the set of methods that the spi implementation classes should use (since C++ doesn't support the
 // idea of interfaces - it's possible this could be done with virtual classes, need to decide if i want that overhead)
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class NRF51SPIOutput {
 
   struct saveData {
diff --git a/platforms/arm/nrf52/clockless_arm_nrf52.h b/platforms/arm/nrf52/clockless_arm_nrf52.h
index d8a5da98..56a1dbe0 100644
--- a/platforms/arm/nrf52/clockless_arm_nrf52.h
+++ b/platforms/arm/nrf52/clockless_arm_nrf52.h
@@ -46,7 +46,7 @@ private:
     // may as well be static, as can only attach one LED string per _DATA_PIN....
     static uint16_t s_SequenceBuffer[_PWM_BUFFER_COUNT];
     static uint16_t s_SequenceBufferValidElements;
-    static uint32_t s_SequenceBufferInUse;
+    static volatile uint32_t s_SequenceBufferInUse;
     static CMinWait<_WAIT_TIME_MICROSECONDS> mWait;  // ensure data has time to latch
 
     FASTLED_NRF52_INLINE_ATTRIBUTE static void startPwmPlayback_InitializePinState() {
@@ -123,6 +123,18 @@ private:
     FASTLED_NRF52_INLINE_ATTRIBUTE static void startPwmPlayback_StartTask(NRF_PWM_Type * pwm) {
         nrf_pwm_task_trigger(pwm, NRF_PWM_TASK_SEQSTART0);
     }
+    FASTLED_NRF52_INLINE_ATTRIBUTE static void spinAcquireSequenceBuffer() {
+        while (!tryAcquireSequenceBuffer());
+    }
+    FASTLED_NRF52_INLINE_ATTRIBUTE static bool tryAcquireSequenceBuffer() {
+        return __sync_bool_compare_and_swap(&s_SequenceBufferInUse, 0, 1);
+    }
+    FASTLED_NRF52_INLINE_ATTRIBUTE static void releaseSequenceBuffer() {
+        uint32_t tmp = __sync_val_compare_and_swap(&s_SequenceBufferInUse, 1, 0);
+        if (tmp != 1) {
+            // TODO: Error / Assert / log ?
+        }
+    }
 
 public:
     static void isr_handler() {
@@ -134,8 +146,10 @@ public:
         if (nrf_pwm_event_check(pwm,NRF_PWM_EVENT_STOPPED)) {
             nrf_pwm_event_clear(pwm,NRF_PWM_EVENT_STOPPED);
 
+            // update the minimum time to next call
+            mWait.mark();
             // mark the sequence as no longer in use -- pointer, comparator, exchange value
-            __sync_fetch_and_and(&s_SequenceBufferInUse, 0);
+            releaseSequenceBuffer();
             // prevent further interrupts from PWM events
             nrf_pwm_int_set(pwm, 0);
             // disable PWM interrupts - None of the PWM IRQs are shared
@@ -156,14 +170,20 @@ public:
         FASTLED_NRF52_DEBUGPRINT("    T0H == %d", _T0H);
         FASTLED_NRF52_DEBUGPRINT("    T1H == %d", _T1H);
         FASTLED_NRF52_DEBUGPRINT("    TOP == %d\n", _TOP);
+        // to avoid pin initialization from causing first LED to have invalid color,
+        // call mWait.mark() to ensure data latches before color data gets sent.
+        startPwmPlayback_InitializePinState();
+        mWait.mark();
+
     }
     virtual uint16_t getMaxRefreshRate() const { return 800; }
 
     virtual void showPixels(PixelController<_RGB_ORDER> & pixels) {
         // wait for the only sequence buffer to become available
-        while (s_SequenceBufferInUse != 0);
+        spinAcquireSequenceBuffer();
         prepareSequenceBuffers(pixels);
-        mWait.wait(); // ensure min time between updates
+        // ensure any prior data had time to latch
+        mWait.wait();
         startPwmPlayback(s_SequenceBufferValidElements);
         return;
     }
@@ -302,7 +322,7 @@ public:
 template <uint8_t _DATA_PIN, int _T1, int _T2, int _T3, EOrder _RGB_ORDER, int _XTRA0, bool _FLIP, int _WAIT_TIME_MICROSECONDS>
 uint16_t ClocklessController<_DATA_PIN, _T1, _T2, _T3, _RGB_ORDER, _XTRA0, _FLIP, _WAIT_TIME_MICROSECONDS>::s_SequenceBufferValidElements = 0;
 template <uint8_t _DATA_PIN, int _T1, int _T2, int _T3, EOrder _RGB_ORDER, int _XTRA0, bool _FLIP, int _WAIT_TIME_MICROSECONDS>
-uint32_t ClocklessController<_DATA_PIN, _T1, _T2, _T3, _RGB_ORDER, _XTRA0, _FLIP, _WAIT_TIME_MICROSECONDS>::s_SequenceBufferInUse = 0;
+uint32_t volatile ClocklessController<_DATA_PIN, _T1, _T2, _T3, _RGB_ORDER, _XTRA0, _FLIP, _WAIT_TIME_MICROSECONDS>::s_SequenceBufferInUse = 0;
 template <uint8_t _DATA_PIN, int _T1, int _T2, int _T3, EOrder _RGB_ORDER, int _XTRA0, bool _FLIP, int _WAIT_TIME_MICROSECONDS>
 uint16_t ClocklessController<_DATA_PIN, _T1, _T2, _T3, _RGB_ORDER, _XTRA0, _FLIP, _WAIT_TIME_MICROSECONDS>::s_SequenceBuffer[_PWM_BUFFER_COUNT];
 template <uint8_t _DATA_PIN, int _T1, int _T2, int _T3, EOrder _RGB_ORDER, int _XTRA0, bool _FLIP, int _WAIT_TIME_MICROSECONDS>
diff --git a/platforms/arm/nrf52/fastpin_arm_nrf52.h b/platforms/arm/nrf52/fastpin_arm_nrf52.h
index a8684665..b761cfa8 100644
--- a/platforms/arm/nrf52/fastpin_arm_nrf52.h
+++ b/platforms/arm/nrf52/fastpin_arm_nrf52.h
@@ -1,13 +1,13 @@
 #ifndef __FASTPIN_ARM_NRF52_H
 #define __FASTPIN_ARM_NRF52_H
 
-    
+
 /*
 //
 // Background:
 // ===========
 // the nRF52 has more than 32 ports, and thus must support
-// two distinct GPIO port registers.  
+// two distinct GPIO port registers.
 //
 // For the nRF52 series, the structure to control the port is
 // `NRF_GPIO_Type`, with separate addresses mapped for set, clear, etc.
@@ -18,18 +18,18 @@
 //     #define NRF_P0        ((NRF_GPIO_Type*)NRF_P0_BASE)
 //     #define NRF_P1        ((NRF_GPIO_Type*)NRF_P1_BASE)
 //
-// Therefore, ideally, the _DEFPIN_ARM() macro would simply
+// Therefore, ideally, the _FL_DEFPIN() macro would simply
 // conditionally pass either NRF_P0 or NRF_P1 to the underlying
 // FastPin<> template class class.
 //
 // The "pin" provided to the FastLED<> template (and which
-// the _DEFPIN_ARM() macro specializes for valid pins) is NOT
+// the _FL_DEFPIN() macro specializes for valid pins) is NOT
 // the microcontroller port.pin, but the Arduino digital pin.
 // Some boards have an identity mapping (e.g., nRF52832 Feather)
-// but most do not.  Therefore, the _DEFPIN_ARM() macro
+// but most do not.  Therefore, the _FL_DEFPIN() macro
 // must translate the Arduino pin to the mcu port.pin.
 //
-// 
+//
 // Difficulties:
 // =============
 // The goal is to avoid any such lookups, using compile-time
@@ -73,13 +73,13 @@
 
 // manually define two structures, to avoid fighting with preprocessor macros
 struct __generated_struct_NRF_P0 {
-    FASTLED_NRF52_INLINE_ATTRIBUTE constexpr static NRF_GPIO_Type * r() {
-        return NRF_P0;
+    FASTLED_NRF52_INLINE_ATTRIBUTE constexpr static uintptr_t r() {
+        return NRF_P0_BASE;
     }
 };
 struct __generated_struct_NRF_P1 {
-    FASTLED_NRF52_INLINE_ATTRIBUTE constexpr static NRF_GPIO_Type * r() {
-        return NRF_P1;
+    FASTLED_NRF52_INLINE_ATTRIBUTE constexpr static uintptr_t r() {
+        return NRF_P1_BASE;
     }
 };
 
@@ -112,19 +112,19 @@ public:
         NRF_GPIO_PIN_NOSENSE            // pin sense level disabled
         );
   }
-  FASTLED_NRF52_INLINE_ATTRIBUTE static void       hi()        { _PORT::r()->OUTSET = _MASK;            } // sets _MASK in the SET   OUTPUT register (output set high)
-  FASTLED_NRF52_INLINE_ATTRIBUTE static void       lo()        { _PORT::r()->OUTCLR = _MASK;            } // sets _MASK in the CLEAR OUTPUT register (output set low)
-  FASTLED_NRF52_INLINE_ATTRIBUTE static void       toggle()    { _PORT::r()->OUT ^= _MASK;              } // toggles _MASK bits in the OUTPUT GPIO port directly
+  FASTLED_NRF52_INLINE_ATTRIBUTE static void       hi()        { (reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUTSET = _MASK;            } // sets _MASK in the SET   OUTPUT register (output set high)
+  FASTLED_NRF52_INLINE_ATTRIBUTE static void       lo()        { (reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUTCLR = _MASK;            } // sets _MASK in the CLEAR OUTPUT register (output set low)
+  FASTLED_NRF52_INLINE_ATTRIBUTE static void       toggle()    { (reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUT ^= _MASK;              } // toggles _MASK bits in the OUTPUT GPIO port directly
   FASTLED_NRF52_INLINE_ATTRIBUTE static void       strobe()    { toggle();     toggle();                } // BUGBUG -- Is this used by FastLED?  Without knowing (for example) SPI Speed?
-  FASTLED_NRF52_INLINE_ATTRIBUTE static port_t     hival()     { return _PORT::r()->OUT | _MASK;        } // sets all _MASK bit(s) in the OUTPUT GPIO port to 1
-  FASTLED_NRF52_INLINE_ATTRIBUTE static port_t     loval()     { return _PORT::r()->OUT & ~_MASK;       } // sets all _MASK bit(s) in the OUTPUT GPIO port to 0
-  FASTLED_NRF52_INLINE_ATTRIBUTE static port_ptr_t port()      { return &(_PORT::r()->OUT);             } // gets raw pointer to OUTPUT          GPIO port
-  FASTLED_NRF52_INLINE_ATTRIBUTE static port_ptr_t cport()     { return &(_PORT::r()->OUTCLR);          } // gets raw pointer to SET   DIRECTION GPIO port
-  FASTLED_NRF52_INLINE_ATTRIBUTE static port_ptr_t sport()     { return &(_PORT::r()->OUTSET);          } // gets raw pointer to CLEAR DIRECTION GPIO port
+  FASTLED_NRF52_INLINE_ATTRIBUTE static port_t     hival()     { return (reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUT | _MASK;        } // sets all _MASK bit(s) in the OUTPUT GPIO port to 1
+  FASTLED_NRF52_INLINE_ATTRIBUTE static port_t     loval()     { return (reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUT & ~_MASK;       } // sets all _MASK bit(s) in the OUTPUT GPIO port to 0
+  FASTLED_NRF52_INLINE_ATTRIBUTE static port_ptr_t port()      { return &((reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUT);             } // gets raw pointer to OUTPUT          GPIO port
+  FASTLED_NRF52_INLINE_ATTRIBUTE static port_ptr_t cport()     { return &((reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUTCLR);          } // gets raw pointer to SET   DIRECTION GPIO port
+  FASTLED_NRF52_INLINE_ATTRIBUTE static port_ptr_t sport()     { return &((reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUTSET);          } // gets raw pointer to CLEAR DIRECTION GPIO port
   FASTLED_NRF52_INLINE_ATTRIBUTE static port_t     mask()      { return _MASK;                          } // gets the value of _MASK
   FASTLED_NRF52_INLINE_ATTRIBUTE static void hi (register port_ptr_t port) { hi();                      } // sets _MASK in the SET   OUTPUT register (output set high)
   FASTLED_NRF52_INLINE_ATTRIBUTE static void lo (register port_ptr_t port) { lo();                      } // sets _MASK in the CLEAR OUTPUT register (output set low)
-  FASTLED_NRF52_INLINE_ATTRIBUTE static void set(register port_t     val ) { _PORT::r()->OUT = val;     } // sets entire port's value (optimization used by FastLED)
+  FASTLED_NRF52_INLINE_ATTRIBUTE static void set(register port_t     val ) { (reinterpret_cast<NRF_GPIO_Type*>(_PORT::r()))->OUT = val;     } // sets entire port's value (optimization used by FastLED)
   FASTLED_NRF52_INLINE_ATTRIBUTE static void fastset(register port_ptr_t port, register port_t val) { *port = val; }
   constexpr                      static uint32_t   nrf_pin2() { return NRF_GPIO_PIN_MAP(_PORT_NUMBER, _PIN_NUMBER); }
   constexpr                      static bool       LowSpeedOnlyRecommended() {
@@ -269,7 +269,7 @@ public:
             );
     #endif
     #if !defined(_FASTLED_NRF52_LOW_SPEED_ONLY_BOARD_DETECT)
-        #warning "Unknown board / package, ... caller must pins support high-speed"
+        #warning "Unknown board / package, ... caller must determine pins that support high-speed"
         return false; // choosing default to be FALSE, to allow users to ATTEMPT to use high-speed on pins where support is not known
     #endif
   }
@@ -281,16 +281,16 @@ public:
 //
 // BOARD_PIN can be either the pin portion of a port.pin, or the combined NRF_GPIO_PIN_MAP() number.
 // For example both the following two defines refer to P1.15 (pin 47) as Arduino pin 3:
-//     _DEFPIN_ARM(3, 1, 15);
-//     _DEFPIN_ARM(3, 1, 47);
+//     _FL_DEFPIN(3, 15, 1);
+//     _FL_DEFPIN(3, 47, 1);
 //
 // Similarly, the following defines are all equivalent:
 //     _DEFPIN_ARM_IDENTITY_P1(47);
-//     _DEFPIN_ARM(47, 1, 15);
-//     _DEFPIN_ARM(47, 1, 47);
+//     _FL_DEFPIN(47, 15, 1);
+//     _FL_DEFPIN(47, 47, 1);
 //
 
-#define _DEFPIN_ARM(ARDUINO_PIN, BOARD_PORT, BOARD_PIN)  \
+#define _FL_DEFPIN(ARDUINO_PIN, BOARD_PIN, BOARD_PORT)    \
     template<> class FastPin<ARDUINO_PIN> :              \
     public _ARMPIN<                                      \
         1u << (BOARD_PIN & 31u),                         \
diff --git a/platforms/arm/nrf52/fastpin_arm_nrf52_variants.h b/platforms/arm/nrf52/fastpin_arm_nrf52_variants.h
index b3b9ff99..9bb07721 100644
--- a/platforms/arm/nrf52/fastpin_arm_nrf52_variants.h
+++ b/platforms/arm/nrf52/fastpin_arm_nrf52_variants.h
@@ -59,48 +59,48 @@
     #define MAX_PIN (33u) // 34 if wanting to use NFC1 test point
 
     // Arduino pins 0..7
-    _DEFPIN_ARM( 0, 0, 25); // D0  is P0.25 -- UART TX
-    //_DEFPIN_ARM( 1, 0, 24); // D1  is P0.24 -- UART RX
-    _DEFPIN_ARM( 2, 0, 10); // D2  is P0.10 -- NFC2
-    _DEFPIN_ARM( 3, 1, 47); // D3  is P1.15 -- PIN_LED1 (red)
-    _DEFPIN_ARM( 4, 1, 42); // D4  is P1.10 -- PIN_LED2 (blue)
-    _DEFPIN_ARM( 5, 1, 40); // D5  is P1.08 -- SPI/SS
-    _DEFPIN_ARM( 6, 0,  7); // D6  is P0.07
-    _DEFPIN_ARM( 7, 1, 34); // D7  is P1.02 -- PIN_DFU (Button)
+    _FL_DEFPIN( 0, 25, 0); // D0  is P0.25 -- UART TX
+    //_FL_DEFPIN( 1, 24, 0); // D1  is P0.24 -- UART RX
+    _FL_DEFPIN( 2, 10, 0); // D2  is P0.10 -- NFC2
+    _FL_DEFPIN( 3, 47, 1); // D3  is P1.15 -- PIN_LED1 (red)
+    _FL_DEFPIN( 4, 42, 1); // D4  is P1.10 -- PIN_LED2 (blue)
+    _FL_DEFPIN( 5, 40, 1); // D5  is P1.08 -- SPI/SS
+    _FL_DEFPIN( 6,  7, 0); // D6  is P0.07
+    _FL_DEFPIN( 7, 34, 1); // D7  is P1.02 -- PIN_DFU (Button)
     
     // Arduino pins 8..15
-    _DEFPIN_ARM( 8, 0, 16); // D8  is P0.16 -- PIN_NEOPIXEL
-    _DEFPIN_ARM( 9, 0, 26); // D9  is P0.26
-    _DEFPIN_ARM(10, 0, 27); // D10 is P0.27
-    _DEFPIN_ARM(11, 0,  6); // D11 is P0.06
-    _DEFPIN_ARM(12, 0,  8); // D12 is P0.08
-    _DEFPIN_ARM(13, 1, 41); // D13 is P1.09
-    _DEFPIN_ARM(14, 0,  4); // D14 is P0.04 -- A0
-    _DEFPIN_ARM(15, 0,  5); // D15 is P0.05 -- A1
+    _FL_DEFPIN( 8, 16, 0); // D8  is P0.16 -- PIN_NEOPIXEL
+    _FL_DEFPIN( 9, 26, 0); // D9  is P0.26
+    _FL_DEFPIN(10, 27, 0); // D10 is P0.27
+    _FL_DEFPIN(11,  6, 0); // D11 is P0.06
+    _FL_DEFPIN(12,  8, 0); // D12 is P0.08
+    _FL_DEFPIN(13, 41, 1); // D13 is P1.09
+    _FL_DEFPIN(14,  4, 0); // D14 is P0.04 -- A0
+    _FL_DEFPIN(15,  5, 0); // D15 is P0.05 -- A1
 
     // Arduino pins 16..23
-    _DEFPIN_ARM(16, 0, 30); // D16 is P0.30 -- A2
-    _DEFPIN_ARM(17, 0, 28); // D17 is P0.28 -- A3
-    _DEFPIN_ARM(18, 0,  2); // D18 is P0.02 -- A4
-    _DEFPIN_ARM(19, 0,  3); // D19 is P0.03 -- A5
-    //_DEFPIN_ARM(20, 0, 29); // D20 is P0.29 -- A6 -- Connected to battery!
-    //_DEFPIN_ARM(21, 0, 31); // D21 is P0.31 -- A7 -- AREF
-    _DEFPIN_ARM(22, 0, 12); // D22 is P0.12 -- SDA
-    _DEFPIN_ARM(23, 0, 11); // D23 is P0.11 -- SCL
+    _FL_DEFPIN(16, 30, 0); // D16 is P0.30 -- A2
+    _FL_DEFPIN(17, 28, 0); // D17 is P0.28 -- A3
+    _FL_DEFPIN(18,  2, 0); // D18 is P0.02 -- A4
+    _FL_DEFPIN(19,  3, 0); // D19 is P0.03 -- A5
+    //_FL_DEFPIN(20, 29, 0); // D20 is P0.29 -- A6 -- Connected to battery!
+    //_FL_DEFPIN(21, 31, 0); // D21 is P0.31 -- A7 -- AREF
+    _FL_DEFPIN(22, 12, 0); // D22 is P0.12 -- SDA
+    _FL_DEFPIN(23, 11, 0); // D23 is P0.11 -- SCL
 
     // Arduino pins 24..31
-    _DEFPIN_ARM(24, 0, 15); // D24 is P0.15 -- PIN_SPI_MISO
-    _DEFPIN_ARM(25, 0, 13); // D25 is P0.13 -- PIN_SPI_MOSI
-    _DEFPIN_ARM(26, 0, 14); // D26 is P0.14 -- PIN_SPI_SCK
-    //_DEFPIN_ARM(27, 0, 19); // D27 is P0.19 -- PIN_QSPI_SCK
-    //_DEFPIN_ARM(28, 0, 20); // D28 is P0.20 -- PIN_QSPI_CS
-    //_DEFPIN_ARM(29, 0, 17); // D29 is P0.17 -- PIN_QSPI_DATA0
-    //_DEFPIN_ARM(30, 0, 22); // D30 is P0.22 -- PIN_QSPI_DATA1
-    //_DEFPIN_ARM(31, 0, 23); // D31 is P0.23 -- PIN_QSPI_DATA2
+    _FL_DEFPIN(24, 15, 0); // D24 is P0.15 -- PIN_SPI_MISO
+    _FL_DEFPIN(25, 13, 0); // D25 is P0.13 -- PIN_SPI_MOSI
+    _FL_DEFPIN(26, 14, 0); // D26 is P0.14 -- PIN_SPI_SCK
+    //_FL_DEFPIN(27, 19, 0); // D27 is P0.19 -- PIN_QSPI_SCK
+    //_FL_DEFPIN(28, 20, 0); // D28 is P0.20 -- PIN_QSPI_CS
+    //_FL_DEFPIN(29, 17, 0); // D29 is P0.17 -- PIN_QSPI_DATA0
+    //_FL_DEFPIN(30, 22, 0); // D30 is P0.22 -- PIN_QSPI_DATA1
+    //_FL_DEFPIN(31, 23, 0); // D31 is P0.23 -- PIN_QSPI_DATA2
 
     // Arduino pins 32..34
-    //_DEFPIN_ARM(32, 0, 21); // D32 is P0.21 -- PIN_QSPI_DATA3
-    //_DEFPIN_ARM(33, 0,  9); // D33 is NFC1, only accessible via test point
+    //_FL_DEFPIN(32, 21, 0); // D32 is P0.21 -- PIN_QSPI_DATA3
+    //_FL_DEFPIN(33,  9, 0); // D33 is NFC1, only accessible via test point
 #endif // defined (ARDUINO_NRF52840_FEATHER)
 
 // Adafruit Bluefruit nRF52840 Metro Express
@@ -113,46 +113,46 @@
     #endif
     #warning "Adafruit Bluefruit nRF52840 Metro Express is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues"
 
-    _DEFPIN_ARM( 0, 0, 25); // D0  is P0.25 (UART TX)
-    _DEFPIN_ARM( 1, 0, 24); // D1  is P0.24 (UART RX)
-    _DEFPIN_ARM( 2, 1, 10); // D2  is P1.10 
-    _DEFPIN_ARM( 3, 1,  4); // D3  is P1.04 
-    _DEFPIN_ARM( 4, 1, 11); // D4  is P1.11 
-    _DEFPIN_ARM( 5, 1, 12); // D5  is P1.12 
-    _DEFPIN_ARM( 6, 1, 14); // D6  is P1.14
-    _DEFPIN_ARM( 7, 0, 26); // D7  is P0.26
-    _DEFPIN_ARM( 8, 0, 27); // D8  is P0.27
-    _DEFPIN_ARM( 9, 0, 12); // D9  is P0.12
-    _DEFPIN_ARM(10, 0,  6); // D10 is P0.06 
-    _DEFPIN_ARM(11, 0,  8); // D11 is P0.08 
-    _DEFPIN_ARM(12, 1,  9); // D12 is P1.09 
-    _DEFPIN_ARM(13, 0, 14); // D13 is P0.14 
-    _DEFPIN_ARM(14, 0,  4); // D14 is P0.04 (A0)
-    _DEFPIN_ARM(15, 0,  5); // D15 is P0.05 (A1)
-    _DEFPIN_ARM(16, 0, 28); // D16 is P0.28 (A2)
-    _DEFPIN_ARM(17, 0, 30); // D17 is P0.30 (A3)
-    _DEFPIN_ARM(18, 0,  2); // D18 is P0.02 (A4)
-    _DEFPIN_ARM(19, 0,  3); // D19 is P0.03 (A5)
-    _DEFPIN_ARM(20, 0, 29); // D20 is P0.29 (A6, battery)
-    _DEFPIN_ARM(21, 0, 31); // D21 is P0.31 (A7, ARef)
-    _DEFPIN_ARM(22, 0, 15); // D22 is P0.15 (SDA)
-    _DEFPIN_ARM(23, 0, 16); // D23 is P0.16 (SCL)
-    _DEFPIN_ARM(24, 0, 11); // D24 is P0.11 (SPI MISO)
-    _DEFPIN_ARM(25, 1,  8); // D25 is P1.08 (SPI MOSI)
-    _DEFPIN_ARM(26, 0,  7); // D26 is P0.07 (SPI SCK )
-    //_DEFPIN_ARM(27, 0, 19); // D27 is P0.19 (QSPI CLK   )
-    //_DEFPIN_ARM(28, 0, 20); // D28 is P0.20 (QSPI CS    )
-    //_DEFPIN_ARM(29, 0, 17); // D29 is P0.17 (QSPI Data 0)
-    //_DEFPIN_ARM(30, 0, 23); // D30 is P0.23 (QSPI Data 1)
-    //_DEFPIN_ARM(31, 0, 22); // D31 is P0.22 (QSPI Data 2)
-    //_DEFPIN_ARM(32, 0, 21); // D32 is P0.21 (QSPI Data 3)
-    _DEFPIN_ARM(33, 1, 13); // D33 is P1.13 LED1
-    _DEFPIN_ARM(34, 1, 15); // D34 is P1.15 LED2
-    _DEFPIN_ARM(35, 0, 13); // D35 is P0.13 NeoPixel
-    _DEFPIN_ARM(36, 1,  0); // D36 is P1.02 Switch
-    _DEFPIN_ARM(37, 1,  0); // D37 is P1.00 SWO/DFU
-    _DEFPIN_ARM(38, 0,  9); // D38 is P0.09 NFC1
-    _DEFPIN_ARM(39, 0, 10); // D39 is P0.10 NFC2
+    _FL_DEFPIN( 0, 25, 0); // D0  is P0.25 (UART TX)
+    _FL_DEFPIN( 1, 24, 0); // D1  is P0.24 (UART RX)
+    _FL_DEFPIN( 2, 10, 1); // D2  is P1.10 
+    _FL_DEFPIN( 3,  4, 1); // D3  is P1.04 
+    _FL_DEFPIN( 4, 11, 1); // D4  is P1.11 
+    _FL_DEFPIN( 5, 12, 1); // D5  is P1.12 
+    _FL_DEFPIN( 6, 14, 1); // D6  is P1.14
+    _FL_DEFPIN( 7, 26, 0); // D7  is P0.26
+    _FL_DEFPIN( 8, 27, 0); // D8  is P0.27
+    _FL_DEFPIN( 9, 12, 0); // D9  is P0.12
+    _FL_DEFPIN(10,  6, 0); // D10 is P0.06 
+    _FL_DEFPIN(11,  8, 0); // D11 is P0.08 
+    _FL_DEFPIN(12,  9, 1); // D12 is P1.09 
+    _FL_DEFPIN(13, 14, 0); // D13 is P0.14 
+    _FL_DEFPIN(14,  4, 0); // D14 is P0.04 (A0)
+    _FL_DEFPIN(15,  5, 0); // D15 is P0.05 (A1)
+    _FL_DEFPIN(16, 28, 0); // D16 is P0.28 (A2)
+    _FL_DEFPIN(17, 30, 0); // D17 is P0.30 (A3)
+    _FL_DEFPIN(18,  2, 0); // D18 is P0.02 (A4)
+    _FL_DEFPIN(19,  3, 0); // D19 is P0.03 (A5)
+    _FL_DEFPIN(20, 29, 0); // D20 is P0.29 (A6, battery)
+    _FL_DEFPIN(21, 31, 0); // D21 is P0.31 (A7, ARef)
+    _FL_DEFPIN(22, 15, 0); // D22 is P0.15 (SDA)
+    _FL_DEFPIN(23, 16, 0); // D23 is P0.16 (SCL)
+    _FL_DEFPIN(24, 11, 0); // D24 is P0.11 (SPI MISO)
+    _FL_DEFPIN(25,  8, 1); // D25 is P1.08 (SPI MOSI)
+    _FL_DEFPIN(26,  7, 0); // D26 is P0.07 (SPI SCK )
+    //_FL_DEFPIN(27, 19, 0); // D27 is P0.19 (QSPI CLK   )
+    //_FL_DEFPIN(28, 20, 0); // D28 is P0.20 (QSPI CS    )
+    //_FL_DEFPIN(29, 17, 0); // D29 is P0.17 (QSPI Data 0)
+    //_FL_DEFPIN(30, 23, 0); // D30 is P0.23 (QSPI Data 1)
+    //_FL_DEFPIN(31, 22, 0); // D31 is P0.22 (QSPI Data 2)
+    //_FL_DEFPIN(32, 21, 0); // D32 is P0.21 (QSPI Data 3)
+    _FL_DEFPIN(33, 13, 1); // D33 is P1.13 LED1
+    _FL_DEFPIN(34, 15, 1); // D34 is P1.15 LED2
+    _FL_DEFPIN(35, 13, 0); // D35 is P0.13 NeoPixel
+    _FL_DEFPIN(36,  0, 1); // D36 is P1.02 Switch
+    _FL_DEFPIN(37,  0, 1); // D37 is P1.00 SWO/DFU
+    _FL_DEFPIN(38,  9, 0); // D38 is P0.09 NFC1
+    _FL_DEFPIN(39, 10, 0); // D39 is P0.10 NFC2
 #endif // defined (ARDUINO_NRF52840_METRO)
 
 // Adafruit Bluefruit on nRF52840DK PCA10056
@@ -169,52 +169,52 @@
         /* pca10056_schematic_and_pcb.pdf
            Page 3 shows the Arduino Pin to GPIO Px.xx mapping
         */
-        _DEFPIN_ARM( 0, 1,  1); // D0  is P1.01 
-        _DEFPIN_ARM( 1, 1,  2); // D1  is P1.02 
-        _DEFPIN_ARM( 2, 1,  3); // D2  is P1.03
-        _DEFPIN_ARM( 3, 1,  4); // D3  is P1.04 
-        _DEFPIN_ARM( 4, 1,  5); // D4  is P1.05 
-        _DEFPIN_ARM( 5, 1,  6); // D5  is P1.06 
-        _DEFPIN_ARM( 6, 1,  7); // D6  is P1.07 (BUTTON1 option)
-        _DEFPIN_ARM( 7, 1,  8); // D7  is P1.08 (BUTTON2 option)
-        _DEFPIN_ARM( 8, 1, 10); // D8  is P1.10 
-        _DEFPIN_ARM( 9, 1, 11); // D9  is P1.11 
-        _DEFPIN_ARM(10, 1, 12); // D10 is P1.12 
-        _DEFPIN_ARM(11, 1, 13); // D11 is P1.13 
-        _DEFPIN_ARM(12, 1, 14); // D12 is P1.14
-        _DEFPIN_ARM(13, 1, 15); // D13 is P1.15 
-        _DEFPIN_ARM(14, 0,  0); // D14 is P0.00 (if SB4 bridged)
-        _DEFPIN_ARM(15, 0,  1); // D15 is P0.01 (if SB3 bridged)
-        _DEFPIN_ARM(16, 0,  5); // D16 is P0.05 (aka AIN3, aka UART RTS)
-        _DEFPIN_ARM(17, 0,  6); // D17 is P0.06 (UART TxD)
-        _DEFPIN_ARM(18, 0,  7); // D18 is P0.07 (UART CTS default)
-        _DEFPIN_ARM(19, 0,  8); // D19 is P0.08 (UART RxD)
-        _DEFPIN_ARM(20, 0,  9); // D20 is P0.09 (NFC1)
-        _DEFPIN_ARM(21, 0, 10); // D21 is P0.10 (NFC2)
-        _DEFPIN_ARM(22, 0, 11); // D22 is P0.11 (TRACEDATA2 / BUTTON1 default)
-        _DEFPIN_ARM(23, 0, 12); // D23 is P0.12 (TRACEDATA1 / BUTTON2 default)
-        _DEFPIN_ARM(24, 0, 13); // D24 is P0.13 (LED1)
-        _DEFPIN_ARM(25, 0, 14); // D25 is P0.14 (LED2)
-        _DEFPIN_ARM(26, 0, 15); // D26 is P0.15 (LED3)
-        _DEFPIN_ARM(27, 0, 16); // D27 is P0.16 (LED4)
-        _DEFPIN_ARM(28, 0, 17); // D28 is P0.17 (QSPI !CS , unless SB13 cut)
-        // _DEFPIN_ARM(29, 0, 18); // D29 is P0.18 (RESET)
-        _DEFPIN_ARM(30, 0, 19); // D30 is P0.19 (QSPI CLK , unless SB11 cut)
-        _DEFPIN_ARM(31, 0, 20); // D31 is P0.20 (QSPI DIO0, unless SB12 cut)
-        _DEFPIN_ARM(32, 0, 21); // D32 is P0.21 (QSPI DIO1, unless SB14 cut)
-        _DEFPIN_ARM(33, 0, 22); // D33 is P0.22 (QSPI DIO2, unless SB15 cut)
-        _DEFPIN_ARM(34, 0, 23); // D34 is P0.23 (QSPI DIO3, unless SB10 cut)
-        _DEFPIN_ARM(35, 0, 24); // D35 is P0.24 (BUTTON3)
-        _DEFPIN_ARM(36, 0, 25); // D36 is P0.25 (BUTTON4)
-        _DEFPIN_ARM(37, 1, 00); // D37 is P1.00 (TRACEDATA0 / SWO)
-        _DEFPIN_ARM(38, 1, 09); // D38 is P1.09 (TRACEDATA3)
-        //_DEFPIN_ARM(??, 0,  2); // D?? is P0.02 (AREF, aka AIN0)
-        //_DEFPIN_ARM(??, 0,  3); // D?? is P0.03 (A0,   aka AIN1)
-        //_DEFPIN_ARM(??, 0,  4); // D?? is P0.04 (A1,   aka AIN2, aka UART CTS option)
-        //_DEFPIN_ARM(??, 0, 28); // D?? is P0.28 (A2,   aka AIN4)
-        //_DEFPIN_ARM(??, 0, 29); // D?? is P0.29 (A3,   aka AIN5)
-        //_DEFPIN_ARM(??, 0, 30); // D?? is P0.30 (A4,   aka AIN6)
-        //_DEFPIN_ARM(??, 0, 31); // D?? is P0.31 (A5,   aka AIN7)
+        _FL_DEFPIN( 0,  1, 1); // D0  is P1.01 
+        _FL_DEFPIN( 1,  2, 1); // D1  is P1.02 
+        _FL_DEFPIN( 2,  3, 1); // D2  is P1.03
+        _FL_DEFPIN( 3,  4, 1); // D3  is P1.04 
+        _FL_DEFPIN( 4,  5, 1); // D4  is P1.05 
+        _FL_DEFPIN( 5,  6, 1); // D5  is P1.06 
+        _FL_DEFPIN( 6,  7, 1); // D6  is P1.07 (BUTTON1 option)
+        _FL_DEFPIN( 7,  8, 1); // D7  is P1.08 (BUTTON2 option)
+        _FL_DEFPIN( 8, 10, 1); // D8  is P1.10 
+        _FL_DEFPIN( 9, 11, 1); // D9  is P1.11 
+        _FL_DEFPIN(10, 12, 1); // D10 is P1.12 
+        _FL_DEFPIN(11, 13, 1); // D11 is P1.13 
+        _FL_DEFPIN(12, 14, 1); // D12 is P1.14
+        _FL_DEFPIN(13, 15, 1); // D13 is P1.15 
+        _FL_DEFPIN(14,  0, 0); // D14 is P0.00 (if SB4 bridged)
+        _FL_DEFPIN(15,  1, 0); // D15 is P0.01 (if SB3 bridged)
+        _FL_DEFPIN(16,  5, 0); // D16 is P0.05 (aka AIN3, aka UART RTS)
+        _FL_DEFPIN(17,  6, 0); // D17 is P0.06 (UART TxD)
+        _FL_DEFPIN(18,  7, 0); // D18 is P0.07 (UART CTS default)
+        _FL_DEFPIN(19,  8, 0); // D19 is P0.08 (UART RxD)
+        _FL_DEFPIN(20,  9, 0); // D20 is P0.09 (NFC1)
+        _FL_DEFPIN(21, 10, 0); // D21 is P0.10 (NFC2)
+        _FL_DEFPIN(22, 11, 0); // D22 is P0.11 (TRACEDATA2 / BUTTON1 default)
+        _FL_DEFPIN(23, 12, 0); // D23 is P0.12 (TRACEDATA1 / BUTTON2 default)
+        _FL_DEFPIN(24, 13, 0); // D24 is P0.13 (LED1)
+        _FL_DEFPIN(25, 14, 0); // D25 is P0.14 (LED2)
+        _FL_DEFPIN(26, 15, 0); // D26 is P0.15 (LED3)
+        _FL_DEFPIN(27, 16, 0); // D27 is P0.16 (LED4)
+        _FL_DEFPIN(28, 17, 0); // D28 is P0.17 (QSPI !CS , unless SB13 cut)
+        // _FL_DEFPIN(29, 18, 0); // D29 is P0.18 (RESET)
+        _FL_DEFPIN(30, 19, 0); // D30 is P0.19 (QSPI CLK , unless SB11 cut)
+        _FL_DEFPIN(31, 20, 0); // D31 is P0.20 (QSPI DIO0, unless SB12 cut)
+        _FL_DEFPIN(32, 21, 0); // D32 is P0.21 (QSPI DIO1, unless SB14 cut)
+        _FL_DEFPIN(33, 22, 0); // D33 is P0.22 (QSPI DIO2, unless SB15 cut)
+        _FL_DEFPIN(34, 23, 0); // D34 is P0.23 (QSPI DIO3, unless SB10 cut)
+        _FL_DEFPIN(35, 24, 0); // D35 is P0.24 (BUTTON3)
+        _FL_DEFPIN(36, 25, 0); // D36 is P0.25 (BUTTON4)
+        _FL_DEFPIN(37, 00, 1); // D37 is P1.00 (TRACEDATA0 / SWO)
+        _FL_DEFPIN(38, 09, 1); // D38 is P1.09 (TRACEDATA3)
+        //_FL_DEFPIN(??,  2, 0); // D?? is P0.02 (AREF, aka AIN0)
+        //_FL_DEFPIN(??,  3, 0); // D?? is P0.03 (A0,   aka AIN1)
+        //_FL_DEFPIN(??,  4, 0); // D?? is P0.04 (A1,   aka AIN2, aka UART CTS option)
+        //_FL_DEFPIN(??, 28, 0); // D?? is P0.28 (A2,   aka AIN4)
+        //_FL_DEFPIN(??, 29, 0); // D?? is P0.29 (A3,   aka AIN5)
+        //_FL_DEFPIN(??, 30, 0); // D?? is P0.30 (A4,   aka AIN6)
+        //_FL_DEFPIN(??, 31, 0); // D?? is P0.31 (A5,   aka AIN7)
 
     #else
         /* 48 pins, defined using natural mapping in Adafruit's variant.cpp (!) */
@@ -279,33 +279,33 @@
     #endif
     #warning "Electronut labs bluey is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues"
 
-    _DEFPIN_ARM( 0, 0, 26); // D0  is P0.26
-    _DEFPIN_ARM( 1, 0, 27); // D1  is P0.27
-    _DEFPIN_ARM( 2, 0, 22); // D2  is P0.22 (SPI SS  )
-    _DEFPIN_ARM( 3, 0, 23); // D3  is P0.23 (SPI MOSI)
-    _DEFPIN_ARM( 4, 0, 24); // D4  is P0.24 (SPI MISO, also A3)
-    _DEFPIN_ARM( 5, 0, 25); // D5  is P0.25 (SPI SCK )
-    _DEFPIN_ARM( 6, 0, 16); // D6  is P0.16 (Button)
-    _DEFPIN_ARM( 7, 0, 19); // D7  is P0.19 (R)
-    _DEFPIN_ARM( 8, 0, 18); // D8  is P0.18 (G)
-    _DEFPIN_ARM( 9, 0, 17); // D9  is P0.17 (B)
-    _DEFPIN_ARM(10, 0, 11); // D10 is P0.11 (SCL)
-    _DEFPIN_ARM(11, 0, 12); // D11 is P0.12 (DRDYn)
-    _DEFPIN_ARM(12, 0, 13); // D12 is P0.13 (SDA)
-    _DEFPIN_ARM(13, 0, 14); // D13 is P0.17 (INT)
-    _DEFPIN_ARM(14, 0, 15); // D14 is P0.15 (INT1)
-    _DEFPIN_ARM(15, 0, 20); // D15 is P0.20 (INT2)
-    _DEFPIN_ARM(16, 0,  2); // D16 is P0.02 (A0)
-    _DEFPIN_ARM(17, 0,  3); // D17 is P0.03 (A1)
-    _DEFPIN_ARM(18, 0,  4); // D18 is P0.04 (A2)
-    _DEFPIN_ARM(19, 0, 24); // D19 is P0.24 (A3, also D4/SPI MISO) -- is this right?
-    _DEFPIN_ARM(20, 0, 29); // D20 is P0.29 (A4)
-    _DEFPIN_ARM(21, 0, 30); // D21 is P0.30 (A5)
-    _DEFPIN_ARM(22, 0, 31); // D22 is P0.31 (A6)
-    _DEFPIN_ARM(23, 0,  8); // D23 is P0.08 (RX)
-    _DEFPIN_ARM(24, 0,  6); // D24 is P0.06 (TX)
-    _DEFPIN_ARM(25, 0,  5); // D25 is P0.05 (RTS)
-    _DEFPIN_ARM(26, 0,  7); // D26 is P0.07 (CTS)
+    _FL_DEFPIN( 0, 26, 0); // D0  is P0.26
+    _FL_DEFPIN( 1, 27, 0); // D1  is P0.27
+    _FL_DEFPIN( 2, 22, 0); // D2  is P0.22 (SPI SS  )
+    _FL_DEFPIN( 3, 23, 0); // D3  is P0.23 (SPI MOSI)
+    _FL_DEFPIN( 4, 24, 0); // D4  is P0.24 (SPI MISO, also A3)
+    _FL_DEFPIN( 5, 25, 0); // D5  is P0.25 (SPI SCK )
+    _FL_DEFPIN( 6, 16, 0); // D6  is P0.16 (Button)
+    _FL_DEFPIN( 7, 19, 0); // D7  is P0.19 (R)
+    _FL_DEFPIN( 8, 18, 0); // D8  is P0.18 (G)
+    _FL_DEFPIN( 9, 17, 0); // D9  is P0.17 (B)
+    _FL_DEFPIN(10, 11, 0); // D10 is P0.11 (SCL)
+    _FL_DEFPIN(11, 12, 0); // D11 is P0.12 (DRDYn)
+    _FL_DEFPIN(12, 13, 0); // D12 is P0.13 (SDA)
+    _FL_DEFPIN(13, 14, 0); // D13 is P0.17 (INT)
+    _FL_DEFPIN(14, 15, 0); // D14 is P0.15 (INT1)
+    _FL_DEFPIN(15, 20, 0); // D15 is P0.20 (INT2)
+    _FL_DEFPIN(16,  2, 0); // D16 is P0.02 (A0)
+    _FL_DEFPIN(17,  3, 0); // D17 is P0.03 (A1)
+    _FL_DEFPIN(18,  4, 0); // D18 is P0.04 (A2)
+    _FL_DEFPIN(19, 24, 0); // D19 is P0.24 (A3, also D4/SPI MISO) -- is this right?
+    _FL_DEFPIN(20, 29, 0); // D20 is P0.29 (A4)
+    _FL_DEFPIN(21, 30, 0); // D21 is P0.30 (A5)
+    _FL_DEFPIN(22, 31, 0); // D22 is P0.31 (A6)
+    _FL_DEFPIN(23,  8, 0); // D23 is P0.08 (RX)
+    _FL_DEFPIN(24,  6, 0); // D24 is P0.06 (TX)
+    _FL_DEFPIN(25,  5, 0); // D25 is P0.05 (RTS)
+    _FL_DEFPIN(26,  7, 0); // D26 is P0.07 (CTS)
 #endif // defined(ARDUINO_ELECTRONUT_BLUEY)
 
 // Electronut labs hackaBLE
@@ -317,33 +317,33 @@
         #define __FASTPIN_ARM_NRF52_VARIANT_FOUND
     #endif
     #warning "Electronut labs hackaBLE is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues"
-    _DEFPIN_ARM( 0, 0, 14); // D0  is P0.14 (RX)
-    _DEFPIN_ARM( 1, 0, 13); // D1  is P0.13 (TX)
-    _DEFPIN_ARM( 2, 0, 12); // D2  is P0.12
-    _DEFPIN_ARM( 3, 0, 11); // D3  is P0.11 (SPI MOSI)
-    _DEFPIN_ARM( 4, 0,  8); // D4  is P0.08 (SPI MISO)
-    _DEFPIN_ARM( 5, 0,  7); // D5  is P0.07 (SPI SCK )
-    _DEFPIN_ARM( 6, 0,  6); // D6  is P0.06
-    _DEFPIN_ARM( 7, 0, 27); // D7  is P0.27
-    _DEFPIN_ARM( 8, 0, 26); // D8  is P0.26
-    _DEFPIN_ARM( 9, 0, 25); // D9  is P0.25
-    _DEFPIN_ARM(10, 0,  5); // D10 is P0.05 (A3)
-    _DEFPIN_ARM(11, 0,  4); // D11 is P0.04 (A2)
-    _DEFPIN_ARM(12, 0,  3); // D12 is P0.03 (A1)
-    _DEFPIN_ARM(13, 0,  2); // D13 is P0.02 (A0 / AREF)
-    _DEFPIN_ARM(14, 0, 23); // D14 is P0.23
-    _DEFPIN_ARM(15, 0, 22); // D15 is P0.22
-    _DEFPIN_ARM(16, 0, 18); // D16 is P0.18
-    _DEFPIN_ARM(17, 0, 16); // D17 is P0.16
-    _DEFPIN_ARM(18, 0, 15); // D18 is P0.15
-    _DEFPIN_ARM(19, 0, 24); // D19 is P0.24
-    _DEFPIN_ARM(20, 0, 28); // D20 is P0.28 (A4)
-    _DEFPIN_ARM(21, 0, 29); // D21 is P0.29 (A5)
-    _DEFPIN_ARM(22, 0, 30); // D22 is P0.30 (A6)
-    _DEFPIN_ARM(23, 0, 31); // D23 is P0.31 (A7)
-    _DEFPIN_ARM(24, 0, 19); // D24 is P0.19 (RED LED)
-    _DEFPIN_ARM(25, 0, 20); // D25 is P0.20 (GREEN LED)
-    _DEFPIN_ARM(26, 0, 17); // D26 is P0.17 (BLUE LED)
+    _FL_DEFPIN( 0, 14, 0); // D0  is P0.14 (RX)
+    _FL_DEFPIN( 1, 13, 0); // D1  is P0.13 (TX)
+    _FL_DEFPIN( 2, 12, 0); // D2  is P0.12
+    _FL_DEFPIN( 3, 11, 0); // D3  is P0.11 (SPI MOSI)
+    _FL_DEFPIN( 4,  8, 0); // D4  is P0.08 (SPI MISO)
+    _FL_DEFPIN( 5,  7, 0); // D5  is P0.07 (SPI SCK )
+    _FL_DEFPIN( 6,  6, 0); // D6  is P0.06
+    _FL_DEFPIN( 7, 27, 0); // D7  is P0.27
+    _FL_DEFPIN( 8, 26, 0); // D8  is P0.26
+    _FL_DEFPIN( 9, 25, 0); // D9  is P0.25
+    _FL_DEFPIN(10,  5, 0); // D10 is P0.05 (A3)
+    _FL_DEFPIN(11,  4, 0); // D11 is P0.04 (A2)
+    _FL_DEFPIN(12,  3, 0); // D12 is P0.03 (A1)
+    _FL_DEFPIN(13,  2, 0); // D13 is P0.02 (A0 / AREF)
+    _FL_DEFPIN(14, 23, 0); // D14 is P0.23
+    _FL_DEFPIN(15, 22, 0); // D15 is P0.22
+    _FL_DEFPIN(16, 18, 0); // D16 is P0.18
+    _FL_DEFPIN(17, 16, 0); // D17 is P0.16
+    _FL_DEFPIN(18, 15, 0); // D18 is P0.15
+    _FL_DEFPIN(19, 24, 0); // D19 is P0.24
+    _FL_DEFPIN(20, 28, 0); // D20 is P0.28 (A4)
+    _FL_DEFPIN(21, 29, 0); // D21 is P0.29 (A5)
+    _FL_DEFPIN(22, 30, 0); // D22 is P0.30 (A6)
+    _FL_DEFPIN(23, 31, 0); // D23 is P0.31 (A7)
+    _FL_DEFPIN(24, 19, 0); // D24 is P0.19 (RED LED)
+    _FL_DEFPIN(25, 20, 0); // D25 is P0.20 (GREEN LED)
+    _FL_DEFPIN(26, 17, 0); // D26 is P0.17 (BLUE LED)
 #endif // defined(ARDUINO_ELECTRONUT_HACKABLE)
 
 // Electronut labs hackaBLE_v2
@@ -399,31 +399,31 @@
         #define __FASTPIN_ARM_NRF52_VARIANT_FOUND
     #endif
     #warning "RedBear Blend 2 is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues"
-    _DEFPIN_ARM( 0, 0, 11); // D0  is P0.11
-    _DEFPIN_ARM( 1, 0, 12); // D1  is P0.12
-    _DEFPIN_ARM( 2, 0, 13); // D2  is P0.13
-    _DEFPIN_ARM( 3, 0, 14); // D3  is P0.14
-    _DEFPIN_ARM( 4, 0, 15); // D4  is P0.15
-    _DEFPIN_ARM( 5, 0, 16); // D5  is P0.16
-    _DEFPIN_ARM( 6, 0, 17); // D6  is P0.17
-    _DEFPIN_ARM( 7, 0, 18); // D7  is P0.18
-    _DEFPIN_ARM( 8, 0, 19); // D8  is P0.19
-    _DEFPIN_ARM( 9, 0, 20); // D9  is P0.20
-    _DEFPIN_ARM(10, 0, 22); // D10 is P0.22 (SPI SS  )
-    _DEFPIN_ARM(11, 0, 23); // D11 is P0.23 (SPI MOSI)
-    _DEFPIN_ARM(12, 0, 24); // D12 is P0.24 (SPI MISO)
-    _DEFPIN_ARM(13, 0, 25); // D13 is P0.25 (SPI SCK / LED)
-    _DEFPIN_ARM(14, 0,  3); // D14 is P0.03 (A0)
-    _DEFPIN_ARM(15, 0,  4); // D15 is P0.04 (A1)
-    _DEFPIN_ARM(16, 0, 28); // D16 is P0.28 (A2)
-    _DEFPIN_ARM(17, 0, 29); // D17 is P0.29 (A3)
-    _DEFPIN_ARM(18, 0, 30); // D18 is P0.30 (A4)
-    _DEFPIN_ARM(19, 0, 31); // D19 is P0.31 (A5)
-    _DEFPIN_ARM(20, 0, 26); // D20 is P0.26 (SDA)
-    _DEFPIN_ARM(21, 0, 27); // D21 is P0.27 (SCL)
-    _DEFPIN_ARM(22, 0,  8); // D22 is P0.08 (RX)
-    _DEFPIN_ARM(23, 0,  6); // D23 is P0.06 (TX)
-    _DEFPIN_ARM(24, 0,  2); // D24 is P0.02 (AREF)
+    _FL_DEFPIN( 0, 11, 0); // D0  is P0.11
+    _FL_DEFPIN( 1, 12, 0); // D1  is P0.12
+    _FL_DEFPIN( 2, 13, 0); // D2  is P0.13
+    _FL_DEFPIN( 3, 14, 0); // D3  is P0.14
+    _FL_DEFPIN( 4, 15, 0); // D4  is P0.15
+    _FL_DEFPIN( 5, 16, 0); // D5  is P0.16
+    _FL_DEFPIN( 6, 17, 0); // D6  is P0.17
+    _FL_DEFPIN( 7, 18, 0); // D7  is P0.18
+    _FL_DEFPIN( 8, 19, 0); // D8  is P0.19
+    _FL_DEFPIN( 9, 20, 0); // D9  is P0.20
+    _FL_DEFPIN(10, 22, 0); // D10 is P0.22 (SPI SS  )
+    _FL_DEFPIN(11, 23, 0); // D11 is P0.23 (SPI MOSI)
+    _FL_DEFPIN(12, 24, 0); // D12 is P0.24 (SPI MISO)
+    _FL_DEFPIN(13, 25, 0); // D13 is P0.25 (SPI SCK / LED)
+    _FL_DEFPIN(14,  3, 0); // D14 is P0.03 (A0)
+    _FL_DEFPIN(15,  4, 0); // D15 is P0.04 (A1)
+    _FL_DEFPIN(16, 28, 0); // D16 is P0.28 (A2)
+    _FL_DEFPIN(17, 29, 0); // D17 is P0.29 (A3)
+    _FL_DEFPIN(18, 30, 0); // D18 is P0.30 (A4)
+    _FL_DEFPIN(19, 31, 0); // D19 is P0.31 (A5)
+    _FL_DEFPIN(20, 26, 0); // D20 is P0.26 (SDA)
+    _FL_DEFPIN(21, 27, 0); // D21 is P0.27 (SCL)
+    _FL_DEFPIN(22,  8, 0); // D22 is P0.08 (RX)
+    _FL_DEFPIN(23,  6, 0); // D23 is P0.06 (TX)
+    _FL_DEFPIN(24,  2, 0); // D24 is P0.02 (AREF)
 #endif // defined(ARDUINO_RB_BLEND_2)
 
 // RedBear BLE Nano 2
@@ -435,18 +435,18 @@
         #define __FASTPIN_ARM_NRF52_VARIANT_FOUND
     #endif
     #warning "RedBear BLE Nano 2 is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues"
-    _DEFPIN_ARM( 0, 0, 30); // D0  is P0.30 (A0 / RX)
-    _DEFPIN_ARM( 1, 0, 29); // D1  is P0.29 (A1 / TX)
-    _DEFPIN_ARM( 2, 0, 28); // D2  is P0.28 (A2 / SDA)
-    _DEFPIN_ARM( 3, 0,  2); // D3  is P0.02 (A3 / SCL)
-    _DEFPIN_ARM( 4, 0,  5); // D4  is P0.05 (A4)
-    _DEFPIN_ARM( 5, 0,  4); // D5  is P0.04 (A5)
-    _DEFPIN_ARM( 6, 0,  3); // D6  is P0.03 (SPI SS  )
-    _DEFPIN_ARM( 7, 0,  6); // D7  is P0.06 (SPI MOSI)
-    _DEFPIN_ARM( 8, 0,  7); // D8  is P0.07 (SPI MISO)
-    _DEFPIN_ARM( 9, 0,  8); // D9  is P0.08 (SPI SCK )
-    // _DEFPIN_ARM(10, 0, 21); // D10 is P0.21 (RESET)
-    _DEFPIN_ARM(13, 0, 11); // D11 is P0.11 (LED)
+    _FL_DEFPIN( 0, 30, 0); // D0  is P0.30 (A0 / RX)
+    _FL_DEFPIN( 1, 29, 0); // D1  is P0.29 (A1 / TX)
+    _FL_DEFPIN( 2, 28, 0); // D2  is P0.28 (A2 / SDA)
+    _FL_DEFPIN( 3,  2, 0); // D3  is P0.02 (A3 / SCL)
+    _FL_DEFPIN( 4,  5, 0); // D4  is P0.05 (A4)
+    _FL_DEFPIN( 5,  4, 0); // D5  is P0.04 (A5)
+    _FL_DEFPIN( 6,  3, 0); // D6  is P0.03 (SPI SS  )
+    _FL_DEFPIN( 7,  6, 0); // D7  is P0.06 (SPI MOSI)
+    _FL_DEFPIN( 8,  7, 0); // D8  is P0.07 (SPI MISO)
+    _FL_DEFPIN( 9,  8, 0); // D9  is P0.08 (SPI SCK )
+    // _FL_DEFPIN(10, 21, 0); // D10 is P0.21 (RESET)
+    _FL_DEFPIN(13, 11, 0); // D11 is P0.11 (LED)
 #endif // defined(ARDUINO_RB_BLE_NANO_2)
 
 // Nordic Semiconductor nRF52 DK
@@ -458,32 +458,32 @@
         #define __FASTPIN_ARM_NRF52_VARIANT_FOUND
     #endif
     #warning "Nordic Semiconductor nRF52 DK is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues"
-    _DEFPIN_ARM( 0, 0, 11); // D0  is P0.11
-    _DEFPIN_ARM( 1, 0, 12); // D1  is P0.12
-    _DEFPIN_ARM( 2, 0, 13); // D2  is P0.13 (BUTTON1)
-    _DEFPIN_ARM( 3, 0, 14); // D3  is P0.14 (BUTTON2)
-    _DEFPIN_ARM( 4, 0, 15); // D4  is P0.15 (BUTTON3)
-    _DEFPIN_ARM( 5, 0, 16); // D5  is P0.16 (BUTTON4)
-    _DEFPIN_ARM( 6, 0, 17); // D6  is P0.17 (LED1)
-    _DEFPIN_ARM( 7, 0, 18); // D7  is P0.18 (LED2)
-    _DEFPIN_ARM( 8, 0, 19); // D8  is P0.19 (LED3)
-    _DEFPIN_ARM( 9, 0, 20); // D9  is P0.20 (LED4)
-    _DEFPIN_ARM(10, 0, 22); // D10 is P0.22 (SPI SS  )
-    _DEFPIN_ARM(11, 0, 23); // D11 is P0.23 (SPI MOSI)
-    _DEFPIN_ARM(12, 0, 24); // D12 is P0.24 (SPI MISO)
-    _DEFPIN_ARM(13, 0, 25); // D13 is P0.25 (SPI SCK / LED)
-    _DEFPIN_ARM(14, 0,  3); // D14 is P0.03 (A0)
-    _DEFPIN_ARM(15, 0,  4); // D15 is P0.04 (A1)
-    _DEFPIN_ARM(16, 0, 28); // D16 is P0.28 (A2)
-    _DEFPIN_ARM(17, 0, 29); // D17 is P0.29 (A3)
-    _DEFPIN_ARM(18, 0, 30); // D18 is P0.30 (A4)
-    _DEFPIN_ARM(19, 0, 31); // D19 is P0.31 (A5)
-    _DEFPIN_ARM(20, 0,  5); // D20 is P0.05 (A6)
-    _DEFPIN_ARM(21, 0,  2); // D21 is P0.02 (A7 / AREF)
-    _DEFPIN_ARM(22, 0, 26); // D22 is P0.26 (SDA)
-    _DEFPIN_ARM(23, 0, 27); // D23 is P0.27 (SCL)
-    _DEFPIN_ARM(24, 0,  8); // D24 is P0.08 (RX)
-    _DEFPIN_ARM(25, 0,  6); // D25 is P0.06 (TX)
+    _FL_DEFPIN( 0, 11, 0); // D0  is P0.11
+    _FL_DEFPIN( 1, 12, 0); // D1  is P0.12
+    _FL_DEFPIN( 2, 13, 0); // D2  is P0.13 (BUTTON1)
+    _FL_DEFPIN( 3, 14, 0); // D3  is P0.14 (BUTTON2)
+    _FL_DEFPIN( 4, 15, 0); // D4  is P0.15 (BUTTON3)
+    _FL_DEFPIN( 5, 16, 0); // D5  is P0.16 (BUTTON4)
+    _FL_DEFPIN( 6, 17, 0); // D6  is P0.17 (LED1)
+    _FL_DEFPIN( 7, 18, 0); // D7  is P0.18 (LED2)
+    _FL_DEFPIN( 8, 19, 0); // D8  is P0.19 (LED3)
+    _FL_DEFPIN( 9, 20, 0); // D9  is P0.20 (LED4)
+    _FL_DEFPIN(10, 22, 0); // D10 is P0.22 (SPI SS  )
+    _FL_DEFPIN(11, 23, 0); // D11 is P0.23 (SPI MOSI)
+    _FL_DEFPIN(12, 24, 0); // D12 is P0.24 (SPI MISO)
+    _FL_DEFPIN(13, 25, 0); // D13 is P0.25 (SPI SCK / LED)
+    _FL_DEFPIN(14,  3, 0); // D14 is P0.03 (A0)
+    _FL_DEFPIN(15,  4, 0); // D15 is P0.04 (A1)
+    _FL_DEFPIN(16, 28, 0); // D16 is P0.28 (A2)
+    _FL_DEFPIN(17, 29, 0); // D17 is P0.29 (A3)
+    _FL_DEFPIN(18, 30, 0); // D18 is P0.30 (A4)
+    _FL_DEFPIN(19, 31, 0); // D19 is P0.31 (A5)
+    _FL_DEFPIN(20,  5, 0); // D20 is P0.05 (A6)
+    _FL_DEFPIN(21,  2, 0); // D21 is P0.02 (A7 / AREF)
+    _FL_DEFPIN(22, 26, 0); // D22 is P0.26 (SDA)
+    _FL_DEFPIN(23, 27, 0); // D23 is P0.27 (SCL)
+    _FL_DEFPIN(24,  8, 0); // D24 is P0.08 (RX)
+    _FL_DEFPIN(25,  6, 0); // D25 is P0.06 (TX)
 #endif // defined(ARDUINO_NRF52_DK)
 
 // Taida Century nRF52 mini board
@@ -495,38 +495,38 @@
         #define __FASTPIN_ARM_NRF52_VARIANT_FOUND
     #endif
     #warning "Taida Century nRF52 mini board is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues"
-    //_DEFPIN_ARM( 0, 0, 25); // D0  is P0.xx (near radio!)
-    //_DEFPIN_ARM( 1, 0, 26); // D1  is P0.xx (near radio!)
-    //_DEFPIN_ARM( 2, 0, 27); // D2  is P0.xx (near radio!)
-    //_DEFPIN_ARM( 3, 0, 28); // D3  is P0.xx (near radio!)
-    //_DEFPIN_ARM( 4, 0, 29); // D4  is P0.xx (Not connected, near radio!)
-    //_DEFPIN_ARM( 5, 0, 30); // D5  is P0.xx (LED1, near radio!)
-    //_DEFPIN_ARM( 6, 0, 31); // D6  is P0.xx (LED2, near radio!)
-    _DEFPIN_ARM( 7, 0,  2); // D7  is P0.xx (SDA)
-    _DEFPIN_ARM( 8, 0,  3); // D8  is P0.xx (SCL)
-    _DEFPIN_ARM( 9, 0,  4); // D9  is P0.xx (BUTTON1 / NFC1)
-    _DEFPIN_ARM(10, 0,  5); // D10 is P0.xx
-    //_DEFPIN_ARM(11, 0,  0); // D11 is P0.xx (Not connected)
-    //_DEFPIN_ARM(12, 0,  1); // D12 is P0.xx (Not connected)
-    _DEFPIN_ARM(13, 0,  6); // D13 is P0.xx
-    _DEFPIN_ARM(14, 0,  7); // D14 is P0.xx
-    _DEFPIN_ARM(15, 0,  8); // D15 is P0.xx
-    //_DEFPIN_ARM(16, 0,  9); // D16 is P0.xx (Not connected)
-    //_DEFPIN_ARM(17, 0, 10); // D17 is P0.xx (NFC2, Not connected)
-    _DEFPIN_ARM(18, 0, 11); // D18 is P0.xx (RXD)
-    _DEFPIN_ARM(19, 0, 12); // D19 is P0.xx (TXD)
-    _DEFPIN_ARM(20, 0, 13); // D20 is P0.xx (SPI SS  )
-    _DEFPIN_ARM(21, 0, 14); // D21 is P0.xx (SPI MISO)
-    _DEFPIN_ARM(22, 0, 15); // D22 is P0.xx (SPI MOSI)
-    _DEFPIN_ARM(23, 0, 16); // D23 is P0.xx (SPI SCK )
-    _DEFPIN_ARM(24, 0, 17); // D24 is P0.xx (A0)
-    _DEFPIN_ARM(25, 0, 18); // D25 is P0.xx (A1)
-    _DEFPIN_ARM(26, 0, 19); // D26 is P0.xx (A2)
-    _DEFPIN_ARM(27, 0, 20); // D27 is P0.xx (A3)
-    //_DEFPIN_ARM(28, 0, 22); // D28 is P0.xx (A4, near radio!)
-    //_DEFPIN_ARM(29, 0, 23); // D29 is P0.xx (A5, near radio!)
-    _DEFPIN_ARM(30, 0, 24); // D30 is P0.xx
-    // _DEFPIN_ARM(31, 0, 21); // D31 is P0.21 (RESET)
+    //_FL_DEFPIN( 0, 25, 0); // D0  is P0.xx (near radio!)
+    //_FL_DEFPIN( 1, 26, 0); // D1  is P0.xx (near radio!)
+    //_FL_DEFPIN( 2, 27, 0); // D2  is P0.xx (near radio!)
+    //_FL_DEFPIN( 3, 28, 0); // D3  is P0.xx (near radio!)
+    //_FL_DEFPIN( 4, 29, 0); // D4  is P0.xx (Not connected, near radio!)
+    //_FL_DEFPIN( 5, 30, 0); // D5  is P0.xx (LED1, near radio!)
+    //_FL_DEFPIN( 6, 31, 0); // D6  is P0.xx (LED2, near radio!)
+    _FL_DEFPIN( 7,  2, 0); // D7  is P0.xx (SDA)
+    _FL_DEFPIN( 8,  3, 0); // D8  is P0.xx (SCL)
+    _FL_DEFPIN( 9,  4, 0); // D9  is P0.xx (BUTTON1 / NFC1)
+    _FL_DEFPIN(10,  5, 0); // D10 is P0.xx
+    //_FL_DEFPIN(11,  0, 0); // D11 is P0.xx (Not connected)
+    //_FL_DEFPIN(12,  1, 0); // D12 is P0.xx (Not connected)
+    _FL_DEFPIN(13,  6, 0); // D13 is P0.xx
+    _FL_DEFPIN(14,  7, 0); // D14 is P0.xx
+    _FL_DEFPIN(15,  8, 0); // D15 is P0.xx
+    //_FL_DEFPIN(16,  9, 0); // D16 is P0.xx (Not connected)
+    //_FL_DEFPIN(17, 10, 0); // D17 is P0.xx (NFC2, Not connected)
+    _FL_DEFPIN(18, 11, 0); // D18 is P0.xx (RXD)
+    _FL_DEFPIN(19, 12, 0); // D19 is P0.xx (TXD)
+    _FL_DEFPIN(20, 13, 0); // D20 is P0.xx (SPI SS  )
+    _FL_DEFPIN(21, 14, 0); // D21 is P0.xx (SPI MISO)
+    _FL_DEFPIN(22, 15, 0); // D22 is P0.xx (SPI MOSI)
+    _FL_DEFPIN(23, 16, 0); // D23 is P0.xx (SPI SCK )
+    _FL_DEFPIN(24, 17, 0); // D24 is P0.xx (A0)
+    _FL_DEFPIN(25, 18, 0); // D25 is P0.xx (A1)
+    _FL_DEFPIN(26, 19, 0); // D26 is P0.xx (A2)
+    _FL_DEFPIN(27, 20, 0); // D27 is P0.xx (A3)
+    //_FL_DEFPIN(28, 22, 0); // D28 is P0.xx (A4, near radio!)
+    //_FL_DEFPIN(29, 23, 0); // D29 is P0.xx (A5, near radio!)
+    _FL_DEFPIN(30, 24, 0); // D30 is P0.xx
+    // _FL_DEFPIN(31, 21, 0); // D31 is P0.21 (RESET)
 #endif // defined(ARDUINO_STCT_NRF52_minidev)
 
 // Generic nRF52832
diff --git a/platforms/arm/nrf52/fastspi_arm_nrf52.h b/platforms/arm/nrf52/fastspi_arm_nrf52.h
index 8492282b..9c1a2198 100644
--- a/platforms/arm/nrf52/fastspi_arm_nrf52.h
+++ b/platforms/arm/nrf52/fastspi_arm_nrf52.h
@@ -21,7 +21,7 @@
      */
 
     /// SPI_CLOCK_DIVIDER is number of CPU clock cycles per SPI transmission bit?
-    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
     class NRF52SPIOutput {
 
     private:
@@ -325,13 +325,13 @@
 
     // Static member definition and initialization using templates.
     // see https://stackoverflow.com/questions/3229883/static-member-initialization-in-a-class-template#answer-3229919
-    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
     bool NRF52SPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDER>::s_InUse = false;
-    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
     bool NRF52SPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDER>::s_NeedToWait = false;
-    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
     uint8_t NRF52SPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDER>::s_BufferIndex = 0;
-    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+    template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
     uint8_t NRF52SPIOutput<_DATA_PIN, _CLOCK_PIN, _SPI_CLOCK_DIVIDER>::s_Buffer[2][2] = {{0,0},{0,0}};
 
 #endif // #ifndef FASTLED_FORCE_SOFTWARE_SPI
diff --git a/platforms/arm/sam/fastpin_arm_sam.h b/platforms/arm/sam/fastpin_arm_sam.h
index 2bb78042..339c5e75 100644
--- a/platforms/arm/sam/fastpin_arm_sam.h
+++ b/platforms/arm/sam/fastpin_arm_sam.h
@@ -78,49 +78,50 @@ public:
 #define _R(T) struct __gen_struct_ ## T
 #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
 	template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
-#define DUE_IO32(L) _RD32(REG_PIO ## L ## _ODSR); _RD32(REG_PIO ## L ## _SODR); _RD32(REG_PIO ## L ## _CODR); _RD32(REG_PIO ## L ## _OER);
+#define _FL_IO(L,C) _RD32(REG_PIO ## L ## _ODSR); _RD32(REG_PIO ## L ## _SODR); _RD32(REG_PIO ## L ## _CODR); _RD32(REG_PIO ## L ## _OER); _FL_DEFINE_PORT3(L, C, _R(REG_PIO ## L ## _ODSR));
 
-#define _DEFPIN_DUE(PIN, BIT, L) template<> class FastPin<PIN> : public _DUEPIN<PIN, 1 << BIT, _R(REG_PIO ## L ## _ODSR), _R(REG_PIO ## L ## _SODR), _R(REG_PIO ## L ## _CODR), \
+#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _DUEPIN<PIN, 1 << BIT, _R(REG_PIO ## L ## _ODSR), _R(REG_PIO ## L ## _SODR), _R(REG_PIO ## L ## _CODR), \
   																			_R(GPIO ## L ## _OER)> {}; \
   								   template<> class FastPinBB<PIN> : public _DUEPIN_BITBAND<PIN, BIT, _R(REG_PIO ## L ## _ODSR), _R(REG_PIO ## L ## _SODR), _R(REG_PIO ## L ## _CODR), \
   																			_R(GPIO ## L ## _OER)> {};
 
+_FL_IO(A,0);
+_FL_IO(B,1);
+_FL_IO(C,2);
+_FL_IO(D,3);
+
 #if defined(__SAM3X8E__)
 
-DUE_IO32(A);
-DUE_IO32(B);
-DUE_IO32(C);
-DUE_IO32(D);
 
 #define MAX_PIN 78
-_DEFPIN_DUE(0, 8, A); _DEFPIN_DUE(1, 9, A); _DEFPIN_DUE(2, 25, B); _DEFPIN_DUE(3, 28, C);
-_DEFPIN_DUE(4, 26, C); _DEFPIN_DUE(5, 25, C); _DEFPIN_DUE(6, 24, C); _DEFPIN_DUE(7, 23, C);
-_DEFPIN_DUE(8, 22, C); _DEFPIN_DUE(9, 21, C); _DEFPIN_DUE(10, 29, C); _DEFPIN_DUE(11, 7, D);
-_DEFPIN_DUE(12, 8, D); _DEFPIN_DUE(13, 27, B); _DEFPIN_DUE(14, 4, D); _DEFPIN_DUE(15, 5, D);
-_DEFPIN_DUE(16, 13, A); _DEFPIN_DUE(17, 12, A); _DEFPIN_DUE(18, 11, A); _DEFPIN_DUE(19, 10, A);
-_DEFPIN_DUE(20, 12, B); _DEFPIN_DUE(21, 13, B); _DEFPIN_DUE(22, 26, B); _DEFPIN_DUE(23, 14, A);
-_DEFPIN_DUE(24, 15, A); _DEFPIN_DUE(25, 0, D); _DEFPIN_DUE(26, 1, D); _DEFPIN_DUE(27, 2, D);
-_DEFPIN_DUE(28, 3, D); _DEFPIN_DUE(29, 6, D); _DEFPIN_DUE(30, 9, D); _DEFPIN_DUE(31, 7, A);
-_DEFPIN_DUE(32, 10, D); _DEFPIN_DUE(33, 1, C); _DEFPIN_DUE(34, 2, C); _DEFPIN_DUE(35, 3, C);
-_DEFPIN_DUE(36, 4, C); _DEFPIN_DUE(37, 5, C); _DEFPIN_DUE(38, 6, C); _DEFPIN_DUE(39, 7, C);
-_DEFPIN_DUE(40, 8, C); _DEFPIN_DUE(41, 9, C); _DEFPIN_DUE(42, 19, A); _DEFPIN_DUE(43, 20, A);
-_DEFPIN_DUE(44, 19, C); _DEFPIN_DUE(45, 18, C); _DEFPIN_DUE(46, 17, C); _DEFPIN_DUE(47, 16, C);
-_DEFPIN_DUE(48, 15, C); _DEFPIN_DUE(49, 14, C); _DEFPIN_DUE(50, 13, C); _DEFPIN_DUE(51, 12, C);
-_DEFPIN_DUE(52, 21, B); _DEFPIN_DUE(53, 14, B); _DEFPIN_DUE(54, 16, A); _DEFPIN_DUE(55, 24, A);
-_DEFPIN_DUE(56, 23, A); _DEFPIN_DUE(57, 22, A); _DEFPIN_DUE(58, 6, A); _DEFPIN_DUE(59, 4, A);
-_DEFPIN_DUE(60, 3, A); _DEFPIN_DUE(61, 2, A); _DEFPIN_DUE(62, 17, B); _DEFPIN_DUE(63, 18, B);
-_DEFPIN_DUE(64, 19, B); _DEFPIN_DUE(65, 20, B); _DEFPIN_DUE(66, 15, B); _DEFPIN_DUE(67, 16, B);
-_DEFPIN_DUE(68, 1, A); _DEFPIN_DUE(69, 0, A); _DEFPIN_DUE(70, 17, A); _DEFPIN_DUE(71, 18, A);
-_DEFPIN_DUE(72, 30, C); _DEFPIN_DUE(73, 21, A); _DEFPIN_DUE(74, 25, A); _DEFPIN_DUE(75, 26, A);
-_DEFPIN_DUE(76, 27, A); _DEFPIN_DUE(77, 28, A); _DEFPIN_DUE(78, 23, B);
+_FL_DEFPIN(0, 8, A); _FL_DEFPIN(1, 9, A); _FL_DEFPIN(2, 25, B); _FL_DEFPIN(3, 28, C);
+_FL_DEFPIN(4, 26, C); _FL_DEFPIN(5, 25, C); _FL_DEFPIN(6, 24, C); _FL_DEFPIN(7, 23, C);
+_FL_DEFPIN(8, 22, C); _FL_DEFPIN(9, 21, C); _FL_DEFPIN(10, 29, C); _FL_DEFPIN(11, 7, D);
+_FL_DEFPIN(12, 8, D); _FL_DEFPIN(13, 27, B); _FL_DEFPIN(14, 4, D); _FL_DEFPIN(15, 5, D);
+_FL_DEFPIN(16, 13, A); _FL_DEFPIN(17, 12, A); _FL_DEFPIN(18, 11, A); _FL_DEFPIN(19, 10, A);
+_FL_DEFPIN(20, 12, B); _FL_DEFPIN(21, 13, B); _FL_DEFPIN(22, 26, B); _FL_DEFPIN(23, 14, A);
+_FL_DEFPIN(24, 15, A); _FL_DEFPIN(25, 0, D); _FL_DEFPIN(26, 1, D); _FL_DEFPIN(27, 2, D);
+_FL_DEFPIN(28, 3, D); _FL_DEFPIN(29, 6, D); _FL_DEFPIN(30, 9, D); _FL_DEFPIN(31, 7, A);
+_FL_DEFPIN(32, 10, D); _FL_DEFPIN(33, 1, C); _FL_DEFPIN(34, 2, C); _FL_DEFPIN(35, 3, C);
+_FL_DEFPIN(36, 4, C); _FL_DEFPIN(37, 5, C); _FL_DEFPIN(38, 6, C); _FL_DEFPIN(39, 7, C);
+_FL_DEFPIN(40, 8, C); _FL_DEFPIN(41, 9, C); _FL_DEFPIN(42, 19, A); _FL_DEFPIN(43, 20, A);
+_FL_DEFPIN(44, 19, C); _FL_DEFPIN(45, 18, C); _FL_DEFPIN(46, 17, C); _FL_DEFPIN(47, 16, C);
+_FL_DEFPIN(48, 15, C); _FL_DEFPIN(49, 14, C); _FL_DEFPIN(50, 13, C); _FL_DEFPIN(51, 12, C);
+_FL_DEFPIN(52, 21, B); _FL_DEFPIN(53, 14, B); _FL_DEFPIN(54, 16, A); _FL_DEFPIN(55, 24, A);
+_FL_DEFPIN(56, 23, A); _FL_DEFPIN(57, 22, A); _FL_DEFPIN(58, 6, A); _FL_DEFPIN(59, 4, A);
+_FL_DEFPIN(60, 3, A); _FL_DEFPIN(61, 2, A); _FL_DEFPIN(62, 17, B); _FL_DEFPIN(63, 18, B);
+_FL_DEFPIN(64, 19, B); _FL_DEFPIN(65, 20, B); _FL_DEFPIN(66, 15, B); _FL_DEFPIN(67, 16, B);
+_FL_DEFPIN(68, 1, A); _FL_DEFPIN(69, 0, A); _FL_DEFPIN(70, 17, A); _FL_DEFPIN(71, 18, A);
+_FL_DEFPIN(72, 30, C); _FL_DEFPIN(73, 21, A); _FL_DEFPIN(74, 25, A); _FL_DEFPIN(75, 26, A);
+_FL_DEFPIN(76, 27, A); _FL_DEFPIN(77, 28, A); _FL_DEFPIN(78, 23, B);
 
 // digix pins
-_DEFPIN_DUE(90, 0, B); _DEFPIN_DUE(91, 1, B); _DEFPIN_DUE(92, 2, B); _DEFPIN_DUE(93, 3, B);
-_DEFPIN_DUE(94, 4, B); _DEFPIN_DUE(95, 5, B); _DEFPIN_DUE(96, 6, B); _DEFPIN_DUE(97, 7, B);
-_DEFPIN_DUE(98, 8, B); _DEFPIN_DUE(99, 9, B); _DEFPIN_DUE(100, 5, A); _DEFPIN_DUE(101, 22, B);
-_DEFPIN_DUE(102, 23, B); _DEFPIN_DUE(103, 24, B); _DEFPIN_DUE(104, 27, C); _DEFPIN_DUE(105, 20, C);
-_DEFPIN_DUE(106, 11, C); _DEFPIN_DUE(107, 10, C); _DEFPIN_DUE(108, 21, A); _DEFPIN_DUE(109, 30, C);
-_DEFPIN_DUE(110, 29, B); _DEFPIN_DUE(111, 30, B); _DEFPIN_DUE(112, 31, B); _DEFPIN_DUE(113, 28, B);
+_FL_DEFPIN(90, 0, B); _FL_DEFPIN(91, 1, B); _FL_DEFPIN(92, 2, B); _FL_DEFPIN(93, 3, B);
+_FL_DEFPIN(94, 4, B); _FL_DEFPIN(95, 5, B); _FL_DEFPIN(96, 6, B); _FL_DEFPIN(97, 7, B);
+_FL_DEFPIN(98, 8, B); _FL_DEFPIN(99, 9, B); _FL_DEFPIN(100, 5, A); _FL_DEFPIN(101, 22, B);
+_FL_DEFPIN(102, 23, B); _FL_DEFPIN(103, 24, B); _FL_DEFPIN(104, 27, C); _FL_DEFPIN(105, 20, C);
+_FL_DEFPIN(106, 11, C); _FL_DEFPIN(107, 10, C); _FL_DEFPIN(108, 21, A); _FL_DEFPIN(109, 30, C);
+_FL_DEFPIN(110, 29, B); _FL_DEFPIN(111, 30, B); _FL_DEFPIN(112, 31, B); _FL_DEFPIN(113, 28, B);
 
 #define SPI_DATA 75
 #define SPI_CLOCK 76
diff --git a/platforms/arm/sam/fastspi_arm_sam.h b/platforms/arm/sam/fastspi_arm_sam.h
index eb9abe4c..a9446439 100644
--- a/platforms/arm/sam/fastspi_arm_sam.h
+++ b/platforms/arm/sam/fastspi_arm_sam.h
@@ -6,7 +6,7 @@ FASTLED_NAMESPACE_BEGIN
 #if defined(__SAM3X8E__)
 #define m_SPI ((Spi*)SPI0)
 
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class SAMHardwareSPIOutput {
 	Selectable *m_pSelect;
 
diff --git a/platforms/arm/stm32/fastpin_arm_stm32.h b/platforms/arm/stm32/fastpin_arm_stm32.h
index 57309cd9..274d0f60 100644
--- a/platforms/arm/stm32/fastpin_arm_stm32.h
+++ b/platforms/arm/stm32/fastpin_arm_stm32.h
@@ -56,45 +56,67 @@ public:
 };
 
 #if defined(STM32F10X_MD)
- #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile GPIO_TypeDef * r() { return T; } };
- #define _IO32(L) _RD32(GPIO ## L)
+  #define _R(T) struct __gen_struct_ ## T
+  #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile GPIO_TypeDef * r() { return T; } };
+  #define _FL_IO(L,C) _RD32(GPIO ## L);  _FL_DEFINE_PORT3(L, C, _R(GPIO ## L));
 #elif defined(__STM32F1__)
- #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline gpio_reg_map* r() { return T->regs; } };
- #define _IO32(L) _RD32(GPIO ## L)
+  #define _R(T) struct __gen_struct_ ## T
+  #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline gpio_reg_map* r() { return T->regs; } };
+  #define _FL_IO(L,C) _RD32(GPIO ## L); _FL_DEFINE_PORT3(L, C, _R(GPIO ## L));
 #else
  #error "Platform not supported"
 #endif
 
-#define _R(T) struct __gen_struct_ ## T
-#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L)> {};
+#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L)> {};
+
+#ifdef GPIOA
+_FL_IO(A,0);
+#endif
+#ifdef GPIOB
+_FL_IO(B,1);
+#endif
+#ifdef GPIOC
+_FL_IO(C,2);
+#endif
+#ifdef GPIOD
+_FL_IO(D,3);
+#endif
+#ifdef GPIOE
+_FL_IO(E,4);
+#endif
+#ifdef GPIOF
+_FL_IO(F,5);
+#endif
+#ifdef GPIOG
+_FL_IO(G,6);
+#endif
 
 // Actual pin definitions
 #if defined(SPARK) // Sparkfun STM32F103 based board
 
-_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E); _IO32(F); _IO32(G);
 
 
 #define MAX_PIN 19
-_DEFPIN_ARM(0, 7, B);
-_DEFPIN_ARM(1, 6, B);
-_DEFPIN_ARM(2, 5, B);
-_DEFPIN_ARM(3, 4, B);
-_DEFPIN_ARM(4, 3, B);
-_DEFPIN_ARM(5, 15, A);
-_DEFPIN_ARM(6, 14, A);
-_DEFPIN_ARM(7, 13, A);
-_DEFPIN_ARM(8, 8, A);
-_DEFPIN_ARM(9, 9, A);
-_DEFPIN_ARM(10, 0, A);
-_DEFPIN_ARM(11, 1, A);
-_DEFPIN_ARM(12, 4, A);
-_DEFPIN_ARM(13, 5, A);
-_DEFPIN_ARM(14, 6, A);
-_DEFPIN_ARM(15, 7, A);
-_DEFPIN_ARM(16, 0, B);
-_DEFPIN_ARM(17, 1, B);
-_DEFPIN_ARM(18, 3, A);
-_DEFPIN_ARM(19, 2, A);
+_FL_DEFPIN(0, 7, B);
+_FL_DEFPIN(1, 6, B);
+_FL_DEFPIN(2, 5, B);
+_FL_DEFPIN(3, 4, B);
+_FL_DEFPIN(4, 3, B);
+_FL_DEFPIN(5, 15, A);
+_FL_DEFPIN(6, 14, A);
+_FL_DEFPIN(7, 13, A);
+_FL_DEFPIN(8, 8, A);
+_FL_DEFPIN(9, 9, A);
+_FL_DEFPIN(10, 0, A);
+_FL_DEFPIN(11, 1, A);
+_FL_DEFPIN(12, 4, A);
+_FL_DEFPIN(13, 5, A);
+_FL_DEFPIN(14, 6, A);
+_FL_DEFPIN(15, 7, A);
+_FL_DEFPIN(16, 0, B);
+_FL_DEFPIN(17, 1, B);
+_FL_DEFPIN(18, 3, A);
+_FL_DEFPIN(19, 2, A);
 
 
 #define SPI_DATA 15
@@ -106,43 +128,41 @@ _DEFPIN_ARM(19, 2, A);
 
 #if defined(__STM32F1__) // Generic STM32F103 aka "Blue Pill"
 
-_IO32(A); _IO32(B); _IO32(C);
-
 #define MAX_PIN 46
 
-_DEFPIN_ARM(10, 0, A);	// PA0 - PA7
-_DEFPIN_ARM(11, 1, A);
-_DEFPIN_ARM(12, 2, A);
-_DEFPIN_ARM(13, 3, A);
-_DEFPIN_ARM(14, 4, A);
-_DEFPIN_ARM(15, 5, A);
-_DEFPIN_ARM(16, 6, A);
-_DEFPIN_ARM(17, 7, A);
-_DEFPIN_ARM(29, 8, A);	// PA8 - PA15
-_DEFPIN_ARM(30, 9, A);
-_DEFPIN_ARM(31, 10, A);
-_DEFPIN_ARM(32, 11, A);
-_DEFPIN_ARM(33, 12, A);
-_DEFPIN_ARM(34, 13, A);
-_DEFPIN_ARM(37, 14, A);
-_DEFPIN_ARM(38, 15, A);
-
-_DEFPIN_ARM(18, 0, B);	// PB0 - PB11
-_DEFPIN_ARM(19, 1, B);
-_DEFPIN_ARM(20, 2, B);
-_DEFPIN_ARM(39, 3, B);
-_DEFPIN_ARM(40, 4, B);
-_DEFPIN_ARM(41, 5, B);
-_DEFPIN_ARM(42, 6, B);
-_DEFPIN_ARM(43, 7, B);
-_DEFPIN_ARM(45, 8, B);
-_DEFPIN_ARM(46, 9, B);
-_DEFPIN_ARM(21, 10, B);
-_DEFPIN_ARM(22, 11, B);
-
-_DEFPIN_ARM(2, 13, C);	// PC13 - PC15
-_DEFPIN_ARM(3, 14, C);
-_DEFPIN_ARM(4, 15, C);
+_FL_DEFPIN(10, 0, A);	// PA0 - PA7
+_FL_DEFPIN(11, 1, A);
+_FL_DEFPIN(12, 2, A);
+_FL_DEFPIN(13, 3, A);
+_FL_DEFPIN(14, 4, A);
+_FL_DEFPIN(15, 5, A);
+_FL_DEFPIN(16, 6, A);
+_FL_DEFPIN(17, 7, A);
+_FL_DEFPIN(29, 8, A);	// PA8 - PA15
+_FL_DEFPIN(30, 9, A);
+_FL_DEFPIN(31, 10, A);
+_FL_DEFPIN(32, 11, A);
+_FL_DEFPIN(33, 12, A);
+_FL_DEFPIN(34, 13, A);
+_FL_DEFPIN(37, 14, A);
+_FL_DEFPIN(38, 15, A);
+
+_FL_DEFPIN(18, 0, B);	// PB0 - PB11
+_FL_DEFPIN(19, 1, B);
+_FL_DEFPIN(20, 2, B);
+_FL_DEFPIN(39, 3, B);
+_FL_DEFPIN(40, 4, B);
+_FL_DEFPIN(41, 5, B);
+_FL_DEFPIN(42, 6, B);
+_FL_DEFPIN(43, 7, B);
+_FL_DEFPIN(45, 8, B);
+_FL_DEFPIN(46, 9, B);
+_FL_DEFPIN(21, 10, B);
+_FL_DEFPIN(22, 11, B);
+
+_FL_DEFPIN(2, 13, C);	// PC13 - PC15
+_FL_DEFPIN(3, 14, C);
+_FL_DEFPIN(4, 15, C);
 
 #define SPI_DATA BOARD_SPI1_MOSI_PIN
 #define SPI_CLOCK BOARD_SPI1_SCK_PIN
diff --git a/platforms/avr/fastpin_avr.h b/platforms/avr/fastpin_avr.h
index 4e25cf8d..956e00a9 100644
--- a/platforms/avr/fastpin_avr.h
+++ b/platforms/avr/fastpin_avr.h
@@ -48,11 +48,54 @@ public:
 typedef volatile uint8_t & reg8_t;
 #define _R(T) struct __gen_struct_ ## T
 #define _RD8(T) struct __gen_struct_ ## T { static inline reg8_t r() { return T; }};
-#define _IO(L) _RD8(DDR ## L); _RD8(PORT ## L); _RD8(PIN ## L);
-#define _DEFPIN_AVR(_PIN, MASK, L) template<> class FastPin<_PIN> : public _AVRPIN<_PIN, MASK, _R(PORT ## L), _R(DDR ## L), _R(PIN ## L)> {};
+#define _FL_IO(L,C) _RD8(DDR ## L); _RD8(PORT ## L); _RD8(PIN ## L); _FL_DEFINE_PORT3(L, C, _R(PORT ## L));
+#define _FL_DEFPIN(_PIN, BIT, L) template<> class FastPin<_PIN> : public _AVRPIN<_PIN, 1<<BIT, _R(PORT ## L), _R(DDR ## L), _R(PIN ## L)> {};
+
+// Pre-do all the port definitions
+#ifdef PORTA
+  _FL_IO(A,0)
+#endif
+#ifdef PORTB
+  _FL_IO(B,1)
+#endif
+#ifdef PORTC
+  _FL_IO(C,2)
+#endif
+#ifdef PORTD
+  _FL_IO(D,3)
+#endif
+#ifdef PORTE
+  _FL_IO(E,4)
+#endif
+#ifdef PORTF
+  _FL_IO(F,5)
+#endif
+#ifdef PORTG
+  _FL_IO(G,6)
+#endif
+#ifdef PORTH
+  _FL_IO(H,7)
+#endif
+#ifdef PORTI
+  _FL_IO(I,8)
+#endif
+#ifdef PORTJ
+  _FL_IO(J,9)
+#endif
+#ifdef PORTK
+  _FL_IO(K,10)
+#endif
+#ifdef PORTL
+  _FL_IO(L,11)
+#endif
+#ifdef PORTM
+  _FL_IO(M,12)
+#endif
+#ifdef PORTN
+  _FL_IO(N,13)
+#endif
 
 #if defined(__AVR_ATtiny85__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny25__)
-_IO(B);
 
 #if defined(__AVR_ATtiny25__)
 #pragma message "ATtiny25 has very limited storage. This library could use up to more than 100% of its flash size"
@@ -60,60 +103,55 @@ _IO(B);
 
 #define MAX_PIN 5
 
-_DEFPIN_AVR(0, 0x01, B); _DEFPIN_AVR(1, 0x02, B); _DEFPIN_AVR(2, 0x04, B); _DEFPIN_AVR(3, 0x08, B);
-_DEFPIN_AVR(4, 0x10, B); _DEFPIN_AVR(5, 0x20, B);
+_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B); _FL_DEFPIN(3, 3, B);
+_FL_DEFPIN(4, 4, B); _FL_DEFPIN(5, 5, B);
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 
 #elif defined(__AVR_ATtiny841__) || defined(__AVR_ATtiny441__)
 #define MAX_PIN 11
-_IO(A); _IO(B);
 
-_DEFPIN_AVR(0, 0x01, B); _DEFPIN_AVR(1, 0x02, B); _DEFPIN_AVR(2, 0x04, B);
-_DEFPIN_AVR(3, 0x80, A); _DEFPIN_AVR(4, 0x40, A); _DEFPIN_AVR(5, 0x20, A);
-_DEFPIN_AVR(6, 0x10, A); _DEFPIN_AVR(7, 0x08, A); _DEFPIN_AVR(8, 0x04, A);
-_DEFPIN_AVR(9, 0x02, A); _DEFPIN_AVR(10, 0x01, A); _DEFPIN_AVR(11, 0x08, B);
+_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B);
+_FL_DEFPIN(3, 7, A); _FL_DEFPIN(4, 6, A); _FL_DEFPIN(5, 5, A);
+_FL_DEFPIN(6, 4, A); _FL_DEFPIN(7, 3, A); _FL_DEFPIN(8, 2, A);
+_FL_DEFPIN(9, 1, A); _FL_DEFPIN(10, 0, A); _FL_DEFPIN(11, 3, B);
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 
 #elif defined(ARDUINO_AVR_DIGISPARK) // digispark pin layout
 #define MAX_PIN 5
 #define HAS_HARDWARE_PIN_SUPPORT 1
-_IO(A); _IO(B);
 
-_DEFPIN_AVR(0, 0x01, B); _DEFPIN_AVR(1, 0x02, B); _DEFPIN_AVR(2, 0x04, B);
-_DEFPIN_AVR(3, 0x80, A); _DEFPIN_AVR(4, 0x40, A); _DEFPIN_AVR(5, 0x20, A);
+_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B);
+_FL_DEFPIN(3, 7, A); _FL_DEFPIN(4, 6, A); _FL_DEFPIN(5, 5, A);
 
-#elif defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) 
-_IO(A); _IO(B);
+#elif defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
 
 #define MAX_PIN 10
 
-_DEFPIN_AVR(0, 0x01, A); _DEFPIN_AVR(1, 0x02, A); _DEFPIN_AVR(2, 0x04, A); _DEFPIN_AVR(3, 0x08, A);
-_DEFPIN_AVR(4, 0x10, A); _DEFPIN_AVR(5, 0x20, A); _DEFPIN_AVR(6, 0x40, A); _DEFPIN_AVR(7, 0x80, A);
-_DEFPIN_AVR(8, 0x04, B); _DEFPIN_AVR(9, 0x02, B); _DEFPIN_AVR(10, 0x01, B);
+_FL_DEFPIN(0, 0, A); _FL_DEFPIN(1, 1, A); _FL_DEFPIN(2, 2, A); _FL_DEFPIN(3, 3, A);
+_FL_DEFPIN(4, 4, A); _FL_DEFPIN(5, 5, A); _FL_DEFPIN(6, 6, A); _FL_DEFPIN(7, 7, A);
+_FL_DEFPIN(8, 2, B); _FL_DEFPIN(9, 1, B); _FL_DEFPIN(10, 0, B);
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 
 #elif defined(ARDUINO_AVR_DIGISPARKPRO)
 
-_IO(A); _IO(B);
 #define MAX_PIN 12
 
-_DEFPIN_AVR(0, 0x01, B); _DEFPIN_AVR(1, 0x02, B); _DEFPIN_AVR(2, 0x04, B); _DEFPIN_AVR(3, 0x20, B);
-_DEFPIN_AVR(4, 0x08, B); _DEFPIN_AVR(5, 0x80, A); _DEFPIN_AVR(6, 0x01, A); _DEFPIN_AVR(7, 0x02, A);
-_DEFPIN_AVR(8, 0x04, A); _DEFPIN_AVR(9, 0x08, A); _DEFPIN_AVR(10, 0x10, A); _DEFPIN_AVR(11, 0x20, A);
-_DEFPIN_AVR(12, 0x40, A);
+_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B); _FL_DEFPIN(3, 5, B);
+_FL_DEFPIN(4, 3, B); _FL_DEFPIN(5, 7, A); _FL_DEFPIN(6, 0, A); _FL_DEFPIN(7, 1, A);
+_FL_DEFPIN(8, 2, A); _FL_DEFPIN(9, 3, A); _FL_DEFPIN(10, 4, A); _FL_DEFPIN(11, 5, A);
+_FL_DEFPIN(12, 6, A);
 
 #elif defined(__AVR_ATtiny167__) || defined(__AVR_ATtiny87__)
-_IO(A); _IO(B);
 
 #define MAX_PIN 15
 
-_DEFPIN_AVR(0, 0x01, A);  _DEFPIN_AVR(1, 0x02, A);   _DEFPIN_AVR(2, 0x04, A);  _DEFPIN_AVR(3, 0x08, A);
-_DEFPIN_AVR(4, 0x10, A);  _DEFPIN_AVR(5, 0x20, A);   _DEFPIN_AVR(6, 0x40, A);  _DEFPIN_AVR(7, 0x80, A);
-_DEFPIN_AVR(8, 0x01, B);  _DEFPIN_AVR(9, 0x02, B);   _DEFPIN_AVR(10, 0x04, B); _DEFPIN_AVR(11, 0x08, B);
-_DEFPIN_AVR(12, 0x10, B); _DEFPIN_AVR(13, 0x20, B); _DEFPIN_AVR(14, 0x40, B); _DEFPIN_AVR(15, 0x80, B);
+_FL_DEFPIN(0, 0, A);  _FL_DEFPIN(1, 1, A);   _FL_DEFPIN(2, 2, A);  _FL_DEFPIN(3, 3, A);
+_FL_DEFPIN(4, 4, A);  _FL_DEFPIN(5, 5, A);   _FL_DEFPIN(6, 6, A);  _FL_DEFPIN(7, 7, A);
+_FL_DEFPIN(8, 0, B);  _FL_DEFPIN(9, 1, B);   _FL_DEFPIN(10, 2, B); _FL_DEFPIN(11, 3, B);
+_FL_DEFPIN(12, 4, B); _FL_DEFPIN(13, 5, B); _FL_DEFPIN(14, 6, B); _FL_DEFPIN(15, 7, B);
 
 #define SPI_DATA 4
 #define SPI_CLOCK 5
@@ -122,17 +160,15 @@ _DEFPIN_AVR(12, 0x10, B); _DEFPIN_AVR(13, 0x20, B); _DEFPIN_AVR(14, 0x40, B); _D
 #define HAS_HARDWARE_PIN_SUPPORT 1
 #elif defined(ARDUINO_HOODLOADER2) && (defined(__AVR_ATmega32U2__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega8U2__)) || defined(__AVR_AT90USB82__) || defined(__AVR_AT90USB162__)
 
-_IO(D); _IO(B); _IO(C);
-
 #define MAX_PIN 20
 
-_DEFPIN_AVR( 0, 0x01, B); _DEFPIN_AVR( 1, 0x02, B); _DEFPIN_AVR( 2, 0x04, B); _DEFPIN_AVR( 3, 0x08, B);
-_DEFPIN_AVR( 4, 0x10, B); _DEFPIN_AVR( 5, 0x20, B); _DEFPIN_AVR( 6, 0x40, B); _DEFPIN_AVR( 7, 0x80, B);
+_FL_DEFPIN( 0, 0, B); _FL_DEFPIN( 1, 1, B); _FL_DEFPIN( 2, 2, B); _FL_DEFPIN( 3, 3, B);
+_FL_DEFPIN( 4, 4, B); _FL_DEFPIN( 5, 5, B); _FL_DEFPIN( 6, 6, B); _FL_DEFPIN( 7, 7, B);
 
-_DEFPIN_AVR( 8, 0x80, C); _DEFPIN_AVR( 9, 0x40, C); _DEFPIN_AVR( 10, 0x20,C); _DEFPIN_AVR( 11, 0x10, C);
-_DEFPIN_AVR( 12, 0x04, C); _DEFPIN_AVR( 13, 0x01, D); _DEFPIN_AVR( 14, 0x02, D); _DEFPIN_AVR(15, 0x04, D);
-_DEFPIN_AVR( 16, 0x08, D); _DEFPIN_AVR( 17, 0x10, D); _DEFPIN_AVR( 18, 0x20, D); _DEFPIN_AVR( 19, 0x40, D);
-_DEFPIN_AVR( 20, 0x80, D);
+_FL_DEFPIN( 8, 7, C); _FL_DEFPIN( 9, 6, C); _FL_DEFPIN( 10, 5,C); _FL_DEFPIN( 11, 4, C);
+_FL_DEFPIN( 12, 2, C); _FL_DEFPIN( 13, 0, D); _FL_DEFPIN( 14, 1, D); _FL_DEFPIN(15, 2, D);
+_FL_DEFPIN( 16, 3, D); _FL_DEFPIN( 17, 4, D); _FL_DEFPIN( 18, 5, D); _FL_DEFPIN( 19, 6, D);
+_FL_DEFPIN( 20, 7, D);
 
 #define HAS_HARDWARE_PIN_SUPPORT 1
 // #define SPI_DATA 2
@@ -141,15 +177,12 @@ _DEFPIN_AVR( 20, 0x80, D);
 
 #elif defined(IS_BEAN)
 
-// Accelerated port definitions for arduino avrs
-_IO(D); _IO(B); _IO(C);
-
 #define MAX_PIN 19
-_DEFPIN_AVR( 0, 0x40, D); _DEFPIN_AVR( 1, 0x02, B); _DEFPIN_AVR( 2, 0x04, B); _DEFPIN_AVR( 3, 0x08, B);
-_DEFPIN_AVR( 4, 0x10, B); _DEFPIN_AVR( 5, 0x20, B); _DEFPIN_AVR( 6, 0x01, D); _DEFPIN_AVR( 7, 0x80, D);
-_DEFPIN_AVR( 8, 0x01, B); _DEFPIN_AVR( 9, 0x02, D); _DEFPIN_AVR(10, 0x04, D); _DEFPIN_AVR(11, 0x08, D);
-_DEFPIN_AVR(12, 0x10, D); _DEFPIN_AVR(13, 0x20, D); _DEFPIN_AVR(14, 0x01, C); _DEFPIN_AVR(15, 0x02, C);
-_DEFPIN_AVR(16, 0x04, C); _DEFPIN_AVR(17, 0x08, C); _DEFPIN_AVR(18, 0x10, C); _DEFPIN_AVR(19, 0x20, C);
+_FL_DEFPIN( 0, 6, D); _FL_DEFPIN( 1, 1, B); _FL_DEFPIN( 2, 2, B); _FL_DEFPIN( 3, 3, B);
+_FL_DEFPIN( 4, 4, B); _FL_DEFPIN( 5, 5, B); _FL_DEFPIN( 6, 0, D); _FL_DEFPIN( 7, 7, D);
+_FL_DEFPIN( 8, 0, B); _FL_DEFPIN( 9, 1, D); _FL_DEFPIN(10, 2, D); _FL_DEFPIN(11, 3, D);
+_FL_DEFPIN(12, 4, D); _FL_DEFPIN(13, 5, D); _FL_DEFPIN(14, 0, C); _FL_DEFPIN(15, 1, C);
+_FL_DEFPIN(16, 2, C); _FL_DEFPIN(17, 3, C); _FL_DEFPIN(18, 4, C); _FL_DEFPIN(19, 5, C);
 
 #define SPI_DATA 3
 #define SPI_CLOCK 5
@@ -163,15 +196,13 @@ _DEFPIN_AVR(16, 0x04, C); _DEFPIN_AVR(17, 0x08, C); _DEFPIN_AVR(18, 0x10, C); _D
 #endif
 
 #elif defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328PB__) || defined(__AVR_ATmega328__) || defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega8__)
-// Accelerated port definitions for arduino avrs
-_IO(D); _IO(B); _IO(C);
 
 #define MAX_PIN 19
-_DEFPIN_AVR( 0, 0x01, D); _DEFPIN_AVR( 1, 0x02, D); _DEFPIN_AVR( 2, 0x04, D); _DEFPIN_AVR( 3, 0x08, D);
-_DEFPIN_AVR( 4, 0x10, D); _DEFPIN_AVR( 5, 0x20, D); _DEFPIN_AVR( 6, 0x40, D); _DEFPIN_AVR( 7, 0x80, D);
-_DEFPIN_AVR( 8, 0x01, B); _DEFPIN_AVR( 9, 0x02, B); _DEFPIN_AVR(10, 0x04, B); _DEFPIN_AVR(11, 0x08, B);
-_DEFPIN_AVR(12, 0x10, B); _DEFPIN_AVR(13, 0x20, B); _DEFPIN_AVR(14, 0x01, C); _DEFPIN_AVR(15, 0x02, C);
-_DEFPIN_AVR(16, 0x04, C); _DEFPIN_AVR(17, 0x08, C); _DEFPIN_AVR(18, 0x10, C); _DEFPIN_AVR(19, 0x20, C);
+_FL_DEFPIN( 0, 0, D); _FL_DEFPIN( 1, 1, D); _FL_DEFPIN( 2, 2, D); _FL_DEFPIN( 3, 3, D);
+_FL_DEFPIN( 4, 4, D); _FL_DEFPIN( 5, 5, D); _FL_DEFPIN( 6, 6, D); _FL_DEFPIN( 7, 7, D);
+_FL_DEFPIN( 8, 0, B); _FL_DEFPIN( 9, 1, B); _FL_DEFPIN(10, 2, B); _FL_DEFPIN(11, 3, B);
+_FL_DEFPIN(12, 4, B); _FL_DEFPIN(13, 5, B); _FL_DEFPIN(14, 0, C); _FL_DEFPIN(15, 1, C);
+_FL_DEFPIN(16, 2, C); _FL_DEFPIN(17, 3, C); _FL_DEFPIN(18, 4, C); _FL_DEFPIN(19, 5, C);
 
 #define SPI_DATA 11
 #define SPI_CLOCK 13
@@ -184,19 +215,17 @@ _DEFPIN_AVR(16, 0x04, C); _DEFPIN_AVR(17, 0x08, C); _DEFPIN_AVR(18, 0x10, C); _D
 #define SPI_UART0_CLOCK 4
 #endif
 
-#elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__)
-
-_IO(A); _IO(B); _IO(C); _IO(D);
+#elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__) || defined(__AVR_ATmega32__) || defined(__AVR_ATmega16__)
 
 #define MAX_PIN 31
-_DEFPIN_AVR(0, 1<<0, B); _DEFPIN_AVR(1, 1<<1, B); _DEFPIN_AVR(2, 1<<2, B); _DEFPIN_AVR(3, 1<<3, B);
-_DEFPIN_AVR(4, 1<<4, B); _DEFPIN_AVR(5, 1<<5, B); _DEFPIN_AVR(6, 1<<6, B); _DEFPIN_AVR(7, 1<<7, B);
-_DEFPIN_AVR(8, 1<<0, D); _DEFPIN_AVR(9, 1<<1, D); _DEFPIN_AVR(10, 1<<2, D); _DEFPIN_AVR(11, 1<<3, D);
-_DEFPIN_AVR(12, 1<<4, D); _DEFPIN_AVR(13, 1<<5, D); _DEFPIN_AVR(14, 1<<6, D); _DEFPIN_AVR(15, 1<<7, D);
-_DEFPIN_AVR(16, 1<<0, C); _DEFPIN_AVR(17, 1<<1, C); _DEFPIN_AVR(18, 1<<2, C); _DEFPIN_AVR(19, 1<<3, C);
-_DEFPIN_AVR(20, 1<<4, C); _DEFPIN_AVR(21, 1<<5, C); _DEFPIN_AVR(22, 1<<6, C); _DEFPIN_AVR(23, 1<<7, C);
-_DEFPIN_AVR(24, 1<<0, A); _DEFPIN_AVR(25, 1<<1, A); _DEFPIN_AVR(26, 1<<2, A); _DEFPIN_AVR(27, 1<<3, A);
-_DEFPIN_AVR(28, 1<<4, A); _DEFPIN_AVR(29, 1<<5, A); _DEFPIN_AVR(30, 1<<6, A); _DEFPIN_AVR(31, 1<<7, A);
+_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B); _FL_DEFPIN(3, 3, B);
+_FL_DEFPIN(4, 4, B); _FL_DEFPIN(5, 5, B); _FL_DEFPIN(6, 6, B); _FL_DEFPIN(7, 7, B);
+_FL_DEFPIN(8, 0, D); _FL_DEFPIN(9, 1, D); _FL_DEFPIN(10, 2, D); _FL_DEFPIN(11, 3, D);
+_FL_DEFPIN(12, 4, D); _FL_DEFPIN(13, 5, D); _FL_DEFPIN(14, 6, D); _FL_DEFPIN(15, 7, D);
+_FL_DEFPIN(16, 0, C); _FL_DEFPIN(17, 1, C); _FL_DEFPIN(18, 2, C); _FL_DEFPIN(19, 3, C);
+_FL_DEFPIN(20, 4, C); _FL_DEFPIN(21, 5, C); _FL_DEFPIN(22, 6, C); _FL_DEFPIN(23, 7, C);
+_FL_DEFPIN(24, 0, A); _FL_DEFPIN(25, 1, A); _FL_DEFPIN(26, 2, A); _FL_DEFPIN(27, 3, A);
+_FL_DEFPIN(28, 4, A); _FL_DEFPIN(29, 5, A); _FL_DEFPIN(30, 6, A); _FL_DEFPIN(31, 7, A);
 
 #define SPI_DATA 5
 #define SPI_CLOCK 7
@@ -207,17 +236,14 @@ _DEFPIN_AVR(28, 1<<4, A); _DEFPIN_AVR(29, 1<<5, A); _DEFPIN_AVR(30, 1<<6, A); _D
 #elif  defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega256RFR2__)
 
 // AKA the Pinoccio
-
-_IO(A); _IO(B); _IO(C); _IO(D); _IO(E); _IO(F);
-
-_DEFPIN_AVR( 0, 1<<0, E); _DEFPIN_AVR( 1, 1<<1, E); _DEFPIN_AVR( 2, 1<<7, B); _DEFPIN_AVR( 3, 1<<3, E);
-_DEFPIN_AVR( 4, 1<<4, E); _DEFPIN_AVR( 5, 1<<5, E); _DEFPIN_AVR( 6, 1<<2, E); _DEFPIN_AVR( 7, 1<<6, E);
-_DEFPIN_AVR( 8, 1<<5, D); _DEFPIN_AVR( 9, 1<<0, B); _DEFPIN_AVR(10, 1<<2, B); _DEFPIN_AVR(11, 1<<3, B);
-_DEFPIN_AVR(12, 1<<1, B); _DEFPIN_AVR(13, 1<<2, D); _DEFPIN_AVR(14, 1<<3, D); _DEFPIN_AVR(15, 1<<0, D);
-_DEFPIN_AVR(16, 1<<1, D); _DEFPIN_AVR(17, 1<<4, D); _DEFPIN_AVR(18, 1<<7, E); _DEFPIN_AVR(19, 1<<6, D);
-_DEFPIN_AVR(20, 1<<7, D); _DEFPIN_AVR(21, 1<<4, B); _DEFPIN_AVR(22, 1<<5, B); _DEFPIN_AVR(23, 1<<6, B);
-_DEFPIN_AVR(24, 1<<0, F); _DEFPIN_AVR(25, 1<<1, F); _DEFPIN_AVR(26, 1<<2, F); _DEFPIN_AVR(27, 1<<3, F);
-_DEFPIN_AVR(28, 1<<4, F); _DEFPIN_AVR(29, 1<<5, F); _DEFPIN_AVR(30, 1<<6, F); _DEFPIN_AVR(31, 1<<7, F);
+_FL_DEFPIN( 0, 0, E); _FL_DEFPIN( 1, 1, E); _FL_DEFPIN( 2, 7, B); _FL_DEFPIN( 3, 3, E);
+_FL_DEFPIN( 4, 4, E); _FL_DEFPIN( 5, 5, E); _FL_DEFPIN( 6, 2, E); _FL_DEFPIN( 7, 6, E);
+_FL_DEFPIN( 8, 5, D); _FL_DEFPIN( 9, 0, B); _FL_DEFPIN(10, 2, B); _FL_DEFPIN(11, 3, B);
+_FL_DEFPIN(12, 1, B); _FL_DEFPIN(13, 2, D); _FL_DEFPIN(14, 3, D); _FL_DEFPIN(15, 0, D);
+_FL_DEFPIN(16, 1, D); _FL_DEFPIN(17, 4, D); _FL_DEFPIN(18, 7, E); _FL_DEFPIN(19, 6, D);
+_FL_DEFPIN(20, 7, D); _FL_DEFPIN(21, 4, B); _FL_DEFPIN(22, 5, B); _FL_DEFPIN(23, 6, B);
+_FL_DEFPIN(24, 0, F); _FL_DEFPIN(25, 1, F); _FL_DEFPIN(26, 2, F); _FL_DEFPIN(27, 3, F);
+_FL_DEFPIN(28, 4, F); _FL_DEFPIN(29, 5, F); _FL_DEFPIN(30, 6, F); _FL_DEFPIN(31, 7, F);
 
 #define SPI_DATA 10
 #define SPI_CLOCK 12
@@ -228,28 +254,25 @@ _DEFPIN_AVR(28, 1<<4, F); _DEFPIN_AVR(29, 1<<5, F); _DEFPIN_AVR(30, 1<<6, F); _D
 
 #elif defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
 // megas
-
-_IO(A); _IO(B); _IO(C); _IO(D); _IO(E); _IO(F); _IO(G); _IO(H); _IO(J); _IO(K); _IO(L);
-
 #define MAX_PIN 69
-_DEFPIN_AVR(0, 1, E); _DEFPIN_AVR(1, 2, E); _DEFPIN_AVR(2, 16, E); _DEFPIN_AVR(3, 32, E);
-_DEFPIN_AVR(4, 32, G); _DEFPIN_AVR(5, 8, E); _DEFPIN_AVR(6, 8, H); _DEFPIN_AVR(7, 16, H);
-_DEFPIN_AVR(8, 32, H); _DEFPIN_AVR(9, 64, H); _DEFPIN_AVR(10, 16, B); _DEFPIN_AVR(11, 32, B);
-_DEFPIN_AVR(12, 64, B); _DEFPIN_AVR(13, 128, B); _DEFPIN_AVR(14, 2, J); _DEFPIN_AVR(15, 1, J);
-_DEFPIN_AVR(16, 2, H); _DEFPIN_AVR(17, 1, H); _DEFPIN_AVR(18, 8, D); _DEFPIN_AVR(19, 4, D);
-_DEFPIN_AVR(20, 2, D); _DEFPIN_AVR(21, 1, D); _DEFPIN_AVR(22, 1, A); _DEFPIN_AVR(23, 2, A);
-_DEFPIN_AVR(24, 4, A); _DEFPIN_AVR(25, 8, A); _DEFPIN_AVR(26, 16, A); _DEFPIN_AVR(27, 32, A);
-_DEFPIN_AVR(28, 64, A); _DEFPIN_AVR(29, 128, A); _DEFPIN_AVR(30, 128, C); _DEFPIN_AVR(31, 64, C);
-_DEFPIN_AVR(32, 32, C); _DEFPIN_AVR(33, 16, C); _DEFPIN_AVR(34, 8, C); _DEFPIN_AVR(35, 4, C);
-_DEFPIN_AVR(36, 2, C); _DEFPIN_AVR(37, 1, C); _DEFPIN_AVR(38, 128, D); _DEFPIN_AVR(39, 4, G);
-_DEFPIN_AVR(40, 2, G); _DEFPIN_AVR(41, 1, G); _DEFPIN_AVR(42, 128, L); _DEFPIN_AVR(43, 64, L);
-_DEFPIN_AVR(44, 32, L); _DEFPIN_AVR(45, 16, L); _DEFPIN_AVR(46, 8, L); _DEFPIN_AVR(47, 4, L);
-_DEFPIN_AVR(48, 2, L); _DEFPIN_AVR(49, 1, L); _DEFPIN_AVR(50, 8, B); _DEFPIN_AVR(51, 4, B);
-_DEFPIN_AVR(52, 2, B); _DEFPIN_AVR(53, 1, B); _DEFPIN_AVR(54, 1, F); _DEFPIN_AVR(55, 2, F);
-_DEFPIN_AVR(56, 4, F); _DEFPIN_AVR(57, 8, F); _DEFPIN_AVR(58, 16, F); _DEFPIN_AVR(59, 32, F);
-_DEFPIN_AVR(60, 64, F); _DEFPIN_AVR(61, 128, F); _DEFPIN_AVR(62, 1, K); _DEFPIN_AVR(63, 2, K);
-_DEFPIN_AVR(64, 4, K); _DEFPIN_AVR(65, 8, K); _DEFPIN_AVR(66, 16, K); _DEFPIN_AVR(67, 32, K);
-_DEFPIN_AVR(68, 64, K); _DEFPIN_AVR(69, 128, K);
+_FL_DEFPIN(0, 0, E); _FL_DEFPIN(1, 1, E); _FL_DEFPIN(2, 4, E); _FL_DEFPIN(3, 5, E);
+_FL_DEFPIN(4, 5, G); _FL_DEFPIN(5, 3, E); _FL_DEFPIN(6, 3, H); _FL_DEFPIN(7, 4, H);
+_FL_DEFPIN(8, 5, H); _FL_DEFPIN(9, 6, H); _FL_DEFPIN(10, 4, B); _FL_DEFPIN(11, 5, B);
+_FL_DEFPIN(12, 6, B); _FL_DEFPIN(13, 7, B); _FL_DEFPIN(14, 1, J); _FL_DEFPIN(15, 0, J);
+_FL_DEFPIN(16, 1, H); _FL_DEFPIN(17, 0, H); _FL_DEFPIN(18, 3, D); _FL_DEFPIN(19, 2, D);
+_FL_DEFPIN(20, 1, D); _FL_DEFPIN(21, 0, D); _FL_DEFPIN(22, 0, A); _FL_DEFPIN(23, 1, A);
+_FL_DEFPIN(24, 2, A); _FL_DEFPIN(25, 3, A); _FL_DEFPIN(26, 4, A); _FL_DEFPIN(27, 5, A);
+_FL_DEFPIN(28, 6, A); _FL_DEFPIN(29, 7, A); _FL_DEFPIN(30, 7, C); _FL_DEFPIN(31, 6, C);
+_FL_DEFPIN(32, 5, C); _FL_DEFPIN(33, 4, C); _FL_DEFPIN(34, 3, C); _FL_DEFPIN(35, 2, C);
+_FL_DEFPIN(36, 1, C); _FL_DEFPIN(37, 0, C); _FL_DEFPIN(38, 7, D); _FL_DEFPIN(39, 2, G);
+_FL_DEFPIN(40, 1, G); _FL_DEFPIN(41, 0, G); _FL_DEFPIN(42, 7, L); _FL_DEFPIN(43, 6, L);
+_FL_DEFPIN(44, 5, L); _FL_DEFPIN(45, 4, L); _FL_DEFPIN(46, 3, L); _FL_DEFPIN(47, 2, L);
+_FL_DEFPIN(48, 1, L); _FL_DEFPIN(49, 0, L); _FL_DEFPIN(50, 3, B); _FL_DEFPIN(51, 2, B);
+_FL_DEFPIN(52, 1, B); _FL_DEFPIN(53, 0, B); _FL_DEFPIN(54, 0, F); _FL_DEFPIN(55, 1, F);
+_FL_DEFPIN(56, 2, F); _FL_DEFPIN(57, 3, F); _FL_DEFPIN(58, 4, F); _FL_DEFPIN(59, 5, F);
+_FL_DEFPIN(60, 6, F); _FL_DEFPIN(61, 7, F); _FL_DEFPIN(62, 0, K); _FL_DEFPIN(63, 1, K);
+_FL_DEFPIN(64, 2, K); _FL_DEFPIN(65, 3, K); _FL_DEFPIN(66, 4, K); _FL_DEFPIN(67, 5, K);
+_FL_DEFPIN(68, 6, K); _FL_DEFPIN(69, 7, K);
 
 #define SPI_DATA 51
 #define SPI_CLOCK 52
@@ -261,15 +284,13 @@ _DEFPIN_AVR(68, 64, K); _DEFPIN_AVR(69, 128, K);
 #elif defined(__AVR_ATmega32U4__) && defined(CORE_TEENSY)
 
 // teensy defs
-_IO(B); _IO(C); _IO(D); _IO(E); _IO(F);
-
 #define MAX_PIN 23
-_DEFPIN_AVR(0, 1, B); _DEFPIN_AVR(1, 2, B); _DEFPIN_AVR(2, 4, B); _DEFPIN_AVR(3, 8, B);
-_DEFPIN_AVR(4, 128, B); _DEFPIN_AVR(5, 1, D); _DEFPIN_AVR(6, 2, D); _DEFPIN_AVR(7, 4, D);
-_DEFPIN_AVR(8, 8, D); _DEFPIN_AVR(9, 64, C); _DEFPIN_AVR(10, 128, C); _DEFPIN_AVR(11, 64, D);
-_DEFPIN_AVR(12, 128, D); _DEFPIN_AVR(13, 16, B); _DEFPIN_AVR(14, 32, B); _DEFPIN_AVR(15, 64, B);
-_DEFPIN_AVR(16, 128, F); _DEFPIN_AVR(17, 64, F); _DEFPIN_AVR(18, 32, F); _DEFPIN_AVR(19, 16, F);
-_DEFPIN_AVR(20, 2, F); _DEFPIN_AVR(21, 1, F); _DEFPIN_AVR(22, 16, D); _DEFPIN_AVR(23, 32, D);
+_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B); _FL_DEFPIN(3, 3, B);
+_FL_DEFPIN(4, 7, B); _FL_DEFPIN(5, 0, D); _FL_DEFPIN(6, 1, D); _FL_DEFPIN(7, 2, D);
+_FL_DEFPIN(8, 3, D); _FL_DEFPIN(9, 6, C); _FL_DEFPIN(10, 7, C); _FL_DEFPIN(11, 6, D);
+_FL_DEFPIN(12, 7, D); _FL_DEFPIN(13, 4, B); _FL_DEFPIN(14, 5, B); _FL_DEFPIN(15, 6, B);
+_FL_DEFPIN(16, 7, F); _FL_DEFPIN(17, 6, F); _FL_DEFPIN(18, 5, F); _FL_DEFPIN(19, 4, F);
+_FL_DEFPIN(20, 1, F); _FL_DEFPIN(21, 0, F); _FL_DEFPIN(22, 4, D); _FL_DEFPIN(23, 5, D);
 
 #define SPI_DATA 2
 #define SPI_CLOCK 1
@@ -283,22 +304,19 @@ _DEFPIN_AVR(20, 2, F); _DEFPIN_AVR(21, 1, F); _DEFPIN_AVR(22, 16, D); _DEFPIN_AV
 
 #elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
 // teensy++ 2 defs
-
-_IO(A); _IO(B); _IO(C); _IO(D); _IO(E); _IO(F);
-
 #define MAX_PIN 45
-_DEFPIN_AVR(0, 1, D); _DEFPIN_AVR(1, 2, D); _DEFPIN_AVR(2, 4, D); _DEFPIN_AVR(3, 8, D);
-_DEFPIN_AVR(4, 16, D); _DEFPIN_AVR(5, 32, D); _DEFPIN_AVR(6, 64, D); _DEFPIN_AVR(7, 128, D);
-_DEFPIN_AVR(8, 1, E); _DEFPIN_AVR(9, 2, E); _DEFPIN_AVR(10, 1, C); _DEFPIN_AVR(11, 2, C);
-_DEFPIN_AVR(12, 4, C); _DEFPIN_AVR(13, 8, C); _DEFPIN_AVR(14, 16, C); _DEFPIN_AVR(15, 32, C);
-_DEFPIN_AVR(16, 64, C); _DEFPIN_AVR(17, 128, C); _DEFPIN_AVR(18, 64, E); _DEFPIN_AVR(19, 128, E);
-_DEFPIN_AVR(20, 1, B); _DEFPIN_AVR(21, 2, B); _DEFPIN_AVR(22, 4, B); _DEFPIN_AVR(23, 8, B);
-_DEFPIN_AVR(24, 16, B); _DEFPIN_AVR(25, 32, B); _DEFPIN_AVR(26, 64, B); _DEFPIN_AVR(27, 128, B);
-_DEFPIN_AVR(28, 1, A); _DEFPIN_AVR(29, 2, A); _DEFPIN_AVR(30, 4, A); _DEFPIN_AVR(31, 8, A);
-_DEFPIN_AVR(32, 16, A); _DEFPIN_AVR(33, 32, A); _DEFPIN_AVR(34, 64, A); _DEFPIN_AVR(35, 128, A);
-_DEFPIN_AVR(36, 16, E); _DEFPIN_AVR(37, 32, E); _DEFPIN_AVR(38, 1, F); _DEFPIN_AVR(39, 2, F);
-_DEFPIN_AVR(40, 4, F); _DEFPIN_AVR(41, 8, F); _DEFPIN_AVR(42, 16, F); _DEFPIN_AVR(43, 32, F);
-_DEFPIN_AVR(44, 64, F); _DEFPIN_AVR(45, 128, F);
+_FL_DEFPIN(0, 0, D); _FL_DEFPIN(1, 1, D); _FL_DEFPIN(2, 2, D); _FL_DEFPIN(3, 3, D);
+_FL_DEFPIN(4, 4, D); _FL_DEFPIN(5, 5, D); _FL_DEFPIN(6, 6, D); _FL_DEFPIN(7, 7, D);
+_FL_DEFPIN(8, 0, E); _FL_DEFPIN(9, 1, E); _FL_DEFPIN(10, 0, C); _FL_DEFPIN(11, 1, C);
+_FL_DEFPIN(12, 2, C); _FL_DEFPIN(13, 3, C); _FL_DEFPIN(14, 4, C); _FL_DEFPIN(15, 5, C);
+_FL_DEFPIN(16, 6, C); _FL_DEFPIN(17, 7, C); _FL_DEFPIN(18, 6, E); _FL_DEFPIN(19, 7, E);
+_FL_DEFPIN(20, 0, B); _FL_DEFPIN(21, 1, B); _FL_DEFPIN(22, 2, B); _FL_DEFPIN(23, 3, B);
+_FL_DEFPIN(24, 4, B); _FL_DEFPIN(25, 5, B); _FL_DEFPIN(26, 6, B); _FL_DEFPIN(27, 7, B);
+_FL_DEFPIN(28, 0, A); _FL_DEFPIN(29, 1, A); _FL_DEFPIN(30, 2, A); _FL_DEFPIN(31, 3, A);
+_FL_DEFPIN(32, 4, A); _FL_DEFPIN(33, 5, A); _FL_DEFPIN(34, 6, A); _FL_DEFPIN(35, 7, A);
+_FL_DEFPIN(36, 4, E); _FL_DEFPIN(37, 5, E); _FL_DEFPIN(38, 0, F); _FL_DEFPIN(39, 1, F);
+_FL_DEFPIN(40, 2, F); _FL_DEFPIN(41, 3, F); _FL_DEFPIN(42, 4, F); _FL_DEFPIN(43, 5, F);
+_FL_DEFPIN(44, 6, F); _FL_DEFPIN(45, 7, F);
 
 #define SPI_DATA 22
 #define SPI_CLOCK 21
@@ -314,17 +332,15 @@ _DEFPIN_AVR(44, 64, F); _DEFPIN_AVR(45, 128, F);
 #elif defined(__AVR_ATmega32U4__)
 
 // leonard defs
-_IO(B); _IO(C); _IO(D); _IO(E); _IO(F);
-
 #define MAX_PIN 30
-_DEFPIN_AVR(0, 4, D); _DEFPIN_AVR(1, 8, D); _DEFPIN_AVR(2, 2, D); _DEFPIN_AVR(3, 1, D);
-_DEFPIN_AVR(4, 16, D); _DEFPIN_AVR(5, 64, C); _DEFPIN_AVR(6, 128, D); _DEFPIN_AVR(7, 64, E);
-_DEFPIN_AVR(8, 16, B); _DEFPIN_AVR(9, 32, B); _DEFPIN_AVR(10, 64, B); _DEFPIN_AVR(11, 128, B);
-_DEFPIN_AVR(12, 64, D); _DEFPIN_AVR(13, 128, C); _DEFPIN_AVR(14, 8, B); _DEFPIN_AVR(15, 2, B);
-_DEFPIN_AVR(16, 4, B); _DEFPIN_AVR(17, 1, B); _DEFPIN_AVR(18, 128, F); _DEFPIN_AVR(19, 64, F);
-_DEFPIN_AVR(20, 32, F); _DEFPIN_AVR(21, 16, F); _DEFPIN_AVR(22, 2, F); _DEFPIN_AVR(23, 1, F);
-_DEFPIN_AVR(24, 16, D); _DEFPIN_AVR(25, 128, D); _DEFPIN_AVR(26, 16, B); _DEFPIN_AVR(27, 32, B);
-_DEFPIN_AVR(28, 64, B); _DEFPIN_AVR(29, 64, D); _DEFPIN_AVR(30, 32, D);
+_FL_DEFPIN(0, 2, D); _FL_DEFPIN(1, 3, D); _FL_DEFPIN(2, 1, D); _FL_DEFPIN(3, 0, D);
+_FL_DEFPIN(4, 4, D); _FL_DEFPIN(5, 6, C); _FL_DEFPIN(6, 7, D); _FL_DEFPIN(7, 6, E);
+_FL_DEFPIN(8, 4, B); _FL_DEFPIN(9, 5, B); _FL_DEFPIN(10, 6, B); _FL_DEFPIN(11, 7, B);
+_FL_DEFPIN(12, 6, D); _FL_DEFPIN(13, 7, C); _FL_DEFPIN(14, 3, B); _FL_DEFPIN(15, 1, B);
+_FL_DEFPIN(16, 2, B); _FL_DEFPIN(17, 0, B); _FL_DEFPIN(18, 7, F); _FL_DEFPIN(19, 6, F);
+_FL_DEFPIN(20, 5, F); _FL_DEFPIN(21, 4, F); _FL_DEFPIN(22, 1, F); _FL_DEFPIN(23, 0, F);
+_FL_DEFPIN(24, 4, D); _FL_DEFPIN(25, 7, D); _FL_DEFPIN(26, 4, B); _FL_DEFPIN(27, 5, B);
+_FL_DEFPIN(28, 6, B); _FL_DEFPIN(29, 6, D); _FL_DEFPIN(30, 5, D);
 
 #define SPI_DATA 16
 #define SPI_CLOCK 15
diff --git a/platforms/avr/fastspi_avr.h b/platforms/avr/fastspi_avr.h
index fc14d596..d2edc966 100644
--- a/platforms/avr/fastspi_avr.h
+++ b/platforms/avr/fastspi_avr.h
@@ -20,7 +20,7 @@ FASTLED_NAMESPACE_BEGIN
 #define UCPHA1 1
 #endif
 
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class AVRUSART1SPIOutput {
 	Selectable *m_pSelect;
 
@@ -167,7 +167,7 @@ public:
 #endif
 
 #if defined(UBRR0)
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class AVRUSART0SPIOutput {
 	Selectable *m_pSelect;
 
@@ -329,7 +329,7 @@ public:
 //
 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class AVRHardwareSPIOutput {
 	Selectable *m_pSelect;
 	bool mWait;
@@ -506,7 +506,7 @@ public:
 //
 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 
-template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER>
+template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
 class AVRHardwareSPIOutput {
 	Selectable *m_pSelect;
 	bool mWait;
diff --git a/platforms/esp/32/clockless_rmt_esp32.h b/platforms/esp/32/clockless_rmt_esp32.h
index f75fbce9..1496dc19 100644
--- a/platforms/esp/32/clockless_rmt_esp32.h
+++ b/platforms/esp/32/clockless_rmt_esp32.h
@@ -123,8 +123,12 @@ __attribute__ ((always_inline)) inline static uint32_t __clock_cycles() {
 
 // -- Configuration constants
 #define DIVIDER             2 /* 4, 8 still seem to work, but timings become marginal */
+<<<<<<< HEAD
 #define MAX_PULSES         64 /* A channel has a 64 "pulse" buffer */
 #define PULSES_PER_FILL    24 /* One pixel's worth of pulses */
+=======
+#define MAX_PULSES         32 /* A channel has a 64 "pulse" buffer - we use half per pass */
+>>>>>>> upstream/master
 
 // -- Convert ESP32 CPU cycles to RMT device cycles, taking into account the divider
 #define F_CPU_RMT                   (  80000000L)
@@ -503,6 +507,7 @@ protected:
         }
     }
 
+<<<<<<< HEAD
     // -- Fill RMT buffer
     //    Puts one pixel's worth of data into the next 24 slots in the RMT memory
     void IRAM_ATTR fillNext()
@@ -555,6 +560,8 @@ protected:
     }
 
     // NO LONGER USED
+=======
+>>>>>>> upstream/master
     uint8_t IRAM_ATTR getNextByte() __attribute__ ((always_inline))
     {
         uint8_t byte;
@@ -590,7 +597,7 @@ protected:
     //    buffer with pixel data. It also handles the case where the
     //    pixel data is exhausted, so we need to fill the RMT buffer
     //    with zeros to signal that it's done.
-    void IRAM_ATTR fillHalfRMTBuffer()
+    virtual void IRAM_ATTR fillHalfRMTBuffer()
     {
         uint32_t one_val = mOne.val;
         uint32_t zero_val = mZero.val;
@@ -648,10 +655,17 @@ protected:
         }
         
         // -- When we have filled the back half the buffer, reset the position to the first half
+<<<<<<< HEAD
         if (mCurPulse == MAX_PULSES) {
             mRMT_mem_ptr = & (RMTMEM.chan[mRMT_channel].data32[0].val);
             mCurPulse = 0;
         }
+=======
+        if (mCurPulse >= MAX_PULSES*2) {
+            mRMT_mem_ptr = & (RMTMEM.chan[mRMT_channel].data32[0].val);
+            mCurPulse = 0;
+        }            
+>>>>>>> upstream/master
     }
 };
 
diff --git a/platforms/esp/32/fastpin_esp32.h b/platforms/esp/32/fastpin_esp32.h
index fd03d5c8..d54d7fee 100644
--- a/platforms/esp/32/fastpin_esp32.h
+++ b/platforms/esp/32/fastpin_esp32.h
@@ -11,7 +11,7 @@ public:
   inline static void setOutput() { pinMode(PIN, OUTPUT); }
   inline static void setInput() { pinMode(PIN, INPUT); }
 
-  inline static void hi() __attribute__ ((always_inline)) { 
+  inline static void hi() __attribute__ ((always_inline)) {
       if (PIN < 32) GPIO.out_w1ts = MASK;
       else GPIO.out1_w1ts.val = MASK;
   }
@@ -28,9 +28,9 @@ public:
 
   inline static void strobe() __attribute__ ((always_inline)) { toggle(); toggle(); }
 
-  inline static void toggle() __attribute__ ((always_inline)) { 
-      if(PIN < 32) { GPIO.out ^= MASK; } 
-      else { GPIO.out1.val ^=MASK; } 
+  inline static void toggle() __attribute__ ((always_inline)) {
+      if(PIN < 32) { GPIO.out ^= MASK; }
+      else { GPIO.out1.val ^=MASK; }
   }
 
   inline static void hi(register port_ptr_t port) __attribute__ ((always_inline)) { hi(); }
@@ -52,7 +52,7 @@ public:
       else return &GPIO.out1.val;
   }
 
-  inline static port_ptr_t sport() __attribute__ ((always_inline)) { 
+  inline static port_ptr_t sport() __attribute__ ((always_inline)) {
       if (PIN < 32) return &GPIO.out_w1ts;
       else return &GPIO.out1_w1ts.val;
   }
@@ -70,46 +70,45 @@ public:
   }
 };
 
-#define _DEFPIN_ESP32(PIN)  template<> class FastPin<PIN> : public _ESPPIN<PIN, ((uint32_t)1 << PIN)> {};
-#define _DEFPIN_32_33_ESP32(PIN) template<> class FastPin<PIN> : public _ESPPIN<PIN, ((uint32_t)1 << (PIN-32))> {};
+#define _FL_DEFPIN(PIN)  template<> class FastPin<PIN> : public _ESPPIN<PIN, ((PIN<32)?((uint32_t)1 << PIN):((uint32_t)1 << (PIN-32)))> {};
 
-_DEFPIN_ESP32(0);
-_DEFPIN_ESP32(1); // WARNING: Using TX causes flashiness when uploading
-_DEFPIN_ESP32(2); 
-_DEFPIN_ESP32(3); // WARNING: Using RX causes flashiness when uploading
-_DEFPIN_ESP32(4);
-_DEFPIN_ESP32(5);
+_FL_DEFPIN(0);
+_FL_DEFPIN(1); // WARNING: Using TX causes flashiness when uploading
+_FL_DEFPIN(2);
+_FL_DEFPIN(3); // WARNING: Using RX causes flashiness when uploading
+_FL_DEFPIN(4);
+_FL_DEFPIN(5);
 
 // -- These pins are not safe to use:
-// _DEFPIN_ESP32(6,6); _DEFPIN_ESP32(7,7); _DEFPIN_ESP32(8,8); 
-// _DEFPIN_ESP32(9,9); _DEFPIN_ESP32(10,10); _DEFPIN_ESP32(11,11); 
+// _FL_DEFPIN(6,6); _FL_DEFPIN(7,7); _FL_DEFPIN(8,8);
+// _FL_DEFPIN(9,9); _FL_DEFPIN(10,10); _FL_DEFPIN(11,11);
 
-_DEFPIN_ESP32(12);
-_DEFPIN_ESP32(13);
-_DEFPIN_ESP32(14);
-_DEFPIN_ESP32(15);
-_DEFPIN_ESP32(16);
-_DEFPIN_ESP32(17);
-_DEFPIN_ESP32(18);
-_DEFPIN_ESP32(19);
+_FL_DEFPIN(12);
+_FL_DEFPIN(13);
+_FL_DEFPIN(14);
+_FL_DEFPIN(15);
+_FL_DEFPIN(16);
+_FL_DEFPIN(17);
+_FL_DEFPIN(18);
+_FL_DEFPIN(19);
 
-// No pin 20 : _DEFPIN_ESP32(20,20); 
+// No pin 20 : _FL_DEFPIN(20,20);
 
-_DEFPIN_ESP32(21); // Works, but note that GPIO21 is I2C SDA
-_DEFPIN_ESP32(22); // Works, but note that GPIO22 is I2C SCL
-_DEFPIN_ESP32(23); 
+_FL_DEFPIN(21); // Works, but note that GPIO21 is I2C SDA
+_FL_DEFPIN(22); // Works, but note that GPIO22 is I2C SCL
+_FL_DEFPIN(23);
 
-// No pin 24 : _DEFPIN_ESP32(24,24); 
+// No pin 24 : _FL_DEFPIN(24,24);
 
-_DEFPIN_ESP32(25);
-_DEFPIN_ESP32(26);
-_DEFPIN_ESP32(27); 
+_FL_DEFPIN(25);
+_FL_DEFPIN(26);
+_FL_DEFPIN(27);
 
-// No pin 28-31: _DEFPIN_ESP32(28,28); _DEFPIN_ESP32(29,29); _DEFPIN_ESP32(30,30); _DEFPIN_ESP32(31,31);
+// No pin 28-31: _FL_DEFPIN(28,28); _FL_DEFPIN(29,29); _FL_DEFPIN(30,30); _FL_DEFPIN(31,31);
 
 // Need special handling for pins > 31
-_DEFPIN_32_33_ESP32(32); 
-_DEFPIN_32_33_ESP32(33);
+_FL_DEFPIN(32);
+_FL_DEFPIN(33);
 
 #define HAS_HARDWARE_PIN_SUPPORT
 
diff --git a/platforms/esp/8266/fastpin_esp8266.h b/platforms/esp/8266/fastpin_esp8266.h
index b8095b85..69085bf9 100644
--- a/platforms/esp/8266/fastpin_esp8266.h
+++ b/platforms/esp/8266/fastpin_esp8266.h
@@ -42,40 +42,40 @@ public:
   inline static bool isset() __attribute__ ((always_inline)) { return (PIN < 16) ? (GPO & MASK) : (GP16O & MASK); }
 };
 
-#define _DEFPIN_ESP8266(PIN, REAL_PIN) template<> class FastPin<PIN> : public _ESPPIN<REAL_PIN, (1<<(REAL_PIN & 0xFF))> {};
+#define _FL_DEFPIN(PIN, REAL_PIN) template<> class FastPin<PIN> : public _ESPPIN<REAL_PIN, (1<<(REAL_PIN & 0xFF))> {};
 
 
 #ifdef FASTLED_ESP8266_RAW_PIN_ORDER
 #define MAX_PIN 16
-_DEFPIN_ESP8266(0,0); _DEFPIN_ESP8266(1,1); _DEFPIN_ESP8266(2,2); _DEFPIN_ESP8266(3,3);
-_DEFPIN_ESP8266(4,4); _DEFPIN_ESP8266(5,5);
+_FL_DEFPIN(0,0); _FL_DEFPIN(1,1); _FL_DEFPIN(2,2); _FL_DEFPIN(3,3);
+_FL_DEFPIN(4,4); _FL_DEFPIN(5,5);
 
 // These pins should be disabled, as they always cause WDT resets
-// _DEFPIN_ESP8266(6,6); _DEFPIN_ESP8266(7,7);
-// _DEFPIN_ESP8266(8,8); _DEFPIN_ESP8266(9,9); _DEFPIN_ESP8266(10,10); _DEFPIN_ESP8266(11,11);
+// _FL_DEFPIN(6,6); _FL_DEFPIN(7,7);
+// _FL_DEFPIN(8,8); _FL_DEFPIN(9,9); _FL_DEFPIN(10,10); _FL_DEFPIN(11,11);
 
-_DEFPIN_ESP8266(12,12); _DEFPIN_ESP8266(13,13); _DEFPIN_ESP8266(14,14); _DEFPIN_ESP8266(15,15);
-_DEFPIN_ESP8266(16,16);
+_FL_DEFPIN(12,12); _FL_DEFPIN(13,13); _FL_DEFPIN(14,14); _FL_DEFPIN(15,15);
+_FL_DEFPIN(16,16);
 
 #define PORTA_FIRST_PIN 12
 #elif defined(FASTLED_ESP8266_D1_PIN_ORDER)
 #define MAX_PIN 15
-_DEFPIN_ESP8266(0,3);
-_DEFPIN_ESP8266(1,1);
-_DEFPIN_ESP8266(2,16);
-_DEFPIN_ESP8266(3,5);
-_DEFPIN_ESP8266(4,4);
-_DEFPIN_ESP8266(5,14);
-_DEFPIN_ESP8266(6,12);
-_DEFPIN_ESP8266(7,13);
-_DEFPIN_ESP8266(8,0);
-_DEFPIN_ESP8266(9,2);
-_DEFPIN_ESP8266(10,15);
-_DEFPIN_ESP8266(11,13);
-_DEFPIN_ESP8266(12,12);
-_DEFPIN_ESP8266(13,14);
-_DEFPIN_ESP8266(14,4);
-_DEFPIN_ESP8266(15,5);
+_FL_DEFPIN(0,3);
+_FL_DEFPIN(1,1);
+_FL_DEFPIN(2,16);
+_FL_DEFPIN(3,5);
+_FL_DEFPIN(4,4);
+_FL_DEFPIN(5,14);
+_FL_DEFPIN(6,12);
+_FL_DEFPIN(7,13);
+_FL_DEFPIN(8,0);
+_FL_DEFPIN(9,2);
+_FL_DEFPIN(10,15);
+_FL_DEFPIN(11,13);
+_FL_DEFPIN(12,12);
+_FL_DEFPIN(13,14);
+_FL_DEFPIN(14,4);
+_FL_DEFPIN(15,5);
 
 #define PORTA_FIRST_PIN 12
 
@@ -83,16 +83,16 @@ _DEFPIN_ESP8266(15,5);
 #define MAX_PIN 10
 
 // This seems to be the standard Dxx pin mapping on most of the esp boards that i've found
-_DEFPIN_ESP8266(0,16); _DEFPIN_ESP8266(1,5); _DEFPIN_ESP8266(2,4); _DEFPIN_ESP8266(3,0);
-_DEFPIN_ESP8266(4,2); _DEFPIN_ESP8266(5,14); _DEFPIN_ESP8266(6,12); _DEFPIN_ESP8266(7,13);
-_DEFPIN_ESP8266(8,15); _DEFPIN_ESP8266(9,3); _DEFPIN_ESP8266(10,1);
+_FL_DEFPIN(0,16); _FL_DEFPIN(1,5); _FL_DEFPIN(2,4); _FL_DEFPIN(3,0);
+_FL_DEFPIN(4,2); _FL_DEFPIN(5,14); _FL_DEFPIN(6,12); _FL_DEFPIN(7,13);
+_FL_DEFPIN(8,15); _FL_DEFPIN(9,3); _FL_DEFPIN(10,1);
 
 #define PORTA_FIRST_PIN 6
 
 // The rest of the pins - these are generally not available
-// _DEFPIN_ESP8266(11,6);
-// _DEFPIN_ESP8266(12,7); _DEFPIN_ESP8266(13,8); _DEFPIN_ESP8266(14,9); _DEFPIN_ESP8266(15,10);
-// _DEFPIN_ESP8266(16,11);
+// _FL_DEFPIN(11,6);
+// _FL_DEFPIN(12,7); _FL_DEFPIN(13,8); _FL_DEFPIN(14,9); _FL_DEFPIN(15,10);
+// _FL_DEFPIN(16,11);
 
 #endif
 
diff --git a/release_notes.md b/release_notes.md
index ae9075c0..cf9ce1a3 100644
--- a/release_notes.md
+++ b/release_notes.md
@@ -1,3 +1,29 @@
+FastLED 3.3.2
+=============
+
+* Fix APA102 compile error #870 
+* Normalize pin definition macros so that we can have an .ino file that can be used to output what pin/port mappings should be for a platform
+* Add defnition for ATmega32
+
+FastLED 3.3.1
+=============
+
+* Fix teensy build issue 
+* Bring in sam's RMT timing fix
+
+FastLED 3.3.0
+==============
+* Preliminary Teensy 4 support
+* Fix #861 - power computation for OctoWS2811
+* keywords and other minor changes for compilers (#854, #845)
+* Fix some nrf52 issues (#856), #840
+
+FastLED 3.2.10
+==============
+* Adafruit Metro M4 Airlift support
+* Arduino Nano 33 IOT preliminary definitions
+* Bug fixes
+
 FastLED 3.2.9
 =============
 * Update ItsyBitsy support