diff options
| author | Dan Garcia <dangarcia@apple.com> | 2019-08-15 03:53:21 +0300 |
|---|---|---|
| committer | Dan Garcia <dangarcia@apple.com> | 2019-08-15 03:53:21 +0300 |
| commit | 289cd7f1e29cbebce40c6e076d6ad404de2478c6 (patch) | |
| tree | 06882e6ddcec4564abdfdda1a178c25978645bbe | |
| parent | 437c1aeed56118b94e46b168600f871e4f6afab3 (diff) | |
checkpoint - bring all the arm and esp platforms in line w/defpin macro naming/ordering
| -rw-r--r-- | platforms/arm/d21/fastpin_arm_d21.h | 142 | ||||
| -rw-r--r-- | platforms/arm/d51/fastpin_arm_d51.h | 52 | ||||
| -rw-r--r-- | platforms/arm/k20/fastpin_arm_k20.h | 24 | ||||
| -rw-r--r-- | platforms/arm/k66/fastpin_arm_k66.h | 38 | ||||
| -rw-r--r-- | platforms/arm/kl26/fastpin_arm_kl26.h | 20 | ||||
| -rw-r--r-- | platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h | 28 | ||||
| -rw-r--r-- | platforms/arm/nrf51/fastpin_arm_nrf51.h | 20 | ||||
| -rw-r--r-- | platforms/arm/nrf52/fastpin_arm_nrf52.h | 22 | ||||
| -rw-r--r-- | platforms/arm/nrf52/fastpin_arm_nrf52_variants.h | 538 | ||||
| -rw-r--r-- | platforms/arm/sam/fastpin_arm_sam.h | 64 | ||||
| -rw-r--r-- | platforms/arm/stm32/fastpin_arm_stm32.h | 116 | ||||
| -rw-r--r-- | platforms/esp/32/fastpin_esp32.h | 67 | ||||
| -rw-r--r-- | platforms/esp/8266/fastpin_esp8266.h | 58 |
13 files changed, 594 insertions, 595 deletions
diff --git a/platforms/arm/d21/fastpin_arm_d21.h b/platforms/arm/d21/fastpin_arm_d21.h index 997fb06a..84b0738c 100644 --- a/platforms/arm/d21/fastpin_arm_d21.h +++ b/platforms/arm/d21/fastpin_arm_d21.h @@ -57,19 +57,19 @@ public: #define _R(T) struct __gen_struct_ ## T #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile PortGroup * r() { return T; } }; -#define _IO32(L) _RD32(GPIO ## L) +#define _FL_IO(L) _RD32(GPIO ## L) -#define _DEFPIN_ARM(PIN, L, BIT) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, L> {}; +#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, L> {}; // Actual pin definitions #if defined(ARDUINO_SAMD_CIRCUITPLAYGROUND_EXPRESS) #define MAX_PIN 17 -_DEFPIN_ARM( 8,1,23); -_DEFPIN_ARM( 0,1, 9); _DEFPIN_ARM( 1,1, 8); _DEFPIN_ARM( 2,1, 2); _DEFPIN_ARM( 3,1, 3); -_DEFPIN_ARM( 6,0, 5); _DEFPIN_ARM( 9,0, 6); _DEFPIN_ARM(10,0, 7); _DEFPIN_ARM(12,0, 2); -_DEFPIN_ARM(A6,1, 9); _DEFPIN_ARM(A7,1, 8); _DEFPIN_ARM(A5,1, 2); _DEFPIN_ARM(A4,1, 3); -_DEFPIN_ARM(A1,0, 5); _DEFPIN_ARM(A2,0, 6); _DEFPIN_ARM(A3,0, 7); _DEFPIN_ARM(A0,0, 2); +_FL_DEFPIN( 8,23,1); +_FL_DEFPIN( 0, 9,1); _FL_DEFPIN( 1, 8,1); _FL_DEFPIN( 2, 2,1); _FL_DEFPIN( 3, 3,1); +_FL_DEFPIN( 6, 5,0); _FL_DEFPIN( 9, 6,0); _FL_DEFPIN(10, 7,0); _FL_DEFPIN(12, 2,0); +_FL_DEFPIN(A6, 9,1); _FL_DEFPIN(A7, 8,1); _FL_DEFPIN(A5, 2,1); _FL_DEFPIN(A4, 3,1); +_FL_DEFPIN(A1, 5,0); _FL_DEFPIN(A2, 6,0); _FL_DEFPIN(A3, 7,0); _FL_DEFPIN(A0, 2,0); #define HAS_HARDWARE_PIN_SUPPORT 1 @@ -78,19 +78,19 @@ _DEFPIN_ARM(A1,0, 5); _DEFPIN_ARM(A2,0, 6); _DEFPIN_ARM(A3,0, 7); _DEFPIN_ARM(A0 #define MAX_PIN 20 // 0 & 1 -_DEFPIN_ARM( 0, 0, 9); _DEFPIN_ARM( 1, 0, 10); +_FL_DEFPIN( 0, 9, 0); _FL_DEFPIN( 1, 10, 0); // 2, 3, 4 -_DEFPIN_ARM( 2, 0, 14); _DEFPIN_ARM( 3, 0, 11); _DEFPIN_ARM( 4, 0, 8); +_FL_DEFPIN( 2, 14, 0); _FL_DEFPIN( 3, 11, 0); _FL_DEFPIN( 4, 8, 0); // 5, 6, 7 -_DEFPIN_ARM( 5, 0, 15); _DEFPIN_ARM( 6, 0, 18); _DEFPIN_ARM( 7, 0, 0); +_FL_DEFPIN( 5, 15, 0); _FL_DEFPIN( 6, 18, 0); _FL_DEFPIN( 7, 0, 0); // 8, 9, 10 -_DEFPIN_ARM( 8, 0, 12); _DEFPIN_ARM( 9, 0, 19); _DEFPIN_ARM(10, 0, 20); +_FL_DEFPIN( 8, 12, 0); _FL_DEFPIN( 9, 19, 0); _FL_DEFPIN(10, 20, 0); // 11, 12, 13 -_DEFPIN_ARM(11, 0, 21); _DEFPIN_ARM(12, 0, 22); _DEFPIN_ARM(13, 0, 23); +_FL_DEFPIN(11, 21, 0); _FL_DEFPIN(12, 22, 0); _FL_DEFPIN(13, 23, 0); // 14, 15, 16 (A0 - A2) -_DEFPIN_ARM(14, 0, 2); _DEFPIN_ARM(15, 1, 8); _DEFPIN_ARM(16, 1, 9); +_FL_DEFPIN(14, 2, 0); _FL_DEFPIN(15, 8, 1); _FL_DEFPIN(16, 9, 1); // 17, 18, 19 (A3 - A5) -_DEFPIN_ARM(17, 0, 4); _DEFPIN_ARM(18, 0, 5); _DEFPIN_ARM(19, 0, 6); +_FL_DEFPIN(17, 4, 0); _FL_DEFPIN(18, 5, 0); _FL_DEFPIN(19, 6, 0); #define SPI_DATA PIN_SPI_MOSI #define SPI_CLOCK PIN_SPI_SCK @@ -101,17 +101,17 @@ _DEFPIN_ARM(17, 0, 4); _DEFPIN_ARM(18, 0, 5); _DEFPIN_ARM(19, 0, 6); #elif defined(ARDUINO_SAMD_ZERO) #define MAX_PIN 42 -_DEFPIN_ARM( 0,0,10); _DEFPIN_ARM( 1,0,11); _DEFPIN_ARM( 2,0, 8); _DEFPIN_ARM( 3,0, 9); -_DEFPIN_ARM( 4,0,14); _DEFPIN_ARM( 5,0,15); _DEFPIN_ARM( 6,0,20); _DEFPIN_ARM( 7,0,21); -_DEFPIN_ARM( 8,0, 6); _DEFPIN_ARM( 9,0, 7); _DEFPIN_ARM(10,0,18); _DEFPIN_ARM(11,0,16); -_DEFPIN_ARM(12,0,19); _DEFPIN_ARM(13,0,17); _DEFPIN_ARM(14,0, 2); _DEFPIN_ARM(15,1, 8); -_DEFPIN_ARM(16,1, 9); _DEFPIN_ARM(17,0, 4); _DEFPIN_ARM(18,0, 5); _DEFPIN_ARM(19,1, 2); -_DEFPIN_ARM(20,0,22); _DEFPIN_ARM(21,0,23); _DEFPIN_ARM(22,0,12); _DEFPIN_ARM(23,1,11); -_DEFPIN_ARM(24,1,10); _DEFPIN_ARM(25,1, 3); _DEFPIN_ARM(26,0,27); _DEFPIN_ARM(27,0,28); -_DEFPIN_ARM(28,0,24); _DEFPIN_ARM(29,0,25); _DEFPIN_ARM(30,1,22); _DEFPIN_ARM(31,1,23); -_DEFPIN_ARM(32,0,22); _DEFPIN_ARM(33,0,23); _DEFPIN_ARM(34,0,19); _DEFPIN_ARM(35,0,16); -_DEFPIN_ARM(36,0,18); _DEFPIN_ARM(37,0,17); _DEFPIN_ARM(38,0,13); _DEFPIN_ARM(39,0,21); -_DEFPIN_ARM(40,0, 6); _DEFPIN_ARM(41,0, 7); _DEFPIN_ARM(42,0, 3); +_FL_DEFPIN( 0,10,0); _FL_DEFPIN( 1,11,0); _FL_DEFPIN( 2, 8,0); _FL_DEFPIN( 3, 9,0); +_FL_DEFPIN( 4,14,0); _FL_DEFPIN( 5,15,0); _FL_DEFPIN( 6,20,0); _FL_DEFPIN( 7,21,0); +_FL_DEFPIN( 8, 6,0); _FL_DEFPIN( 9, 7,0); _FL_DEFPIN(10,18,0); _FL_DEFPIN(11,16,0); +_FL_DEFPIN(12,19,0); _FL_DEFPIN(13,17,0); _FL_DEFPIN(14, 2,0); _FL_DEFPIN(15, 8,1); +_FL_DEFPIN(16, 9,1); _FL_DEFPIN(17, 4,0); _FL_DEFPIN(18, 5,0); _FL_DEFPIN(19, 2,1); +_FL_DEFPIN(20,22,0); _FL_DEFPIN(21,23,0); _FL_DEFPIN(22,12,0); _FL_DEFPIN(23,11,1); +_FL_DEFPIN(24,10,1); _FL_DEFPIN(25, 3,1); _FL_DEFPIN(26,27,0); _FL_DEFPIN(27,28,0); +_FL_DEFPIN(28,24,0); _FL_DEFPIN(29,25,0); _FL_DEFPIN(30,22,1); _FL_DEFPIN(31,23,1); +_FL_DEFPIN(32,22,0); _FL_DEFPIN(33,23,0); _FL_DEFPIN(34,19,0); _FL_DEFPIN(35,16,0); +_FL_DEFPIN(36,18,0); _FL_DEFPIN(37,17,0); _FL_DEFPIN(38,13,0); _FL_DEFPIN(39,21,0); +_FL_DEFPIN(40, 6,0); _FL_DEFPIN(41, 7,0); _FL_DEFPIN(42, 3,0); #define SPI_DATA 24 #define SPI_CLOCK 23 @@ -121,21 +121,21 @@ _DEFPIN_ARM(40,0, 6); _DEFPIN_ARM(41,0, 7); _DEFPIN_ARM(42,0, 3); #elif defined(ARDUINO_SODAQ_AUTONOMO) #define MAX_PIN 56 -_DEFPIN_ARM( 0,0, 9); _DEFPIN_ARM( 1,0,10); _DEFPIN_ARM( 2,0,11); _DEFPIN_ARM( 3,1,10); -_DEFPIN_ARM( 4,1,11); _DEFPIN_ARM( 5,1,12); _DEFPIN_ARM( 6,1,13); _DEFPIN_ARM( 7,1,14); -_DEFPIN_ARM( 8,1,15); _DEFPIN_ARM( 9,0,14); _DEFPIN_ARM(10,0,15); _DEFPIN_ARM(11,0,16); -_DEFPIN_ARM(12,0,17); _DEFPIN_ARM(13,0,18); _DEFPIN_ARM(14,0,19); _DEFPIN_ARM(15,1,16); -_DEFPIN_ARM(16,0, 8); _DEFPIN_ARM(17,0,28); _DEFPIN_ARM(18,1,17); _DEFPIN_ARM(19,0, 2); -_DEFPIN_ARM(20,0, 6); _DEFPIN_ARM(21,0, 5); _DEFPIN_ARM(22,0, 4); _DEFPIN_ARM(23,1, 9); -_DEFPIN_ARM(24,1, 8); _DEFPIN_ARM(25,1, 7); _DEFPIN_ARM(26,1, 6); _DEFPIN_ARM(27,1, 5); -_DEFPIN_ARM(28,1, 4); _DEFPIN_ARM(29,0, 7); _DEFPIN_ARM(30,1, 3); _DEFPIN_ARM(31,1, 2); -_DEFPIN_ARM(32,1, 1); _DEFPIN_ARM(33,1, 0); _DEFPIN_ARM(34,0, 3); _DEFPIN_ARM(35,0, 3); -_DEFPIN_ARM(36,1,30); _DEFPIN_ARM(37,1,31); _DEFPIN_ARM(38,1,22); _DEFPIN_ARM(39,1,23); -_DEFPIN_ARM(40,0,12); _DEFPIN_ARM(41,0,13); _DEFPIN_ARM(42,0,22); _DEFPIN_ARM(43,0,23); -_DEFPIN_ARM(44,0,20); _DEFPIN_ARM(45,0,21); _DEFPIN_ARM(46,0,27); _DEFPIN_ARM(47,0,24); -_DEFPIN_ARM(48,0,25); _DEFPIN_ARM(49,1,13); _DEFPIN_ARM(50,1,14); _DEFPIN_ARM(51,0,17); -_DEFPIN_ARM(52,0,18); _DEFPIN_ARM(53,1,12); _DEFPIN_ARM(54,1,13); _DEFPIN_ARM(55,1,14); -_DEFPIN_ARM(56,1,15); +_FL_DEFPIN( 0, 9,0); _FL_DEFPIN( 1,10,0); _FL_DEFPIN( 2,11,0); _FL_DEFPIN( 3,10,1); +_FL_DEFPIN( 4,11,1); _FL_DEFPIN( 5,12,1); _FL_DEFPIN( 6,13,1); _FL_DEFPIN( 7,14,1); +_FL_DEFPIN( 8,15,1); _FL_DEFPIN( 9,14,0); _FL_DEFPIN(10,15,0); _FL_DEFPIN(11,16,0); +_FL_DEFPIN(12,17,0); _FL_DEFPIN(13,18,0); _FL_DEFPIN(14,19,0); _FL_DEFPIN(15,16,1); +_FL_DEFPIN(16, 8,0); _FL_DEFPIN(17,28,0); _FL_DEFPIN(18,17,1); _FL_DEFPIN(19, 2,0); +_FL_DEFPIN(20, 6,0); _FL_DEFPIN(21, 5,0); _FL_DEFPIN(22, 4,0); _FL_DEFPIN(23, 9,1); +_FL_DEFPIN(24, 8,1); _FL_DEFPIN(25, 7,1); _FL_DEFPIN(26, 6,1); _FL_DEFPIN(27, 5,1); +_FL_DEFPIN(28, 4,1); _FL_DEFPIN(29, 7,0); _FL_DEFPIN(30, 3,1); _FL_DEFPIN(31, 2,1); +_FL_DEFPIN(32, 1,1); _FL_DEFPIN(33, 0,1); _FL_DEFPIN(34, 3,0); _FL_DEFPIN(35, 3,0); +_FL_DEFPIN(36,30,1); _FL_DEFPIN(37,31,1); _FL_DEFPIN(38,22,1); _FL_DEFPIN(39,23,1); +_FL_DEFPIN(40,12,0); _FL_DEFPIN(41,13,0); _FL_DEFPIN(42,22,0); _FL_DEFPIN(43,23,0); +_FL_DEFPIN(44,20,0); _FL_DEFPIN(45,21,0); _FL_DEFPIN(46,27,0); _FL_DEFPIN(47,24,0); +_FL_DEFPIN(48,25,0); _FL_DEFPIN(49,13,1); _FL_DEFPIN(50,14,1); _FL_DEFPIN(51,17,0); +_FL_DEFPIN(52,18,0); _FL_DEFPIN(53,12,1); _FL_DEFPIN(54,13,1); _FL_DEFPIN(55,14,1); +_FL_DEFPIN(56,15,1); #define SPI_DATA 44 #define SPI_CLOCK 45 @@ -145,24 +145,24 @@ _DEFPIN_ARM(56,1,15); #elif defined(ARDUINO_SAMD_WINO) #define MAX_PIN 22 -_DEFPIN_ARM( 0, 0, 23); _DEFPIN_ARM( 1, 0, 22); _DEFPIN_ARM( 2, 0, 16); _DEFPIN_ARM( 3, 0, 17); -_DEFPIN_ARM( 4, 0, 18); _DEFPIN_ARM( 5, 0, 19); _DEFPIN_ARM( 6, 0, 24); _DEFPIN_ARM( 7, 0, 25); -_DEFPIN_ARM( 8, 0, 27); _DEFPIN_ARM( 9, 0, 28); _DEFPIN_ARM( 10, 0, 30); _DEFPIN_ARM( 11, 0, 31); -_DEFPIN_ARM( 12, 0, 15); _DEFPIN_ARM( 13, 0, 14); _DEFPIN_ARM( 14, 0, 2); _DEFPIN_ARM( 15, 0, 3); -_DEFPIN_ARM( 16, 0, 4); _DEFPIN_ARM( 17, 0, 5); _DEFPIN_ARM( 18, 0, 6); _DEFPIN_ARM( 19, 0, 7); -_DEFPIN_ARM( 20, 0, 8); _DEFPIN_ARM( 21, 0, 9); _DEFPIN_ARM( 22, 0, 10); _DEFPIN_ARM( 23, 0, 11); +_FL_DEFPIN( 0, 23, 0); _FL_DEFPIN( 1, 22, 0); _FL_DEFPIN( 2, 16, 0); _FL_DEFPIN( 3, 17, 0); +_FL_DEFPIN( 4, 18, 0); _FL_DEFPIN( 5, 19, 0); _FL_DEFPIN( 6, 24, 0); _FL_DEFPIN( 7, 25, 0); +_FL_DEFPIN( 8, 27, 0); _FL_DEFPIN( 9, 28, 0); _FL_DEFPIN( 10, 30, 0); _FL_DEFPIN( 11, 31, 0); +_FL_DEFPIN( 12, 15, 0); _FL_DEFPIN( 13, 14, 0); _FL_DEFPIN( 14, 2, 0); _FL_DEFPIN( 15, 3, 0); +_FL_DEFPIN( 16, 4, 0); _FL_DEFPIN( 17, 5, 0); _FL_DEFPIN( 18, 6, 0); _FL_DEFPIN( 19, 7, 0); +_FL_DEFPIN( 20, 8, 0); _FL_DEFPIN( 21, 9, 0); _FL_DEFPIN( 22, 10, 0); _FL_DEFPIN( 23, 11, 0); #define HAS_HARDWARE_PIN_SUPPORT 1 #elif defined(ARDUINO_SAMD_MKR1000) #define MAX_PIN 22 -_DEFPIN_ARM( 0, 0, 22); _DEFPIN_ARM( 1, 0, 23); _DEFPIN_ARM( 2, 0, 10); _DEFPIN_ARM( 3, 0, 11); -_DEFPIN_ARM( 4, 1, 10); _DEFPIN_ARM( 5, 1, 11); _DEFPIN_ARM( 6, 0, 20); _DEFPIN_ARM( 7, 0, 21); -_DEFPIN_ARM( 8, 0, 16); _DEFPIN_ARM( 9, 0, 17); _DEFPIN_ARM( 10, 0, 19); _DEFPIN_ARM( 11, 0, 8); -_DEFPIN_ARM( 12, 0, 9); _DEFPIN_ARM( 13, 1, 23); _DEFPIN_ARM( 14, 1, 22); _DEFPIN_ARM( 15, 0, 2); -_DEFPIN_ARM( 16, 1, 2); _DEFPIN_ARM( 17, 1, 3); _DEFPIN_ARM( 18, 0, 4); _DEFPIN_ARM( 19, 0, 5); -_DEFPIN_ARM( 20, 0, 6); _DEFPIN_ARM( 21, 0, 7); +_FL_DEFPIN( 0, 22, 0); _FL_DEFPIN( 1, 23, 0); _FL_DEFPIN( 2, 10, 0); _FL_DEFPIN( 3, 11, 0); +_FL_DEFPIN( 4, 10, 1); _FL_DEFPIN( 5, 11, 1); _FL_DEFPIN( 6, 20, 0); _FL_DEFPIN( 7, 21, 0); +_FL_DEFPIN( 8, 16, 0); _FL_DEFPIN( 9, 17, 0); _FL_DEFPIN( 10, 19, 0); _FL_DEFPIN( 11, 8, 0); +_FL_DEFPIN( 12, 9, 0); _FL_DEFPIN( 13, 23, 1); _FL_DEFPIN( 14, 22, 1); _FL_DEFPIN( 15, 2, 0); +_FL_DEFPIN( 16, 2, 1); _FL_DEFPIN( 17, 3, 1); _FL_DEFPIN( 18, 4, 0); _FL_DEFPIN( 19, 5, 0); +_FL_DEFPIN( 20, 6, 0); _FL_DEFPIN( 21, 7, 0); #define SPI_DATA 8 #define SPI_CLOCK 9 @@ -172,13 +172,13 @@ _DEFPIN_ARM( 20, 0, 6); _DEFPIN_ARM( 21, 0, 7); #elif defined(ARDUINO_SAMD_NANO_33_IOT) #define MAX_PIN 25 -_DEFPIN_ARM( 0, 0, 11); _DEFPIN_ARM( 1, 0, 10); _DEFPIN_ARM( 2, 0, 14); _DEFPIN_ARM( 3, 0, 9); -_DEFPIN_ARM( 4, 0, 8); _DEFPIN_ARM( 5, 0, 15); _DEFPIN_ARM( 6, 0, 20); _DEFPIN_ARM( 7, 0, 21); -_DEFPIN_ARM( 8, 0, 6); _DEFPIN_ARM( 9, 0, 7); _DEFPIN_ARM( 10, 0, 18); _DEFPIN_ARM( 11, 0, 16); -_DEFPIN_ARM( 12, 0, 19); _DEFPIN_ARM( 13, 0, 17); _DEFPIN_ARM( 14, 0, 2); _DEFPIN_ARM( 15, 1, 8); -_DEFPIN_ARM( 16, 1, 9); _DEFPIN_ARM( 17, 0, 4); _DEFPIN_ARM( 18, 0, 5); _DEFPIN_ARM( 19, 1, 2); -_DEFPIN_ARM( 20, 0, 22); _DEFPIN_ARM( 21, 0, 23); _DEFPIN_ARM( 22, 0, 12); _DEFPIN_ARM( 23, 1, 10); -_DEFPIN_ARM( 24, 1, 11); +_FL_DEFPIN( 0, 11, 0); _FL_DEFPIN( 1, 10, 0); _FL_DEFPIN( 2, 14, 0); _FL_DEFPIN( 3, 9, 0); +_FL_DEFPIN( 4, 8, 0); _FL_DEFPIN( 5, 15, 0); _FL_DEFPIN( 6, 20, 0); _FL_DEFPIN( 7, 21, 0); +_FL_DEFPIN( 8, 6, 0); _FL_DEFPIN( 9, 7, 0); _FL_DEFPIN( 10, 18, 0); _FL_DEFPIN( 11, 16, 0); +_FL_DEFPIN( 12, 19, 0); _FL_DEFPIN( 13, 17, 0); _FL_DEFPIN( 14, 2, 0); _FL_DEFPIN( 15, 8, 1); +_FL_DEFPIN( 16, 9, 1); _FL_DEFPIN( 17, 4, 0); _FL_DEFPIN( 18, 5, 0); _FL_DEFPIN( 19, 2, 1); +_FL_DEFPIN( 20, 22, 0); _FL_DEFPIN( 21, 23, 0); _FL_DEFPIN( 22, 12, 0); _FL_DEFPIN( 23, 10, 1); +_FL_DEFPIN( 24, 11, 1); #define SPI_DATA 23 #define SPI_CLOCK 24 @@ -188,16 +188,16 @@ _DEFPIN_ARM( 24, 1, 11); #elif defined(ARDUINO_GEMMA_M0) #define MAX_PIN 4 -_DEFPIN_ARM( 0, 0, 4); _DEFPIN_ARM( 1, 0, 2); _DEFPIN_ARM( 2, 0, 5); -_DEFPIN_ARM( 3, 0, 0); _DEFPIN_ARM( 4, 0, 1); +_FL_DEFPIN( 0, 4, 0); _FL_DEFPIN( 1, 2, 0); _FL_DEFPIN( 2, 5, 0); +_FL_DEFPIN( 3, 0, 0); _FL_DEFPIN( 4, 1, 0); #define HAS_HARDWARE_PIN_SUPPORT 1 #elif defined(ADAFRUIT_TRINKET_M0) #define MAX_PIN 7 -_DEFPIN_ARM( 0, 0, 8); _DEFPIN_ARM( 1, 0, 2); _DEFPIN_ARM( 2, 0, 9); -_DEFPIN_ARM( 3, 0, 7); _DEFPIN_ARM( 4, 0, 6); _DEFPIN_ARM( 7, 0, 0); _DEFPIN_ARM( 8, 0, 1); +_FL_DEFPIN( 0, 8, 0); _FL_DEFPIN( 1, 2, 0); _FL_DEFPIN( 2, 9, 0); +_FL_DEFPIN( 3, 7, 0); _FL_DEFPIN( 4, 6, 0); _FL_DEFPIN( 7, 0, 0); _FL_DEFPIN( 8, 1, 0); #define SPI_DATA 4 #define SPI_CLOCK 3 @@ -207,14 +207,14 @@ _DEFPIN_ARM( 3, 0, 7); _DEFPIN_ARM( 4, 0, 6); _DEFPIN_ARM( 7, 0, 0); _DEFPIN_ARM #elif defined(ADAFRUIT_ITSYBITSY_M0) #define MAX_PIN 16 -_DEFPIN_ARM( 2, 0, 14); _DEFPIN_ARM( 3, 0, 9); _DEFPIN_ARM( 4, 0, 8); -_DEFPIN_ARM( 5, 0, 15); _DEFPIN_ARM( 6, 0, 20); _DEFPIN_ARM( 7, 0, 21); -_DEFPIN_ARM( 8, 0, 6); _DEFPIN_ARM( 9, 0, 7); _DEFPIN_ARM( 10, 0, 18); -_DEFPIN_ARM( 11, 0, 16); _DEFPIN_ARM( 12, 0, 19); _DEFPIN_ARM( 13, 0, 17); -_DEFPIN_ARM( 29, 0, 10); // MOSI -_DEFPIN_ARM( 30, 0, 11); // SCK -_DEFPIN_ARM( 40, 0, 0); //APA102 Clock -_DEFPIN_ARM( 41, 0, 1) //APA102 Data +_FL_DEFPIN( 2, 14, 0); _FL_DEFPIN( 3, 9, 0); _FL_DEFPIN( 4, 8, 0); +_FL_DEFPIN( 5, 15, 0); _FL_DEFPIN( 6, 20, 0); _FL_DEFPIN( 7, 21, 0); +_FL_DEFPIN( 8, 6, 0); _FL_DEFPIN( 9, 7, 0); _FL_DEFPIN( 10, 18, 0); +_FL_DEFPIN( 11, 16, 0); _FL_DEFPIN( 12, 19, 0); _FL_DEFPIN( 13, 17, 0); +_FL_DEFPIN( 29, 10, 0); // MOSI +_FL_DEFPIN( 30, 11, 0); // SCK +_FL_DEFPIN( 40, 0, 0); //APA102 Clock +_FL_DEFPIN( 41, 0, 1) //APA102 Data #define SPI_DATA 29 #define SPI_CLOCK 30 diff --git a/platforms/arm/d51/fastpin_arm_d51.h b/platforms/arm/d51/fastpin_arm_d51.h index 5e36023d..dd40dbfd 100644 --- a/platforms/arm/d51/fastpin_arm_d51.h +++ b/platforms/arm/d51/fastpin_arm_d51.h @@ -57,27 +57,27 @@ public: #define _R(T) struct __gen_struct_ ## T #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile PortGroup * r() { return T; } }; -#define _IO32(L) _RD32(GPIO ## L) +#define _FL_IO(L) _RD32(GPIO ## L) -#define _DEFPIN_ARM(PIN, L, BIT) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, L> {}; +#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, L> {}; // Actual pin definitions #if defined(ADAFRUIT_ITSYBITSY_M4_EXPRESS) #define MAX_PIN 19 // D0-D13, including D6+D8 (DotStar CLK + DATA) -_DEFPIN_ARM( 0, 0, 16); _DEFPIN_ARM( 1, 0, 17); _DEFPIN_ARM( 2, 0, 7); _DEFPIN_ARM( 3, 1, 22); -_DEFPIN_ARM( 4, 0, 14); _DEFPIN_ARM( 5, 0, 15); _DEFPIN_ARM( 6, 1, 2); _DEFPIN_ARM( 7, 0, 18); -_DEFPIN_ARM( 8, 1, 3); _DEFPIN_ARM( 9, 0, 19); _DEFPIN_ARM(10, 0, 20); _DEFPIN_ARM(11, 0, 21); -_DEFPIN_ARM(12, 0, 23); _DEFPIN_ARM(13, 0, 22); +_FL_DEFPIN( 0, 16, 0); _FL_DEFPIN( 1, 17, 0); _FL_DEFPIN( 2, 7, 0); _FL_DEFPIN( 3, 22, 1); +_FL_DEFPIN( 4, 14, 0); _FL_DEFPIN( 5, 15, 0); _FL_DEFPIN( 6, 2, 1); _FL_DEFPIN( 7, 18, 0); +_FL_DEFPIN( 8, 3, 1); _FL_DEFPIN( 9, 19, 0); _FL_DEFPIN(10, 20, 0); _FL_DEFPIN(11, 21, 0); +_FL_DEFPIN(12, 23, 0); _FL_DEFPIN(13, 22, 0); // A0-A5 -_DEFPIN_ARM(14, 0, 2); _DEFPIN_ARM(15, 0, 5); _DEFPIN_ARM(16, 1, 8); _DEFPIN_ARM(17, 1, 9); -_DEFPIN_ARM(18, 0, 4); _DEFPIN_ARM(19, 0, 6); /* A6 is present in variant.h but couldn't find it on the schematic */ +_FL_DEFPIN(14, 2, 0); _FL_DEFPIN(15, 5, 0); _FL_DEFPIN(16, 8, 1); _FL_DEFPIN(17, 9, 1); +_FL_DEFPIN(18, 4, 0); _FL_DEFPIN(19, 6, 0); /* A6 is present in variant.h but couldn't find it on the schematic */ // SDA/SCL -_DEFPIN_ARM(21, 0, 12); _DEFPIN_ARM(22, 0, 13); +_FL_DEFPIN(21, 12, 0); _FL_DEFPIN(22, 13, 0); // 23..25 MISO/SCK/MOSI -_DEFPIN_ARM(23, 1, 23); _DEFPIN_ARM(24, 0, 1); _DEFPIN_ARM(25, 0, 0); +_FL_DEFPIN(23, 23, 1); _FL_DEFPIN(24, 1, 0); _FL_DEFPIN(25, 0, 0); #define SPI_DATA 25 #define SPI_CLOCK 24 @@ -89,18 +89,18 @@ _DEFPIN_ARM(23, 1, 23); _DEFPIN_ARM(24, 0, 1); _DEFPIN_ARM(25, 0, 0); #define MAX_PIN 20 // D0-D13, including D6+D8 (DotStar CLK + DATA) -_DEFPIN_ARM( 0, 0, 23); _DEFPIN_ARM( 1, 0, 22); _DEFPIN_ARM( 2, 1, 17); _DEFPIN_ARM( 3, 1, 16); -_DEFPIN_ARM( 4, 1, 13); _DEFPIN_ARM( 5, 1, 14); _DEFPIN_ARM( 6, 1, 15); _DEFPIN_ARM( 7, 1, 12); -_DEFPIN_ARM( 8, 0, 21); _DEFPIN_ARM( 9, 0, 20); _DEFPIN_ARM(10, 0, 18); _DEFPIN_ARM(11, 0, 19); -_DEFPIN_ARM(12, 0, 17); _DEFPIN_ARM(13, 0, 16); +_FL_DEFPIN( 0, 23, 0); _FL_DEFPIN( 1, 22, 0); _FL_DEFPIN( 2, 17, 1); _FL_DEFPIN( 3, 16, 1); +_FL_DEFPIN( 4, 13, 1); _FL_DEFPIN( 5, 14, 1); _FL_DEFPIN( 6, 15, 1); _FL_DEFPIN( 7, 12, 1); +_FL_DEFPIN( 8, 21, 0); _FL_DEFPIN( 9, 20, 0); _FL_DEFPIN(10, 18, 0); _FL_DEFPIN(11, 19, 0); +_FL_DEFPIN(12, 17, 0); _FL_DEFPIN(13, 16, 0); // A0-A5 -_DEFPIN_ARM(14, 0, 2); _DEFPIN_ARM(15, 0, 5); _DEFPIN_ARM(16, 0, 6); _DEFPIN_ARM(17, 1, 0); -_DEFPIN_ARM(18, 1, 8); _DEFPIN_ARM(19, 1, 9); +_FL_DEFPIN(14, 2, 0); _FL_DEFPIN(15, 5, 0); _FL_DEFPIN(16, 6, 0); _FL_DEFPIN(17, 0, 1); +_FL_DEFPIN(18, 8, 1); _FL_DEFPIN(19, 9, 1); // SDA/SCL -_DEFPIN_ARM(22, 1, 2); _DEFPIN_ARM(23, 1, 3); +_FL_DEFPIN(22, 2, 1); _FL_DEFPIN(23, 3, 1); // 23..25 MISO/SCK/MOSI -_DEFPIN_ARM(24, 0, 14); _DEFPIN_ARM(25, 0, 13); _DEFPIN_ARM(26, 0, 12); +_FL_DEFPIN(24, 14, 0); _FL_DEFPIN(25, 13, 0); _FL_DEFPIN(26, 12, 0); #define SPI_DATA 26 #define SPI_CLOCK 25 @@ -111,17 +111,17 @@ _DEFPIN_ARM(24, 0, 14); _DEFPIN_ARM(25, 0, 13); _DEFPIN_ARM(26, 0, 12); #define MAX_PIN 19 // D0-D13, including D8 (neopixel) no pins 2 3 -_DEFPIN_ARM( 0, 1, 17); _DEFPIN_ARM( 1, 1, 16); -_DEFPIN_ARM( 4, 0, 14); _DEFPIN_ARM( 5, 0, 16); _DEFPIN_ARM( 6, 0, 18); -_DEFPIN_ARM( 8, 1, 3); _DEFPIN_ARM( 9, 0, 19); _DEFPIN_ARM(10, 0, 20); _DEFPIN_ARM(11, 0, 21); -_DEFPIN_ARM(12, 0, 22); _DEFPIN_ARM(13, 0, 23); +_FL_DEFPIN( 0, 17, 1); _FL_DEFPIN( 1, 16, 1); +_FL_DEFPIN( 4, 14, 0); _FL_DEFPIN( 5, 16, 0); _FL_DEFPIN( 6, 18, 0); +_FL_DEFPIN( 8, 3, 1); _FL_DEFPIN( 9, 19, 0); _FL_DEFPIN(10, 20, 0); _FL_DEFPIN(11, 21, 0); +_FL_DEFPIN(12, 22, 0); _FL_DEFPIN(13, 23, 0); // A0-A5 -_DEFPIN_ARM(14, 0, 2); _DEFPIN_ARM(15, 0, 5); _DEFPIN_ARM(16, 1, 8); _DEFPIN_ARM(17, 1, 9); -_DEFPIN_ARM(18, 0, 4); _DEFPIN_ARM(19, 0, 6); /* A6 is present in variant.h but couldn't find it on the schematic */ +_FL_DEFPIN(14, 2, 0); _FL_DEFPIN(15, 5, 0); _FL_DEFPIN(16, 8, 1); _FL_DEFPIN(17, 9, 1); +_FL_DEFPIN(18, 4, 0); _FL_DEFPIN(19, 6, 0); /* A6 is present in variant.h but couldn't find it on the schematic */ // SDA/SCL -_DEFPIN_ARM(21, 0, 12); _DEFPIN_ARM(22, 0, 13); +_FL_DEFPIN(21, 12, 0); _FL_DEFPIN(22, 13, 0); // 23..25 MISO/MOSI/SCK -_DEFPIN_ARM(23, 1, 22); _DEFPIN_ARM(24, 1, 23); _DEFPIN_ARM(25, 0, 17); +_FL_DEFPIN(23, 22, 1); _FL_DEFPIN(24, 23, 1); _FL_DEFPIN(25, 17, 0); #define SPI_DATA 24 #define SPI_CLOCK 25 diff --git a/platforms/arm/k20/fastpin_arm_k20.h b/platforms/arm/k20/fastpin_arm_k20.h index b26e5607..54968176 100644 --- a/platforms/arm/k20/fastpin_arm_k20.h +++ b/platforms/arm/k20/fastpin_arm_k20.h @@ -78,9 +78,9 @@ public: #define _R(T) struct __gen_struct_ ## T #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \ template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } }; -#define _IO32(L) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR); +#define _FL_IO(L) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR); -#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \ +#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \ _R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; \ template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \ _R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; @@ -88,18 +88,18 @@ public: // Actual pin definitions #if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY) -_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E); +_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); #define MAX_PIN 33 -_DEFPIN_ARM(0, 16, B); _DEFPIN_ARM(1, 17, B); _DEFPIN_ARM(2, 0, D); _DEFPIN_ARM(3, 12, A); -_DEFPIN_ARM(4, 13, A); _DEFPIN_ARM(5, 7, D); _DEFPIN_ARM(6, 4, D); _DEFPIN_ARM(7, 2, D); -_DEFPIN_ARM(8, 3, D); _DEFPIN_ARM(9, 3, C); _DEFPIN_ARM(10, 4, C); _DEFPIN_ARM(11, 6, C); -_DEFPIN_ARM(12, 7, C); _DEFPIN_ARM(13, 5, C); _DEFPIN_ARM(14, 1, D); _DEFPIN_ARM(15, 0, C); -_DEFPIN_ARM(16, 0, B); _DEFPIN_ARM(17, 1, B); _DEFPIN_ARM(18, 3, B); _DEFPIN_ARM(19, 2, B); -_DEFPIN_ARM(20, 5, D); _DEFPIN_ARM(21, 6, D); _DEFPIN_ARM(22, 1, C); _DEFPIN_ARM(23, 2, C); -_DEFPIN_ARM(24, 5, A); _DEFPIN_ARM(25, 19, B); _DEFPIN_ARM(26, 1, E); _DEFPIN_ARM(27, 9, C); -_DEFPIN_ARM(28, 8, C); _DEFPIN_ARM(29, 10, C); _DEFPIN_ARM(30, 11, C); _DEFPIN_ARM(31, 0, E); -_DEFPIN_ARM(32, 18, B); _DEFPIN_ARM(33, 4, A); +_FL_DEFPIN(0, 16, B); _FL_DEFPIN(1, 17, B); _FL_DEFPIN(2, 0, D); _FL_DEFPIN(3, 12, A); +_FL_DEFPIN(4, 13, A); _FL_DEFPIN(5, 7, D); _FL_DEFPIN(6, 4, D); _FL_DEFPIN(7, 2, D); +_FL_DEFPIN(8, 3, D); _FL_DEFPIN(9, 3, C); _FL_DEFPIN(10, 4, C); _FL_DEFPIN(11, 6, C); +_FL_DEFPIN(12, 7, C); _FL_DEFPIN(13, 5, C); _FL_DEFPIN(14, 1, D); _FL_DEFPIN(15, 0, C); +_FL_DEFPIN(16, 0, B); _FL_DEFPIN(17, 1, B); _FL_DEFPIN(18, 3, B); _FL_DEFPIN(19, 2, B); +_FL_DEFPIN(20, 5, D); _FL_DEFPIN(21, 6, D); _FL_DEFPIN(22, 1, C); _FL_DEFPIN(23, 2, C); +_FL_DEFPIN(24, 5, A); _FL_DEFPIN(25, 19, B); _FL_DEFPIN(26, 1, E); _FL_DEFPIN(27, 9, C); +_FL_DEFPIN(28, 8, C); _FL_DEFPIN(29, 10, C); _FL_DEFPIN(30, 11, C); _FL_DEFPIN(31, 0, E); +_FL_DEFPIN(32, 18, B); _FL_DEFPIN(33, 4, A); #define SPI_DATA 11 #define SPI_CLOCK 13 diff --git a/platforms/arm/k66/fastpin_arm_k66.h b/platforms/arm/k66/fastpin_arm_k66.h index e201096c..92471936 100644 --- a/platforms/arm/k66/fastpin_arm_k66.h +++ b/platforms/arm/k66/fastpin_arm_k66.h @@ -78,9 +78,9 @@ public: #define _R(T) struct __gen_struct_ ## T #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \ template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } }; -#define _IO32(L) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR); +#define _FL_IO(L) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR); -#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \ +#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \ _R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; \ template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \ _R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; @@ -88,25 +88,25 @@ public: // Actual pin definitions #if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY) -_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E); +_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); #define MAX_PIN 63 -_DEFPIN_ARM( 0, 16, B); _DEFPIN_ARM( 1, 17, B); _DEFPIN_ARM( 2, 0, D); _DEFPIN_ARM( 3, 12, A); -_DEFPIN_ARM( 4, 13, A); _DEFPIN_ARM( 5, 7, D); _DEFPIN_ARM( 6, 4, D); _DEFPIN_ARM( 7, 2, D); -_DEFPIN_ARM( 8, 3, D); _DEFPIN_ARM( 9, 3, C); _DEFPIN_ARM(10, 4, C); _DEFPIN_ARM(11, 6, C); -_DEFPIN_ARM(12, 7, C); _DEFPIN_ARM(13, 5, C); _DEFPIN_ARM(14, 1, D); _DEFPIN_ARM(15, 0, C); -_DEFPIN_ARM(16, 0, B); _DEFPIN_ARM(17, 1, B); _DEFPIN_ARM(18, 3, B); _DEFPIN_ARM(19, 2, B); -_DEFPIN_ARM(20, 5, D); _DEFPIN_ARM(21, 6, D); _DEFPIN_ARM(22, 1, C); _DEFPIN_ARM(23, 2, C); -_DEFPIN_ARM(24, 26, E); _DEFPIN_ARM(25, 5, A); _DEFPIN_ARM(26, 14, A); _DEFPIN_ARM(27, 15, A); -_DEFPIN_ARM(28, 16, A); _DEFPIN_ARM(29, 18, B); _DEFPIN_ARM(30, 19, B); _DEFPIN_ARM(31, 10, B); -_DEFPIN_ARM(32, 11, B); _DEFPIN_ARM(33, 24, E); _DEFPIN_ARM(34, 25, E); _DEFPIN_ARM(35, 8, C); -_DEFPIN_ARM(36, 9, C); _DEFPIN_ARM(37, 10, C); _DEFPIN_ARM(38, 11, C); _DEFPIN_ARM(39, 17, A); -_DEFPIN_ARM(40, 28, A); _DEFPIN_ARM(41, 29, A); _DEFPIN_ARM(42, 26, A); _DEFPIN_ARM(43, 20, B); -_DEFPIN_ARM(44, 22, B); _DEFPIN_ARM(45, 23, B); _DEFPIN_ARM(46, 21, B); _DEFPIN_ARM(47, 8, D); -_DEFPIN_ARM(48, 9, D); _DEFPIN_ARM(49, 4, B); _DEFPIN_ARM(50, 5, B); _DEFPIN_ARM(51, 14, D); -_DEFPIN_ARM(52, 13, D); _DEFPIN_ARM(53, 12, D); _DEFPIN_ARM(54, 15, D); _DEFPIN_ARM(55, 11, D); -_DEFPIN_ARM(56, 10, E); _DEFPIN_ARM(57, 11, E); _DEFPIN_ARM(58, 0, E); _DEFPIN_ARM(59, 1, E); -_DEFPIN_ARM(60, 2, E); _DEFPIN_ARM(61, 3, E); _DEFPIN_ARM(62, 4, E); _DEFPIN_ARM(63, 5, E); +_FL_DEFPIN( 0, 16, B); _FL_DEFPIN( 1, 17, B); _FL_DEFPIN( 2, 0, D); _FL_DEFPIN( 3, 12, A); +_FL_DEFPIN( 4, 13, A); _FL_DEFPIN( 5, 7, D); _FL_DEFPIN( 6, 4, D); _FL_DEFPIN( 7, 2, D); +_FL_DEFPIN( 8, 3, D); _FL_DEFPIN( 9, 3, C); _FL_DEFPIN(10, 4, C); _FL_DEFPIN(11, 6, C); +_FL_DEFPIN(12, 7, C); _FL_DEFPIN(13, 5, C); _FL_DEFPIN(14, 1, D); _FL_DEFPIN(15, 0, C); +_FL_DEFPIN(16, 0, B); _FL_DEFPIN(17, 1, B); _FL_DEFPIN(18, 3, B); _FL_DEFPIN(19, 2, B); +_FL_DEFPIN(20, 5, D); _FL_DEFPIN(21, 6, D); _FL_DEFPIN(22, 1, C); _FL_DEFPIN(23, 2, C); +_FL_DEFPIN(24, 26, E); _FL_DEFPIN(25, 5, A); _FL_DEFPIN(26, 14, A); _FL_DEFPIN(27, 15, A); +_FL_DEFPIN(28, 16, A); _FL_DEFPIN(29, 18, B); _FL_DEFPIN(30, 19, B); _FL_DEFPIN(31, 10, B); +_FL_DEFPIN(32, 11, B); _FL_DEFPIN(33, 24, E); _FL_DEFPIN(34, 25, E); _FL_DEFPIN(35, 8, C); +_FL_DEFPIN(36, 9, C); _FL_DEFPIN(37, 10, C); _FL_DEFPIN(38, 11, C); _FL_DEFPIN(39, 17, A); +_FL_DEFPIN(40, 28, A); _FL_DEFPIN(41, 29, A); _FL_DEFPIN(42, 26, A); _FL_DEFPIN(43, 20, B); +_FL_DEFPIN(44, 22, B); _FL_DEFPIN(45, 23, B); _FL_DEFPIN(46, 21, B); _FL_DEFPIN(47, 8, D); +_FL_DEFPIN(48, 9, D); _FL_DEFPIN(49, 4, B); _FL_DEFPIN(50, 5, B); _FL_DEFPIN(51, 14, D); +_FL_DEFPIN(52, 13, D); _FL_DEFPIN(53, 12, D); _FL_DEFPIN(54, 15, D); _FL_DEFPIN(55, 11, D); +_FL_DEFPIN(56, 10, E); _FL_DEFPIN(57, 11, E); _FL_DEFPIN(58, 0, E); _FL_DEFPIN(59, 1, E); +_FL_DEFPIN(60, 2, E); _FL_DEFPIN(61, 3, E); _FL_DEFPIN(62, 4, E); _FL_DEFPIN(63, 5, E); diff --git a/platforms/arm/kl26/fastpin_arm_kl26.h b/platforms/arm/kl26/fastpin_arm_kl26.h index 4c30cd78..b66948cd 100644 --- a/platforms/arm/kl26/fastpin_arm_kl26.h +++ b/platforms/arm/kl26/fastpin_arm_kl26.h @@ -50,9 +50,9 @@ public: #define _R(T) struct __gen_struct_ ## T #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \ template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } }; -#define _IO32(L) _RD32(FGPIO ## L ## _PDOR); _RD32(FGPIO ## L ## _PSOR); _RD32(FGPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(FGPIO ## L ## _PDIR); _RD32(FGPIO ## L ## _PDDR); +#define _FL_IO(L) _RD32(FGPIO ## L ## _PDOR); _RD32(FGPIO ## L ## _PSOR); _RD32(FGPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(FGPIO ## L ## _PDIR); _RD32(FGPIO ## L ## _PDDR); -#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(FGPIO ## L ## _PDOR), _R(FGPIO ## L ## _PSOR), _R(FGPIO ## L ## _PCOR), \ +#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(FGPIO ## L ## _PDOR), _R(FGPIO ## L ## _PSOR), _R(FGPIO ## L ## _PCOR), \ _R(GPIO ## L ## _PTOR), _R(FGPIO ## L ## _PDIR), _R(FGPIO ## L ## _PDDR)> {}; \ /* template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \ _R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; */ @@ -60,16 +60,16 @@ _R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; */ // Actual pin definitions #if defined(FASTLED_TEENSYLC) && defined(CORE_TEENSY) -_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E); +_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); #define MAX_PIN 26 -_DEFPIN_ARM(0, 16, B); _DEFPIN_ARM(1, 17, B); _DEFPIN_ARM(2, 0, D); _DEFPIN_ARM(3, 1, A); -_DEFPIN_ARM(4, 2, A); _DEFPIN_ARM(5, 7, D); _DEFPIN_ARM(6, 4, D); _DEFPIN_ARM(7, 2, D); -_DEFPIN_ARM(8, 3, D); _DEFPIN_ARM(9, 3, C); _DEFPIN_ARM(10, 4, C); _DEFPIN_ARM(11, 6, C); -_DEFPIN_ARM(12, 7, C); _DEFPIN_ARM(13, 5, C); _DEFPIN_ARM(14, 1, D); _DEFPIN_ARM(15, 0, C); -_DEFPIN_ARM(16, 0, B); _DEFPIN_ARM(17, 1, B); _DEFPIN_ARM(18, 3, B); _DEFPIN_ARM(19, 2, B); -_DEFPIN_ARM(20, 5, D); _DEFPIN_ARM(21, 6, D); _DEFPIN_ARM(22, 1, C); _DEFPIN_ARM(23, 2, C); -_DEFPIN_ARM(24, 20, E); _DEFPIN_ARM(25, 21, E); _DEFPIN_ARM(26, 30, E); +_FL_DEFPIN(0, 16, B); _FL_DEFPIN(1, 17, B); _FL_DEFPIN(2, 0, D); _FL_DEFPIN(3, 1, A); +_FL_DEFPIN(4, 2, A); _FL_DEFPIN(5, 7, D); _FL_DEFPIN(6, 4, D); _FL_DEFPIN(7, 2, D); +_FL_DEFPIN(8, 3, D); _FL_DEFPIN(9, 3, C); _FL_DEFPIN(10, 4, C); _FL_DEFPIN(11, 6, C); +_FL_DEFPIN(12, 7, C); _FL_DEFPIN(13, 5, C); _FL_DEFPIN(14, 1, D); _FL_DEFPIN(15, 0, C); +_FL_DEFPIN(16, 0, B); _FL_DEFPIN(17, 1, B); _FL_DEFPIN(18, 3, B); _FL_DEFPIN(19, 2, B); +_FL_DEFPIN(20, 5, D); _FL_DEFPIN(21, 6, D); _FL_DEFPIN(22, 1, C); _FL_DEFPIN(23, 2, C); +_FL_DEFPIN(24, 20, E); _FL_DEFPIN(25, 21, E); _FL_DEFPIN(26, 30, E); #define SPI_DATA 11 #define SPI_CLOCK 13 diff --git a/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h b/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h index e1b15674..6ee6d8f6 100644 --- a/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h +++ b/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h @@ -45,30 +45,30 @@ public: #define _R(T) struct __gen_struct_ ## T #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } }; -#define _IO32(L) _RD32(GPIO ## L ## _DR); _RD32(GPIO ## L ## _DR_SET); _RD32(GPIO ## L ## _DR_CLEAR); _RD32(GPIO ## L ## _DR_TOGGLE); +#define _FL_IO(L) _RD32(GPIO ## L ## _DR); _RD32(GPIO ## L ## _DR_SET); _RD32(GPIO ## L ## _DR_CLEAR); _RD32(GPIO ## L ## _DR_TOGGLE); // From the teensy core - it looks like there's the "default set" of port registers at GPIO1-5 - but then there // are a mirrored set for GPIO1-4 at GPIO6-9, which in the teensy core is referred to as "fast" - while the pin definitiosn // at https://forum.pjrc.com/threads/54711-Teensy-4-0-First-Beta-Test?p=193716&viewfull=1#post193716 // refer to GPIO1-4, we're going to use GPIO6-9 in the definitions below because the fast registers are what // the teensy core is using internally -#define _DEFPIN_T4(PIN, L, BIT) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L ## _DR), _R(GPIO ## L ## _DR_SET), _R(GPIO ## L ## _DR_CLEAR), _R(GPIO ## L ## _DR_TOGGLE)> {}; +#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L ## _DR), _R(GPIO ## L ## _DR_SET), _R(GPIO ## L ## _DR_CLEAR), _R(GPIO ## L ## _DR_TOGGLE)> {}; #if defined(FASTLED_TEENSY4) && defined(CORE_TEENSY) -_IO32(1); _IO32(2); _IO32(3); _IO32(4); _IO32(5); -_IO32(6); _IO32(7); _IO32(8); _IO32(9); +_FL_IO(1); _FL_IO(2); _FL_IO(3); _FL_IO(4); _FL_IO(5); +_FL_IO(6); _FL_IO(7); _FL_IO(8); _FL_IO(9); #define MAX_PIN 39 -_DEFPIN_T4( 0,6, 3); _DEFPIN_T4( 1,6, 2); _DEFPIN_T4( 2,9, 4); _DEFPIN_T4( 3,9, 5); -_DEFPIN_T4( 4,9, 6); _DEFPIN_T4( 5,9, 8); _DEFPIN_T4( 6,7,10); _DEFPIN_T4( 7,7,17); -_DEFPIN_T4( 8,7,16); _DEFPIN_T4( 9,7,11); _DEFPIN_T4(10,7, 0); _DEFPIN_T4(11,7, 2); -_DEFPIN_T4(12,7, 1); _DEFPIN_T4(13,7, 3); _DEFPIN_T4(14,6,18); _DEFPIN_T4(15,6,19); -_DEFPIN_T4(16,6,23); _DEFPIN_T4(17,6,22); _DEFPIN_T4(18,6,17); _DEFPIN_T4(19,6,16); -_DEFPIN_T4(20,6,26); _DEFPIN_T4(21,6,27); _DEFPIN_T4(22,6,24); _DEFPIN_T4(23,6,25); -_DEFPIN_T4(24,6,12); _DEFPIN_T4(25,6,13); _DEFPIN_T4(26,6,30); _DEFPIN_T4(27,6,31); -_DEFPIN_T4(28,8,18); _DEFPIN_T4(29,9,31); _DEFPIN_T4(30,8,23); _DEFPIN_T4(31,8,22); -_DEFPIN_T4(32,7,12); _DEFPIN_T4(33,9, 7); _DEFPIN_T4(34,8,15); _DEFPIN_T4(35,8,14); -_DEFPIN_T4(36,8,13); _DEFPIN_T4(37,8,12); _DEFPIN_T4(38,8,17); _DEFPIN_T4(39,8,16); +_FL_DEFPIN( 0, 3,6); _FL_DEFPIN( 1, 2,6); _FL_DEFPIN( 2, 4,9); _FL_DEFPIN( 3, 5,9); +_FL_DEFPIN( 4, 6,9); _FL_DEFPIN( 5, 8,9); _FL_DEFPIN( 6,10,7); _FL_DEFPIN( 7,17,7); +_FL_DEFPIN( 8,16,7); _FL_DEFPIN( 9,11,7); _FL_DEFPIN(10, 0,7); _FL_DEFPIN(11, 2,7); +_FL_DEFPIN(12, 1,7); _FL_DEFPIN(13, 3,7); _FL_DEFPIN(14,18,6); _FL_DEFPIN(15,19,6); +_FL_DEFPIN(16,23,6); _FL_DEFPIN(17,22,6); _FL_DEFPIN(18,17,6); _FL_DEFPIN(19,16,6); +_FL_DEFPIN(20,26,6); _FL_DEFPIN(21,27,6); _FL_DEFPIN(22,24,6); _FL_DEFPIN(23,25,6); +_FL_DEFPIN(24,12,6); _FL_DEFPIN(25,13,6); _FL_DEFPIN(26,30,6); _FL_DEFPIN(27,31,6); +_FL_DEFPIN(28,18,8); _FL_DEFPIN(29,31,9); _FL_DEFPIN(30,23,8); _FL_DEFPIN(31,22,8); +_FL_DEFPIN(32,12,7); _FL_DEFPIN(33, 7,9); _FL_DEFPIN(34,15,8); _FL_DEFPIN(35,14,8); +_FL_DEFPIN(36,13,8); _FL_DEFPIN(37,12,8); _FL_DEFPIN(38,17,8); _FL_DEFPIN(39,16,8); #define HAS_HARDWARE_PIN_SUPPORT diff --git a/platforms/arm/nrf51/fastpin_arm_nrf51.h b/platforms/arm/nrf51/fastpin_arm_nrf51.h index 4125f9a3..3d02edc1 100644 --- a/platforms/arm/nrf51/fastpin_arm_nrf51.h +++ b/platforms/arm/nrf51/fastpin_arm_nrf51.h @@ -49,7 +49,7 @@ _RD32_NRF(NR_OUTSET); _RD32_NRF(NR_OUTCLR); _RD32_NRF(NR_OUT); -#define _DEFPIN_ARM(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN, \ +#define _FL_DEFPIN(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN, \ _R(NR_DIRSET), _R(NR_DIRCLR), _R(NR_OUTSET), _R(NR_OUTCLR), _R(NR_OUT)> {}; #else @@ -98,19 +98,19 @@ public: }; -#define _DEFPIN_ARM(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN> {}; +#define _FL_DEFPIN(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN> {}; #endif // Actual pin definitions #define MAX_PIN 31 -_DEFPIN_ARM(0); _DEFPIN_ARM(1); _DEFPIN_ARM(2); _DEFPIN_ARM(3); -_DEFPIN_ARM(4); _DEFPIN_ARM(5); _DEFPIN_ARM(6); _DEFPIN_ARM(7); -_DEFPIN_ARM(8); _DEFPIN_ARM(9); _DEFPIN_ARM(10); _DEFPIN_ARM(11); -_DEFPIN_ARM(12); _DEFPIN_ARM(13); _DEFPIN_ARM(14); _DEFPIN_ARM(15); -_DEFPIN_ARM(16); _DEFPIN_ARM(17); _DEFPIN_ARM(18); _DEFPIN_ARM(19); -_DEFPIN_ARM(20); _DEFPIN_ARM(21); _DEFPIN_ARM(22); _DEFPIN_ARM(23); -_DEFPIN_ARM(24); _DEFPIN_ARM(25); _DEFPIN_ARM(26); _DEFPIN_ARM(27); -_DEFPIN_ARM(28); _DEFPIN_ARM(29); _DEFPIN_ARM(30); _DEFPIN_ARM(31); +_FL_DEFPIN(0); _FL_DEFPIN(1); _FL_DEFPIN(2); _FL_DEFPIN(3); +_FL_DEFPIN(4); _FL_DEFPIN(5); _FL_DEFPIN(6); _FL_DEFPIN(7); +_FL_DEFPIN(8); _FL_DEFPIN(9); _FL_DEFPIN(10); _FL_DEFPIN(11); +_FL_DEFPIN(12); _FL_DEFPIN(13); _FL_DEFPIN(14); _FL_DEFPIN(15); +_FL_DEFPIN(16); _FL_DEFPIN(17); _FL_DEFPIN(18); _FL_DEFPIN(19); +_FL_DEFPIN(20); _FL_DEFPIN(21); _FL_DEFPIN(22); _FL_DEFPIN(23); +_FL_DEFPIN(24); _FL_DEFPIN(25); _FL_DEFPIN(26); _FL_DEFPIN(27); +_FL_DEFPIN(28); _FL_DEFPIN(29); _FL_DEFPIN(30); _FL_DEFPIN(31); #define HAS_HARDWARE_PIN_SUPPORT diff --git a/platforms/arm/nrf52/fastpin_arm_nrf52.h b/platforms/arm/nrf52/fastpin_arm_nrf52.h index 60fb3594..75260004 100644 --- a/platforms/arm/nrf52/fastpin_arm_nrf52.h +++ b/platforms/arm/nrf52/fastpin_arm_nrf52.h @@ -1,13 +1,13 @@ #ifndef __FASTPIN_ARM_NRF52_H #define __FASTPIN_ARM_NRF52_H - + /* // // Background: // =========== // the nRF52 has more than 32 ports, and thus must support -// two distinct GPIO port registers. +// two distinct GPIO port registers. // // For the nRF52 series, the structure to control the port is // `NRF_GPIO_Type`, with separate addresses mapped for set, clear, etc. @@ -18,18 +18,18 @@ // #define NRF_P0 ((NRF_GPIO_Type*)NRF_P0_BASE) // #define NRF_P1 ((NRF_GPIO_Type*)NRF_P1_BASE) // -// Therefore, ideally, the _DEFPIN_ARM() macro would simply +// Therefore, ideally, the _FL_DEFPIN() macro would simply // conditionally pass either NRF_P0 or NRF_P1 to the underlying // FastPin<> template class class. // // The "pin" provided to the FastLED<> template (and which -// the _DEFPIN_ARM() macro specializes for valid pins) is NOT +// the _FL_DEFPIN() macro specializes for valid pins) is NOT // the microcontroller port.pin, but the Arduino digital pin. // Some boards have an identity mapping (e.g., nRF52832 Feather) -// but most do not. Therefore, the _DEFPIN_ARM() macro +// but most do not. Therefore, the _FL_DEFPIN() macro // must translate the Arduino pin to the mcu port.pin. // -// +// // Difficulties: // ============= // The goal is to avoid any such lookups, using compile-time @@ -281,16 +281,16 @@ public: // // BOARD_PIN can be either the pin portion of a port.pin, or the combined NRF_GPIO_PIN_MAP() number. // For example both the following two defines refer to P1.15 (pin 47) as Arduino pin 3: -// _DEFPIN_ARM(3, 1, 15); -// _DEFPIN_ARM(3, 1, 47); +// _FL_DEFPIN(3, 15, 1); +// _FL_DEFPIN(3, 47, 1); // // Similarly, the following defines are all equivalent: // _DEFPIN_ARM_IDENTITY_P1(47); -// _DEFPIN_ARM(47, 1, 15); -// _DEFPIN_ARM(47, 1, 47); +// _FL_DEFPIN(47, 15, 1); +// _FL_DEFPIN(47, 47, 1); // -#define _DEFPIN_ARM(ARDUINO_PIN, BOARD_PORT, BOARD_PIN) \ +#define FL_DEFPIN(ARDUINO_PIN, BOARD_PIN, BOARD_PORT) \ template<> class FastPin<ARDUINO_PIN> : \ public _ARMPIN< \ 1u << (BOARD_PIN & 31u), \ diff --git a/platforms/arm/nrf52/fastpin_arm_nrf52_variants.h b/platforms/arm/nrf52/fastpin_arm_nrf52_variants.h index b3b9ff99..9bb07721 100644 --- a/platforms/arm/nrf52/fastpin_arm_nrf52_variants.h +++ b/platforms/arm/nrf52/fastpin_arm_nrf52_variants.h @@ -59,48 +59,48 @@ #define MAX_PIN (33u) // 34 if wanting to use NFC1 test point // Arduino pins 0..7 - _DEFPIN_ARM( 0, 0, 25); // D0 is P0.25 -- UART TX - //_DEFPIN_ARM( 1, 0, 24); // D1 is P0.24 -- UART RX - _DEFPIN_ARM( 2, 0, 10); // D2 is P0.10 -- NFC2 - _DEFPIN_ARM( 3, 1, 47); // D3 is P1.15 -- PIN_LED1 (red) - _DEFPIN_ARM( 4, 1, 42); // D4 is P1.10 -- PIN_LED2 (blue) - _DEFPIN_ARM( 5, 1, 40); // D5 is P1.08 -- SPI/SS - _DEFPIN_ARM( 6, 0, 7); // D6 is P0.07 - _DEFPIN_ARM( 7, 1, 34); // D7 is P1.02 -- PIN_DFU (Button) + _FL_DEFPIN( 0, 25, 0); // D0 is P0.25 -- UART TX + //_FL_DEFPIN( 1, 24, 0); // D1 is P0.24 -- UART RX + _FL_DEFPIN( 2, 10, 0); // D2 is P0.10 -- NFC2 + _FL_DEFPIN( 3, 47, 1); // D3 is P1.15 -- PIN_LED1 (red) + _FL_DEFPIN( 4, 42, 1); // D4 is P1.10 -- PIN_LED2 (blue) + _FL_DEFPIN( 5, 40, 1); // D5 is P1.08 -- SPI/SS + _FL_DEFPIN( 6, 7, 0); // D6 is P0.07 + _FL_DEFPIN( 7, 34, 1); // D7 is P1.02 -- PIN_DFU (Button) // Arduino pins 8..15 - _DEFPIN_ARM( 8, 0, 16); // D8 is P0.16 -- PIN_NEOPIXEL - _DEFPIN_ARM( 9, 0, 26); // D9 is P0.26 - _DEFPIN_ARM(10, 0, 27); // D10 is P0.27 - _DEFPIN_ARM(11, 0, 6); // D11 is P0.06 - _DEFPIN_ARM(12, 0, 8); // D12 is P0.08 - _DEFPIN_ARM(13, 1, 41); // D13 is P1.09 - _DEFPIN_ARM(14, 0, 4); // D14 is P0.04 -- A0 - _DEFPIN_ARM(15, 0, 5); // D15 is P0.05 -- A1 + _FL_DEFPIN( 8, 16, 0); // D8 is P0.16 -- PIN_NEOPIXEL + _FL_DEFPIN( 9, 26, 0); // D9 is P0.26 + _FL_DEFPIN(10, 27, 0); // D10 is P0.27 + _FL_DEFPIN(11, 6, 0); // D11 is P0.06 + _FL_DEFPIN(12, 8, 0); // D12 is P0.08 + _FL_DEFPIN(13, 41, 1); // D13 is P1.09 + _FL_DEFPIN(14, 4, 0); // D14 is P0.04 -- A0 + _FL_DEFPIN(15, 5, 0); // D15 is P0.05 -- A1 // Arduino pins 16..23 - _DEFPIN_ARM(16, 0, 30); // D16 is P0.30 -- A2 - _DEFPIN_ARM(17, 0, 28); // D17 is P0.28 -- A3 - _DEFPIN_ARM(18, 0, 2); // D18 is P0.02 -- A4 - _DEFPIN_ARM(19, 0, 3); // D19 is P0.03 -- A5 - //_DEFPIN_ARM(20, 0, 29); // D20 is P0.29 -- A6 -- Connected to battery! - //_DEFPIN_ARM(21, 0, 31); // D21 is P0.31 -- A7 -- AREF - _DEFPIN_ARM(22, 0, 12); // D22 is P0.12 -- SDA - _DEFPIN_ARM(23, 0, 11); // D23 is P0.11 -- SCL + _FL_DEFPIN(16, 30, 0); // D16 is P0.30 -- A2 + _FL_DEFPIN(17, 28, 0); // D17 is P0.28 -- A3 + _FL_DEFPIN(18, 2, 0); // D18 is P0.02 -- A4 + _FL_DEFPIN(19, 3, 0); // D19 is P0.03 -- A5 + //_FL_DEFPIN(20, 29, 0); // D20 is P0.29 -- A6 -- Connected to battery! + //_FL_DEFPIN(21, 31, 0); // D21 is P0.31 -- A7 -- AREF + _FL_DEFPIN(22, 12, 0); // D22 is P0.12 -- SDA + _FL_DEFPIN(23, 11, 0); // D23 is P0.11 -- SCL // Arduino pins 24..31 - _DEFPIN_ARM(24, 0, 15); // D24 is P0.15 -- PIN_SPI_MISO - _DEFPIN_ARM(25, 0, 13); // D25 is P0.13 -- PIN_SPI_MOSI - _DEFPIN_ARM(26, 0, 14); // D26 is P0.14 -- PIN_SPI_SCK - //_DEFPIN_ARM(27, 0, 19); // D27 is P0.19 -- PIN_QSPI_SCK - //_DEFPIN_ARM(28, 0, 20); // D28 is P0.20 -- PIN_QSPI_CS - //_DEFPIN_ARM(29, 0, 17); // D29 is P0.17 -- PIN_QSPI_DATA0 - //_DEFPIN_ARM(30, 0, 22); // D30 is P0.22 -- PIN_QSPI_DATA1 - //_DEFPIN_ARM(31, 0, 23); // D31 is P0.23 -- PIN_QSPI_DATA2 + _FL_DEFPIN(24, 15, 0); // D24 is P0.15 -- PIN_SPI_MISO + _FL_DEFPIN(25, 13, 0); // D25 is P0.13 -- PIN_SPI_MOSI + _FL_DEFPIN(26, 14, 0); // D26 is P0.14 -- PIN_SPI_SCK + //_FL_DEFPIN(27, 19, 0); // D27 is P0.19 -- PIN_QSPI_SCK + //_FL_DEFPIN(28, 20, 0); // D28 is P0.20 -- PIN_QSPI_CS + //_FL_DEFPIN(29, 17, 0); // D29 is P0.17 -- PIN_QSPI_DATA0 + //_FL_DEFPIN(30, 22, 0); // D30 is P0.22 -- PIN_QSPI_DATA1 + //_FL_DEFPIN(31, 23, 0); // D31 is P0.23 -- PIN_QSPI_DATA2 // Arduino pins 32..34 - //_DEFPIN_ARM(32, 0, 21); // D32 is P0.21 -- PIN_QSPI_DATA3 - //_DEFPIN_ARM(33, 0, 9); // D33 is NFC1, only accessible via test point + //_FL_DEFPIN(32, 21, 0); // D32 is P0.21 -- PIN_QSPI_DATA3 + //_FL_DEFPIN(33, 9, 0); // D33 is NFC1, only accessible via test point #endif // defined (ARDUINO_NRF52840_FEATHER) // Adafruit Bluefruit nRF52840 Metro Express @@ -113,46 +113,46 @@ #endif #warning "Adafruit Bluefruit nRF52840 Metro Express is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues" - _DEFPIN_ARM( 0, 0, 25); // D0 is P0.25 (UART TX) - _DEFPIN_ARM( 1, 0, 24); // D1 is P0.24 (UART RX) - _DEFPIN_ARM( 2, 1, 10); // D2 is P1.10 - _DEFPIN_ARM( 3, 1, 4); // D3 is P1.04 - _DEFPIN_ARM( 4, 1, 11); // D4 is P1.11 - _DEFPIN_ARM( 5, 1, 12); // D5 is P1.12 - _DEFPIN_ARM( 6, 1, 14); // D6 is P1.14 - _DEFPIN_ARM( 7, 0, 26); // D7 is P0.26 - _DEFPIN_ARM( 8, 0, 27); // D8 is P0.27 - _DEFPIN_ARM( 9, 0, 12); // D9 is P0.12 - _DEFPIN_ARM(10, 0, 6); // D10 is P0.06 - _DEFPIN_ARM(11, 0, 8); // D11 is P0.08 - _DEFPIN_ARM(12, 1, 9); // D12 is P1.09 - _DEFPIN_ARM(13, 0, 14); // D13 is P0.14 - _DEFPIN_ARM(14, 0, 4); // D14 is P0.04 (A0) - _DEFPIN_ARM(15, 0, 5); // D15 is P0.05 (A1) - _DEFPIN_ARM(16, 0, 28); // D16 is P0.28 (A2) - _DEFPIN_ARM(17, 0, 30); // D17 is P0.30 (A3) - _DEFPIN_ARM(18, 0, 2); // D18 is P0.02 (A4) - _DEFPIN_ARM(19, 0, 3); // D19 is P0.03 (A5) - _DEFPIN_ARM(20, 0, 29); // D20 is P0.29 (A6, battery) - _DEFPIN_ARM(21, 0, 31); // D21 is P0.31 (A7, ARef) - _DEFPIN_ARM(22, 0, 15); // D22 is P0.15 (SDA) - _DEFPIN_ARM(23, 0, 16); // D23 is P0.16 (SCL) - _DEFPIN_ARM(24, 0, 11); // D24 is P0.11 (SPI MISO) - _DEFPIN_ARM(25, 1, 8); // D25 is P1.08 (SPI MOSI) - _DEFPIN_ARM(26, 0, 7); // D26 is P0.07 (SPI SCK ) - //_DEFPIN_ARM(27, 0, 19); // D27 is P0.19 (QSPI CLK ) - //_DEFPIN_ARM(28, 0, 20); // D28 is P0.20 (QSPI CS ) - //_DEFPIN_ARM(29, 0, 17); // D29 is P0.17 (QSPI Data 0) - //_DEFPIN_ARM(30, 0, 23); // D30 is P0.23 (QSPI Data 1) - //_DEFPIN_ARM(31, 0, 22); // D31 is P0.22 (QSPI Data 2) - //_DEFPIN_ARM(32, 0, 21); // D32 is P0.21 (QSPI Data 3) - _DEFPIN_ARM(33, 1, 13); // D33 is P1.13 LED1 - _DEFPIN_ARM(34, 1, 15); // D34 is P1.15 LED2 - _DEFPIN_ARM(35, 0, 13); // D35 is P0.13 NeoPixel - _DEFPIN_ARM(36, 1, 0); // D36 is P1.02 Switch - _DEFPIN_ARM(37, 1, 0); // D37 is P1.00 SWO/DFU - _DEFPIN_ARM(38, 0, 9); // D38 is P0.09 NFC1 - _DEFPIN_ARM(39, 0, 10); // D39 is P0.10 NFC2 + _FL_DEFPIN( 0, 25, 0); // D0 is P0.25 (UART TX) + _FL_DEFPIN( 1, 24, 0); // D1 is P0.24 (UART RX) + _FL_DEFPIN( 2, 10, 1); // D2 is P1.10 + _FL_DEFPIN( 3, 4, 1); // D3 is P1.04 + _FL_DEFPIN( 4, 11, 1); // D4 is P1.11 + _FL_DEFPIN( 5, 12, 1); // D5 is P1.12 + _FL_DEFPIN( 6, 14, 1); // D6 is P1.14 + _FL_DEFPIN( 7, 26, 0); // D7 is P0.26 + _FL_DEFPIN( 8, 27, 0); // D8 is P0.27 + _FL_DEFPIN( 9, 12, 0); // D9 is P0.12 + _FL_DEFPIN(10, 6, 0); // D10 is P0.06 + _FL_DEFPIN(11, 8, 0); // D11 is P0.08 + _FL_DEFPIN(12, 9, 1); // D12 is P1.09 + _FL_DEFPIN(13, 14, 0); // D13 is P0.14 + _FL_DEFPIN(14, 4, 0); // D14 is P0.04 (A0) + _FL_DEFPIN(15, 5, 0); // D15 is P0.05 (A1) + _FL_DEFPIN(16, 28, 0); // D16 is P0.28 (A2) + _FL_DEFPIN(17, 30, 0); // D17 is P0.30 (A3) + _FL_DEFPIN(18, 2, 0); // D18 is P0.02 (A4) + _FL_DEFPIN(19, 3, 0); // D19 is P0.03 (A5) + _FL_DEFPIN(20, 29, 0); // D20 is P0.29 (A6, battery) + _FL_DEFPIN(21, 31, 0); // D21 is P0.31 (A7, ARef) + _FL_DEFPIN(22, 15, 0); // D22 is P0.15 (SDA) + _FL_DEFPIN(23, 16, 0); // D23 is P0.16 (SCL) + _FL_DEFPIN(24, 11, 0); // D24 is P0.11 (SPI MISO) + _FL_DEFPIN(25, 8, 1); // D25 is P1.08 (SPI MOSI) + _FL_DEFPIN(26, 7, 0); // D26 is P0.07 (SPI SCK ) + //_FL_DEFPIN(27, 19, 0); // D27 is P0.19 (QSPI CLK ) + //_FL_DEFPIN(28, 20, 0); // D28 is P0.20 (QSPI CS ) + //_FL_DEFPIN(29, 17, 0); // D29 is P0.17 (QSPI Data 0) + //_FL_DEFPIN(30, 23, 0); // D30 is P0.23 (QSPI Data 1) + //_FL_DEFPIN(31, 22, 0); // D31 is P0.22 (QSPI Data 2) + //_FL_DEFPIN(32, 21, 0); // D32 is P0.21 (QSPI Data 3) + _FL_DEFPIN(33, 13, 1); // D33 is P1.13 LED1 + _FL_DEFPIN(34, 15, 1); // D34 is P1.15 LED2 + _FL_DEFPIN(35, 13, 0); // D35 is P0.13 NeoPixel + _FL_DEFPIN(36, 0, 1); // D36 is P1.02 Switch + _FL_DEFPIN(37, 0, 1); // D37 is P1.00 SWO/DFU + _FL_DEFPIN(38, 9, 0); // D38 is P0.09 NFC1 + _FL_DEFPIN(39, 10, 0); // D39 is P0.10 NFC2 #endif // defined (ARDUINO_NRF52840_METRO) // Adafruit Bluefruit on nRF52840DK PCA10056 @@ -169,52 +169,52 @@ /* pca10056_schematic_and_pcb.pdf Page 3 shows the Arduino Pin to GPIO Px.xx mapping */ - _DEFPIN_ARM( 0, 1, 1); // D0 is P1.01 - _DEFPIN_ARM( 1, 1, 2); // D1 is P1.02 - _DEFPIN_ARM( 2, 1, 3); // D2 is P1.03 - _DEFPIN_ARM( 3, 1, 4); // D3 is P1.04 - _DEFPIN_ARM( 4, 1, 5); // D4 is P1.05 - _DEFPIN_ARM( 5, 1, 6); // D5 is P1.06 - _DEFPIN_ARM( 6, 1, 7); // D6 is P1.07 (BUTTON1 option) - _DEFPIN_ARM( 7, 1, 8); // D7 is P1.08 (BUTTON2 option) - _DEFPIN_ARM( 8, 1, 10); // D8 is P1.10 - _DEFPIN_ARM( 9, 1, 11); // D9 is P1.11 - _DEFPIN_ARM(10, 1, 12); // D10 is P1.12 - _DEFPIN_ARM(11, 1, 13); // D11 is P1.13 - _DEFPIN_ARM(12, 1, 14); // D12 is P1.14 - _DEFPIN_ARM(13, 1, 15); // D13 is P1.15 - _DEFPIN_ARM(14, 0, 0); // D14 is P0.00 (if SB4 bridged) - _DEFPIN_ARM(15, 0, 1); // D15 is P0.01 (if SB3 bridged) - _DEFPIN_ARM(16, 0, 5); // D16 is P0.05 (aka AIN3, aka UART RTS) - _DEFPIN_ARM(17, 0, 6); // D17 is P0.06 (UART TxD) - _DEFPIN_ARM(18, 0, 7); // D18 is P0.07 (UART CTS default) - _DEFPIN_ARM(19, 0, 8); // D19 is P0.08 (UART RxD) - _DEFPIN_ARM(20, 0, 9); // D20 is P0.09 (NFC1) - _DEFPIN_ARM(21, 0, 10); // D21 is P0.10 (NFC2) - _DEFPIN_ARM(22, 0, 11); // D22 is P0.11 (TRACEDATA2 / BUTTON1 default) - _DEFPIN_ARM(23, 0, 12); // D23 is P0.12 (TRACEDATA1 / BUTTON2 default) - _DEFPIN_ARM(24, 0, 13); // D24 is P0.13 (LED1) - _DEFPIN_ARM(25, 0, 14); // D25 is P0.14 (LED2) - _DEFPIN_ARM(26, 0, 15); // D26 is P0.15 (LED3) - _DEFPIN_ARM(27, 0, 16); // D27 is P0.16 (LED4) - _DEFPIN_ARM(28, 0, 17); // D28 is P0.17 (QSPI !CS , unless SB13 cut) - // _DEFPIN_ARM(29, 0, 18); // D29 is P0.18 (RESET) - _DEFPIN_ARM(30, 0, 19); // D30 is P0.19 (QSPI CLK , unless SB11 cut) - _DEFPIN_ARM(31, 0, 20); // D31 is P0.20 (QSPI DIO0, unless SB12 cut) - _DEFPIN_ARM(32, 0, 21); // D32 is P0.21 (QSPI DIO1, unless SB14 cut) - _DEFPIN_ARM(33, 0, 22); // D33 is P0.22 (QSPI DIO2, unless SB15 cut) - _DEFPIN_ARM(34, 0, 23); // D34 is P0.23 (QSPI DIO3, unless SB10 cut) - _DEFPIN_ARM(35, 0, 24); // D35 is P0.24 (BUTTON3) - _DEFPIN_ARM(36, 0, 25); // D36 is P0.25 (BUTTON4) - _DEFPIN_ARM(37, 1, 00); // D37 is P1.00 (TRACEDATA0 / SWO) - _DEFPIN_ARM(38, 1, 09); // D38 is P1.09 (TRACEDATA3) - //_DEFPIN_ARM(??, 0, 2); // D?? is P0.02 (AREF, aka AIN0) - //_DEFPIN_ARM(??, 0, 3); // D?? is P0.03 (A0, aka AIN1) - //_DEFPIN_ARM(??, 0, 4); // D?? is P0.04 (A1, aka AIN2, aka UART CTS option) - //_DEFPIN_ARM(??, 0, 28); // D?? is P0.28 (A2, aka AIN4) - //_DEFPIN_ARM(??, 0, 29); // D?? is P0.29 (A3, aka AIN5) - //_DEFPIN_ARM(??, 0, 30); // D?? is P0.30 (A4, aka AIN6) - //_DEFPIN_ARM(??, 0, 31); // D?? is P0.31 (A5, aka AIN7) + _FL_DEFPIN( 0, 1, 1); // D0 is P1.01 + _FL_DEFPIN( 1, 2, 1); // D1 is P1.02 + _FL_DEFPIN( 2, 3, 1); // D2 is P1.03 + _FL_DEFPIN( 3, 4, 1); // D3 is P1.04 + _FL_DEFPIN( 4, 5, 1); // D4 is P1.05 + _FL_DEFPIN( 5, 6, 1); // D5 is P1.06 + _FL_DEFPIN( 6, 7, 1); // D6 is P1.07 (BUTTON1 option) + _FL_DEFPIN( 7, 8, 1); // D7 is P1.08 (BUTTON2 option) + _FL_DEFPIN( 8, 10, 1); // D8 is P1.10 + _FL_DEFPIN( 9, 11, 1); // D9 is P1.11 + _FL_DEFPIN(10, 12, 1); // D10 is P1.12 + _FL_DEFPIN(11, 13, 1); // D11 is P1.13 + _FL_DEFPIN(12, 14, 1); // D12 is P1.14 + _FL_DEFPIN(13, 15, 1); // D13 is P1.15 + _FL_DEFPIN(14, 0, 0); // D14 is P0.00 (if SB4 bridged) + _FL_DEFPIN(15, 1, 0); // D15 is P0.01 (if SB3 bridged) + _FL_DEFPIN(16, 5, 0); // D16 is P0.05 (aka AIN3, aka UART RTS) + _FL_DEFPIN(17, 6, 0); // D17 is P0.06 (UART TxD) + _FL_DEFPIN(18, 7, 0); // D18 is P0.07 (UART CTS default) + _FL_DEFPIN(19, 8, 0); // D19 is P0.08 (UART RxD) + _FL_DEFPIN(20, 9, 0); // D20 is P0.09 (NFC1) + _FL_DEFPIN(21, 10, 0); // D21 is P0.10 (NFC2) + _FL_DEFPIN(22, 11, 0); // D22 is P0.11 (TRACEDATA2 / BUTTON1 default) + _FL_DEFPIN(23, 12, 0); // D23 is P0.12 (TRACEDATA1 / BUTTON2 default) + _FL_DEFPIN(24, 13, 0); // D24 is P0.13 (LED1) + _FL_DEFPIN(25, 14, 0); // D25 is P0.14 (LED2) + _FL_DEFPIN(26, 15, 0); // D26 is P0.15 (LED3) + _FL_DEFPIN(27, 16, 0); // D27 is P0.16 (LED4) + _FL_DEFPIN(28, 17, 0); // D28 is P0.17 (QSPI !CS , unless SB13 cut) + // _FL_DEFPIN(29, 18, 0); // D29 is P0.18 (RESET) + _FL_DEFPIN(30, 19, 0); // D30 is P0.19 (QSPI CLK , unless SB11 cut) + _FL_DEFPIN(31, 20, 0); // D31 is P0.20 (QSPI DIO0, unless SB12 cut) + _FL_DEFPIN(32, 21, 0); // D32 is P0.21 (QSPI DIO1, unless SB14 cut) + _FL_DEFPIN(33, 22, 0); // D33 is P0.22 (QSPI DIO2, unless SB15 cut) + _FL_DEFPIN(34, 23, 0); // D34 is P0.23 (QSPI DIO3, unless SB10 cut) + _FL_DEFPIN(35, 24, 0); // D35 is P0.24 (BUTTON3) + _FL_DEFPIN(36, 25, 0); // D36 is P0.25 (BUTTON4) + _FL_DEFPIN(37, 00, 1); // D37 is P1.00 (TRACEDATA0 / SWO) + _FL_DEFPIN(38, 09, 1); // D38 is P1.09 (TRACEDATA3) + //_FL_DEFPIN(??, 2, 0); // D?? is P0.02 (AREF, aka AIN0) + //_FL_DEFPIN(??, 3, 0); // D?? is P0.03 (A0, aka AIN1) + //_FL_DEFPIN(??, 4, 0); // D?? is P0.04 (A1, aka AIN2, aka UART CTS option) + //_FL_DEFPIN(??, 28, 0); // D?? is P0.28 (A2, aka AIN4) + //_FL_DEFPIN(??, 29, 0); // D?? is P0.29 (A3, aka AIN5) + //_FL_DEFPIN(??, 30, 0); // D?? is P0.30 (A4, aka AIN6) + //_FL_DEFPIN(??, 31, 0); // D?? is P0.31 (A5, aka AIN7) #else /* 48 pins, defined using natural mapping in Adafruit's variant.cpp (!) */ @@ -279,33 +279,33 @@ #endif #warning "Electronut labs bluey is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues" - _DEFPIN_ARM( 0, 0, 26); // D0 is P0.26 - _DEFPIN_ARM( 1, 0, 27); // D1 is P0.27 - _DEFPIN_ARM( 2, 0, 22); // D2 is P0.22 (SPI SS ) - _DEFPIN_ARM( 3, 0, 23); // D3 is P0.23 (SPI MOSI) - _DEFPIN_ARM( 4, 0, 24); // D4 is P0.24 (SPI MISO, also A3) - _DEFPIN_ARM( 5, 0, 25); // D5 is P0.25 (SPI SCK ) - _DEFPIN_ARM( 6, 0, 16); // D6 is P0.16 (Button) - _DEFPIN_ARM( 7, 0, 19); // D7 is P0.19 (R) - _DEFPIN_ARM( 8, 0, 18); // D8 is P0.18 (G) - _DEFPIN_ARM( 9, 0, 17); // D9 is P0.17 (B) - _DEFPIN_ARM(10, 0, 11); // D10 is P0.11 (SCL) - _DEFPIN_ARM(11, 0, 12); // D11 is P0.12 (DRDYn) - _DEFPIN_ARM(12, 0, 13); // D12 is P0.13 (SDA) - _DEFPIN_ARM(13, 0, 14); // D13 is P0.17 (INT) - _DEFPIN_ARM(14, 0, 15); // D14 is P0.15 (INT1) - _DEFPIN_ARM(15, 0, 20); // D15 is P0.20 (INT2) - _DEFPIN_ARM(16, 0, 2); // D16 is P0.02 (A0) - _DEFPIN_ARM(17, 0, 3); // D17 is P0.03 (A1) - _DEFPIN_ARM(18, 0, 4); // D18 is P0.04 (A2) - _DEFPIN_ARM(19, 0, 24); // D19 is P0.24 (A3, also D4/SPI MISO) -- is this right? - _DEFPIN_ARM(20, 0, 29); // D20 is P0.29 (A4) - _DEFPIN_ARM(21, 0, 30); // D21 is P0.30 (A5) - _DEFPIN_ARM(22, 0, 31); // D22 is P0.31 (A6) - _DEFPIN_ARM(23, 0, 8); // D23 is P0.08 (RX) - _DEFPIN_ARM(24, 0, 6); // D24 is P0.06 (TX) - _DEFPIN_ARM(25, 0, 5); // D25 is P0.05 (RTS) - _DEFPIN_ARM(26, 0, 7); // D26 is P0.07 (CTS) + _FL_DEFPIN( 0, 26, 0); // D0 is P0.26 + _FL_DEFPIN( 1, 27, 0); // D1 is P0.27 + _FL_DEFPIN( 2, 22, 0); // D2 is P0.22 (SPI SS ) + _FL_DEFPIN( 3, 23, 0); // D3 is P0.23 (SPI MOSI) + _FL_DEFPIN( 4, 24, 0); // D4 is P0.24 (SPI MISO, also A3) + _FL_DEFPIN( 5, 25, 0); // D5 is P0.25 (SPI SCK ) + _FL_DEFPIN( 6, 16, 0); // D6 is P0.16 (Button) + _FL_DEFPIN( 7, 19, 0); // D7 is P0.19 (R) + _FL_DEFPIN( 8, 18, 0); // D8 is P0.18 (G) + _FL_DEFPIN( 9, 17, 0); // D9 is P0.17 (B) + _FL_DEFPIN(10, 11, 0); // D10 is P0.11 (SCL) + _FL_DEFPIN(11, 12, 0); // D11 is P0.12 (DRDYn) + _FL_DEFPIN(12, 13, 0); // D12 is P0.13 (SDA) + _FL_DEFPIN(13, 14, 0); // D13 is P0.17 (INT) + _FL_DEFPIN(14, 15, 0); // D14 is P0.15 (INT1) + _FL_DEFPIN(15, 20, 0); // D15 is P0.20 (INT2) + _FL_DEFPIN(16, 2, 0); // D16 is P0.02 (A0) + _FL_DEFPIN(17, 3, 0); // D17 is P0.03 (A1) + _FL_DEFPIN(18, 4, 0); // D18 is P0.04 (A2) + _FL_DEFPIN(19, 24, 0); // D19 is P0.24 (A3, also D4/SPI MISO) -- is this right? + _FL_DEFPIN(20, 29, 0); // D20 is P0.29 (A4) + _FL_DEFPIN(21, 30, 0); // D21 is P0.30 (A5) + _FL_DEFPIN(22, 31, 0); // D22 is P0.31 (A6) + _FL_DEFPIN(23, 8, 0); // D23 is P0.08 (RX) + _FL_DEFPIN(24, 6, 0); // D24 is P0.06 (TX) + _FL_DEFPIN(25, 5, 0); // D25 is P0.05 (RTS) + _FL_DEFPIN(26, 7, 0); // D26 is P0.07 (CTS) #endif // defined(ARDUINO_ELECTRONUT_BLUEY) // Electronut labs hackaBLE @@ -317,33 +317,33 @@ #define __FASTPIN_ARM_NRF52_VARIANT_FOUND #endif #warning "Electronut labs hackaBLE is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues" - _DEFPIN_ARM( 0, 0, 14); // D0 is P0.14 (RX) - _DEFPIN_ARM( 1, 0, 13); // D1 is P0.13 (TX) - _DEFPIN_ARM( 2, 0, 12); // D2 is P0.12 - _DEFPIN_ARM( 3, 0, 11); // D3 is P0.11 (SPI MOSI) - _DEFPIN_ARM( 4, 0, 8); // D4 is P0.08 (SPI MISO) - _DEFPIN_ARM( 5, 0, 7); // D5 is P0.07 (SPI SCK ) - _DEFPIN_ARM( 6, 0, 6); // D6 is P0.06 - _DEFPIN_ARM( 7, 0, 27); // D7 is P0.27 - _DEFPIN_ARM( 8, 0, 26); // D8 is P0.26 - _DEFPIN_ARM( 9, 0, 25); // D9 is P0.25 - _DEFPIN_ARM(10, 0, 5); // D10 is P0.05 (A3) - _DEFPIN_ARM(11, 0, 4); // D11 is P0.04 (A2) - _DEFPIN_ARM(12, 0, 3); // D12 is P0.03 (A1) - _DEFPIN_ARM(13, 0, 2); // D13 is P0.02 (A0 / AREF) - _DEFPIN_ARM(14, 0, 23); // D14 is P0.23 - _DEFPIN_ARM(15, 0, 22); // D15 is P0.22 - _DEFPIN_ARM(16, 0, 18); // D16 is P0.18 - _DEFPIN_ARM(17, 0, 16); // D17 is P0.16 - _DEFPIN_ARM(18, 0, 15); // D18 is P0.15 - _DEFPIN_ARM(19, 0, 24); // D19 is P0.24 - _DEFPIN_ARM(20, 0, 28); // D20 is P0.28 (A4) - _DEFPIN_ARM(21, 0, 29); // D21 is P0.29 (A5) - _DEFPIN_ARM(22, 0, 30); // D22 is P0.30 (A6) - _DEFPIN_ARM(23, 0, 31); // D23 is P0.31 (A7) - _DEFPIN_ARM(24, 0, 19); // D24 is P0.19 (RED LED) - _DEFPIN_ARM(25, 0, 20); // D25 is P0.20 (GREEN LED) - _DEFPIN_ARM(26, 0, 17); // D26 is P0.17 (BLUE LED) + _FL_DEFPIN( 0, 14, 0); // D0 is P0.14 (RX) + _FL_DEFPIN( 1, 13, 0); // D1 is P0.13 (TX) + _FL_DEFPIN( 2, 12, 0); // D2 is P0.12 + _FL_DEFPIN( 3, 11, 0); // D3 is P0.11 (SPI MOSI) + _FL_DEFPIN( 4, 8, 0); // D4 is P0.08 (SPI MISO) + _FL_DEFPIN( 5, 7, 0); // D5 is P0.07 (SPI SCK ) + _FL_DEFPIN( 6, 6, 0); // D6 is P0.06 + _FL_DEFPIN( 7, 27, 0); // D7 is P0.27 + _FL_DEFPIN( 8, 26, 0); // D8 is P0.26 + _FL_DEFPIN( 9, 25, 0); // D9 is P0.25 + _FL_DEFPIN(10, 5, 0); // D10 is P0.05 (A3) + _FL_DEFPIN(11, 4, 0); // D11 is P0.04 (A2) + _FL_DEFPIN(12, 3, 0); // D12 is P0.03 (A1) + _FL_DEFPIN(13, 2, 0); // D13 is P0.02 (A0 / AREF) + _FL_DEFPIN(14, 23, 0); // D14 is P0.23 + _FL_DEFPIN(15, 22, 0); // D15 is P0.22 + _FL_DEFPIN(16, 18, 0); // D16 is P0.18 + _FL_DEFPIN(17, 16, 0); // D17 is P0.16 + _FL_DEFPIN(18, 15, 0); // D18 is P0.15 + _FL_DEFPIN(19, 24, 0); // D19 is P0.24 + _FL_DEFPIN(20, 28, 0); // D20 is P0.28 (A4) + _FL_DEFPIN(21, 29, 0); // D21 is P0.29 (A5) + _FL_DEFPIN(22, 30, 0); // D22 is P0.30 (A6) + _FL_DEFPIN(23, 31, 0); // D23 is P0.31 (A7) + _FL_DEFPIN(24, 19, 0); // D24 is P0.19 (RED LED) + _FL_DEFPIN(25, 20, 0); // D25 is P0.20 (GREEN LED) + _FL_DEFPIN(26, 17, 0); // D26 is P0.17 (BLUE LED) #endif // defined(ARDUINO_ELECTRONUT_HACKABLE) // Electronut labs hackaBLE_v2 @@ -399,31 +399,31 @@ #define __FASTPIN_ARM_NRF52_VARIANT_FOUND #endif #warning "RedBear Blend 2 is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues" - _DEFPIN_ARM( 0, 0, 11); // D0 is P0.11 - _DEFPIN_ARM( 1, 0, 12); // D1 is P0.12 - _DEFPIN_ARM( 2, 0, 13); // D2 is P0.13 - _DEFPIN_ARM( 3, 0, 14); // D3 is P0.14 - _DEFPIN_ARM( 4, 0, 15); // D4 is P0.15 - _DEFPIN_ARM( 5, 0, 16); // D5 is P0.16 - _DEFPIN_ARM( 6, 0, 17); // D6 is P0.17 - _DEFPIN_ARM( 7, 0, 18); // D7 is P0.18 - _DEFPIN_ARM( 8, 0, 19); // D8 is P0.19 - _DEFPIN_ARM( 9, 0, 20); // D9 is P0.20 - _DEFPIN_ARM(10, 0, 22); // D10 is P0.22 (SPI SS ) - _DEFPIN_ARM(11, 0, 23); // D11 is P0.23 (SPI MOSI) - _DEFPIN_ARM(12, 0, 24); // D12 is P0.24 (SPI MISO) - _DEFPIN_ARM(13, 0, 25); // D13 is P0.25 (SPI SCK / LED) - _DEFPIN_ARM(14, 0, 3); // D14 is P0.03 (A0) - _DEFPIN_ARM(15, 0, 4); // D15 is P0.04 (A1) - _DEFPIN_ARM(16, 0, 28); // D16 is P0.28 (A2) - _DEFPIN_ARM(17, 0, 29); // D17 is P0.29 (A3) - _DEFPIN_ARM(18, 0, 30); // D18 is P0.30 (A4) - _DEFPIN_ARM(19, 0, 31); // D19 is P0.31 (A5) - _DEFPIN_ARM(20, 0, 26); // D20 is P0.26 (SDA) - _DEFPIN_ARM(21, 0, 27); // D21 is P0.27 (SCL) - _DEFPIN_ARM(22, 0, 8); // D22 is P0.08 (RX) - _DEFPIN_ARM(23, 0, 6); // D23 is P0.06 (TX) - _DEFPIN_ARM(24, 0, 2); // D24 is P0.02 (AREF) + _FL_DEFPIN( 0, 11, 0); // D0 is P0.11 + _FL_DEFPIN( 1, 12, 0); // D1 is P0.12 + _FL_DEFPIN( 2, 13, 0); // D2 is P0.13 + _FL_DEFPIN( 3, 14, 0); // D3 is P0.14 + _FL_DEFPIN( 4, 15, 0); // D4 is P0.15 + _FL_DEFPIN( 5, 16, 0); // D5 is P0.16 + _FL_DEFPIN( 6, 17, 0); // D6 is P0.17 + _FL_DEFPIN( 7, 18, 0); // D7 is P0.18 + _FL_DEFPIN( 8, 19, 0); // D8 is P0.19 + _FL_DEFPIN( 9, 20, 0); // D9 is P0.20 + _FL_DEFPIN(10, 22, 0); // D10 is P0.22 (SPI SS ) + _FL_DEFPIN(11, 23, 0); // D11 is P0.23 (SPI MOSI) + _FL_DEFPIN(12, 24, 0); // D12 is P0.24 (SPI MISO) + _FL_DEFPIN(13, 25, 0); // D13 is P0.25 (SPI SCK / LED) + _FL_DEFPIN(14, 3, 0); // D14 is P0.03 (A0) + _FL_DEFPIN(15, 4, 0); // D15 is P0.04 (A1) + _FL_DEFPIN(16, 28, 0); // D16 is P0.28 (A2) + _FL_DEFPIN(17, 29, 0); // D17 is P0.29 (A3) + _FL_DEFPIN(18, 30, 0); // D18 is P0.30 (A4) + _FL_DEFPIN(19, 31, 0); // D19 is P0.31 (A5) + _FL_DEFPIN(20, 26, 0); // D20 is P0.26 (SDA) + _FL_DEFPIN(21, 27, 0); // D21 is P0.27 (SCL) + _FL_DEFPIN(22, 8, 0); // D22 is P0.08 (RX) + _FL_DEFPIN(23, 6, 0); // D23 is P0.06 (TX) + _FL_DEFPIN(24, 2, 0); // D24 is P0.02 (AREF) #endif // defined(ARDUINO_RB_BLEND_2) // RedBear BLE Nano 2 @@ -435,18 +435,18 @@ #define __FASTPIN_ARM_NRF52_VARIANT_FOUND #endif #warning "RedBear BLE Nano 2 is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues" - _DEFPIN_ARM( 0, 0, 30); // D0 is P0.30 (A0 / RX) - _DEFPIN_ARM( 1, 0, 29); // D1 is P0.29 (A1 / TX) - _DEFPIN_ARM( 2, 0, 28); // D2 is P0.28 (A2 / SDA) - _DEFPIN_ARM( 3, 0, 2); // D3 is P0.02 (A3 / SCL) - _DEFPIN_ARM( 4, 0, 5); // D4 is P0.05 (A4) - _DEFPIN_ARM( 5, 0, 4); // D5 is P0.04 (A5) - _DEFPIN_ARM( 6, 0, 3); // D6 is P0.03 (SPI SS ) - _DEFPIN_ARM( 7, 0, 6); // D7 is P0.06 (SPI MOSI) - _DEFPIN_ARM( 8, 0, 7); // D8 is P0.07 (SPI MISO) - _DEFPIN_ARM( 9, 0, 8); // D9 is P0.08 (SPI SCK ) - // _DEFPIN_ARM(10, 0, 21); // D10 is P0.21 (RESET) - _DEFPIN_ARM(13, 0, 11); // D11 is P0.11 (LED) + _FL_DEFPIN( 0, 30, 0); // D0 is P0.30 (A0 / RX) + _FL_DEFPIN( 1, 29, 0); // D1 is P0.29 (A1 / TX) + _FL_DEFPIN( 2, 28, 0); // D2 is P0.28 (A2 / SDA) + _FL_DEFPIN( 3, 2, 0); // D3 is P0.02 (A3 / SCL) + _FL_DEFPIN( 4, 5, 0); // D4 is P0.05 (A4) + _FL_DEFPIN( 5, 4, 0); // D5 is P0.04 (A5) + _FL_DEFPIN( 6, 3, 0); // D6 is P0.03 (SPI SS ) + _FL_DEFPIN( 7, 6, 0); // D7 is P0.06 (SPI MOSI) + _FL_DEFPIN( 8, 7, 0); // D8 is P0.07 (SPI MISO) + _FL_DEFPIN( 9, 8, 0); // D9 is P0.08 (SPI SCK ) + // _FL_DEFPIN(10, 21, 0); // D10 is P0.21 (RESET) + _FL_DEFPIN(13, 11, 0); // D11 is P0.11 (LED) #endif // defined(ARDUINO_RB_BLE_NANO_2) // Nordic Semiconductor nRF52 DK @@ -458,32 +458,32 @@ #define __FASTPIN_ARM_NRF52_VARIANT_FOUND #endif #warning "Nordic Semiconductor nRF52 DK is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues" - _DEFPIN_ARM( 0, 0, 11); // D0 is P0.11 - _DEFPIN_ARM( 1, 0, 12); // D1 is P0.12 - _DEFPIN_ARM( 2, 0, 13); // D2 is P0.13 (BUTTON1) - _DEFPIN_ARM( 3, 0, 14); // D3 is P0.14 (BUTTON2) - _DEFPIN_ARM( 4, 0, 15); // D4 is P0.15 (BUTTON3) - _DEFPIN_ARM( 5, 0, 16); // D5 is P0.16 (BUTTON4) - _DEFPIN_ARM( 6, 0, 17); // D6 is P0.17 (LED1) - _DEFPIN_ARM( 7, 0, 18); // D7 is P0.18 (LED2) - _DEFPIN_ARM( 8, 0, 19); // D8 is P0.19 (LED3) - _DEFPIN_ARM( 9, 0, 20); // D9 is P0.20 (LED4) - _DEFPIN_ARM(10, 0, 22); // D10 is P0.22 (SPI SS ) - _DEFPIN_ARM(11, 0, 23); // D11 is P0.23 (SPI MOSI) - _DEFPIN_ARM(12, 0, 24); // D12 is P0.24 (SPI MISO) - _DEFPIN_ARM(13, 0, 25); // D13 is P0.25 (SPI SCK / LED) - _DEFPIN_ARM(14, 0, 3); // D14 is P0.03 (A0) - _DEFPIN_ARM(15, 0, 4); // D15 is P0.04 (A1) - _DEFPIN_ARM(16, 0, 28); // D16 is P0.28 (A2) - _DEFPIN_ARM(17, 0, 29); // D17 is P0.29 (A3) - _DEFPIN_ARM(18, 0, 30); // D18 is P0.30 (A4) - _DEFPIN_ARM(19, 0, 31); // D19 is P0.31 (A5) - _DEFPIN_ARM(20, 0, 5); // D20 is P0.05 (A6) - _DEFPIN_ARM(21, 0, 2); // D21 is P0.02 (A7 / AREF) - _DEFPIN_ARM(22, 0, 26); // D22 is P0.26 (SDA) - _DEFPIN_ARM(23, 0, 27); // D23 is P0.27 (SCL) - _DEFPIN_ARM(24, 0, 8); // D24 is P0.08 (RX) - _DEFPIN_ARM(25, 0, 6); // D25 is P0.06 (TX) + _FL_DEFPIN( 0, 11, 0); // D0 is P0.11 + _FL_DEFPIN( 1, 12, 0); // D1 is P0.12 + _FL_DEFPIN( 2, 13, 0); // D2 is P0.13 (BUTTON1) + _FL_DEFPIN( 3, 14, 0); // D3 is P0.14 (BUTTON2) + _FL_DEFPIN( 4, 15, 0); // D4 is P0.15 (BUTTON3) + _FL_DEFPIN( 5, 16, 0); // D5 is P0.16 (BUTTON4) + _FL_DEFPIN( 6, 17, 0); // D6 is P0.17 (LED1) + _FL_DEFPIN( 7, 18, 0); // D7 is P0.18 (LED2) + _FL_DEFPIN( 8, 19, 0); // D8 is P0.19 (LED3) + _FL_DEFPIN( 9, 20, 0); // D9 is P0.20 (LED4) + _FL_DEFPIN(10, 22, 0); // D10 is P0.22 (SPI SS ) + _FL_DEFPIN(11, 23, 0); // D11 is P0.23 (SPI MOSI) + _FL_DEFPIN(12, 24, 0); // D12 is P0.24 (SPI MISO) + _FL_DEFPIN(13, 25, 0); // D13 is P0.25 (SPI SCK / LED) + _FL_DEFPIN(14, 3, 0); // D14 is P0.03 (A0) + _FL_DEFPIN(15, 4, 0); // D15 is P0.04 (A1) + _FL_DEFPIN(16, 28, 0); // D16 is P0.28 (A2) + _FL_DEFPIN(17, 29, 0); // D17 is P0.29 (A3) + _FL_DEFPIN(18, 30, 0); // D18 is P0.30 (A4) + _FL_DEFPIN(19, 31, 0); // D19 is P0.31 (A5) + _FL_DEFPIN(20, 5, 0); // D20 is P0.05 (A6) + _FL_DEFPIN(21, 2, 0); // D21 is P0.02 (A7 / AREF) + _FL_DEFPIN(22, 26, 0); // D22 is P0.26 (SDA) + _FL_DEFPIN(23, 27, 0); // D23 is P0.27 (SCL) + _FL_DEFPIN(24, 8, 0); // D24 is P0.08 (RX) + _FL_DEFPIN(25, 6, 0); // D25 is P0.06 (TX) #endif // defined(ARDUINO_NRF52_DK) // Taida Century nRF52 mini board @@ -495,38 +495,38 @@ #define __FASTPIN_ARM_NRF52_VARIANT_FOUND #endif #warning "Taida Century nRF52 mini board is an untested board -- test and let use know your results via https://github.com/FastLED/FastLED/issues" - //_DEFPIN_ARM( 0, 0, 25); // D0 is P0.xx (near radio!) - //_DEFPIN_ARM( 1, 0, 26); // D1 is P0.xx (near radio!) - //_DEFPIN_ARM( 2, 0, 27); // D2 is P0.xx (near radio!) - //_DEFPIN_ARM( 3, 0, 28); // D3 is P0.xx (near radio!) - //_DEFPIN_ARM( 4, 0, 29); // D4 is P0.xx (Not connected, near radio!) - //_DEFPIN_ARM( 5, 0, 30); // D5 is P0.xx (LED1, near radio!) - //_DEFPIN_ARM( 6, 0, 31); // D6 is P0.xx (LED2, near radio!) - _DEFPIN_ARM( 7, 0, 2); // D7 is P0.xx (SDA) - _DEFPIN_ARM( 8, 0, 3); // D8 is P0.xx (SCL) - _DEFPIN_ARM( 9, 0, 4); // D9 is P0.xx (BUTTON1 / NFC1) - _DEFPIN_ARM(10, 0, 5); // D10 is P0.xx - //_DEFPIN_ARM(11, 0, 0); // D11 is P0.xx (Not connected) - //_DEFPIN_ARM(12, 0, 1); // D12 is P0.xx (Not connected) - _DEFPIN_ARM(13, 0, 6); // D13 is P0.xx - _DEFPIN_ARM(14, 0, 7); // D14 is P0.xx - _DEFPIN_ARM(15, 0, 8); // D15 is P0.xx - //_DEFPIN_ARM(16, 0, 9); // D16 is P0.xx (Not connected) - //_DEFPIN_ARM(17, 0, 10); // D17 is P0.xx (NFC2, Not connected) - _DEFPIN_ARM(18, 0, 11); // D18 is P0.xx (RXD) - _DEFPIN_ARM(19, 0, 12); // D19 is P0.xx (TXD) - _DEFPIN_ARM(20, 0, 13); // D20 is P0.xx (SPI SS ) - _DEFPIN_ARM(21, 0, 14); // D21 is P0.xx (SPI MISO) - _DEFPIN_ARM(22, 0, 15); // D22 is P0.xx (SPI MOSI) - _DEFPIN_ARM(23, 0, 16); // D23 is P0.xx (SPI SCK ) - _DEFPIN_ARM(24, 0, 17); // D24 is P0.xx (A0) - _DEFPIN_ARM(25, 0, 18); // D25 is P0.xx (A1) - _DEFPIN_ARM(26, 0, 19); // D26 is P0.xx (A2) - _DEFPIN_ARM(27, 0, 20); // D27 is P0.xx (A3) - //_DEFPIN_ARM(28, 0, 22); // D28 is P0.xx (A4, near radio!) - //_DEFPIN_ARM(29, 0, 23); // D29 is P0.xx (A5, near radio!) - _DEFPIN_ARM(30, 0, 24); // D30 is P0.xx - // _DEFPIN_ARM(31, 0, 21); // D31 is P0.21 (RESET) + //_FL_DEFPIN( 0, 25, 0); // D0 is P0.xx (near radio!) + //_FL_DEFPIN( 1, 26, 0); // D1 is P0.xx (near radio!) + //_FL_DEFPIN( 2, 27, 0); // D2 is P0.xx (near radio!) + //_FL_DEFPIN( 3, 28, 0); // D3 is P0.xx (near radio!) + //_FL_DEFPIN( 4, 29, 0); // D4 is P0.xx (Not connected, near radio!) + //_FL_DEFPIN( 5, 30, 0); // D5 is P0.xx (LED1, near radio!) + //_FL_DEFPIN( 6, 31, 0); // D6 is P0.xx (LED2, near radio!) + _FL_DEFPIN( 7, 2, 0); // D7 is P0.xx (SDA) + _FL_DEFPIN( 8, 3, 0); // D8 is P0.xx (SCL) + _FL_DEFPIN( 9, 4, 0); // D9 is P0.xx (BUTTON1 / NFC1) + _FL_DEFPIN(10, 5, 0); // D10 is P0.xx + //_FL_DEFPIN(11, 0, 0); // D11 is P0.xx (Not connected) + //_FL_DEFPIN(12, 1, 0); // D12 is P0.xx (Not connected) + _FL_DEFPIN(13, 6, 0); // D13 is P0.xx + _FL_DEFPIN(14, 7, 0); // D14 is P0.xx + _FL_DEFPIN(15, 8, 0); // D15 is P0.xx + //_FL_DEFPIN(16, 9, 0); // D16 is P0.xx (Not connected) + //_FL_DEFPIN(17, 10, 0); // D17 is P0.xx (NFC2, Not connected) + _FL_DEFPIN(18, 11, 0); // D18 is P0.xx (RXD) + _FL_DEFPIN(19, 12, 0); // D19 is P0.xx (TXD) + _FL_DEFPIN(20, 13, 0); // D20 is P0.xx (SPI SS ) + _FL_DEFPIN(21, 14, 0); // D21 is P0.xx (SPI MISO) + _FL_DEFPIN(22, 15, 0); // D22 is P0.xx (SPI MOSI) + _FL_DEFPIN(23, 16, 0); // D23 is P0.xx (SPI SCK ) + _FL_DEFPIN(24, 17, 0); // D24 is P0.xx (A0) + _FL_DEFPIN(25, 18, 0); // D25 is P0.xx (A1) + _FL_DEFPIN(26, 19, 0); // D26 is P0.xx (A2) + _FL_DEFPIN(27, 20, 0); // D27 is P0.xx (A3) + //_FL_DEFPIN(28, 22, 0); // D28 is P0.xx (A4, near radio!) + //_FL_DEFPIN(29, 23, 0); // D29 is P0.xx (A5, near radio!) + _FL_DEFPIN(30, 24, 0); // D30 is P0.xx + // _FL_DEFPIN(31, 21, 0); // D31 is P0.21 (RESET) #endif // defined(ARDUINO_STCT_NRF52_minidev) // Generic nRF52832 diff --git a/platforms/arm/sam/fastpin_arm_sam.h b/platforms/arm/sam/fastpin_arm_sam.h index 2bb78042..62b00aa4 100644 --- a/platforms/arm/sam/fastpin_arm_sam.h +++ b/platforms/arm/sam/fastpin_arm_sam.h @@ -78,49 +78,49 @@ public: #define _R(T) struct __gen_struct_ ## T #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \ template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } }; -#define DUE_IO32(L) _RD32(REG_PIO ## L ## _ODSR); _RD32(REG_PIO ## L ## _SODR); _RD32(REG_PIO ## L ## _CODR); _RD32(REG_PIO ## L ## _OER); +#define _FL_IO(L) _RD32(REG_PIO ## L ## _ODSR); _RD32(REG_PIO ## L ## _SODR); _RD32(REG_PIO ## L ## _CODR); _RD32(REG_PIO ## L ## _OER); -#define _DEFPIN_DUE(PIN, BIT, L) template<> class FastPin<PIN> : public _DUEPIN<PIN, 1 << BIT, _R(REG_PIO ## L ## _ODSR), _R(REG_PIO ## L ## _SODR), _R(REG_PIO ## L ## _CODR), \ +#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _DUEPIN<PIN, 1 << BIT, _R(REG_PIO ## L ## _ODSR), _R(REG_PIO ## L ## _SODR), _R(REG_PIO ## L ## _CODR), \ _R(GPIO ## L ## _OER)> {}; \ template<> class FastPinBB<PIN> : public _DUEPIN_BITBAND<PIN, BIT, _R(REG_PIO ## L ## _ODSR), _R(REG_PIO ## L ## _SODR), _R(REG_PIO ## L ## _CODR), \ _R(GPIO ## L ## _OER)> {}; #if defined(__SAM3X8E__) -DUE_IO32(A); -DUE_IO32(B); -DUE_IO32(C); -DUE_IO32(D); +_FL_IO(A); +_FL_IO(B); +_FL_IO(C); +_FL_IO(D); #define MAX_PIN 78 -_DEFPIN_DUE(0, 8, A); _DEFPIN_DUE(1, 9, A); _DEFPIN_DUE(2, 25, B); _DEFPIN_DUE(3, 28, C); -_DEFPIN_DUE(4, 26, C); _DEFPIN_DUE(5, 25, C); _DEFPIN_DUE(6, 24, C); _DEFPIN_DUE(7, 23, C); -_DEFPIN_DUE(8, 22, C); _DEFPIN_DUE(9, 21, C); _DEFPIN_DUE(10, 29, C); _DEFPIN_DUE(11, 7, D); -_DEFPIN_DUE(12, 8, D); _DEFPIN_DUE(13, 27, B); _DEFPIN_DUE(14, 4, D); _DEFPIN_DUE(15, 5, D); -_DEFPIN_DUE(16, 13, A); _DEFPIN_DUE(17, 12, A); _DEFPIN_DUE(18, 11, A); _DEFPIN_DUE(19, 10, A); -_DEFPIN_DUE(20, 12, B); _DEFPIN_DUE(21, 13, B); _DEFPIN_DUE(22, 26, B); _DEFPIN_DUE(23, 14, A); -_DEFPIN_DUE(24, 15, A); _DEFPIN_DUE(25, 0, D); _DEFPIN_DUE(26, 1, D); _DEFPIN_DUE(27, 2, D); -_DEFPIN_DUE(28, 3, D); _DEFPIN_DUE(29, 6, D); _DEFPIN_DUE(30, 9, D); _DEFPIN_DUE(31, 7, A); -_DEFPIN_DUE(32, 10, D); _DEFPIN_DUE(33, 1, C); _DEFPIN_DUE(34, 2, C); _DEFPIN_DUE(35, 3, C); -_DEFPIN_DUE(36, 4, C); _DEFPIN_DUE(37, 5, C); _DEFPIN_DUE(38, 6, C); _DEFPIN_DUE(39, 7, C); -_DEFPIN_DUE(40, 8, C); _DEFPIN_DUE(41, 9, C); _DEFPIN_DUE(42, 19, A); _DEFPIN_DUE(43, 20, A); -_DEFPIN_DUE(44, 19, C); _DEFPIN_DUE(45, 18, C); _DEFPIN_DUE(46, 17, C); _DEFPIN_DUE(47, 16, C); -_DEFPIN_DUE(48, 15, C); _DEFPIN_DUE(49, 14, C); _DEFPIN_DUE(50, 13, C); _DEFPIN_DUE(51, 12, C); -_DEFPIN_DUE(52, 21, B); _DEFPIN_DUE(53, 14, B); _DEFPIN_DUE(54, 16, A); _DEFPIN_DUE(55, 24, A); -_DEFPIN_DUE(56, 23, A); _DEFPIN_DUE(57, 22, A); _DEFPIN_DUE(58, 6, A); _DEFPIN_DUE(59, 4, A); -_DEFPIN_DUE(60, 3, A); _DEFPIN_DUE(61, 2, A); _DEFPIN_DUE(62, 17, B); _DEFPIN_DUE(63, 18, B); -_DEFPIN_DUE(64, 19, B); _DEFPIN_DUE(65, 20, B); _DEFPIN_DUE(66, 15, B); _DEFPIN_DUE(67, 16, B); -_DEFPIN_DUE(68, 1, A); _DEFPIN_DUE(69, 0, A); _DEFPIN_DUE(70, 17, A); _DEFPIN_DUE(71, 18, A); -_DEFPIN_DUE(72, 30, C); _DEFPIN_DUE(73, 21, A); _DEFPIN_DUE(74, 25, A); _DEFPIN_DUE(75, 26, A); -_DEFPIN_DUE(76, 27, A); _DEFPIN_DUE(77, 28, A); _DEFPIN_DUE(78, 23, B); +_FL_DEFPIN(0, 8, A); _FL_DEFPIN(1, 9, A); _FL_DEFPIN(2, 25, B); _FL_DEFPIN(3, 28, C); +_FL_DEFPIN(4, 26, C); _FL_DEFPIN(5, 25, C); _FL_DEFPIN(6, 24, C); _FL_DEFPIN(7, 23, C); +_FL_DEFPIN(8, 22, C); _FL_DEFPIN(9, 21, C); _FL_DEFPIN(10, 29, C); _FL_DEFPIN(11, 7, D); +_FL_DEFPIN(12, 8, D); _FL_DEFPIN(13, 27, B); _FL_DEFPIN(14, 4, D); _FL_DEFPIN(15, 5, D); +_FL_DEFPIN(16, 13, A); _FL_DEFPIN(17, 12, A); _FL_DEFPIN(18, 11, A); _FL_DEFPIN(19, 10, A); +_FL_DEFPIN(20, 12, B); _FL_DEFPIN(21, 13, B); _FL_DEFPIN(22, 26, B); _FL_DEFPIN(23, 14, A); +_FL_DEFPIN(24, 15, A); _FL_DEFPIN(25, 0, D); _FL_DEFPIN(26, 1, D); _FL_DEFPIN(27, 2, D); +_FL_DEFPIN(28, 3, D); _FL_DEFPIN(29, 6, D); _FL_DEFPIN(30, 9, D); _FL_DEFPIN(31, 7, A); +_FL_DEFPIN(32, 10, D); _FL_DEFPIN(33, 1, C); _FL_DEFPIN(34, 2, C); _FL_DEFPIN(35, 3, C); +_FL_DEFPIN(36, 4, C); _FL_DEFPIN(37, 5, C); _FL_DEFPIN(38, 6, C); _FL_DEFPIN(39, 7, C); +_FL_DEFPIN(40, 8, C); _FL_DEFPIN(41, 9, C); _FL_DEFPIN(42, 19, A); _FL_DEFPIN(43, 20, A); +_FL_DEFPIN(44, 19, C); _FL_DEFPIN(45, 18, C); _FL_DEFPIN(46, 17, C); _FL_DEFPIN(47, 16, C); +_FL_DEFPIN(48, 15, C); _FL_DEFPIN(49, 14, C); _FL_DEFPIN(50, 13, C); _FL_DEFPIN(51, 12, C); +_FL_DEFPIN(52, 21, B); _FL_DEFPIN(53, 14, B); _FL_DEFPIN(54, 16, A); _FL_DEFPIN(55, 24, A); +_FL_DEFPIN(56, 23, A); _FL_DEFPIN(57, 22, A); _FL_DEFPIN(58, 6, A); _FL_DEFPIN(59, 4, A); +_FL_DEFPIN(60, 3, A); _FL_DEFPIN(61, 2, A); _FL_DEFPIN(62, 17, B); _FL_DEFPIN(63, 18, B); +_FL_DEFPIN(64, 19, B); _FL_DEFPIN(65, 20, B); _FL_DEFPIN(66, 15, B); _FL_DEFPIN(67, 16, B); +_FL_DEFPIN(68, 1, A); _FL_DEFPIN(69, 0, A); _FL_DEFPIN(70, 17, A); _FL_DEFPIN(71, 18, A); +_FL_DEFPIN(72, 30, C); _FL_DEFPIN(73, 21, A); _FL_DEFPIN(74, 25, A); _FL_DEFPIN(75, 26, A); +_FL_DEFPIN(76, 27, A); _FL_DEFPIN(77, 28, A); _FL_DEFPIN(78, 23, B); // digix pins -_DEFPIN_DUE(90, 0, B); _DEFPIN_DUE(91, 1, B); _DEFPIN_DUE(92, 2, B); _DEFPIN_DUE(93, 3, B); -_DEFPIN_DUE(94, 4, B); _DEFPIN_DUE(95, 5, B); _DEFPIN_DUE(96, 6, B); _DEFPIN_DUE(97, 7, B); -_DEFPIN_DUE(98, 8, B); _DEFPIN_DUE(99, 9, B); _DEFPIN_DUE(100, 5, A); _DEFPIN_DUE(101, 22, B); -_DEFPIN_DUE(102, 23, B); _DEFPIN_DUE(103, 24, B); _DEFPIN_DUE(104, 27, C); _DEFPIN_DUE(105, 20, C); -_DEFPIN_DUE(106, 11, C); _DEFPIN_DUE(107, 10, C); _DEFPIN_DUE(108, 21, A); _DEFPIN_DUE(109, 30, C); -_DEFPIN_DUE(110, 29, B); _DEFPIN_DUE(111, 30, B); _DEFPIN_DUE(112, 31, B); _DEFPIN_DUE(113, 28, B); +_FL_DEFPIN(90, 0, B); _FL_DEFPIN(91, 1, B); _FL_DEFPIN(92, 2, B); _FL_DEFPIN(93, 3, B); +_FL_DEFPIN(94, 4, B); _FL_DEFPIN(95, 5, B); _FL_DEFPIN(96, 6, B); _FL_DEFPIN(97, 7, B); +_FL_DEFPIN(98, 8, B); _FL_DEFPIN(99, 9, B); _FL_DEFPIN(100, 5, A); _FL_DEFPIN(101, 22, B); +_FL_DEFPIN(102, 23, B); _FL_DEFPIN(103, 24, B); _FL_DEFPIN(104, 27, C); _FL_DEFPIN(105, 20, C); +_FL_DEFPIN(106, 11, C); _FL_DEFPIN(107, 10, C); _FL_DEFPIN(108, 21, A); _FL_DEFPIN(109, 30, C); +_FL_DEFPIN(110, 29, B); _FL_DEFPIN(111, 30, B); _FL_DEFPIN(112, 31, B); _FL_DEFPIN(113, 28, B); #define SPI_DATA 75 #define SPI_CLOCK 76 diff --git a/platforms/arm/stm32/fastpin_arm_stm32.h b/platforms/arm/stm32/fastpin_arm_stm32.h index 57309cd9..bb8981d3 100644 --- a/platforms/arm/stm32/fastpin_arm_stm32.h +++ b/platforms/arm/stm32/fastpin_arm_stm32.h @@ -57,44 +57,44 @@ public: #if defined(STM32F10X_MD) #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile GPIO_TypeDef * r() { return T; } }; - #define _IO32(L) _RD32(GPIO ## L) + #define _FL_IO(L) _RD32(GPIO ## L) #elif defined(__STM32F1__) #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline gpio_reg_map* r() { return T->regs; } }; - #define _IO32(L) _RD32(GPIO ## L) + #define _FL_IO(L) _RD32(GPIO ## L) #else #error "Platform not supported" #endif #define _R(T) struct __gen_struct_ ## T -#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L)> {}; +#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L)> {}; // Actual pin definitions #if defined(SPARK) // Sparkfun STM32F103 based board -_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E); _IO32(F); _IO32(G); +_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); _FL_IO(F); _FL_IO(G); #define MAX_PIN 19 -_DEFPIN_ARM(0, 7, B); -_DEFPIN_ARM(1, 6, B); -_DEFPIN_ARM(2, 5, B); -_DEFPIN_ARM(3, 4, B); -_DEFPIN_ARM(4, 3, B); -_DEFPIN_ARM(5, 15, A); -_DEFPIN_ARM(6, 14, A); -_DEFPIN_ARM(7, 13, A); -_DEFPIN_ARM(8, 8, A); -_DEFPIN_ARM(9, 9, A); -_DEFPIN_ARM(10, 0, A); -_DEFPIN_ARM(11, 1, A); -_DEFPIN_ARM(12, 4, A); -_DEFPIN_ARM(13, 5, A); -_DEFPIN_ARM(14, 6, A); -_DEFPIN_ARM(15, 7, A); -_DEFPIN_ARM(16, 0, B); -_DEFPIN_ARM(17, 1, B); -_DEFPIN_ARM(18, 3, A); -_DEFPIN_ARM(19, 2, A); +_FL_DEFPIN(0, 7, B); +_FL_DEFPIN(1, 6, B); +_FL_DEFPIN(2, 5, B); +_FL_DEFPIN(3, 4, B); +_FL_DEFPIN(4, 3, B); +_FL_DEFPIN(5, 15, A); +_FL_DEFPIN(6, 14, A); +_FL_DEFPIN(7, 13, A); +_FL_DEFPIN(8, 8, A); +_FL_DEFPIN(9, 9, A); +_FL_DEFPIN(10, 0, A); +_FL_DEFPIN(11, 1, A); +_FL_DEFPIN(12, 4, A); +_FL_DEFPIN(13, 5, A); +_FL_DEFPIN(14, 6, A); +_FL_DEFPIN(15, 7, A); +_FL_DEFPIN(16, 0, B); +_FL_DEFPIN(17, 1, B); +_FL_DEFPIN(18, 3, A); +_FL_DEFPIN(19, 2, A); #define SPI_DATA 15 @@ -106,43 +106,43 @@ _DEFPIN_ARM(19, 2, A); #if defined(__STM32F1__) // Generic STM32F103 aka "Blue Pill" -_IO32(A); _IO32(B); _IO32(C); +_FL_IO(A); _FL_IO(B); _FL_IO(C); #define MAX_PIN 46 -_DEFPIN_ARM(10, 0, A); // PA0 - PA7 -_DEFPIN_ARM(11, 1, A); -_DEFPIN_ARM(12, 2, A); -_DEFPIN_ARM(13, 3, A); -_DEFPIN_ARM(14, 4, A); -_DEFPIN_ARM(15, 5, A); -_DEFPIN_ARM(16, 6, A); -_DEFPIN_ARM(17, 7, A); -_DEFPIN_ARM(29, 8, A); // PA8 - PA15 -_DEFPIN_ARM(30, 9, A); -_DEFPIN_ARM(31, 10, A); -_DEFPIN_ARM(32, 11, A); -_DEFPIN_ARM(33, 12, A); -_DEFPIN_ARM(34, 13, A); -_DEFPIN_ARM(37, 14, A); -_DEFPIN_ARM(38, 15, A); - -_DEFPIN_ARM(18, 0, B); // PB0 - PB11 -_DEFPIN_ARM(19, 1, B); -_DEFPIN_ARM(20, 2, B); -_DEFPIN_ARM(39, 3, B); -_DEFPIN_ARM(40, 4, B); -_DEFPIN_ARM(41, 5, B); -_DEFPIN_ARM(42, 6, B); -_DEFPIN_ARM(43, 7, B); -_DEFPIN_ARM(45, 8, B); -_DEFPIN_ARM(46, 9, B); -_DEFPIN_ARM(21, 10, B); -_DEFPIN_ARM(22, 11, B); - -_DEFPIN_ARM(2, 13, C); // PC13 - PC15 -_DEFPIN_ARM(3, 14, C); -_DEFPIN_ARM(4, 15, C); +_FL_DEFPIN(10, 0, A); // PA0 - PA7 +_FL_DEFPIN(11, 1, A); +_FL_DEFPIN(12, 2, A); +_FL_DEFPIN(13, 3, A); +_FL_DEFPIN(14, 4, A); +_FL_DEFPIN(15, 5, A); +_FL_DEFPIN(16, 6, A); +_FL_DEFPIN(17, 7, A); +_FL_DEFPIN(29, 8, A); // PA8 - PA15 +_FL_DEFPIN(30, 9, A); +_FL_DEFPIN(31, 10, A); +_FL_DEFPIN(32, 11, A); +_FL_DEFPIN(33, 12, A); +_FL_DEFPIN(34, 13, A); +_FL_DEFPIN(37, 14, A); +_FL_DEFPIN(38, 15, A); + +_FL_DEFPIN(18, 0, B); // PB0 - PB11 +_FL_DEFPIN(19, 1, B); +_FL_DEFPIN(20, 2, B); +_FL_DEFPIN(39, 3, B); +_FL_DEFPIN(40, 4, B); +_FL_DEFPIN(41, 5, B); +_FL_DEFPIN(42, 6, B); +_FL_DEFPIN(43, 7, B); +_FL_DEFPIN(45, 8, B); +_FL_DEFPIN(46, 9, B); +_FL_DEFPIN(21, 10, B); +_FL_DEFPIN(22, 11, B); + +_FL_DEFPIN(2, 13, C); // PC13 - PC15 +_FL_DEFPIN(3, 14, C); +_FL_DEFPIN(4, 15, C); #define SPI_DATA BOARD_SPI1_MOSI_PIN #define SPI_CLOCK BOARD_SPI1_SCK_PIN diff --git a/platforms/esp/32/fastpin_esp32.h b/platforms/esp/32/fastpin_esp32.h index fd03d5c8..d54d7fee 100644 --- a/platforms/esp/32/fastpin_esp32.h +++ b/platforms/esp/32/fastpin_esp32.h @@ -11,7 +11,7 @@ public: inline static void setOutput() { pinMode(PIN, OUTPUT); } inline static void setInput() { pinMode(PIN, INPUT); } - inline static void hi() __attribute__ ((always_inline)) { + inline static void hi() __attribute__ ((always_inline)) { if (PIN < 32) GPIO.out_w1ts = MASK; else GPIO.out1_w1ts.val = MASK; } @@ -28,9 +28,9 @@ public: inline static void strobe() __attribute__ ((always_inline)) { toggle(); toggle(); } - inline static void toggle() __attribute__ ((always_inline)) { - if(PIN < 32) { GPIO.out ^= MASK; } - else { GPIO.out1.val ^=MASK; } + inline static void toggle() __attribute__ ((always_inline)) { + if(PIN < 32) { GPIO.out ^= MASK; } + else { GPIO.out1.val ^=MASK; } } inline static void hi(register port_ptr_t port) __attribute__ ((always_inline)) { hi(); } @@ -52,7 +52,7 @@ public: else return &GPIO.out1.val; } - inline static port_ptr_t sport() __attribute__ ((always_inline)) { + inline static port_ptr_t sport() __attribute__ ((always_inline)) { if (PIN < 32) return &GPIO.out_w1ts; else return &GPIO.out1_w1ts.val; } @@ -70,46 +70,45 @@ public: } }; -#define _DEFPIN_ESP32(PIN) template<> class FastPin<PIN> : public _ESPPIN<PIN, ((uint32_t)1 << PIN)> {}; -#define _DEFPIN_32_33_ESP32(PIN) template<> class FastPin<PIN> : public _ESPPIN<PIN, ((uint32_t)1 << (PIN-32))> {}; +#define _FL_DEFPIN(PIN) template<> class FastPin<PIN> : public _ESPPIN<PIN, ((PIN<32)?((uint32_t)1 << PIN):((uint32_t)1 << (PIN-32)))> {}; -_DEFPIN_ESP32(0); -_DEFPIN_ESP32(1); // WARNING: Using TX causes flashiness when uploading -_DEFPIN_ESP32(2); -_DEFPIN_ESP32(3); // WARNING: Using RX causes flashiness when uploading -_DEFPIN_ESP32(4); -_DEFPIN_ESP32(5); +_FL_DEFPIN(0); +_FL_DEFPIN(1); // WARNING: Using TX causes flashiness when uploading +_FL_DEFPIN(2); +_FL_DEFPIN(3); // WARNING: Using RX causes flashiness when uploading +_FL_DEFPIN(4); +_FL_DEFPIN(5); // -- These pins are not safe to use: -// _DEFPIN_ESP32(6,6); _DEFPIN_ESP32(7,7); _DEFPIN_ESP32(8,8); -// _DEFPIN_ESP32(9,9); _DEFPIN_ESP32(10,10); _DEFPIN_ESP32(11,11); +// _FL_DEFPIN(6,6); _FL_DEFPIN(7,7); _FL_DEFPIN(8,8); +// _FL_DEFPIN(9,9); _FL_DEFPIN(10,10); _FL_DEFPIN(11,11); -_DEFPIN_ESP32(12); -_DEFPIN_ESP32(13); -_DEFPIN_ESP32(14); -_DEFPIN_ESP32(15); -_DEFPIN_ESP32(16); -_DEFPIN_ESP32(17); -_DEFPIN_ESP32(18); -_DEFPIN_ESP32(19); +_FL_DEFPIN(12); +_FL_DEFPIN(13); +_FL_DEFPIN(14); +_FL_DEFPIN(15); +_FL_DEFPIN(16); +_FL_DEFPIN(17); +_FL_DEFPIN(18); +_FL_DEFPIN(19); -// No pin 20 : _DEFPIN_ESP32(20,20); +// No pin 20 : _FL_DEFPIN(20,20); -_DEFPIN_ESP32(21); // Works, but note that GPIO21 is I2C SDA -_DEFPIN_ESP32(22); // Works, but note that GPIO22 is I2C SCL -_DEFPIN_ESP32(23); +_FL_DEFPIN(21); // Works, but note that GPIO21 is I2C SDA +_FL_DEFPIN(22); // Works, but note that GPIO22 is I2C SCL +_FL_DEFPIN(23); -// No pin 24 : _DEFPIN_ESP32(24,24); +// No pin 24 : _FL_DEFPIN(24,24); -_DEFPIN_ESP32(25); -_DEFPIN_ESP32(26); -_DEFPIN_ESP32(27); +_FL_DEFPIN(25); +_FL_DEFPIN(26); +_FL_DEFPIN(27); -// No pin 28-31: _DEFPIN_ESP32(28,28); _DEFPIN_ESP32(29,29); _DEFPIN_ESP32(30,30); _DEFPIN_ESP32(31,31); +// No pin 28-31: _FL_DEFPIN(28,28); _FL_DEFPIN(29,29); _FL_DEFPIN(30,30); _FL_DEFPIN(31,31); // Need special handling for pins > 31 -_DEFPIN_32_33_ESP32(32); -_DEFPIN_32_33_ESP32(33); +_FL_DEFPIN(32); +_FL_DEFPIN(33); #define HAS_HARDWARE_PIN_SUPPORT diff --git a/platforms/esp/8266/fastpin_esp8266.h b/platforms/esp/8266/fastpin_esp8266.h index b8095b85..69085bf9 100644 --- a/platforms/esp/8266/fastpin_esp8266.h +++ b/platforms/esp/8266/fastpin_esp8266.h @@ -42,40 +42,40 @@ public: inline static bool isset() __attribute__ ((always_inline)) { return (PIN < 16) ? (GPO & MASK) : (GP16O & MASK); } }; -#define _DEFPIN_ESP8266(PIN, REAL_PIN) template<> class FastPin<PIN> : public _ESPPIN<REAL_PIN, (1<<(REAL_PIN & 0xFF))> {}; +#define _FL_DEFPIN(PIN, REAL_PIN) template<> class FastPin<PIN> : public _ESPPIN<REAL_PIN, (1<<(REAL_PIN & 0xFF))> {}; #ifdef FASTLED_ESP8266_RAW_PIN_ORDER #define MAX_PIN 16 -_DEFPIN_ESP8266(0,0); _DEFPIN_ESP8266(1,1); _DEFPIN_ESP8266(2,2); _DEFPIN_ESP8266(3,3); -_DEFPIN_ESP8266(4,4); _DEFPIN_ESP8266(5,5); +_FL_DEFPIN(0,0); _FL_DEFPIN(1,1); _FL_DEFPIN(2,2); _FL_DEFPIN(3,3); +_FL_DEFPIN(4,4); _FL_DEFPIN(5,5); // These pins should be disabled, as they always cause WDT resets -// _DEFPIN_ESP8266(6,6); _DEFPIN_ESP8266(7,7); -// _DEFPIN_ESP8266(8,8); _DEFPIN_ESP8266(9,9); _DEFPIN_ESP8266(10,10); _DEFPIN_ESP8266(11,11); +// _FL_DEFPIN(6,6); _FL_DEFPIN(7,7); +// _FL_DEFPIN(8,8); _FL_DEFPIN(9,9); _FL_DEFPIN(10,10); _FL_DEFPIN(11,11); -_DEFPIN_ESP8266(12,12); _DEFPIN_ESP8266(13,13); _DEFPIN_ESP8266(14,14); _DEFPIN_ESP8266(15,15); -_DEFPIN_ESP8266(16,16); +_FL_DEFPIN(12,12); _FL_DEFPIN(13,13); _FL_DEFPIN(14,14); _FL_DEFPIN(15,15); +_FL_DEFPIN(16,16); #define PORTA_FIRST_PIN 12 #elif defined(FASTLED_ESP8266_D1_PIN_ORDER) #define MAX_PIN 15 -_DEFPIN_ESP8266(0,3); -_DEFPIN_ESP8266(1,1); -_DEFPIN_ESP8266(2,16); -_DEFPIN_ESP8266(3,5); -_DEFPIN_ESP8266(4,4); -_DEFPIN_ESP8266(5,14); -_DEFPIN_ESP8266(6,12); -_DEFPIN_ESP8266(7,13); -_DEFPIN_ESP8266(8,0); -_DEFPIN_ESP8266(9,2); -_DEFPIN_ESP8266(10,15); -_DEFPIN_ESP8266(11,13); -_DEFPIN_ESP8266(12,12); -_DEFPIN_ESP8266(13,14); -_DEFPIN_ESP8266(14,4); -_DEFPIN_ESP8266(15,5); +_FL_DEFPIN(0,3); +_FL_DEFPIN(1,1); +_FL_DEFPIN(2,16); +_FL_DEFPIN(3,5); +_FL_DEFPIN(4,4); +_FL_DEFPIN(5,14); +_FL_DEFPIN(6,12); +_FL_DEFPIN(7,13); +_FL_DEFPIN(8,0); +_FL_DEFPIN(9,2); +_FL_DEFPIN(10,15); +_FL_DEFPIN(11,13); +_FL_DEFPIN(12,12); +_FL_DEFPIN(13,14); +_FL_DEFPIN(14,4); +_FL_DEFPIN(15,5); #define PORTA_FIRST_PIN 12 @@ -83,16 +83,16 @@ _DEFPIN_ESP8266(15,5); #define MAX_PIN 10 // This seems to be the standard Dxx pin mapping on most of the esp boards that i've found -_DEFPIN_ESP8266(0,16); _DEFPIN_ESP8266(1,5); _DEFPIN_ESP8266(2,4); _DEFPIN_ESP8266(3,0); -_DEFPIN_ESP8266(4,2); _DEFPIN_ESP8266(5,14); _DEFPIN_ESP8266(6,12); _DEFPIN_ESP8266(7,13); -_DEFPIN_ESP8266(8,15); _DEFPIN_ESP8266(9,3); _DEFPIN_ESP8266(10,1); +_FL_DEFPIN(0,16); _FL_DEFPIN(1,5); _FL_DEFPIN(2,4); _FL_DEFPIN(3,0); +_FL_DEFPIN(4,2); _FL_DEFPIN(5,14); _FL_DEFPIN(6,12); _FL_DEFPIN(7,13); +_FL_DEFPIN(8,15); _FL_DEFPIN(9,3); _FL_DEFPIN(10,1); #define PORTA_FIRST_PIN 6 // The rest of the pins - these are generally not available -// _DEFPIN_ESP8266(11,6); -// _DEFPIN_ESP8266(12,7); _DEFPIN_ESP8266(13,8); _DEFPIN_ESP8266(14,9); _DEFPIN_ESP8266(15,10); -// _DEFPIN_ESP8266(16,11); +// _FL_DEFPIN(11,6); +// _FL_DEFPIN(12,7); _FL_DEFPIN(13,8); _FL_DEFPIN(14,9); _FL_DEFPIN(15,10); +// _FL_DEFPIN(16,11); #endif |