Enable support for using both sets of hardware SPI pins on the teensy 3.1.

3 files changed, 52 insertions, 41 deletions

diff --git a/platforms/arm/k20/fastpin_arm_k20.h b/platforms/arm/k20/fastpin_arm_k20.h
index 99666a49..497ae256 100644
--- a/platforms/arm/k20/fastpin_arm_k20.h
+++ b/platforms/arm/k20/fastpin_arm_k20.h
@@ -103,10 +103,8 @@ _DEFPIN_ARM(32, 18, B); _DEFPIN_ARM(33, 4, A);
 #define SPI_CLOCK 13
 #define SPI1            (*(SPI_t *)0x4002D000)
 
-#if  defined(__MK20DX256__)
 #define SPI2_DATA 7
 #define SPI2_CLOCK 14
-#endif
 
 #define FASTLED_TEENSY3
 #define ARM_HARDWARE_SPI
diff --git a/platforms/arm/k20/fastspi_arm_k20.h b/platforms/arm/k20/fastspi_arm_k20.h
index ad9598ae..0ad05ef9 100644
--- a/platforms/arm/k20/fastspi_arm_k20.h
+++ b/platforms/arm/k20/fastspi_arm_k20.h
@@ -144,42 +144,42 @@ public:
     }
 
     void setSPIRate() {
-		// Configure CTAR0, defaulting to 8 bits and CTAR1, defaulting to 16 bits
-	 	uint32_t _PBR = 0;
-	 	uint32_t _BR = 0;
-	 	uint32_t _CSSCK = 0;
-	 	uint32_t _DBR = 0;
-
-	 	// if(_SPI_CLOCK_DIVIDER >= 256) 		{ _PBR = 0; _BR = _CSSCK = 7; _DBR = 0; } // osc/256
-	 	// else if(_SPI_CLOCK_DIVIDER >= 128) 	{ _PBR = 0; _BR = _CSSCK = 6; _DBR = 0; } // osc/128
-	 	// else if(_SPI_CLOCK_DIVIDER >= 64) 	{ _PBR = 0; _BR = _CSSCK = 5; _DBR = 0; } // osc/64
-	 	// else if(_SPI_CLOCK_DIVIDER >= 32) 	{ _PBR = 0; _BR = _CSSCK = 4; _DBR = 0; } // osc/32
-	 	// else if(_SPI_CLOCK_DIVIDER >= 16) 	{ _PBR = 0; _BR = _CSSCK = 3; _DBR = 0; } // osc/16
-	 	// else if(_SPI_CLOCK_DIVIDER >= 8) 	{ _PBR = 0; _BR = _CSSCK = 1; _DBR = 0; } // osc/8
-	 	// else if(_SPI_CLOCK_DIVIDER >= 7) 	{ _PBR = 3; _BR = _CSSCK = 0; _DBR = 1; } // osc/7
-	 	// else if(_SPI_CLOCK_DIVIDER >= 5) 	{ _PBR = 2; _BR = _CSSCK = 0; _DBR = 1; } // osc/5
-	 	// else if(_SPI_CLOCK_DIVIDER >= 4) 	{ _PBR = 0; _BR = _CSSCK = 0; _DBR = 0; } // osc/4
-	 	// else if(_SPI_CLOCK_DIVIDER >= 3) 	{ _PBR = 1; _BR = _CSSCK = 0; _DBR = 1; } // osc/3
-	 	// else                                { _PBR = 0; _BR = _CSSCK = 0; _DBR = 1; } // osc/2
-
-	 	getScalars<_SPI_CLOCK_DIVIDER>(_PBR, _BR, _DBR);
-	 	_CSSCK = _BR;
-
-	 	uint32_t ctar0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(_PBR) | SPI_CTAR_BR(_BR) | SPI_CTAR_CSSCK(_CSSCK);
-	 	uint32_t ctar1 = SPI_CTAR_FMSZ(15) | SPI_CTAR_PBR(_PBR) | SPI_CTAR_BR(_BR) | SPI_CTAR_CSSCK(_CSSCK);
-
-#if USE_CONT == 1
-	 	ctar0 |= SPI_CTAR_CPHA | SPI_CTAR_CPOL;
-	 	ctar1 |= SPI_CTAR_CPHA | SPI_CTAR_CPOL;
-#endif
-
-	 	if(_DBR) {
-	 		ctar0 |= SPI_CTAR_DBR;
-	 		ctar1 |= SPI_CTAR_DBR;
-	 	}
-
-	    update_ctar0(ctar0);
-	    update_ctar1(ctar1);
+			// Configure CTAR0, defaulting to 8 bits and CTAR1, defaulting to 16 bits
+		 	uint32_t _PBR = 0;
+		 	uint32_t _BR = 0;
+		 	uint32_t _CSSCK = 0;
+		 	uint32_t _DBR = 0;
+
+		 	// if(_SPI_CLOCK_DIVIDER >= 256) 		{ _PBR = 0; _BR = _CSSCK = 7; _DBR = 0; } // osc/256
+		 	// else if(_SPI_CLOCK_DIVIDER >= 128) 	{ _PBR = 0; _BR = _CSSCK = 6; _DBR = 0; } // osc/128
+		 	// else if(_SPI_CLOCK_DIVIDER >= 64) 	{ _PBR = 0; _BR = _CSSCK = 5; _DBR = 0; } // osc/64
+		 	// else if(_SPI_CLOCK_DIVIDER >= 32) 	{ _PBR = 0; _BR = _CSSCK = 4; _DBR = 0; } // osc/32
+		 	// else if(_SPI_CLOCK_DIVIDER >= 16) 	{ _PBR = 0; _BR = _CSSCK = 3; _DBR = 0; } // osc/16
+		 	// else if(_SPI_CLOCK_DIVIDER >= 8) 	{ _PBR = 0; _BR = _CSSCK = 1; _DBR = 0; } // osc/8
+		 	// else if(_SPI_CLOCK_DIVIDER >= 7) 	{ _PBR = 3; _BR = _CSSCK = 0; _DBR = 1; } // osc/7
+		 	// else if(_SPI_CLOCK_DIVIDER >= 5) 	{ _PBR = 2; _BR = _CSSCK = 0; _DBR = 1; } // osc/5
+		 	// else if(_SPI_CLOCK_DIVIDER >= 4) 	{ _PBR = 0; _BR = _CSSCK = 0; _DBR = 0; } // osc/4
+		 	// else if(_SPI_CLOCK_DIVIDER >= 3) 	{ _PBR = 1; _BR = _CSSCK = 0; _DBR = 1; } // osc/3
+		 	// else                                { _PBR = 0; _BR = _CSSCK = 0; _DBR = 1; } // osc/2
+
+		 	getScalars<_SPI_CLOCK_DIVIDER>(_PBR, _BR, _DBR);
+		 	_CSSCK = _BR;
+
+		 	uint32_t ctar0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(_PBR) | SPI_CTAR_BR(_BR) | SPI_CTAR_CSSCK(_CSSCK);
+		 	uint32_t ctar1 = SPI_CTAR_FMSZ(15) | SPI_CTAR_PBR(_PBR) | SPI_CTAR_BR(_BR) | SPI_CTAR_CSSCK(_CSSCK);
+
+	#if USE_CONT == 1
+		 	ctar0 |= SPI_CTAR_CPHA | SPI_CTAR_CPOL;
+		 	ctar1 |= SPI_CTAR_CPHA | SPI_CTAR_CPOL;
+	#endif
+
+		 	if(_DBR) {
+		 		ctar0 |= SPI_CTAR_DBR;
+		 		ctar1 |= SPI_CTAR_DBR;
+		 	}
+
+		    update_ctar0(ctar0);
+		    update_ctar1(ctar1);
 
     }
 
@@ -204,6 +204,8 @@ public:
 				SPIX.CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1);
 			}
 		}
+
+
 		setSPIRate();
 
 		// Configure SPI as the master and enable
@@ -280,8 +282,15 @@ public:
 		update_ctar1(ctar1_save);
 	}
 
-	void inline select() __attribute__((always_inline)) { if(m_pSelect != NULL) { m_pSelect->select(); } }
-	void inline release() __attribute__((always_inline)) { if(m_pSelect != NULL) { m_pSelect->release(); } }
+	void inline select() __attribute__((always_inline)) {
+		if(m_pSelect != NULL) { m_pSelect->select(); }
+		enable_pins();
+	}
+
+	void inline release() __attribute__((always_inline)) {
+		disable_pins();
+		if(m_pSelect != NULL) { m_pSelect->release(); }
+	}
 
 	static void writeBytesValueRaw(uint8_t value, int len) {
 		while(len--) { Write<CM, WM, NOTLAST>::writeByte(value); }
diff --git a/preview_changes.txt b/preview_changes.txt
index d20d5084..f58f911a 100644
--- a/preview_changes.txt
+++ b/preview_changes.txt
@@ -1,10 +1,14 @@
 FastLED 3.1 preview changes:
+* Support for using both hardware SPI pinsets on the Teensy 3.x - 11/13 and 7/14.
+* Added UCS1904 support
+* Better AVR cycle counting
+* Split WS2812/WS2811 timings
 * Added DOTSTAR definition for adafruit dotstar pixels (aka APA102)
 * 8-way parallel output on teensy 3, 3.1 (portc,portd), due/digix (porta, portb, portd)
 * 12-way parallel output on teensy 3, 3.1 (portc)
 * 16-way parallel output on teensy 3, 3.1 (portd & portd paired)
 * refresh rate limiting
 * interrupt friendly code on teensy 3/3.1
-* interrupt friendly code on AVR
+* -interrupt friendly code on AVR- <-- disabled for now
 * interrupt friendly code on the due
 * code re-org for future wider platform support