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-rw-r--r--examples/Pintest/Pintest.ino79
-rw-r--r--fastpin.h22
-rw-r--r--platforms/arm/k20/fastpin_arm_k20.h6
-rw-r--r--platforms/arm/k66/fastpin_arm_k66.h6
-rw-r--r--platforms/arm/kl26/fastpin_arm_kl26.h6
-rw-r--r--platforms/arm/kl26/led_sysdefs_arm_kl26.h2
-rw-r--r--platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h2
-rw-r--r--platforms/arm/sam/fastpin_arm_sam.h11
-rw-r--r--platforms/arm/stm32/fastpin_arm_stm32.h36
-rw-r--r--platforms/avr/fastpin_avr.h74
10 files changed, 186 insertions, 58 deletions
diff --git a/examples/Pintest/Pintest.ino b/examples/Pintest/Pintest.ino
index f0a0dadc..a8141520 100644
--- a/examples/Pintest/Pintest.ino
+++ b/examples/Pintest/Pintest.ino
@@ -94,12 +94,12 @@ template<uint8_t PIN> void CheckPin()
{
CheckPin<PIN - 1>();
- RwReg *systemThinksPortIs = portOutputRegister(digitalPinToPort(PIN));
+ void *systemThinksPortIs = (void*)portOutputRegister(digitalPinToPort(PIN));
RwReg systemThinksMaskIs = digitalPinToBitMask(PIN);
Serial.print("Pin "); Serial.print(PIN); Serial.print(": Port ");
- if(systemThinksPortIs == FastPin<PIN>::port()) {
+ if(systemThinksPortIs == (void*)FastPin<PIN>::port()) {
Serial.print("valid & mask ");
} else {
Serial.print("invalid, is "); Serial.print(getPort((void*)FastPin<PIN>::port())); Serial.print(" should be ");
@@ -114,8 +114,68 @@ template<uint8_t PIN> void CheckPin()
}
}
-template<> void CheckPin<-1> () {}
+template<> void CheckPin<255> () {}
+
+
+template<uint8_t _PORT> const char *_GetPinPort(void *ptr) {
+ if (__FL_PORT_INFO<_PORT>::hasPort() && (ptr == (void*)__FL_PORT_INFO<_PORT>::portAddr())) {
+ return __FL_PORT_INFO<_PORT>::portName();
+ } else {
+ return _GetPinPort<_PORT - 1>(ptr);
+ }
+}
+template<> const char *_GetPinPort<-1>(void *ptr) {
+ return NULL;
+}
+
+const char *GetPinPort(void *ptr) {
+ return _GetPinPort<'Z'>(ptr);
+}
+
+static uint8_t pcount = 0;
+
+
+template<uint8_t PIN> void PrintPins() {
+ PrintPins<PIN - 1>();
+
+ RwReg *systemThinksPortIs = portOutputRegister(digitalPinToPort(PIN));
+ RwReg systemThinksMaskIs = digitalPinToBitMask(PIN);
+
+ int maskBit = 0;
+ while(systemThinksMaskIs > 1) { systemThinksMaskIs >>= 1; maskBit++; }
+ const char *pinport = GetPinPort((void*)systemThinksPortIs);
+ if (pinport) {
+ Serial.print("__FL_DEFPIN("); Serial.print(PIN);
+ Serial.print(","); Serial.print(maskBit);
+ Serial.print(","); Serial.print(pinport);
+ Serial.print("); ");
+ pcount++;
+ if(pcount == 4) { pcount = 0; Serial.println(""); }
+ } else {
+ // Serial.print("Not found for pin "); Serial.println(PIN);
+ }
+}
+
+template<> void PrintPins<0>() {
+ RwReg *systemThinksPortIs = portOutputRegister(digitalPinToPort(0));
+ RwReg systemThinksMaskIs = digitalPinToBitMask(0);
+
+ int maskBit = 0;
+ while(systemThinksMaskIs > 1) { systemThinksMaskIs >>= 1; maskBit++; }
+
+ const char *pinport = GetPinPort((void*)systemThinksPortIs);
+ if (pinport) {
+ Serial.print("__FL_DEFPIN("); Serial.print(0);
+ Serial.print(","); Serial.print(maskBit);
+ Serial.print(","); Serial.print(pinport);
+ Serial.print("); ");
+ pcount++;
+ if(pcount == 4) { pcount = 0; Serial.println(""); }
+ }
+}
+
+int counter = 0;
void setup() {
delay(5000);
Serial.begin(38400);
@@ -123,8 +183,17 @@ void setup() {
}
void loop() {
+ Serial.println(counter);
+
+#ifdef MAX_PIN
CheckPin<MAX_PIN>();
- delay(100000);
+#endif
- Serial.print("GPIO_1_DR is: "); Serial.print(getPort((void*)&(GPIO1_DR)));
+ Serial.println("-----");
+#ifdef NUM_DIGITAL_PINS
+ PrintPins<NUM_DIGITAL_PINS>();
+#endif
+ Serial.println("------");
+
+ delay(100000);
}
diff --git a/fastpin.h b/fastpin.h
index beb3a2d8..ed2b8e7e 100644
--- a/fastpin.h
+++ b/fastpin.h
@@ -241,6 +241,28 @@ template<uint8_t PIN> class FastPinBB : public FastPin<PIN> {};
typedef volatile uint32_t & reg32_t;
typedef volatile uint32_t * ptr_reg32_t;
+// Utility templates for tracking down information about pins and ports
+template<uint8_t port> struct __FL_PORT_INFO {
+ static bool hasPort() { return 0; }
+ static const char *portName() { return "--"; }
+ static const void *portAddr() { return NULL; }
+};
+
+// Give us our instantiations for defined ports - we're going to abuse this later for
+// auto discovery of pin/port mappings for new variants. Use _FL_DEFINE_PORT for ports that
+// are numeric in nature, e.g. GPIO0, GPIO1. Use _FL_DEFINE_PORT3 for ports that are letters.
+// The first parameter will be the letter, the second parameter will be an integer/counter of smoe kind
+// (this is because attempts to turn macro parameters into character constants break in some compilers)
+#define _FL_DEFINE_PORT(L, BASE) template<> struct __FL_PORT_INFO<L> { static bool hasPort() { return 1; } \
+ static const char *portName() { return #L; } \
+ typedef BASE __t_baseType; \
+ static const void *portAddr() { return (void*)&__t_baseType::r(); } };
+
+#define _FL_DEFINE_PORT3(L, LC, BASE) template<> struct __FL_PORT_INFO<LC> { static bool hasPort() { return 1; } \
+ static const char *portName() { return #L; } \
+ typedef BASE __t_baseType; \
+ static const void *portAddr() { return (void*)&__t_baseType::r(); } };
+
FASTLED_NAMESPACE_END
#pragma GCC diagnostic pop
diff --git a/platforms/arm/k20/fastpin_arm_k20.h b/platforms/arm/k20/fastpin_arm_k20.h
index 54968176..736bd461 100644
--- a/platforms/arm/k20/fastpin_arm_k20.h
+++ b/platforms/arm/k20/fastpin_arm_k20.h
@@ -78,7 +78,7 @@ public:
#define _R(T) struct __gen_struct_ ## T
#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
-#define _FL_IO(L) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR);
+#define _FL_IO(L,C) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR); _FL_DEFINE_PORT3(L,C,_R(GPIO ## L ## _PDOR));
#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; \
@@ -86,9 +86,9 @@ public:
_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {};
// Actual pin definitions
-#if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY)
+_FL_IO(A,0); _FL_IO(B,1); _FL_IO(C,2); _FL_IO(D,3); _FL_IO(E,4);
-_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E);
+#if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY)
#define MAX_PIN 33
_FL_DEFPIN(0, 16, B); _FL_DEFPIN(1, 17, B); _FL_DEFPIN(2, 0, D); _FL_DEFPIN(3, 12, A);
diff --git a/platforms/arm/k66/fastpin_arm_k66.h b/platforms/arm/k66/fastpin_arm_k66.h
index 92471936..ef48396c 100644
--- a/platforms/arm/k66/fastpin_arm_k66.h
+++ b/platforms/arm/k66/fastpin_arm_k66.h
@@ -78,18 +78,18 @@ public:
#define _R(T) struct __gen_struct_ ## T
#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
-#define _FL_IO(L) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR);
+#define _FL_IO(L,C) _RD32(GPIO ## L ## _PDOR); _RD32(GPIO ## L ## _PSOR); _RD32(GPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(GPIO ## L ## _PDIR); _RD32(GPIO ## L ## _PDDR); _FL_DEFINE_PORT3(L,C,_R(GPIO ## L ## _PDOR));
#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; \
template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {};
+_FL_IO(A,0); _FL_IO(B,1); _FL_IO(C,2); _FL_IO(D,3); _FL_IO(E,4);
+
// Actual pin definitions
#if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY)
-_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E);
-
#define MAX_PIN 63
_FL_DEFPIN( 0, 16, B); _FL_DEFPIN( 1, 17, B); _FL_DEFPIN( 2, 0, D); _FL_DEFPIN( 3, 12, A);
_FL_DEFPIN( 4, 13, A); _FL_DEFPIN( 5, 7, D); _FL_DEFPIN( 6, 4, D); _FL_DEFPIN( 7, 2, D);
diff --git a/platforms/arm/kl26/fastpin_arm_kl26.h b/platforms/arm/kl26/fastpin_arm_kl26.h
index b66948cd..8b3cbdfe 100644
--- a/platforms/arm/kl26/fastpin_arm_kl26.h
+++ b/platforms/arm/kl26/fastpin_arm_kl26.h
@@ -50,18 +50,18 @@ public:
#define _R(T) struct __gen_struct_ ## T
#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
-#define _FL_IO(L) _RD32(FGPIO ## L ## _PDOR); _RD32(FGPIO ## L ## _PSOR); _RD32(FGPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(FGPIO ## L ## _PDIR); _RD32(FGPIO ## L ## _PDDR);
+#define _FL_IO(L,C) _RD32(FGPIO ## L ## _PDOR); _RD32(FGPIO ## L ## _PSOR); _RD32(FGPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(FGPIO ## L ## _PDIR); _RD32(FGPIO ## L ## _PDDR); _FL_DEFINE_PORT3(L,C,_R(FGPIO ## L ## _PDOR));
#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(FGPIO ## L ## _PDOR), _R(FGPIO ## L ## _PSOR), _R(FGPIO ## L ## _PCOR), \
_R(GPIO ## L ## _PTOR), _R(FGPIO ## L ## _PDIR), _R(FGPIO ## L ## _PDDR)> {}; \
/* template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; */
+_FL_IO(A,0); _FL_IO(B,1); _FL_IO(C,2); _FL_IO(D,3); _FL_IO(E,4);
+
// Actual pin definitions
#if defined(FASTLED_TEENSYLC) && defined(CORE_TEENSY)
-_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E);
-
#define MAX_PIN 26
_FL_DEFPIN(0, 16, B); _FL_DEFPIN(1, 17, B); _FL_DEFPIN(2, 0, D); _FL_DEFPIN(3, 1, A);
_FL_DEFPIN(4, 2, A); _FL_DEFPIN(5, 7, D); _FL_DEFPIN(6, 4, D); _FL_DEFPIN(7, 2, D);
diff --git a/platforms/arm/kl26/led_sysdefs_arm_kl26.h b/platforms/arm/kl26/led_sysdefs_arm_kl26.h
index 466d7295..575e6399 100644
--- a/platforms/arm/kl26/led_sysdefs_arm_kl26.h
+++ b/platforms/arm/kl26/led_sysdefs_arm_kl26.h
@@ -13,7 +13,7 @@
// Default to allowing interrupts
#ifndef FASTLED_ALLOW_INTERRUPTS
-#define FASTLED_ALLOW_INTERRUPTS 1
+// #define FASTLED_ALLOW_INTERRUPTS 1
#endif
#if FASTLED_ALLOW_INTERRUPTS == 1
diff --git a/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h b/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h
index 6ee6d8f6..38c88410 100644
--- a/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h
+++ b/platforms/arm/mxrt1062/fastpin_arm_mxrt1062.h
@@ -45,7 +45,7 @@ public:
#define _R(T) struct __gen_struct_ ## T
#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } };
-#define _FL_IO(L) _RD32(GPIO ## L ## _DR); _RD32(GPIO ## L ## _DR_SET); _RD32(GPIO ## L ## _DR_CLEAR); _RD32(GPIO ## L ## _DR_TOGGLE);
+#define _FL_IO(L) _RD32(GPIO ## L ## _DR); _RD32(GPIO ## L ## _DR_SET); _RD32(GPIO ## L ## _DR_CLEAR); _RD32(GPIO ## L ## _DR_TOGGLE); _FL_DEFINE_PORT(L, _R(GPIO ## L ## _DR));
// From the teensy core - it looks like there's the "default set" of port registers at GPIO1-5 - but then there
// are a mirrored set for GPIO1-4 at GPIO6-9, which in the teensy core is referred to as "fast" - while the pin definitiosn
diff --git a/platforms/arm/sam/fastpin_arm_sam.h b/platforms/arm/sam/fastpin_arm_sam.h
index 62b00aa4..339c5e75 100644
--- a/platforms/arm/sam/fastpin_arm_sam.h
+++ b/platforms/arm/sam/fastpin_arm_sam.h
@@ -78,19 +78,20 @@ public:
#define _R(T) struct __gen_struct_ ## T
#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
-#define _FL_IO(L) _RD32(REG_PIO ## L ## _ODSR); _RD32(REG_PIO ## L ## _SODR); _RD32(REG_PIO ## L ## _CODR); _RD32(REG_PIO ## L ## _OER);
+#define _FL_IO(L,C) _RD32(REG_PIO ## L ## _ODSR); _RD32(REG_PIO ## L ## _SODR); _RD32(REG_PIO ## L ## _CODR); _RD32(REG_PIO ## L ## _OER); _FL_DEFINE_PORT3(L, C, _R(REG_PIO ## L ## _ODSR));
#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _DUEPIN<PIN, 1 << BIT, _R(REG_PIO ## L ## _ODSR), _R(REG_PIO ## L ## _SODR), _R(REG_PIO ## L ## _CODR), \
_R(GPIO ## L ## _OER)> {}; \
template<> class FastPinBB<PIN> : public _DUEPIN_BITBAND<PIN, BIT, _R(REG_PIO ## L ## _ODSR), _R(REG_PIO ## L ## _SODR), _R(REG_PIO ## L ## _CODR), \
_R(GPIO ## L ## _OER)> {};
+_FL_IO(A,0);
+_FL_IO(B,1);
+_FL_IO(C,2);
+_FL_IO(D,3);
+
#if defined(__SAM3X8E__)
-_FL_IO(A);
-_FL_IO(B);
-_FL_IO(C);
-_FL_IO(D);
#define MAX_PIN 78
_FL_DEFPIN(0, 8, A); _FL_DEFPIN(1, 9, A); _FL_DEFPIN(2, 25, B); _FL_DEFPIN(3, 28, C);
diff --git a/platforms/arm/stm32/fastpin_arm_stm32.h b/platforms/arm/stm32/fastpin_arm_stm32.h
index bb8981d3..c80390f3 100644
--- a/platforms/arm/stm32/fastpin_arm_stm32.h
+++ b/platforms/arm/stm32/fastpin_arm_stm32.h
@@ -56,22 +56,44 @@ public:
};
#if defined(STM32F10X_MD)
- #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile GPIO_TypeDef * r() { return T; } };
- #define _FL_IO(L) _RD32(GPIO ## L)
+ #define _R(T) struct __gen_struct_ ## T
+ #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile GPIO_TypeDef * r() { return T; } };
+ #define _FL_IO(L,C) _RD32(GPIO ## L); __FL_DEFINE_PORT3(L, C, _R(GPIO ## L));
#elif defined(__STM32F1__)
- #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline gpio_reg_map* r() { return T->regs; } };
- #define _FL_IO(L) _RD32(GPIO ## L)
+ #define _R(T) struct __gen_struct_ ## T
+ #define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline gpio_reg_map* r() { return T->regs; } };
+ #define _FL_IO(L,C) _RD32(GPIO ## L); __FL_DEFINE_PORT3(L, C, _R(GPIO ## L));
#else
#error "Platform not supported"
#endif
-#define _R(T) struct __gen_struct_ ## T
#define _FL_DEFPIN(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L)> {};
+#ifdef GPIOA
+_FL_IO(A,0);
+#endif
+#ifdef GPIOB
+_FL_IO(B,1);
+#endif
+#ifdef GPIOC
+_FL_IO(C,2);
+#endif
+#ifdef GPIOD
+_FL_IO(D,3);
+#endif
+#ifdef GPIOE
+_FL_IO(E,4);
+#endif
+#ifdef GPIOF
+_FL_IO(F,5);
+#endif
+#ifdef GPIOG
+_FL_IO(G,6);
+#endif
+
// Actual pin definitions
#if defined(SPARK) // Sparkfun STM32F103 based board
-_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); _FL_IO(F); _FL_IO(G);
#define MAX_PIN 19
@@ -106,8 +128,6 @@ _FL_DEFPIN(19, 2, A);
#if defined(__STM32F1__) // Generic STM32F103 aka "Blue Pill"
-_FL_IO(A); _FL_IO(B); _FL_IO(C);
-
#define MAX_PIN 46
_FL_DEFPIN(10, 0, A); // PA0 - PA7
diff --git a/platforms/avr/fastpin_avr.h b/platforms/avr/fastpin_avr.h
index 29456b23..a8df76c4 100644
--- a/platforms/avr/fastpin_avr.h
+++ b/platforms/avr/fastpin_avr.h
@@ -48,11 +48,54 @@ public:
typedef volatile uint8_t & reg8_t;
#define _R(T) struct __gen_struct_ ## T
#define _RD8(T) struct __gen_struct_ ## T { static inline reg8_t r() { return T; }};
-#define _FL_IO(L) _RD8(DDR ## L); _RD8(PORT ## L); _RD8(PIN ## L);
+#define _FL_IO(L,C) _RD8(DDR ## L); _RD8(PORT ## L); _RD8(PIN ## L); _FL_DEFINE_PORT3(L, C, _R(PORT ## L));
#define _FL_DEFPIN(_PIN, BIT, L) template<> class FastPin<_PIN> : public _AVRPIN<_PIN, 1<<BIT, _R(PORT ## L), _R(DDR ## L), _R(PIN ## L)> {};
+// Pre-do all the port definitions
+#ifdef PORTA
+ _FL_IO(A,0)
+#endif
+#ifdef PORTB
+ _FL_IO(B,1)
+#endif
+#ifdef PORTC
+ _FL_IO(C,2)
+#endif
+#ifdef PORTD
+ _FL_IO(D,3)
+#endif
+#ifdef PORTE
+ _FL_IO(E,4)
+#endif
+#ifdef PORTF
+ _FL_IO(F,5)
+#endif
+#ifdef PORTG
+ _FL_IO(G,6)
+#endif
+#ifdef PORTH
+ _FL_IO(H,7)
+#endif
+#ifdef PORTI
+ _FL_IO(I,8)
+#endif
+#ifdef PORTJ
+ _FL_IO(J,9)
+#endif
+#ifdef PORTK
+ _FL_IO(K,10)
+#endif
+#ifdef PORTL
+ _FL_IO(L,11)
+#endif
+#ifdef PORTM
+ _FL_IO(M,12)
+#endif
+#ifdef PORTN
+ _FL_IO(N,13)
+#endif
+
#if defined(__AVR_ATtiny85__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny25__)
-_FL_IO(B);
#if defined(__AVR_ATtiny25__)
#pragma message "ATtiny25 has very limited storage. This library could use up to more than 100% of its flash size"
@@ -67,7 +110,6 @@ _FL_DEFPIN(4, 4, B); _FL_DEFPIN(5, 5, B);
#elif defined(__AVR_ATtiny841__) || defined(__AVR_ATtiny441__)
#define MAX_PIN 11
-_FL_IO(A); _FL_IO(B);
_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B);
_FL_DEFPIN(3, 7, A); _FL_DEFPIN(4, 6, A); _FL_DEFPIN(5, 5, A);
@@ -79,13 +121,11 @@ _FL_DEFPIN(9, 1, A); _FL_DEFPIN(10, 0, A); _FL_DEFPIN(11, 3, B);
#elif defined(ARDUINO_AVR_DIGISPARK) // digispark pin layout
#define MAX_PIN 5
#define HAS_HARDWARE_PIN_SUPPORT 1
-_FL_IO(A); _FL_IO(B);
_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B);
_FL_DEFPIN(3, 7, A); _FL_DEFPIN(4, 6, A); _FL_DEFPIN(5, 5, A);
#elif defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
-_FL_IO(A); _FL_IO(B);
#define MAX_PIN 10
@@ -97,7 +137,6 @@ _FL_DEFPIN(8, 2, B); _FL_DEFPIN(9, 1, B); _FL_DEFPIN(10, 0, B);
#elif defined(ARDUINO_AVR_DIGISPARKPRO)
-_FL_IO(A); _FL_IO(B);
#define MAX_PIN 12
_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B); _FL_DEFPIN(3, 5, B);
@@ -106,7 +145,6 @@ _FL_DEFPIN(8, 2, A); _FL_DEFPIN(9, 3, A); _FL_DEFPIN(10, 4, A); _FL_DEFPIN(11, 5
_FL_DEFPIN(12, 6, A);
#elif defined(__AVR_ATtiny167__) || defined(__AVR_ATtiny87__)
-_FL_IO(A); _FL_IO(B);
#define MAX_PIN 15
@@ -122,8 +160,6 @@ _FL_DEFPIN(12, 4, B); _FL_DEFPIN(13, 5, B); _FL_DEFPIN(14, 6, B); _FL_DEFPIN(15,
#define HAS_HARDWARE_PIN_SUPPORT 1
#elif defined(ARDUINO_HOODLOADER2) && (defined(__AVR_ATmega32U2__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega8U2__)) || defined(__AVR_AT90USB82__) || defined(__AVR_AT90USB162__)
-_FL_IO(D); _FL_IO(B); _FL_IO(C);
-
#define MAX_PIN 20
_FL_DEFPIN( 0, 0, B); _FL_DEFPIN( 1, 1, B); _FL_DEFPIN( 2, 2, B); _FL_DEFPIN( 3, 3, B);
@@ -141,9 +177,6 @@ _FL_DEFPIN( 20, 7, D);
#elif defined(IS_BEAN)
-// Accelerated port definitions for arduino avrs
-_FL_IO(D); _FL_IO(B); _FL_IO(C);
-
#define MAX_PIN 19
_FL_DEFPIN( 0, 6, D); _FL_DEFPIN( 1, 1, B); _FL_DEFPIN( 2, 2, B); _FL_DEFPIN( 3, 3, B);
_FL_DEFPIN( 4, 4, B); _FL_DEFPIN( 5, 5, B); _FL_DEFPIN( 6, 0, D); _FL_DEFPIN( 7, 7, D);
@@ -163,8 +196,6 @@ _FL_DEFPIN(16, 2, C); _FL_DEFPIN(17, 3, C); _FL_DEFPIN(18, 4, C); _FL_DEFPIN(19,
#endif
#elif defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328PB__) || defined(__AVR_ATmega328__) || defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega8__)
-// Accelerated port definitions for arduino avrs
-_FL_IO(D); _FL_IO(B); _FL_IO(C);
#define MAX_PIN 19
_FL_DEFPIN( 0, 0, D); _FL_DEFPIN( 1, 1, D); _FL_DEFPIN( 2, 2, D); _FL_DEFPIN( 3, 3, D);
@@ -186,8 +217,6 @@ _FL_DEFPIN(16, 2, C); _FL_DEFPIN(17, 3, C); _FL_DEFPIN(18, 4, C); _FL_DEFPIN(19,
#elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__)
-_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D);
-
#define MAX_PIN 31
_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B); _FL_DEFPIN(3, 3, B);
_FL_DEFPIN(4, 4, B); _FL_DEFPIN(5, 5, B); _FL_DEFPIN(6, 6, B); _FL_DEFPIN(7, 7, B);
@@ -207,9 +236,6 @@ _FL_DEFPIN(28, 4, A); _FL_DEFPIN(29, 5, A); _FL_DEFPIN(30, 6, A); _FL_DEFPIN(31,
#elif defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega256RFR2__)
// AKA the Pinoccio
-
-_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); _FL_IO(F);
-
_FL_DEFPIN( 0, 0, E); _FL_DEFPIN( 1, 1, E); _FL_DEFPIN( 2, 7, B); _FL_DEFPIN( 3, 3, E);
_FL_DEFPIN( 4, 4, E); _FL_DEFPIN( 5, 5, E); _FL_DEFPIN( 6, 2, E); _FL_DEFPIN( 7, 6, E);
_FL_DEFPIN( 8, 5, D); _FL_DEFPIN( 9, 0, B); _FL_DEFPIN(10, 2, B); _FL_DEFPIN(11, 3, B);
@@ -228,9 +254,6 @@ _FL_DEFPIN(28, 4, F); _FL_DEFPIN(29, 5, F); _FL_DEFPIN(30, 6, F); _FL_DEFPIN(31,
#elif defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
// megas
-
-_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); _FL_IO(F); _FL_IO(G); _FL_IO(H); _FL_IO(J); _FL_IO(K); _FL_IO(L);
-
#define MAX_PIN 69
_FL_DEFPIN(0, 0, E); _FL_DEFPIN(1, 1, E); _FL_DEFPIN(2, 4, E); _FL_DEFPIN(3, 5, E);
_FL_DEFPIN(4, 5, G); _FL_DEFPIN(5, 3, E); _FL_DEFPIN(6, 3, H); _FL_DEFPIN(7, 4, H);
@@ -261,8 +284,6 @@ _FL_DEFPIN(68, 6, K); _FL_DEFPIN(69, 7, K);
#elif defined(__AVR_ATmega32U4__) && defined(CORE_TEENSY)
// teensy defs
-_FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); _FL_IO(F);
-
#define MAX_PIN 23
_FL_DEFPIN(0, 0, B); _FL_DEFPIN(1, 1, B); _FL_DEFPIN(2, 2, B); _FL_DEFPIN(3, 3, B);
_FL_DEFPIN(4, 7, B); _FL_DEFPIN(5, 0, D); _FL_DEFPIN(6, 1, D); _FL_DEFPIN(7, 2, D);
@@ -283,9 +304,6 @@ _FL_DEFPIN(20, 1, F); _FL_DEFPIN(21, 0, F); _FL_DEFPIN(22, 4, D); _FL_DEFPIN(23,
#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
// teensy++ 2 defs
-
-_FL_IO(A); _FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); _FL_IO(F);
-
#define MAX_PIN 45
_FL_DEFPIN(0, 0, D); _FL_DEFPIN(1, 1, D); _FL_DEFPIN(2, 2, D); _FL_DEFPIN(3, 3, D);
_FL_DEFPIN(4, 4, D); _FL_DEFPIN(5, 5, D); _FL_DEFPIN(6, 6, D); _FL_DEFPIN(7, 7, D);
@@ -314,8 +332,6 @@ _FL_DEFPIN(44, 6, F); _FL_DEFPIN(45, 7, F);
#elif defined(__AVR_ATmega32U4__)
// leonard defs
-_FL_IO(B); _FL_IO(C); _FL_IO(D); _FL_IO(E); _FL_IO(F);
-
#define MAX_PIN 30
_FL_DEFPIN(0, 2, D); _FL_DEFPIN(1, 3, D); _FL_DEFPIN(2, 1, D); _FL_DEFPIN(3, 0, D);
_FL_DEFPIN(4, 4, D); _FL_DEFPIN(5, 6, C); _FL_DEFPIN(6, 7, D); _FL_DEFPIN(7, 6, E);
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 04:54:50 +0300