Merge pull request #1794 from etra0/master

Add 64 bit support for OpSwitch

1 files changed, 23 insertions, 2 deletions

diff --git a/spirv_parser.cpp b/spirv_parser.cpp
index 58fcec10..da39367d 100644
--- a/spirv_parser.cpp
+++ b/spirv_parser.cpp
@@ -1018,8 +1018,21 @@ void Parser::parse(const Instruction &instruction)
 		current_block->condition = ops[0];
 		current_block->default_block = ops[1];
 
-		for (uint32_t i = 2; i + 2 <= length; i += 2)
-			current_block->cases.push_back({ ops[i], ops[i + 1] });
+		uint32_t remaining_ops = length - 2;
+		if ((remaining_ops % 2) == 0)
+		{
+			for (uint32_t i = 2; i + 2 <= length; i += 2)
+				current_block->cases_32bit.push_back({ ops[i], ops[i + 1] });
+		}
+
+		if ((remaining_ops % 3) == 0)
+		{
+			for (uint32_t i = 2; i + 3 <= length; i += 3)
+			{
+				uint64_t value = (static_cast<uint64_t>(ops[i]) << 32) | ops[i + 1];
+				current_block->cases_64bit.push_back({ value, ops[i + 2] });
+			}
+		}
 
 		// If we jump to next block, make it break instead since we're inside a switch case block at that point.
 		ir.block_meta[current_block->next_block] |= ParsedIR::BLOCK_META_MULTISELECT_MERGE_BIT;
@@ -1177,6 +1190,14 @@ void Parser::parse(const Instruction &instruction)
 	// Actual opcodes.
 	default:
 	{
+		if (length >= 2)
+		{
+			const auto *type = maybe_get<SPIRType>(ops[0]);
+			if (type)
+			{
+				ir.load_type_width.insert({ ops[1], type->width });
+			}
+		}
 		if (!current_block)
 			SPIRV_CROSS_THROW("Currently no block to insert opcode.");