Welcome to mirror list, hosted at ThFree Co, Russian Federation.

github.com/KhronosGroup/SPIRV-Headers.git - Unnamed repository; edit this file 'description' to name the repository.
summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--include/spirv/spir-v.xml10
-rw-r--r--include/spirv/unified1/spirv.core.grammar.json113
-rw-r--r--include/spirv/unified1/spirv.cs13
-rw-r--r--include/spirv/unified1/spirv.h18
-rw-r--r--include/spirv/unified1/spirv.hpp18
-rw-r--r--include/spirv/unified1/spirv.hpp1118
-rw-r--r--include/spirv/unified1/spirv.json17
-rw-r--r--include/spirv/unified1/spirv.lua13
-rw-r--r--include/spirv/unified1/spirv.py13
-rw-r--r--include/spirv/unified1/spv.d13
10 files changed, 238 insertions, 8 deletions
diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml
index eb4452b..3078e77 100644
--- a/include/spirv/spir-v.xml
+++ b/include/spirv/spir-v.xml
@@ -83,7 +83,8 @@
<id value="30" vendor="SpvGenTwo community" tool="SpvGenTwo SPIR-V IR Tools" comment="https://github.com/rAzoR8/SpvGenTwo"/>
<id value="31" vendor="Google" tool="Skia SkSL" comment="Contact Ethan Nicholas, ethannicholas@google.com"/>
<id value="32" vendor="TornadoVM" tool="SPIRV Beehive Toolkit" comment="https://github.com/beehive-lab/spirv-beehive-toolkit"/>
- <unused start="33" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
+ <id value="33" vendor="DragonJoker" tool="ShaderWriter" comment="Contact Sylvain Doremus, https://github.com/DragonJoker/ShaderWriter"/>
+ <unused start="34" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
</ids>
<!-- SECTION: SPIR-V Opcodes and Enumerants -->
@@ -165,13 +166,14 @@
<ids type="enumerant" start="6144" end="6271" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
<ids type="enumerant" start="6272" end="6399" vendor="Huawei" comment="Contact wanghuilong2@xunweitech.com"/>
<ids type="enumerant" start="6400" end="6463" vendor="Intel" comment="Contact ben.ashbaugh@intel.com"/>
+ <ids type="enumerant" start="6464" end="6527" vendor="Mikkosoft Productions" comment="Contact Mikko Rasa, tdb@tdb.fi"/>
<!-- Enumerants to reserve for future use. To get a block, allocate
multiples of 64 starting at the lowest available point in this
block and add a corresponding <ids> tag immediately above. Make
sure to fill in the vendor attribute, and preferably add a contact
person/address in a comment attribute. -->
<!-- Example new block: <ids type="enumerant" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> -->
- <ids type="enumerant" start="6464" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
+ <ids type="enumerant" start="6528" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<!-- End reservations of enumerants -->
@@ -191,8 +193,8 @@
<!-- Reserved loop control bits -->
<ids type="LoopControl" start="0" end="15" vendor="Khronos" comment="Reserved LoopControl bits, not available to vendors - see the SPIR-V Specification"/>
- <ids type="LoopControl" start="16" end="24" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
- <ids type="LoopControl" start="25" end="30" comment="Unreserved bits reservable for use by vendors"/>
+ <ids type="LoopControl" start="16" end="25" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
+ <ids type="LoopControl" start="26" end="30" comment="Unreserved bits reservable for use by vendors"/>
<ids type="LoopControl" start="31" end="31" vendor="Khronos" comment="Reserved LoopControl bit, not available to vendors"/>
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index 766a4ed..d0d9a36 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -5029,7 +5029,7 @@
"opname" : "OpDemoteToHelperInvocationEXT",
"class" : "Control-Flow",
"opcode" : 5380,
- "capabilities" : [ "DemoteToHelperInvocation" ],
+ "capabilities" : [ "DemoteToHelperInvocationEXT" ],
"version" : "1.6"
},
{
@@ -7870,6 +7870,43 @@
"version" : "None"
},
{
+ "opname" : "OpAliasDomainDeclINTEL",
+ "class" : "@exclude",
+ "opcode" : 5911,
+ "operands" : [
+ { "kind" : "IdResult"},
+ { "kind" : "IdRef", "quantifier" : "?", "name" : "'Name'" }
+ ],
+ "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+ "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpAliasScopeDeclINTEL",
+ "class" : "@exclude",
+ "opcode" : 5912,
+ "operands" : [
+ { "kind" : "IdResult"},
+ { "kind" : "IdRef", "name" : "'Alias Domain'"},
+ { "kind" : "IdRef", "quantifier" : "?", "name" : "'Name'" }
+ ],
+ "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+ "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpAliasScopeListDeclINTEL",
+ "class" : "@exclude",
+ "opcode" : 5913,
+ "operands" : [
+ { "kind" : "IdResult"},
+ { "kind" : "IdRef", "quantifier" : "*", "name" : "'AliasScope1, AliasScope2, ...'" }
+ ],
+ "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+ "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpFixedSqrtINTEL",
"class" : "@exclude",
"opcode" : 5923,
@@ -8512,6 +8549,30 @@
],
"capabilities" : [ "LongConstantCompositeINTEL" ],
"version" : "None"
+ },
+ {
+ "opname" : "OpControlBarrierArriveINTEL",
+ "class" : "Barrier",
+ "opcode" : 6142,
+ "operands" : [
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "IdScope", "name" : "'Memory'" },
+ { "kind" : "IdMemorySemantics", "name" : "'Semantics'" }
+ ],
+ "capabilities" : [ "SplitBarrierINTEL" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpControlBarrierWaitINTEL",
+ "class" : "Barrier",
+ "opcode" : 6143,
+ "operands" : [
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "IdScope", "name" : "'Memory'" },
+ { "kind" : "IdMemorySemantics", "name" : "'Semantics'" }
+ ],
+ "capabilities" : [ "SplitBarrierINTEL" ],
+ "version" : "None"
}
],
"operand_kinds" : [
@@ -9090,6 +9151,26 @@
"capabilities" : [ "VulkanMemoryModel" ],
"extensions" : [ "SPV_KHR_vulkan_memory_model" ],
"version" : "1.5"
+ },
+ {
+ "enumerant" : "AliasScopeINTELMask",
+ "value" : "0x10000",
+ "parameters" : [
+ { "kind" : "IdRef" }
+ ],
+ "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+ "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "NoAliasINTELMask",
+ "parameters" : [
+ { "kind" : "IdRef" }
+ ],
+ "value" : "0x20000",
+ "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+ "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+ "version" : "None"
}
]
},
@@ -11580,6 +11661,24 @@
"version" : "None"
},
{
+ "enumerant" : "AliasScopeINTEL",
+ "value" : 5914,
+ "parameters" : [
+ { "kind" : "IdRef", "name" : "'Aliasing Scopes List'" }
+ ],
+ "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "NoAliasINTEL",
+ "value" : 5915,
+ "parameters" : [
+ { "kind" : "IdRef", "name" : "'Aliasing Scopes List'" }
+ ],
+ "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "BufferLocationINTEL",
"value" : 5921,
"parameters" : [
@@ -13678,6 +13777,12 @@
"version" : "None"
},
{
+ "enumerant" : "MemoryAccessAliasingINTEL",
+ "value" : 5910,
+ "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "FPGABufferLocationINTEL",
"value" : 5920,
"extensions" : [ "SPV_INTEL_fpga_buffer_location" ],
@@ -13800,6 +13905,12 @@
"value" : 6114,
"extensions" : [ "SPV_INTEL_debug_module" ],
"version" : "None"
+ },
+ {
+ "enumerant" : "SplitBarrierINTEL",
+ "value" : 6141,
+ "extensions" : [ "SPV_INTEL_split_barrier" ],
+ "version" : "None"
}
]
},
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 9cf00ec..53821a3 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -540,6 +540,8 @@ namespace Spv
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ AliasScopeINTEL = 5914,
+ NoAliasINTEL = 5915,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -802,6 +804,8 @@ namespace Spv
MakePointerVisibleKHR = 4,
NonPrivatePointer = 5,
NonPrivatePointerKHR = 5,
+ AliasScopeINTELMask = 16,
+ NoAliasINTELMask = 17,
}
public enum MemoryAccessMask
@@ -816,6 +820,8 @@ namespace Spv
MakePointerVisibleKHR = 0x00000010,
NonPrivatePointer = 0x00000020,
NonPrivatePointerKHR = 0x00000020,
+ AliasScopeINTELMask = 0x00010000,
+ NoAliasINTELMask = 0x00020000,
}
public enum Scope
@@ -1059,6 +1065,7 @@ namespace Spv
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ MemoryAccessAliasingINTEL = 5910,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
@@ -1080,6 +1087,7 @@ namespace Spv
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
}
public enum RayFlagsShift
@@ -1803,6 +1811,9 @@ namespace Spv
OpArbitraryFloatPowRINTEL = 5881,
OpArbitraryFloatPowNINTEL = 5882,
OpLoopControlINTEL = 5887,
+ OpAliasDomainDeclINTEL = 5911,
+ OpAliasScopeDeclINTEL = 5912,
+ OpAliasScopeListDeclINTEL = 5913,
OpFixedSqrtINTEL = 5923,
OpFixedRecipINTEL = 5924,
OpFixedRsqrtINTEL = 5925,
@@ -1841,6 +1852,8 @@ namespace Spv
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
}
}
}
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index fa9828a..2b6b35f 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -546,6 +546,8 @@ typedef enum SpvDecoration_ {
SpvDecorationPrefetchINTEL = 5902,
SpvDecorationStallEnableINTEL = 5905,
SpvDecorationFuseLoopsInFunctionINTEL = 5907,
+ SpvDecorationAliasScopeINTEL = 5914,
+ SpvDecorationNoAliasINTEL = 5915,
SpvDecorationBufferLocationINTEL = 5921,
SpvDecorationIOPipeStorageINTEL = 5944,
SpvDecorationFunctionFloatingPointModeINTEL = 6080,
@@ -804,6 +806,8 @@ typedef enum SpvMemoryAccessShift_ {
SpvMemoryAccessMakePointerVisibleKHRShift = 4,
SpvMemoryAccessNonPrivatePointerShift = 5,
SpvMemoryAccessNonPrivatePointerKHRShift = 5,
+ SpvMemoryAccessAliasScopeINTELMaskShift = 16,
+ SpvMemoryAccessNoAliasINTELMaskShift = 17,
SpvMemoryAccessMax = 0x7fffffff,
} SpvMemoryAccessShift;
@@ -818,6 +822,8 @@ typedef enum SpvMemoryAccessMask_ {
SpvMemoryAccessMakePointerVisibleKHRMask = 0x00000010,
SpvMemoryAccessNonPrivatePointerMask = 0x00000020,
SpvMemoryAccessNonPrivatePointerKHRMask = 0x00000020,
+ SpvMemoryAccessAliasScopeINTELMaskMask = 0x00010000,
+ SpvMemoryAccessNoAliasINTELMaskMask = 0x00020000,
} SpvMemoryAccessMask;
typedef enum SpvScope_ {
@@ -1059,6 +1065,7 @@ typedef enum SpvCapability_ {
SpvCapabilityFPGAMemoryAccessesINTEL = 5898,
SpvCapabilityFPGAClusterAttributesINTEL = 5904,
SpvCapabilityLoopFuseINTEL = 5906,
+ SpvCapabilityMemoryAccessAliasingINTEL = 5910,
SpvCapabilityFPGABufferLocationINTEL = 5920,
SpvCapabilityArbitraryPrecisionFixedPointINTEL = 5922,
SpvCapabilityUSMStorageClassesINTEL = 5935,
@@ -1080,6 +1087,7 @@ typedef enum SpvCapability_ {
SpvCapabilityOptNoneINTEL = 6094,
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
+ SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityMax = 0x7fffffff,
} SpvCapability;
@@ -1801,6 +1809,9 @@ typedef enum SpvOp_ {
SpvOpArbitraryFloatPowRINTEL = 5881,
SpvOpArbitraryFloatPowNINTEL = 5882,
SpvOpLoopControlINTEL = 5887,
+ SpvOpAliasDomainDeclINTEL = 5911,
+ SpvOpAliasScopeDeclINTEL = 5912,
+ SpvOpAliasScopeListDeclINTEL = 5913,
SpvOpFixedSqrtINTEL = 5923,
SpvOpFixedRecipINTEL = 5924,
SpvOpFixedRsqrtINTEL = 5925,
@@ -1839,6 +1850,8 @@ typedef enum SpvOp_ {
SpvOpTypeStructContinuedINTEL = 6090,
SpvOpConstantCompositeContinuedINTEL = 6091,
SpvOpSpecConstantCompositeContinuedINTEL = 6092,
+ SpvOpControlBarrierArriveINTEL = 6142,
+ SpvOpControlBarrierWaitINTEL = 6143,
SpvOpMax = 0x7fffffff,
} SpvOp;
@@ -2455,6 +2468,9 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpArbitraryFloatPowRINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpArbitraryFloatPowNINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpAliasDomainDeclINTEL: *hasResult = true; *hasResultType = false; break;
+ case SpvOpAliasScopeDeclINTEL: *hasResult = true; *hasResultType = false; break;
+ case SpvOpAliasScopeListDeclINTEL: *hasResult = true; *hasResultType = false; break;
case SpvOpFixedSqrtINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpFixedRecipINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpFixedRsqrtINTEL: *hasResult = true; *hasResultType = true; break;
@@ -2493,6 +2509,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
}
}
#endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index c3d2060..08eae15 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -542,6 +542,8 @@ enum Decoration {
DecorationPrefetchINTEL = 5902,
DecorationStallEnableINTEL = 5905,
DecorationFuseLoopsInFunctionINTEL = 5907,
+ DecorationAliasScopeINTEL = 5914,
+ DecorationNoAliasINTEL = 5915,
DecorationBufferLocationINTEL = 5921,
DecorationIOPipeStorageINTEL = 5944,
DecorationFunctionFloatingPointModeINTEL = 6080,
@@ -800,6 +802,8 @@ enum MemoryAccessShift {
MemoryAccessMakePointerVisibleKHRShift = 4,
MemoryAccessNonPrivatePointerShift = 5,
MemoryAccessNonPrivatePointerKHRShift = 5,
+ MemoryAccessAliasScopeINTELMaskShift = 16,
+ MemoryAccessNoAliasINTELMaskShift = 17,
MemoryAccessMax = 0x7fffffff,
};
@@ -814,6 +818,8 @@ enum MemoryAccessMask {
MemoryAccessMakePointerVisibleKHRMask = 0x00000010,
MemoryAccessNonPrivatePointerMask = 0x00000020,
MemoryAccessNonPrivatePointerKHRMask = 0x00000020,
+ MemoryAccessAliasScopeINTELMaskMask = 0x00010000,
+ MemoryAccessNoAliasINTELMaskMask = 0x00020000,
};
enum Scope {
@@ -1055,6 +1061,7 @@ enum Capability {
CapabilityFPGAMemoryAccessesINTEL = 5898,
CapabilityFPGAClusterAttributesINTEL = 5904,
CapabilityLoopFuseINTEL = 5906,
+ CapabilityMemoryAccessAliasingINTEL = 5910,
CapabilityFPGABufferLocationINTEL = 5920,
CapabilityArbitraryPrecisionFixedPointINTEL = 5922,
CapabilityUSMStorageClassesINTEL = 5935,
@@ -1076,6 +1083,7 @@ enum Capability {
CapabilityOptNoneINTEL = 6094,
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
+ CapabilitySplitBarrierINTEL = 6141,
CapabilityMax = 0x7fffffff,
};
@@ -1797,6 +1805,9 @@ enum Op {
OpArbitraryFloatPowRINTEL = 5881,
OpArbitraryFloatPowNINTEL = 5882,
OpLoopControlINTEL = 5887,
+ OpAliasDomainDeclINTEL = 5911,
+ OpAliasScopeDeclINTEL = 5912,
+ OpAliasScopeListDeclINTEL = 5913,
OpFixedSqrtINTEL = 5923,
OpFixedRecipINTEL = 5924,
OpFixedRsqrtINTEL = 5925,
@@ -1835,6 +1846,8 @@ enum Op {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
OpMax = 0x7fffffff,
};
@@ -2451,6 +2464,9 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpArbitraryFloatPowRINTEL: *hasResult = true; *hasResultType = true; break;
case OpArbitraryFloatPowNINTEL: *hasResult = true; *hasResultType = true; break;
case OpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpAliasDomainDeclINTEL: *hasResult = true; *hasResultType = false; break;
+ case OpAliasScopeDeclINTEL: *hasResult = true; *hasResultType = false; break;
+ case OpAliasScopeListDeclINTEL: *hasResult = true; *hasResultType = false; break;
case OpFixedSqrtINTEL: *hasResult = true; *hasResultType = true; break;
case OpFixedRecipINTEL: *hasResult = true; *hasResultType = true; break;
case OpFixedRsqrtINTEL: *hasResult = true; *hasResultType = true; break;
@@ -2489,6 +2505,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
}
}
#endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index 38e71c5..d203289 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -542,6 +542,8 @@ enum class Decoration : unsigned {
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ AliasScopeINTEL = 5914,
+ NoAliasINTEL = 5915,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -800,6 +802,8 @@ enum class MemoryAccessShift : unsigned {
MakePointerVisibleKHR = 4,
NonPrivatePointer = 5,
NonPrivatePointerKHR = 5,
+ AliasScopeINTELMask = 16,
+ NoAliasINTELMask = 17,
Max = 0x7fffffff,
};
@@ -814,6 +818,8 @@ enum class MemoryAccessMask : unsigned {
MakePointerVisibleKHR = 0x00000010,
NonPrivatePointer = 0x00000020,
NonPrivatePointerKHR = 0x00000020,
+ AliasScopeINTELMask = 0x00010000,
+ NoAliasINTELMask = 0x00020000,
};
enum class Scope : unsigned {
@@ -1055,6 +1061,7 @@ enum class Capability : unsigned {
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ MemoryAccessAliasingINTEL = 5910,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
@@ -1076,6 +1083,7 @@ enum class Capability : unsigned {
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
Max = 0x7fffffff,
};
@@ -1797,6 +1805,9 @@ enum class Op : unsigned {
OpArbitraryFloatPowRINTEL = 5881,
OpArbitraryFloatPowNINTEL = 5882,
OpLoopControlINTEL = 5887,
+ OpAliasDomainDeclINTEL = 5911,
+ OpAliasScopeDeclINTEL = 5912,
+ OpAliasScopeListDeclINTEL = 5913,
OpFixedSqrtINTEL = 5923,
OpFixedRecipINTEL = 5924,
OpFixedRsqrtINTEL = 5925,
@@ -1835,6 +1846,8 @@ enum class Op : unsigned {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
Max = 0x7fffffff,
};
@@ -2451,6 +2464,9 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpArbitraryFloatPowRINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpArbitraryFloatPowNINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpAliasDomainDeclINTEL: *hasResult = true; *hasResultType = false; break;
+ case Op::OpAliasScopeDeclINTEL: *hasResult = true; *hasResultType = false; break;
+ case Op::OpAliasScopeListDeclINTEL: *hasResult = true; *hasResultType = false; break;
case Op::OpFixedSqrtINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpFixedRecipINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpFixedRsqrtINTEL: *hasResult = true; *hasResultType = true; break;
@@ -2489,6 +2505,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
}
}
#endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index e80d3bd..33ba1f3 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -568,6 +568,8 @@
"PrefetchINTEL": 5902,
"StallEnableINTEL": 5905,
"FuseLoopsInFunctionINTEL": 5907,
+ "AliasScopeINTEL": 5914,
+ "NoAliasINTEL": 5915,
"BufferLocationINTEL": 5921,
"IOPipeStorageINTEL": 5944,
"FunctionFloatingPointModeINTEL": 6080,
@@ -786,7 +788,9 @@
"MakePointerVisible": 4,
"MakePointerVisibleKHR": 4,
"NonPrivatePointer": 5,
- "NonPrivatePointerKHR": 5
+ "NonPrivatePointerKHR": 5,
+ "AliasScopeINTELMask": 16,
+ "NoAliasINTELMask": 17
}
},
{
@@ -1039,6 +1043,7 @@
"FPGAMemoryAccessesINTEL": 5898,
"FPGAClusterAttributesINTEL": 5904,
"LoopFuseINTEL": 5906,
+ "MemoryAccessAliasingINTEL": 5910,
"FPGABufferLocationINTEL": 5920,
"ArbitraryPrecisionFixedPointINTEL": 5922,
"USMStorageClassesINTEL": 5935,
@@ -1059,7 +1064,8 @@
"LongConstantCompositeINTEL": 6089,
"OptNoneINTEL": 6094,
"AtomicFloat16AddEXT": 6095,
- "DebugInfoModuleINTEL": 6114
+ "DebugInfoModuleINTEL": 6114,
+ "SplitBarrierINTEL": 6141
}
},
{
@@ -1792,6 +1798,9 @@
"OpArbitraryFloatPowRINTEL": 5881,
"OpArbitraryFloatPowNINTEL": 5882,
"OpLoopControlINTEL": 5887,
+ "OpAliasDomainDeclINTEL": 5911,
+ "OpAliasScopeDeclINTEL": 5912,
+ "OpAliasScopeListDeclINTEL": 5913,
"OpFixedSqrtINTEL": 5923,
"OpFixedRecipINTEL": 5924,
"OpFixedRsqrtINTEL": 5925,
@@ -1829,7 +1838,9 @@
"OpTypeBufferSurfaceINTEL": 6086,
"OpTypeStructContinuedINTEL": 6090,
"OpConstantCompositeContinuedINTEL": 6091,
- "OpSpecConstantCompositeContinuedINTEL": 6092
+ "OpSpecConstantCompositeContinuedINTEL": 6092,
+ "OpControlBarrierArriveINTEL": 6142,
+ "OpControlBarrierWaitINTEL": 6143
}
}
]
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index 2f5e803..4e4dc84 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -515,6 +515,8 @@ spv = {
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ AliasScopeINTEL = 5914,
+ NoAliasINTEL = 5915,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -767,6 +769,8 @@ spv = {
MakePointerVisibleKHR = 4,
NonPrivatePointer = 5,
NonPrivatePointerKHR = 5,
+ AliasScopeINTELMask = 16,
+ NoAliasINTELMask = 17,
},
MemoryAccessMask = {
@@ -780,6 +784,8 @@ spv = {
MakePointerVisibleKHR = 0x00000010,
NonPrivatePointer = 0x00000020,
NonPrivatePointerKHR = 0x00000020,
+ AliasScopeINTELMask = 0x00010000,
+ NoAliasINTELMask = 0x00020000,
},
Scope = {
@@ -1017,6 +1023,7 @@ spv = {
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ MemoryAccessAliasingINTEL = 5910,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
@@ -1038,6 +1045,7 @@ spv = {
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
},
RayFlagsShift = {
@@ -1748,6 +1756,9 @@ spv = {
OpArbitraryFloatPowRINTEL = 5881,
OpArbitraryFloatPowNINTEL = 5882,
OpLoopControlINTEL = 5887,
+ OpAliasDomainDeclINTEL = 5911,
+ OpAliasScopeDeclINTEL = 5912,
+ OpAliasScopeListDeclINTEL = 5913,
OpFixedSqrtINTEL = 5923,
OpFixedRecipINTEL = 5924,
OpFixedRsqrtINTEL = 5925,
@@ -1786,6 +1797,8 @@ spv = {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
},
}
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index 7aee89f..47e7c4c 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -515,6 +515,8 @@ spv = {
'PrefetchINTEL' : 5902,
'StallEnableINTEL' : 5905,
'FuseLoopsInFunctionINTEL' : 5907,
+ 'AliasScopeINTEL' : 5914,
+ 'NoAliasINTEL' : 5915,
'BufferLocationINTEL' : 5921,
'IOPipeStorageINTEL' : 5944,
'FunctionFloatingPointModeINTEL' : 6080,
@@ -767,6 +769,8 @@ spv = {
'MakePointerVisibleKHR' : 4,
'NonPrivatePointer' : 5,
'NonPrivatePointerKHR' : 5,
+ 'AliasScopeINTELMask' : 16,
+ 'NoAliasINTELMask' : 17,
},
'MemoryAccessMask' : {
@@ -780,6 +784,8 @@ spv = {
'MakePointerVisibleKHR' : 0x00000010,
'NonPrivatePointer' : 0x00000020,
'NonPrivatePointerKHR' : 0x00000020,
+ 'AliasScopeINTELMask' : 0x00010000,
+ 'NoAliasINTELMask' : 0x00020000,
},
'Scope' : {
@@ -1017,6 +1023,7 @@ spv = {
'FPGAMemoryAccessesINTEL' : 5898,
'FPGAClusterAttributesINTEL' : 5904,
'LoopFuseINTEL' : 5906,
+ 'MemoryAccessAliasingINTEL' : 5910,
'FPGABufferLocationINTEL' : 5920,
'ArbitraryPrecisionFixedPointINTEL' : 5922,
'USMStorageClassesINTEL' : 5935,
@@ -1038,6 +1045,7 @@ spv = {
'OptNoneINTEL' : 6094,
'AtomicFloat16AddEXT' : 6095,
'DebugInfoModuleINTEL' : 6114,
+ 'SplitBarrierINTEL' : 6141,
},
'RayFlagsShift' : {
@@ -1748,6 +1756,9 @@ spv = {
'OpArbitraryFloatPowRINTEL' : 5881,
'OpArbitraryFloatPowNINTEL' : 5882,
'OpLoopControlINTEL' : 5887,
+ 'OpAliasDomainDeclINTEL' : 5911,
+ 'OpAliasScopeDeclINTEL' : 5912,
+ 'OpAliasScopeListDeclINTEL' : 5913,
'OpFixedSqrtINTEL' : 5923,
'OpFixedRecipINTEL' : 5924,
'OpFixedRsqrtINTEL' : 5925,
@@ -1786,6 +1797,8 @@ spv = {
'OpTypeStructContinuedINTEL' : 6090,
'OpConstantCompositeContinuedINTEL' : 6091,
'OpSpecConstantCompositeContinuedINTEL' : 6092,
+ 'OpControlBarrierArriveINTEL' : 6142,
+ 'OpControlBarrierWaitINTEL' : 6143,
},
}
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index a17e63d..6cd26ce 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -543,6 +543,8 @@ enum Decoration : uint
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ AliasScopeINTEL = 5914,
+ NoAliasINTEL = 5915,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -805,6 +807,8 @@ enum MemoryAccessShift : uint
MakePointerVisibleKHR = 4,
NonPrivatePointer = 5,
NonPrivatePointerKHR = 5,
+ AliasScopeINTELMask = 16,
+ NoAliasINTELMask = 17,
}
enum MemoryAccessMask : uint
@@ -819,6 +823,8 @@ enum MemoryAccessMask : uint
MakePointerVisibleKHR = 0x00000010,
NonPrivatePointer = 0x00000020,
NonPrivatePointerKHR = 0x00000020,
+ AliasScopeINTELMask = 0x00010000,
+ NoAliasINTELMask = 0x00020000,
}
enum Scope : uint
@@ -1062,6 +1068,7 @@ enum Capability : uint
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ MemoryAccessAliasingINTEL = 5910,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
@@ -1083,6 +1090,7 @@ enum Capability : uint
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
}
enum RayFlagsShift : uint
@@ -1806,6 +1814,9 @@ enum Op : uint
OpArbitraryFloatPowRINTEL = 5881,
OpArbitraryFloatPowNINTEL = 5882,
OpLoopControlINTEL = 5887,
+ OpAliasDomainDeclINTEL = 5911,
+ OpAliasScopeDeclINTEL = 5912,
+ OpAliasScopeListDeclINTEL = 5913,
OpFixedSqrtINTEL = 5923,
OpFixedRecipINTEL = 5924,
OpFixedRsqrtINTEL = 5925,
@@ -1844,6 +1855,8 @@ enum Op : uint
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-04 12:21:42 +0300