From 00191b5cc4c626c61ff45afa1949e3977547909e Mon Sep 17 00:00:00 2001
From: D4SK <konstantin.vogel@gmx.net>
Date: Thu, 20 Oct 2022 21:59:38 +0200
Subject: stm32: Enable instruction and data cache on stm32h7

Signed-off-by: Konstantin Vogel <konstantin.vogel@gmx.net>
---
 src/stm32/stm32h7.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c
index 056f7be29..d24d07b7f 100644
--- a/src/stm32/stm32h7.c
+++ b/src/stm32/stm32h7.c
@@ -148,6 +148,9 @@ clock_setup(void)
             ;
     }
 
+    SCB_EnableICache();
+    SCB_EnableDCache();
+
     // Set flash latency according to clock frequency (pg.159)
     uint32_t flash_acr_latency = (CONFIG_CLOCK_FREQ > 450000000) ?
         FLASH_ACR_LATENCY_4WS : FLASH_ACR_LATENCY_2WS;
-- 
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