/*++ Copyright (c) Alex Ionescu. All rights reserved. Header Name: vmx.h Abstract: This header defines the MSRs and VMCS fields for Intel x64 VT-x support. Author: Alex Ionescu (@aionescu) 16-Mar-2016 - Initial version Environment: Kernel mode only. --*/ #pragma once #pragma warning(disable:4201) #pragma warning(disable:4214) #define DPL_USER 3 #define DPL_SYSTEM 0 #define MSR_GS_BASE 0xC0000101 #define MSR_DEBUG_CTL 0x1D9 #define RPL_MASK 3 #define MTRR_TYPE_UC 0 #define MTRR_TYPE_USWC 1 #define MTRR_TYPE_WT 4 #define MTRR_TYPE_WP 5 #define MTRR_TYPE_WB 6 #define MTRR_TYPE_MAX 7 #define SELECTOR_TABLE_INDEX 0x04 #define EFLAGS_ALIGN_CHECK 0x40000 #define AMD64_TSS 9 #ifndef PAGE_SIZE #define PAGE_SIZE 4096 #endif #define MTRR_MSR_CAPABILITIES 0x0fe #define MTRR_MSR_DEFAULT 0x2ff #define MTRR_MSR_VARIABLE_BASE 0x200 #define MTRR_MSR_VARIABLE_MASK (MTRR_MSR_VARIABLE_BASE+1) #define MTRR_PAGE_SIZE 4096 #define MTRR_PAGE_MASK (~(MTRR_PAGE_SIZE-1)) typedef struct _KDESCRIPTOR { UINT16 Pad[3]; UINT16 Limit; void* Base; } KDESCRIPTOR, *PKDESCRIPTOR; typedef union _KGDTENTRY64 { struct { UINT16 LimitLow; UINT16 BaseLow; union { struct { UINT8 BaseMiddle; UINT8 Flags1; UINT8 Flags2; UINT8 BaseHigh; } Bytes; struct { UINT32 BaseMiddle : 8; UINT32 Type : 5; UINT32 Dpl : 2; UINT32 Present : 1; UINT32 LimitHigh : 4; UINT32 System : 1; UINT32 LongMode : 1; UINT32 DefaultBig : 1; UINT32 Granularity : 1; UINT32 BaseHigh : 8; } Bits; }; UINT32 BaseUpper; UINT32 MustBeZero; }; struct { INT64 DataLow; INT64 DataHigh; }; } KGDTENTRY64, *PKGDTENTRY64; #pragma pack(push,4) typedef struct _KTSS64 { UINT32 Reserved0; UINT64 Rsp0; UINT64 Rsp1; UINT64 Rsp2; UINT64 Ist[8]; UINT64 Reserved1; UINT16 Reserved2; UINT16 IoMapBase; } KTSS64, *PKTSS64; #pragma pack(pop) typedef struct _MTRR_CAPABILITIES { union { struct { UINT64 VarCnt : 8; UINT64 FixedSupported : 1; UINT64 Reserved : 1; UINT64 WcSupported : 1; UINT64 SmrrSupported : 1; UINT64 Reserved_2 : 52; }; UINT64 AsUlonglong; }; } MTRR_CAPABILITIES, *PMTRR_CAPABILITIES; C_ASSERT(sizeof(MTRR_CAPABILITIES) == sizeof(UINT64)); typedef struct _MTRR_VARIABLE_BASE { union { struct { UINT64 Type : 8; UINT64 Reserved : 4; UINT64 PhysBase : 36; UINT64 Reserved2 : 16; }; UINT64 AsUlonglong; }; } MTRR_VARIABLE_BASE, *PMTRR_VARIABLE_BASE; C_ASSERT(sizeof(MTRR_VARIABLE_BASE) == sizeof(UINT64)); typedef struct _MTRR_VARIABLE_MASK { union { struct { UINT64 Reserved : 11; UINT64 Enabled : 1; UINT64 PhysMask : 36; UINT64 Reserved2 : 16; }; UINT64 AsUlonglong; }; } MTRR_VARIABLE_MASK, *PMTRR_VARIABLE_MASK; C_ASSERT(sizeof(MTRR_VARIABLE_MASK) == sizeof(UINT64)); #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008 #define CPU_BASED_HLT_EXITING 0x00000080 #define CPU_BASED_INVLPG_EXITING 0x00000200 #define CPU_BASED_MWAIT_EXITING 0x00000400 #define CPU_BASED_RDPMC_EXITING 0x00000800 #define CPU_BASED_RDTSC_EXITING 0x00001000 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000 #define CPU_BASED_CR3_STORE_EXITING 0x00010000 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 #define CPU_BASED_TPR_SHADOW 0x00200000 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 #define CPU_BASED_MOV_DR_EXITING 0x00800000 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000 #define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 #define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000 #define CPU_BASED_MONITOR_EXITING 0x20000000 #define CPU_BASED_PAUSE_EXITING 0x40000000 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 #define PIN_BASED_EXT_INTR_MASK 0x00000001 #define PIN_BASED_NMI_EXITING 0x00000008 #define PIN_BASED_VIRTUAL_NMIS 0x00000020 #define PIN_BASED_PREEMPT_TIMER 0x00000040 #define PIN_BASED_POSTED_INTERRUPT 0x00000080 #define VM_EXIT_SAVE_DEBUG_CNTRLS 0x00000004 #define VM_EXIT_IA32E_MODE 0x00000200 #define VM_EXIT_LOAD_PERF_GLOBAL_CTRL 0x00001000 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 #define VM_EXIT_SAVE_GUEST_PAT 0x00040000 #define VM_EXIT_LOAD_HOST_PAT 0x00080000 #define VM_EXIT_SAVE_GUEST_EFER 0x00100000 #define VM_EXIT_LOAD_HOST_EFER 0x00200000 #define VM_EXIT_SAVE_PREEMPT_TIMER 0x00400000 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000 #define VM_ENTRY_IA32E_MODE 0x00000200 #define VM_ENTRY_SMM 0x00000400 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 #define VM_ENTRY_LOAD_PERF_GLOBAL_CTRL 0x00002000 #define VM_ENTRY_LOAD_GUEST_PAT 0x00004000 #define VM_ENTRY_LOAD_GUEST_EFER 0x00008000 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002 #define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004 #define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 #define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000 #define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000 #define SECONDARY_EXEC_ENABLE_PML 0x00020000 #define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 #define SECONDARY_EXEC_XSAVES 0x00100000 #define SECONDARY_EXEC_PCOMMIT 0x00200000 #define SECONDARY_EXEC_TSC_SCALING 0x02000000 #define VMX_BASIC_REVISION_MASK 0x7fffffff #define VMX_BASIC_VMCS_SIZE_MASK (0x1fffULL << 32) #define VMX_BASIC_32BIT_ADDRESSES (1ULL << 48) #define VMX_BASIC_DUAL_MONITOR (1ULL << 49) #define VMX_BASIC_MEMORY_TYPE_MASK (0xfULL << 50) #define VMX_BASIC_INS_OUT_INFO (1ULL << 54) #define VMX_BASIC_DEFAULT1_ZERO (1ULL << 55) #define VMX_EPT_EXECUTE_ONLY_BIT (1ULL) #define VMX_EPT_PAGE_WALK_4_BIT (1ULL << 6) #define VMX_EPTP_UC_BIT (1ULL << 8) #define VMX_EPTP_WB_BIT (1ULL << 14) #define VMX_EPT_2MB_PAGE_BIT (1ULL << 16) #define VMX_EPT_1GB_PAGE_BIT (1ULL << 17) #define VMX_EPT_INVEPT_BIT (1ULL << 20) #define VMX_EPT_AD_BIT (1ULL << 21) #define VMX_EPT_EXTENT_CONTEXT_BIT (1ULL << 25) #define VMX_EPT_EXTENT_GLOBAL_BIT (1ULL << 26) /* MSRs & bits used for VMX enabling */ #define MSR_IA32_VMX_BASIC 0x480 #define MSR_IA32_VMX_PINBASED_CTLS 0x481 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 #define MSR_IA32_VMX_EXIT_CTLS 0x483 #define MSR_IA32_VMX_ENTRY_CTLS 0x484 #define MSR_IA32_VMX_MISC 0x485 #define MSR_IA32_VMX_CR0_FIXED0 0x486 #define MSR_IA32_VMX_CR0_FIXED1 0x487 #define MSR_IA32_VMX_CR4_FIXED0 0x488 #define MSR_IA32_VMX_CR4_FIXED1 0x489 #define MSR_IA32_VMX_VMCS_ENUM 0x48a #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 #define IA32_FEATURE_CONTROL_MSR 0x3a #define IA32_FEATURE_CONTROL_MSR_LOCK 0x0001 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX 0x0002 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX 0x0004 #define IA32_FEATURE_CONTROL_MSR_SENTER_PARAM_CTL 0x7f00 #define IA32_FEATURE_CONTROL_MSR_ENABLE_SENTER 0x8000 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 #define HYPERV_CPUID_INTERFACE 0x40000001 #define HYPERV_CPUID_VERSION 0x40000002 #define HYPERV_CPUID_FEATURES 0x40000003 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 #define HYPERV_CPUID_MIN 0x40000005 #define HYPERV_CPUID_MAX 0x4000ffff enum vmcs_field { VIRTUAL_PROCESSOR_ID = 0x00000000, POSTED_INTR_NOTIFICATION_VECTOR = 0x00000002, EPTP_INDEX = 0x00000004, GUEST_ES_SELECTOR = 0x00000800, GUEST_CS_SELECTOR = 0x00000802, GUEST_SS_SELECTOR = 0x00000804, GUEST_DS_SELECTOR = 0x00000806, GUEST_FS_SELECTOR = 0x00000808, GUEST_GS_SELECTOR = 0x0000080a, GUEST_LDTR_SELECTOR = 0x0000080c, GUEST_TR_SELECTOR = 0x0000080e, GUEST_INTR_STATUS = 0x00000810, GUEST_PML_INDEX = 0x00000812, HOST_ES_SELECTOR = 0x00000c00, HOST_CS_SELECTOR = 0x00000c02, HOST_SS_SELECTOR = 0x00000c04, HOST_DS_SELECTOR = 0x00000c06, HOST_FS_SELECTOR = 0x00000c08, HOST_GS_SELECTOR = 0x00000c0a, HOST_TR_SELECTOR = 0x00000c0c, IO_BITMAP_A = 0x00002000, IO_BITMAP_B = 0x00002002, MSR_BITMAP = 0x00002004, VM_EXIT_MSR_STORE_ADDR = 0x00002006, VM_EXIT_MSR_LOAD_ADDR = 0x00002008, VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, PML_ADDRESS = 0x0000200e, TSC_OFFSET = 0x00002010, VIRTUAL_APIC_PAGE_ADDR = 0x00002012, APIC_ACCESS_ADDR = 0x00002014, PI_DESC_ADDR = 0x00002016, VM_FUNCTION_CONTROL = 0x00002018, EPT_POINTER = 0x0000201a, EOI_EXIT_BITMAP0 = 0x0000201c, EPTP_LIST_ADDR = 0x00002024, VMREAD_BITMAP = 0x00002026, VMWRITE_BITMAP = 0x00002028, VIRT_EXCEPTION_INFO = 0x0000202a, XSS_EXIT_BITMAP = 0x0000202c, TSC_MULTIPLIER = 0x00002032, GUEST_PHYSICAL_ADDRESS = 0x00002400, VMCS_LINK_POINTER = 0x00002800, GUEST_IA32_DEBUGCTL = 0x00002802, GUEST_PAT = 0x00002804, GUEST_EFER = 0x00002806, GUEST_PERF_GLOBAL_CTRL = 0x00002808, GUEST_PDPTE0 = 0x0000280a, GUEST_BNDCFGS = 0x00002812, HOST_PAT = 0x00002c00, HOST_EFER = 0x00002c02, HOST_PERF_GLOBAL_CTRL = 0x00002c04, PIN_BASED_VM_EXEC_CONTROL = 0x00004000, CPU_BASED_VM_EXEC_CONTROL = 0x00004002, EXCEPTION_BITMAP = 0x00004004, PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, CR3_TARGET_COUNT = 0x0000400a, VM_EXIT_CONTROLS = 0x0000400c, VM_EXIT_MSR_STORE_COUNT = 0x0000400e, VM_EXIT_MSR_LOAD_COUNT = 0x00004010, VM_ENTRY_CONTROLS = 0x00004012, VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, VM_ENTRY_INTR_INFO = 0x00004016, VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, TPR_THRESHOLD = 0x0000401c, SECONDARY_VM_EXEC_CONTROL = 0x0000401e, PLE_GAP = 0x00004020, PLE_WINDOW = 0x00004022, VM_INSTRUCTION_ERROR = 0x00004400, VM_EXIT_REASON = 0x00004402, VM_EXIT_INTR_INFO = 0x00004404, VM_EXIT_INTR_ERROR_CODE = 0x00004406, IDT_VECTORING_INFO = 0x00004408, IDT_VECTORING_ERROR_CODE = 0x0000440a, VM_EXIT_INSTRUCTION_LEN = 0x0000440c, VMX_INSTRUCTION_INFO = 0x0000440e, GUEST_ES_LIMIT = 0x00004800, GUEST_CS_LIMIT = 0x00004802, GUEST_SS_LIMIT = 0x00004804, GUEST_DS_LIMIT = 0x00004806, GUEST_FS_LIMIT = 0x00004808, GUEST_GS_LIMIT = 0x0000480a, GUEST_LDTR_LIMIT = 0x0000480c, GUEST_TR_LIMIT = 0x0000480e, GUEST_GDTR_LIMIT = 0x00004810, GUEST_IDTR_LIMIT = 0x00004812, GUEST_ES_AR_BYTES = 0x00004814, GUEST_CS_AR_BYTES = 0x00004816, GUEST_SS_AR_BYTES = 0x00004818, GUEST_DS_AR_BYTES = 0x0000481a, GUEST_FS_AR_BYTES = 0x0000481c, GUEST_GS_AR_BYTES = 0x0000481e, GUEST_LDTR_AR_BYTES = 0x00004820, GUEST_TR_AR_BYTES = 0x00004822, GUEST_INTERRUPTIBILITY_INFO = 0x00004824, GUEST_ACTIVITY_STATE = 0x00004826, GUEST_SMBASE = 0x00004828, GUEST_SYSENTER_CS = 0x0000482a, GUEST_PREEMPTION_TIMER = 0x0000482e, HOST_SYSENTER_CS = 0x00004c00, CR0_GUEST_HOST_MASK = 0x00006000, CR4_GUEST_HOST_MASK = 0x00006002, CR0_READ_SHADOW = 0x00006004, CR4_READ_SHADOW = 0x00006006, CR3_TARGET_VALUE0 = 0x00006008, EXIT_QUALIFICATION = 0x00006400, GUEST_LINEAR_ADDRESS = 0x0000640a, GUEST_CR0 = 0x00006800, GUEST_CR3 = 0x00006802, GUEST_CR4 = 0x00006804, GUEST_ES_BASE = 0x00006806, GUEST_CS_BASE = 0x00006808, GUEST_SS_BASE = 0x0000680a, GUEST_DS_BASE = 0x0000680c, GUEST_FS_BASE = 0x0000680e, GUEST_GS_BASE = 0x00006810, GUEST_LDTR_BASE = 0x00006812, GUEST_TR_BASE = 0x00006814, GUEST_GDTR_BASE = 0x00006816, GUEST_IDTR_BASE = 0x00006818, GUEST_DR7 = 0x0000681a, GUEST_RSP = 0x0000681c, GUEST_RIP = 0x0000681e, GUEST_RFLAGS = 0x00006820, GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, GUEST_SYSENTER_ESP = 0x00006824, GUEST_SYSENTER_EIP = 0x00006826, HOST_CR0 = 0x00006c00, HOST_CR3 = 0x00006c02, HOST_CR4 = 0x00006c04, HOST_FS_BASE = 0x00006c06, HOST_GS_BASE = 0x00006c08, HOST_TR_BASE = 0x00006c0a, HOST_GDTR_BASE = 0x00006c0c, HOST_IDTR_BASE = 0x00006c0e, HOST_SYSENTER_ESP = 0x00006c10, HOST_SYSENTER_EIP = 0x00006c12, HOST_RSP = 0x00006c14, HOST_RIP = 0x00006c16, }; #define EXIT_REASON_EXCEPTION_NMI 0 #define EXIT_REASON_EXTERNAL_INTERRUPT 1 #define EXIT_REASON_TRIPLE_FAULT 2 #define EXIT_REASON_INIT 3 #define EXIT_REASON_SIPI 4 #define EXIT_REASON_IO_SMI 5 #define EXIT_REASON_OTHER_SMI 6 #define EXIT_REASON_PENDING_VIRT_INTR 7 #define EXIT_REASON_PENDING_VIRT_NMI 8 #define EXIT_REASON_TASK_SWITCH 9 #define EXIT_REASON_CPUID 10 #define EXIT_REASON_GETSEC 11 #define EXIT_REASON_HLT 12 #define EXIT_REASON_INVD 13 #define EXIT_REASON_INVLPG 14 #define EXIT_REASON_RDPMC 15 #define EXIT_REASON_RDTSC 16 #define EXIT_REASON_RSM 17 #define EXIT_REASON_VMCALL 18 #define EXIT_REASON_VMCLEAR 19 #define EXIT_REASON_VMLAUNCH 20 #define EXIT_REASON_VMPTRLD 21 #define EXIT_REASON_VMPTRST 22 #define EXIT_REASON_VMREAD 23 #define EXIT_REASON_VMRESUME 24 #define EXIT_REASON_VMWRITE 25 #define EXIT_REASON_VMXOFF 26 #define EXIT_REASON_VMXON 27 #define EXIT_REASON_CR_ACCESS 28 #define EXIT_REASON_DR_ACCESS 29 #define EXIT_REASON_IO_INSTRUCTION 30 #define EXIT_REASON_MSR_READ 31 #define EXIT_REASON_MSR_WRITE 32 #define EXIT_REASON_INVALID_GUEST_STATE 33 #define EXIT_REASON_MSR_LOADING 34 #define EXIT_REASON_MWAIT_INSTRUCTION 36 #define EXIT_REASON_MONITOR_TRAP_FLAG 37 #define EXIT_REASON_MONITOR_INSTRUCTION 39 #define EXIT_REASON_PAUSE_INSTRUCTION 40 #define EXIT_REASON_MCE_DURING_VMENTRY 41 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43 #define EXIT_REASON_APIC_ACCESS 44 #define EXIT_REASON_ACCESS_GDTR_OR_IDTR 46 #define EXIT_REASON_ACCESS_LDTR_OR_TR 47 #define EXIT_REASON_EPT_VIOLATION 48 #define EXIT_REASON_EPT_MISCONFIG 49 #define EXIT_REASON_INVEPT 50 #define EXIT_REASON_RDTSCP 51 #define EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED 52 #define EXIT_REASON_INVVPID 53 #define EXIT_REASON_WBINVD 54 #define EXIT_REASON_XSETBV 55 #define EXIT_REASON_APIC_WRITE 56 #define EXIT_REASON_RDRAND 57 #define EXIT_REASON_INVPCID 58 #define EXIT_REASON_RDSEED 61 #define EXIT_REASON_PML_FULL 62 #define EXIT_REASON_XSAVES 63 #define EXIT_REASON_XRSTORS 64 #define EXIT_REASON_PCOMMIT 65 #define GUEST_ACTIVITY_ACTIVE 0 #define GUEST_ACTIVITY_HLT 1 typedef struct _VMX_GDTENTRY64 { UINT64 Base; UINT32 Limit; union { struct { UINT8 Flags1; UINT8 Flags2; UINT8 Flags3; UINT8 Flags4; } Bytes; struct { UINT16 SegmentType : 4; UINT16 DescriptorType : 1; UINT16 Dpl : 2; UINT16 Present : 1; UINT16 Reserved : 4; UINT16 System : 1; UINT16 LongMode : 1; UINT16 DefaultBig : 1; UINT16 Granularity : 1; UINT16 Unusable : 1; UINT16 Reserved2 : 15; } Bits; UINT32 AccessRights; }; UINT16 Selector; } VMX_GDTENTRY64, *PVMX_GDTENTRY64; typedef struct _VMX_VMCS { UINT32 RevisionId; UINT32 AbortIndicator; UINT8 Data[PAGE_SIZE - 8]; } VMX_VMCS, *PVMX_VMCS; typedef struct _VMX_EPTP { union { struct { UINT64 Type : 3; UINT64 PageWalkLength : 3; UINT64 EnableAccessAndDirtyFlags : 1; UINT64 Reserved : 5; UINT64 PageFrameNumber : 36; UINT64 ReservedHigh : 16; }; UINT64 AsUlonglong; }; } VMX_EPTP, *PVMX_EPTP; typedef struct _VMX_EPML4E { union { struct { UINT64 Read : 1; UINT64 Write : 1; UINT64 Execute : 1; UINT64 Reserved : 5; UINT64 Accessed : 1; UINT64 SoftwareUse : 1; UINT64 UserModeExecute : 1; UINT64 SoftwareUse2 : 1; UINT64 PageFrameNumber : 36; UINT64 ReservedHigh : 4; UINT64 SoftwareUseHigh : 12; }; UINT64 AsUlonglong; }; } VMX_EPML4E, *PVMX_EPML4E; typedef struct _VMX_HUGE_PDPTE { union { struct { UINT64 Read : 1; UINT64 Write : 1; UINT64 Execute : 1; UINT64 Type : 3; UINT64 IgnorePat : 1; UINT64 Large : 1; UINT64 Accessed : 1; UINT64 Dirty : 1; UINT64 UserModeExecute : 1; UINT64 SoftwareUse : 1; UINT64 Reserved : 18; UINT64 PageFrameNumber : 18; UINT64 ReservedHigh : 4; UINT64 SoftwareUseHigh : 11; UINT64 SupressVme : 1; }; UINT64 AsUlonglong; }; } VMX_HUGE_PDPTE, *PVMX_HUGE_PDPTE; typedef struct _VMX_PDPTE { union { struct { UINT64 Read : 1; UINT64 Write : 1; UINT64 Execute : 1; UINT64 Reserved : 5; UINT64 Accessed : 1; UINT64 SoftwareUse : 1; UINT64 UserModeExecute : 1; UINT64 SoftwareUse2 : 1; UINT64 PageFrameNumber : 36; UINT64 ReservedHigh : 4; UINT64 SoftwareUseHigh : 12; }; UINT64 AsUlonglong; }; } VMX_PDPTE, *PVMX_PDPTE; typedef struct _VMX_LARGE_PDE { union { struct { UINT64 Read : 1; UINT64 Write : 1; UINT64 Execute : 1; UINT64 Type : 3; UINT64 IgnorePat : 1; UINT64 Large : 1; UINT64 Accessed : 1; UINT64 Dirty : 1; UINT64 UserModeExecute : 1; UINT64 SoftwareUse : 1; UINT64 Reserved : 9; UINT64 PageFrameNumber : 27; UINT64 ReservedHigh : 4; UINT64 SoftwareUseHigh : 11; UINT64 SupressVme : 1; }; UINT64 AsUlonglong; }; } VMX_LARGE_PDE, *PVMX_LARGE_PDE; static_assert(sizeof(VMX_EPTP) == sizeof(UINT64), "EPTP Size Mismatch"); static_assert(sizeof(VMX_EPML4E) == sizeof(UINT64), "EPML4E Size Mismatch"); static_assert(sizeof(VMX_PDPTE) == sizeof(UINT64), "EPDPTE Size Mismatch"); #define PML4E_ENTRY_COUNT 512 #define PDPTE_ENTRY_COUNT 512 #define PDE_ENTRY_COUNT 512