From 0512f4d9164ed928bd374376fd375e35af6be483 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 13 Jan 2018 19:59:47 +0800 Subject: fel: ignore more bits in SCTLR Some bits are not meaningful both in ARMv5 and ARMv7/8, however they're read as 0 in ARMv5 but 1 in ARMv7/8. Ignore them. Signed-off-by: Icenowy Zheng Signed-off-by: Andre Przywara --- fel.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/fel.c b/fel.c index 8268a1a..2881587 100644 --- a/fel.c +++ b/fel.c @@ -623,9 +623,14 @@ uint32_t *aw_backup_and_disable_mmu(feldev_handle *dev, * checks needs to be relaxed). */ - /* Basically, ignore M/Z/I/V/UNK bits and expect no TEX remap */ + /* + * Basically, ignore M/Z/I/V/UNK bits and expect no TEX remap. + * Bits [23:22] are Read-As-One on ARMv7, but Should-Be-Zero + * on ARMv5, so ignore them. + * We need the RES1 bits[18,16,4,3] and CP15BEN[5]. + */ sctlr = aw_get_sctlr(dev, soc_info); - if ((sctlr & ~((0x7 << 11) | (1 << 6) | 1)) != 0x00C50038) + if ((sctlr & ~((0x3 << 22) | (0x7 << 11) | (1 << 6) | 1)) != 0x00050038) pr_fatal("Unexpected SCTLR (%08X)\n", sctlr); if (!(sctlr & 1)) { -- cgit v1.2.3