diff options
| author | Adam Langley <agl@google.com> | 2015-02-21 02:00:30 +0300 |
|---|---|---|
| committer | Adam Langley <agl@google.com> | 2015-02-21 02:59:59 +0300 |
| commit | 04c36b5062b3cb6149e549f9f6f5f6fb49d19c2e (patch) | |
| tree | d02927053603993d0ed26619943b0db71b98d13e | |
| parent | 3f309aef45e24dfdfc800b1cb0b6d9734ba9aff2 (diff) | |
Never set RC4_CHAR.
RC4_CHAR is a bit in the x86(-64) CPUID information that switches the
RC4 asm code from using an array of 256 uint32_t's to 256 uint8_t's. It
was originally written for the P4, where the uint8_t style was faster.
(On modern chips, setting RC4_CHAR took RC4-MD5 from 458 to 304 MB/s.
Although I wonder whether, on a server with many connections, using less
cache wouldn't be better.)
However, I'm not too worried about a slowdown of RC4 on P4 systems these
days (the last new P4 chip was released nine years ago) and I want the
code to be simplier.
Also, RC4_CHAR was set when the CPUID family was 15, but Intel actually
lists 15 as a special code meaning "also check the extended family
bits", which the asm didn't do.
The RC4_CHAR support remains in the RC4 asm code to avoid drift with
upstream.
Change-Id: If3febc925a83a76f453b9e9f8de5ee43759927c6
Reviewed-on: https://boringssl-review.googlesource.com/3550
Reviewed-by: David Benjamin <davidben@chromium.org>
Reviewed-by: Adam Langley <agl@google.com>
| -rw-r--r-- | crypto/cpu-x86-asm.pl | 4 | ||||
| -rw-r--r-- | crypto/cpu-x86_64-asm.pl | 4 | ||||
| -rw-r--r-- | include/openssl/cpu.h | 1 | ||||
| -rw-r--r-- | include/openssl/rc4.h | 2 |
4 files changed, 0 insertions, 11 deletions
diff --git a/crypto/cpu-x86-asm.pl b/crypto/cpu-x86-asm.pl index 1ac7d847..319c436d 100644 --- a/crypto/cpu-x86-asm.pl +++ b/crypto/cpu-x86-asm.pl @@ -110,10 +110,6 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); } &cmp ("ebp",0); &jne (&label("notintel")); &or ("edx",1<<30); # set reserved bit#30 on Intel CPUs - &and (&HB("eax"),15); # familiy ID - &cmp (&HB("eax"),15); # P4? - &jne (&label("notintel")); - &or ("edx",1<<20); # set reserved bit#20 to engage RC4_CHAR &set_label("notintel"); &bt ("edx",28); # test hyper-threading bit &jnc (&label("generic")); diff --git a/crypto/cpu-x86_64-asm.pl b/crypto/cpu-x86_64-asm.pl index 9ba5c84f..af1c7a5a 100644 --- a/crypto/cpu-x86_64-asm.pl +++ b/crypto/cpu-x86_64-asm.pl @@ -123,10 +123,6 @@ OPENSSL_ia32_cpuid: cmp \$0,%r9d jne .Lnotintel or \$0x40000000,%edx # set reserved bit#30 on Intel CPUs - and \$15,%ah - cmp \$15,%ah # examine Family ID - jne .Lnotintel - or \$0x00100000,%edx # set reserved bit#20 to engage RC4_CHAR .Lnotintel: bt \$28,%edx # test hyper-threading bit jnc .Lgeneric diff --git a/include/openssl/cpu.h b/include/openssl/cpu.h index 79441ae6..83ec473f 100644 --- a/include/openssl/cpu.h +++ b/include/openssl/cpu.h @@ -78,7 +78,6 @@ extern "C" { * Index 0: * EDX for CPUID where EAX = 1 * Bit 30 is used to indicate an Intel CPU - * Bit 20 is used to indicate RC4_CHAR * Index 1: * ECX for CPUID where EAX = 1 * Index 2: diff --git a/include/openssl/rc4.h b/include/openssl/rc4.h index 727b4740..b5fc8ede 100644 --- a/include/openssl/rc4.h +++ b/include/openssl/rc4.h @@ -69,8 +69,6 @@ extern "C" { typedef struct rc4_key_st { uint32_t x, y; - /* data is sometimes used as an array of 32-bit values and sometimes as 8-bit - * values, depending on the platform. */ uint32_t data[256]; } RC4_KEY; |