diff options
| author | David Benjamin <davidben@chromium.org> | 2015-07-11 16:46:55 +0300 |
|---|---|---|
| committer | Adam Langley <agl@google.com> | 2015-07-17 00:05:24 +0300 |
| commit | c3717f4a00ed234d778897e09419ee1b1d650233 (patch) | |
| tree | 603e31a48c7bf3df007ae3b54fb10ad7938ee3a4 /include/openssl/cpu.h | |
| parent | c4737331a332988a5bf55614863b7c25ec84494b (diff) | |
Extra documentation.
Some other reserved bits are repurposed. Also explicitly mention that
bit 20 is zero (formerly RC4_CHAR), so it's not accidentally repurposed
later.
Change-Id: Idc4b32efe089ae7b7295472c4488f75258b7f962
Reviewed-on: https://boringssl-review.googlesource.com/5432
Reviewed-by: Adam Langley <agl@google.com>
Diffstat (limited to 'include/openssl/cpu.h')
| -rw-r--r-- | include/openssl/cpu.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/include/openssl/cpu.h b/include/openssl/cpu.h index 83ec473f..08dbae0c 100644 --- a/include/openssl/cpu.h +++ b/include/openssl/cpu.h @@ -77,14 +77,20 @@ extern "C" { * * Index 0: * EDX for CPUID where EAX = 1 + * Bit 20 is always zero + * Bit 28 is adjusted to reflect whether the data cache is shared between + * multiple logical cores * Bit 30 is used to indicate an Intel CPU * Index 1: * ECX for CPUID where EAX = 1 + * Bit 11 is used to indicate AMD XOP support, not SDBG * Index 2: * EBX for CPUID where EAX = 7 + * Index 3 is set to zero. * * Note: the CPUID bits are pre-adjusted for the OSXSAVE bit and the YMM and XMM - * bits in XCR0, so it is not necessary to check those. */ + * bits in XCR0, so it is not necessary to check those. However, instructions + * requiring XMM support are not preadjusted for the FXSR bit. */ extern uint32_t OPENSSL_ia32cap_P[4]; #endif |