diff options
| author | Jan Kotas <jkotas@microsoft.com> | 2017-01-25 04:45:59 +0300 |
|---|---|---|
| committer | Jan Kotas <jkotas@microsoft.com> | 2017-01-25 04:45:59 +0300 |
| commit | 9271b7edd05f4f10dd25d8ab7a8402cd1e4a89cd (patch) | |
| tree | 477972b5437e60dd5979a9a22cf02ddefd0f1ed1 /src/Native/Runtime/amd64 | |
| parent | 30fc995b02807f7863cd6dde5d4944dc7ce7d0f2 (diff) | |
Change stackwalking to always use unadjusted IP
Handling of hardware exceptions had a hack to add +1 to the actual instruction IP. Windows x64 unwinder
is disassembling instructions at the IP passed in to detect method epilogs. If the bytes at IP + 1
happened to match the epilog pattern, the unwind is done as if we were in the middle of the epilog that
lead to spectacular crash.
This change is moving this adjustment to be done later for EH related things only, and not interfere
with stackwalking.
Fixes #2535
[tfs-changeset: 1645602]
Diffstat (limited to 'src/Native/Runtime/amd64')
| -rw-r--r-- | src/Native/Runtime/amd64/ExceptionHandling.S | 8 | ||||
| -rw-r--r-- | src/Native/Runtime/amd64/ExceptionHandling.asm | 8 |
2 files changed, 0 insertions, 16 deletions
diff --git a/src/Native/Runtime/amd64/ExceptionHandling.S b/src/Native/Runtime/amd64/ExceptionHandling.S index 360f5bbae..a1a9c43ce 100644 --- a/src/Native/Runtime/amd64/ExceptionHandling.S +++ b/src/Native/Runtime/amd64/ExceptionHandling.S @@ -26,14 +26,6 @@ NESTED_ENTRY RhpThrowHwEx, _TEXT, NoHandler // Align the stack towards zero and rsp, -16 - add rsi, 1 // 'faulting IP' += 1, we do this because everywhere else we treat the faulting IP as - // a return-address and optionally subtract one when doing EH-related things (but not - // subtracting 1 when doing GC-related things). The fault IP here will be the start - // of the faulting instruction, so +1 will point to either the next instruction or the - // middle of this instruction. Either way, when the dispatch / stackwalk code deals - // with this address it'll apply a -1 for EH range checks and the GC-related operations - // don't need to be precise here because the fault location isn't a GC safe point - xor rdx, rdx // struct PAL_LIMITED_CONTEXT diff --git a/src/Native/Runtime/amd64/ExceptionHandling.asm b/src/Native/Runtime/amd64/ExceptionHandling.asm index baf89e9ea..a8ba9ef77 100644 --- a/src/Native/Runtime/amd64/ExceptionHandling.asm +++ b/src/Native/Runtime/amd64/ExceptionHandling.asm @@ -40,14 +40,6 @@ NESTED_ENTRY RhpThrowHwEx, _TEXT ; Tell the unwinder that the frame is there now .pushframe - add rdx, 1 ;; 'faulting IP' += 1, we do this because everywhere else we treat the faulting IP as - ;; a return-address and optionally subtract one when doing EH-related things (but not - ;; subtracting 1 when doing GC-related things). The fault IP here will be the start - ;; of the faulting instruction, so +1 will point to either the next instruction or the - ;; middle of this instruction. Either way, when the dispatch / stackwalk code deals - ;; with this address it'll apply a -1 for EH range checks and the GC-related operations - ;; don't need to be precise here because the fault location isn't a GC safe point - alloc_stack SIZEOF_XmmSaves + 8h ;; reserve stack for the xmm saves (+8h to realign stack) push_vol_reg r8 ;; padding push_nonvol_reg r15 |