diff options
author | Julius Härtl <jus@bitgrid.net> | 2019-09-04 10:59:31 +0300 |
---|---|---|
committer | npmbuildbot[bot] <npmbuildbot[bot]@users.noreply.github.com> | 2019-09-04 11:44:00 +0300 |
commit | 930909d7ad2da93644ecb4df02f4f69fc96ae81d (patch) | |
tree | aec9e2e2444b518d756d73503fa023d61e8fb4ef /js/highlight/vhdl.js.map | |
parent | a89449926a62529b5c29b1108e7e8c6c02e48bf6 (diff) |
Use tightLists option
Signed-off-by: Julius Härtl <jus@bitgrid.net>
Signed-off-by: npmbuildbot[bot] <npmbuildbot[bot]@users.noreply.github.com>
Diffstat (limited to 'js/highlight/vhdl.js.map')
-rw-r--r-- | js/highlight/vhdl.js.map | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/js/highlight/vhdl.js.map b/js/highlight/vhdl.js.map index 454b740aa..933e0c4ba 100644 --- a/js/highlight/vhdl.js.map +++ b/js/highlight/vhdl.js.map @@ -1 +1 @@ -{"version":3,"sources":["webpack:///./node_modules/highlight.js/lib/languages/vhdl.js"],"names":["module","exports","hljs","case_insensitive","keywords","keyword","built_in","literal","illegal","contains","C_BLOCK_COMMENT_MODE","COMMENT","QUOTE_STRING_MODE","className","begin","relevance","BACKSLASH_ESCAPE"],"mappings":"6EAAAA,EAAOC,QAAU,SAASC,GAaxB,MAAO,CACLC,kBAAkB,EAClBC,SAAU,CACRC,QACE,4vBASFC,SACE,6SAMFC,QACE,8DAGJC,QAAS,IACTC,SAAU,CACRP,EAAKQ,qBACLR,EAAKS,QAAQ,KAAM,KACnBT,EAAKU,kBACL,CACEC,UAAW,SACXC,MAjCU,8GAkCVC,UAAW,GAEb,CACEF,UAAW,SACXC,MAAO,wBACPL,SAAU,CAACP,EAAKc,mBAElB,CACEH,UAAW,SACXC,MAAO,4BACPL,SAAU,CAACP,EAAKc","file":"highlight/vhdl.js?v=46a3622cb7863721c084","sourcesContent":["module.exports = function(hljs) {\n // Regular expression for VHDL numeric literals.\n\n // Decimal literal:\n var INTEGER_RE = '\\\\d(_|\\\\d)*';\n var EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;\n var DECIMAL_LITERAL_RE = INTEGER_RE + '(\\\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';\n // Based literal:\n var BASED_INTEGER_RE = '\\\\w+';\n var BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';\n\n var NUMBER_RE = '\\\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';\n\n return {\n case_insensitive: true,\n keywords: {\n keyword:\n 'abs access after alias all and architecture array assert assume assume_guarantee attribute ' +\n 'begin block body buffer bus case component configuration constant context cover disconnect ' +\n 'downto default else elsif end entity exit fairness file for force function generate ' +\n 'generic group guarded if impure in inertial inout is label library linkage literal ' +\n 'loop map mod nand new next nor not null of on open or others out package parameter port ' +\n 'postponed procedure process property protected pure range record register reject ' +\n 'release rem report restrict restrict_guarantee return rol ror select sequence ' +\n 'severity shared signal sla sll sra srl strong subtype then to transport type ' +\n 'unaffected units until use variable view vmode vprop vunit wait when while with xnor xor',\n built_in:\n 'boolean bit character ' +\n 'integer time delay_length natural positive ' +\n 'string bit_vector file_open_kind file_open_status ' +\n 'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' +\n 'std_ulogic std_ulogic_vector unresolved_unsigned u_unsigned unresolved_signed u_signed ' +\n 'real_vector time_vector',\n literal:\n 'false true note warning error failure ' + // severity_level\n 'line text side width' // textio\n },\n illegal: '{',\n contains: [\n hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.\n hljs.COMMENT('--', '$'),\n hljs.QUOTE_STRING_MODE,\n {\n className: 'number',\n begin: NUMBER_RE,\n relevance: 0\n },\n {\n className: 'string',\n begin: '\\'(U|X|0|1|Z|W|L|H|-)\\'',\n contains: [hljs.BACKSLASH_ESCAPE]\n },\n {\n className: 'symbol',\n begin: '\\'[A-Za-z](_?[A-Za-z0-9])*',\n contains: [hljs.BACKSLASH_ESCAPE]\n }\n ]\n };\n};"],"sourceRoot":""}
\ No newline at end of file +{"version":3,"sources":["webpack:///./node_modules/highlight.js/lib/languages/vhdl.js"],"names":["module","exports","hljs","case_insensitive","keywords","keyword","built_in","literal","illegal","contains","C_BLOCK_COMMENT_MODE","COMMENT","QUOTE_STRING_MODE","className","begin","relevance","BACKSLASH_ESCAPE"],"mappings":"qFAAAA,EAAOC,QAAU,SAASC,GAaxB,MAAO,CACLC,kBAAkB,EAClBC,SAAU,CACRC,QACE,4vBASFC,SACE,6SAMFC,QACE,8DAGJC,QAAS,IACTC,SAAU,CACRP,EAAKQ,qBACLR,EAAKS,QAAQ,KAAM,KACnBT,EAAKU,kBACL,CACEC,UAAW,SACXC,MAjCU,8GAkCVC,UAAW,GAEb,CACEF,UAAW,SACXC,MAAO,wBACPL,SAAU,CAACP,EAAKc,mBAElB,CACEH,UAAW,SACXC,MAAO,4BACPL,SAAU,CAACP,EAAKc","file":"highlight/vhdl.js?v=877f04b04078c149c961","sourcesContent":["module.exports = function(hljs) {\n // Regular expression for VHDL numeric literals.\n\n // Decimal literal:\n var INTEGER_RE = '\\\\d(_|\\\\d)*';\n var EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;\n var DECIMAL_LITERAL_RE = INTEGER_RE + '(\\\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';\n // Based literal:\n var BASED_INTEGER_RE = '\\\\w+';\n var BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';\n\n var NUMBER_RE = '\\\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';\n\n return {\n case_insensitive: true,\n keywords: {\n keyword:\n 'abs access after alias all and architecture array assert assume assume_guarantee attribute ' +\n 'begin block body buffer bus case component configuration constant context cover disconnect ' +\n 'downto default else elsif end entity exit fairness file for force function generate ' +\n 'generic group guarded if impure in inertial inout is label library linkage literal ' +\n 'loop map mod nand new next nor not null of on open or others out package parameter port ' +\n 'postponed procedure process property protected pure range record register reject ' +\n 'release rem report restrict restrict_guarantee return rol ror select sequence ' +\n 'severity shared signal sla sll sra srl strong subtype then to transport type ' +\n 'unaffected units until use variable view vmode vprop vunit wait when while with xnor xor',\n built_in:\n 'boolean bit character ' +\n 'integer time delay_length natural positive ' +\n 'string bit_vector file_open_kind file_open_status ' +\n 'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' +\n 'std_ulogic std_ulogic_vector unresolved_unsigned u_unsigned unresolved_signed u_signed ' +\n 'real_vector time_vector',\n literal:\n 'false true note warning error failure ' + // severity_level\n 'line text side width' // textio\n },\n illegal: '{',\n contains: [\n hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.\n hljs.COMMENT('--', '$'),\n hljs.QUOTE_STRING_MODE,\n {\n className: 'number',\n begin: NUMBER_RE,\n relevance: 0\n },\n {\n className: 'string',\n begin: '\\'(U|X|0|1|Z|W|L|H|-)\\'',\n contains: [hljs.BACKSLASH_ESCAPE]\n },\n {\n className: 'symbol',\n begin: '\\'[A-Za-z](_?[A-Za-z0-9])*',\n contains: [hljs.BACKSLASH_ESCAPE]\n }\n ]\n };\n};"],"sourceRoot":""}
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