diff options
| author | Michaël Zasso <targos@protonmail.com> | 2021-04-17 17:28:40 +0300 |
|---|---|---|
| committer | Michaël Zasso <targos@protonmail.com> | 2021-04-30 13:53:44 +0300 |
| commit | 31154a5611e4e2367ec7e468af02d2b47e790a30 (patch) | |
| tree | d653284e34fb1f5b2d56d03b7582b45aec57018a /deps | |
| parent | de654bf5b4860fdfa74682a626fb3b903b33aa93 (diff) | |
deps: V8: cherry-pick 516b5d3f9cfe
Original commit message:
Merged: [wasm-simd][x64] Check for register when emitting shuffles
Some shuffles take have either register or memory operand for second
input, but the codegen incorrectly assumes that it is always a register.
Bug: v8:10824
(cherry picked from commit ddf30bea13902829eeb71aa0ec747155e27e5a68)
Change-Id: I897c4290a8b91ff2ab839e98b16a9696c0bae511
No-Try: true
No-Presubmit: true
No-Tree-Checks: true
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2391280
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/branch-heads/8.6@{#6}
Cr-Branched-From: a64aed2333abf49e494d2a5ce24bbd14fff19f60-refs/heads/8.6.395@{#1}
Cr-Branched-From: a626bc036236c9bf92ac7b87dc40c9e538b087e3-refs/heads/master@{#69472}
Refs: https://github.com/v8/v8/commit/516b5d3f9cfe5cfe78cf38cce0069f8f3d211e7c
PR-URL: https://github.com/nodejs/node/pull/38275
Reviewed-By: Matteo Collina <matteo.collina@gmail.com>
Reviewed-By: Jiawen Geng <technicalcute@gmail.com>
Reviewed-By: Shelley Vohr <codebytere@gmail.com>
Diffstat (limited to 'deps')
| -rw-r--r-- | deps/v8/src/codegen/x64/assembler-x64.h | 4 | ||||
| -rw-r--r-- | deps/v8/src/compiler/backend/x64/code-generator-x64.cc | 12 | ||||
| -rw-r--r-- | deps/v8/test/cctest/test-disasm-x64.cc | 1 |
3 files changed, 13 insertions, 4 deletions
diff --git a/deps/v8/src/codegen/x64/assembler-x64.h b/deps/v8/src/codegen/x64/assembler-x64.h index 24eb9765782..c1c4194f9c3 100644 --- a/deps/v8/src/codegen/x64/assembler-x64.h +++ b/deps/v8/src/codegen/x64/assembler-x64.h @@ -1562,6 +1562,10 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG); emit(imm8); } + void vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) { + vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG); + emit(imm8); + } void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2); diff --git a/deps/v8/src/compiler/backend/x64/code-generator-x64.cc b/deps/v8/src/compiler/backend/x64/code-generator-x64.cc index 4f99ad49ba8..e32a98e78fc 100644 --- a/deps/v8/src/compiler/backend/x64/code-generator-x64.cc +++ b/deps/v8/src/compiler/backend/x64/code-generator-x64.cc @@ -579,10 +579,14 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen, ASSEMBLE_SIMD_INSTR(opcode, dst, input_index); \ } while (false) -#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm) \ - do { \ - DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0)); \ - __ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1), imm); \ +#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm) \ + do { \ + DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0)); \ + if (instr->InputAt(1)->IsSimd128Register()) { \ + __ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1), imm); \ + } else { \ + __ opcode(i.OutputSimd128Register(), i.InputOperand(1), imm); \ + } \ } while (false) #define ASSEMBLE_SIMD_ALL_TRUE(opcode) \ diff --git a/deps/v8/test/cctest/test-disasm-x64.cc b/deps/v8/test/cctest/test-disasm-x64.cc index 8e9eadca25e..290a57653a6 100644 --- a/deps/v8/test/cctest/test-disasm-x64.cc +++ b/deps/v8/test/cctest/test-disasm-x64.cc @@ -813,6 +813,7 @@ TEST(DisasmX64) { __ vpblendw(xmm1, xmm2, xmm3, 23); __ vpblendw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 23); __ vpalignr(xmm1, xmm2, xmm3, 4); + __ vpalignr(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 4); __ vblendvpd(xmm1, xmm2, xmm3, xmm4); |