diff options
| author | luyahan <yahan@iscas.ac.cn> | 2021-03-29 08:45:47 +0300 |
|---|---|---|
| committer | gengjiawen <technicalcute@gmail.com> | 2021-04-14 10:06:29 +0300 |
| commit | 1d21a8d140f78d4408c5375caedc917a83902a80 (patch) | |
| tree | eef63b1764fd61f352b4f679de5367df4d8f1e27 /tools | |
| parent | 8d9d8236b79ea91640f973cc8c1423603694b482 (diff) | |
build: add riscv64 configure
v8 had been add riscv64 backend, so i open this
pr to add riscv64 configure.
Refs: https://github.com/nodejs/node/issues/37856
PR-URL: https://github.com/nodejs/node/pull/37980
Fixes: https://github.com/nodejs/node/issues/37856
Reviewed-By: Richard Lau <rlau@redhat.com>
Reviewed-By: Michaël Zasso <targos@protonmail.com>
Reviewed-By: Jiawen Geng <technicalcute@gmail.com>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/v8_gypfiles/toolchain.gypi | 7 | ||||
| -rw-r--r-- | tools/v8_gypfiles/v8.gyp | 17 |
2 files changed, 23 insertions, 1 deletions
diff --git a/tools/v8_gypfiles/toolchain.gypi b/tools/v8_gypfiles/toolchain.gypi index 165ba936e56..564f775f21f 100644 --- a/tools/v8_gypfiles/toolchain.gypi +++ b/tools/v8_gypfiles/toolchain.gypi @@ -273,6 +273,13 @@ }], ], }], + ['v8_target_arch=="riscv64"', { + 'defines': [ + 'V8_TARGET_ARCH_RISCV64', + '__riscv_xlen=64', + 'CAN_USE_FPU_INSTRUCTIONS' + ], + }], ['v8_target_arch=="s390x"', { 'defines': [ 'V8_TARGET_ARCH_S390', diff --git a/tools/v8_gypfiles/v8.gyp b/tools/v8_gypfiles/v8.gyp index 2b2d4234a66..ef5319fa08f 100644 --- a/tools/v8_gypfiles/v8.gyp +++ b/tools/v8_gypfiles/v8.gyp @@ -274,6 +274,11 @@ '<(V8_ROOT)/src/builtins/mips/builtins-mips.cc', ], }], + ['v8_target_arch=="riscv64" or v8_target_arch=="riscv64"', { + 'sources': [ + '<(V8_ROOT)/src/builtins/riscv64/builtins-riscv64.cc', + ], + }], ['v8_target_arch=="mips64" or v8_target_arch=="mips64el"', { 'sources': [ '<(V8_ROOT)/src/builtins/mips64/builtins-mips64.cc', @@ -686,6 +691,11 @@ '<!@pymod_do_main(GN-scraper "<(V8_ROOT)/BUILD.gn" "\\"v8_base_without_compiler.*?v8_current_cpu == \\"mips\\".*?sources \+= ")', ], }], + ['v8_target_arch=="riscv64"', { + 'sources': [ ### gcmole(arch:riscv64) ### + '<!@pymod_do_main(GN-scraper "<(V8_ROOT)/BUILD.gn" "\\"v8_base_without_compiler.*?v8_current_cpu == \\"riscv64.*?sources \+= ")', + ], + }], ['v8_target_arch=="mips64" or v8_target_arch=="mips64el"', { 'sources': [ ### gcmole(arch:mips64el) ### '<!@pymod_do_main(GN-scraper "<(V8_ROOT)/BUILD.gn" "\\"v8_base_without_compiler.*?v8_current_cpu == \\"mips64\\".*?sources \+= ")', @@ -764,7 +774,7 @@ }], # Platforms that don't have Compare-And-Swap (CAS) support need to link atomic library # to implement atomic memory access - ['v8_current_cpu in ["mips", "mipsel", "mips64", "mips64el", "ppc", "arm"]', { + ['v8_current_cpu in ["mips", "mipsel", "mips64", "mips64el", "ppc", "arm", "riscv64"]', { 'link_settings': { 'libraries': ['-latomic', ], }, @@ -1410,6 +1420,11 @@ '<(V8_ROOT)/src/heap/base/asm/mips64/push_registers_asm.cc', ], }], + ['_toolset == "host" and host_arch == "riscv64" or _toolset == "target" and target_arch=="riscv64"', { + 'sources': [ + '<(V8_ROOT)/src/heap/base/asm/riscv64/push_registers_asm.cc', + ], + }], ] }], ['OS=="win"', { |